Whitespace removal.

3 files changed, 28 insertions, 28 deletions

diff --git a/c/src/lib/libbsp/m68k/uC5282/start/start.S b/c/src/lib/libbsp/m68k/uC5282/start/start.S
index 03ec2731ba..a4dfae810e 100644
--- a/c/src/lib/libbsp/m68k/uC5282/start/start.S
+++ b/c/src/lib/libbsp/m68k/uC5282/start/start.S
@@ -298,9 +298,9 @@ Entry:
  */
 .align 4
     PUBLIC (_uhoh)
-SYM(_uhoh): 
+SYM(_uhoh):
     nop                 | Leave spot for breakpoint
-    stop    #0x2700             | Stop with interrupts disabled 
+    stop    #0x2700             | Stop with interrupts disabled
     bra.w   SYM(_uhoh)          | Stuck forever
 
 .align 4
@@ -336,16 +336,16 @@ vectcpy:
     move.l a0@+,a1@+       | Copy the vector table
     sub.l  #1,d0
     bne.s  vectcpy
-     
+
     /*
      * Remainder of the startup code is handled by C code
      */
     jmp SYM(Init5282)       | Start C code (which never returns)
-    
+
 /***************************************************************************
    Function : CopyDataClearBSSAndStart
 
-   Description : Copy DATA segment, Copy SRAM segment, clear BSS segment, 
+   Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
    start C program. Assume that DATA and BSS sizes are multiples of 4.
  ***************************************************************************/
 .align 4
@@ -354,7 +354,7 @@ vectcpy:
 SYM(CopyDataClearBSSAndStart):
     lea SYM(_data_dest_start),a0        | Get start of DATA in RAM
     lea SYM(_data_src_start),a2     | Get start of DATA in ROM
-        sub.l   #SYM(_header_offset),a2          | Change source by the amount of the header offset 
+        sub.l   #SYM(_header_offset),a2          | Change source by the amount of the header offset
     cmpl    a0,a2                   | Are they the same?
     beq.s   NODATACOPY              | Yes, no copy necessary
     lea SYM(_data_dest_end),a1      | Get end of DATA in RAM
@@ -365,7 +365,7 @@ DATACOPYLOOPTEST:
     cmpl    a1,a0                   | Done?
     bcs.s   DATACOPYLOOP                | No, skip
 NODATACOPY:
-        
+
 /* Now, clear BSS */
         lea _clear_start,a0     | Get start of BSS
     lea _clear_end,a1       | Get end of BSS
@@ -389,7 +389,7 @@ MULTI_TASK_EXIT:
         nop
         nop
         trap    #14
-        bra     MULTI_TASK_EXIT      
+        bra     MULTI_TASK_EXIT
 
 
 END_CODE
diff --git a/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c b/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
index c56197c690..22fc635dcd 100644
--- a/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
+++ b/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
@@ -14,14 +14,14 @@
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
- * 
+ *
  *  $Id$
  */
 
 #include <bsp.h>
 #include <rtems/error.h>
 #include <errno.h>
- 
+
 /*
  * Location of 'VME' access
  */
@@ -53,7 +53,7 @@ extern char RamBase[];
  * If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
  * and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
  * then cache corruption may  occur.
- * 
+ *
  * 6.2 Workaround
  * All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
  * should be followed immediately by a NOP instruction.  This avoids the cache
@@ -63,16 +63,16 @@ extern char RamBase[];
  *
  * Buffered writes must be disabled as described in "MCF5282 Chip Errata",
  * MCF5282DE, Rev. 6, 5/2009:
- *   SECF124: Buffered Write May Be Executed Twice 
- *   Errata type: Silicon 
- *   Affected component: Cache 
+ *   SECF124: Buffered Write May Be Executed Twice
+ *   Errata type: Silicon
+ *   Affected component: Cache
  *   Description: If buffered writes are enabled using the CACR or ACR
  *                registers, the imprecise write transaction generated
- *                by a buffered write may be executed twice. 
- *   Workaround: Do not enable buffered writes in the CACR or ACR registers: 
- *               CACR[8] = DBWE (default buffered write enable) must be 0 
- *               ACRn[5] = BUFW (buffered write enable) must be 0 
- *   Fix plan: Currently, there are no plans to fix this. 
+ *                by a buffered write may be executed twice.
+ *   Workaround: Do not enable buffered writes in the CACR or ACR registers:
+ *               CACR[8] = DBWE (default buffered write enable) must be 0
+ *               ACRn[5] = BUFW (buffered write enable) must be 0
+ *   Fix plan: Currently, there are no plans to fix this.
  */
 #define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
 #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
@@ -282,7 +282,7 @@ void bsp_start( void )
    *   Two A24/D16 spaces, supervisor data acces
    */
   MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
-  MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | 
+  MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M |
                      MCF5282_CS_CSMR_CI |
                      MCF5282_CS_CSMR_SC |
                      MCF5282_CS_CSMR_UC |
@@ -290,7 +290,7 @@ void bsp_start( void )
                      MCF5282_CS_CSMR_V;
   MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
   MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
-  MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | 
+  MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M |
                      MCF5282_CS_CSMR_CI |
                      MCF5282_CS_CSMR_SC |
                      MCF5282_CS_CSMR_UC |
@@ -511,7 +511,7 @@ fpga_trampoline (rtems_vector_number v)
 static rtems_isr
 trampoline (rtems_vector_number v)
 {
-    if (handlerTab[v].func) 
+    if (handlerTab[v].func)
         (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
 }
 
@@ -605,7 +605,7 @@ rtems_interrupt_level level;
                     if (source < 8)
                         MCF5282_EPORT_EPIER |= 1 << source;
                     else
-                        *(&MCF5282_INTC0_ICR1 + (source - 1)) = 
+                        *(&MCF5282_INTC0_ICR1 + (source - 1)) =
                                                        MCF5282_INTC_ICR_IL(l) |
                                                        MCF5282_INTC_ICR_IP(p);
           enable_irq(source);
@@ -691,7 +691,7 @@ rtems_bsp_reset_cause(char *buf, size_t capacity)
   int bit, rsr;
   size_t i;
   const char *cp;
-    
+
   if (buf == NULL)
     return;
   if (capacity)
@@ -709,13 +709,13 @@ rtems_bsp_reset_cause(char *buf, size_t capacity)
         case MCF5282_RESET_RSR_LOL:  cp = "Loss of lock";       break;
         default:                     cp = "??";                 break;
       }
-      i += snprintf(buf+i, capacity-i, cp); 
+      i += snprintf(buf+i, capacity-i, cp);
       if (i >= capacity)
         break;
       rsr &= ~bit;
       if (rsr == 0)
         break;
-      i += snprintf(buf+i, capacity-i, ", "); 
+      i += snprintf(buf+i, capacity-i, ", ");
       if (i >= capacity)
         break;
     }
diff --git a/c/src/lib/libbsp/m68k/uC5282/startup/init5282.c b/c/src/lib/libbsp/m68k/uC5282/startup/init5282.c
index 6eaef35262..83b3501b0b 100644
--- a/c/src/lib/libbsp/m68k/uC5282/startup/init5282.c
+++ b/c/src/lib/libbsp/m68k/uC5282/startup/init5282.c
@@ -2,7 +2,7 @@
  * This is where the real hardware setup is done. A minimal stack
  * has been provided by the start.S code. No normal C or RTEMS
  * functions can be called from here.
- * 
+ *
  * This routine is pretty simple for the uC5282 because all the hard
  * work has been done by the bootstrap dBUG code.
  *
@@ -26,7 +26,7 @@
 void Init5282 (void)
 {
     extern void CopyDataClearBSSAndStart (void);
-    
+
     /*
      * Copy data, clear BSS and call boot_card()
      */