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| author | James Fitzsimons <james.fitzsimons@gmail.com> | 2014-03-24 22:32:10 +1300 |
|---|---|---|
| committer | Gedare Bloom <gedare@rtems.org> | 2014-03-26 11:32:52 -0400 |
| commit | 89aa1ec87da68b8a6cff2233552a739173e676a4 (patch) | |
| tree | 5127f83e144564b4a21250775cb3c93fbdc69628 /c/src/lib/libbsp/m68k/mrm332/include/mrm332.h | |
| parent | tests: Produce proper begin/end messages (diff) | |
| download | rtems-89aa1ec87da68b8a6cff2233552a739173e676a4.tar.bz2 | |
m68k/mrm332: changes required to get the mrm332 bsp working again.
Changed console driver to use interrupts instead of polling.
Change to avoid overwriting CPU32Bug interrupt vector when setting up the Sci interrupt handler.
Fixed type for boolean flag in bsp.h.
Changed mrm332.h to use 25Mhz clock.
Fixes to mrm332.cfg to use correct mcpu32 value for RTEMS_CPU_MODEL instead of m68332 which is no longer supported.
Added -mcpu=cpu32 to compiler options.
Removed broken ROM linker script and replaced broken RAM linker script with working ROM linker script.
Removed no longer required file except_vect_332_ROM.S.
Enabled 0xbeefbeef magic string in start.S to allow MRM version of CPU32Bug to auto run RTEMS.
Removed old code from start.S
Changed compiler optimization flag to optimize for size.
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libbsp/m68k/mrm332/include/mrm332.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/m68k/mrm332/include/mrm332.h b/c/src/lib/libbsp/m68k/mrm332/include/mrm332.h index 58e5b2035a..1b8672752d 100644 --- a/c/src/lib/libbsp/m68k/mrm332/include/mrm332.h +++ b/c/src/lib/libbsp/m68k/mrm332/include/mrm332.h @@ -27,6 +27,8 @@ /* System Clock definitions */ #define XTAL 32768.0 /* crystal frequency in Hz */ +/* Specify the CPU frequency. Do not specify a faster clock than your */ +/* CPU is rated for! */ #if 0 /* Default MRM clock rate (8.388688 MHz) set by CPU32: */ #define MRM_W 0 /* system clock parameters */ @@ -34,18 +36,19 @@ #define MRM_Y 0x3f #endif -#if 1 +#if 0 /* 16.77722 MHz: */ #define MRM_W 1 /* system clock parameters */ #define MRM_X 1 #define MRM_Y 0x0f #endif -#if 0 +#if 1 /* 25.16582 MHz: */ #define MRM_W 1 /* system clock parameters */ #define MRM_X 1 #define MRM_Y 0x17 +#define SET_EDIV #endif #define SYS_CLOCK (XTAL*4.0*(MRM_Y+1)*(1 << (2*MRM_W+MRM_X))) |