Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

7 files changed, 0 insertions, 1032 deletions

diff --git a/c/src/lib/libbsp/m68k/gen68340/include/bsp.h b/c/src/lib/libbsp/m68k/gen68340/include/bsp.h
deleted file mode 100644
index 28d86ff2f7..0000000000
--- a/c/src/lib/libbsp/m68k/gen68340/include/bsp.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/**
- * @file
- *
- * @ingroup m68k_gen68340
- *
- * @brief Global BSP definitions.
- */
-
-/*
- * Board Support Package for `Generic' Motorola MC68340
- *
- * Based on the `gen68360' board support package, and covered by the
- * original distribution terms.
- */
-
-/*  bsp.h
- *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef LIBBSP_M68K_GEN68340_BSP_H
-#define LIBBSP_M68K_GEN68340_BSP_H
-
-#ifndef ASM
-
-#include <bspopts.h>
-#include <bsp/default-initial-extension.h>
-
-#include <rtems.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup m68k_gen68340 Motorola MC68340 Support
- *
- * @ingroup bsp_m68k
- *
- * @brief Motorola MC68340 support.
- */
-
-/* Constants */
-
-/* Structures */
-
-extern rtems_isr_entry M68Kvec[];   /* vector table address */
-
-/* functions */
-
-rtems_isr_entry set_vector(
-  rtems_isr_entry     handler,
-  rtems_vector_number vector,
-  int                 type
-);
-
-/*
- *  Methods used across files inside the BSP
- */
-int dbug_in_char( int minor );
-void dbug_out_char( int minor, int ch );
-int dbug_char_present( int minor );
-void _dbug_dumpanic(void);
-
-/*
- *  Only called from .S but prototyped here to capture the dependecy.
- */
-void _Init68340 (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !ASM */
-
-#endif
diff --git a/c/src/lib/libbsp/m68k/gen68340/include/m340timer.h b/c/src/lib/libbsp/m68k/gen68340/include/m340timer.h
deleted file mode 100644
index 892c690e5f..0000000000
--- a/c/src/lib/libbsp/m68k/gen68340/include/m340timer.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * @file
- *
- * @ingroup m68k_gen68340
- *
- * @brief Time driver definitions.
- */
-
-/*
- *  Header file for timer driver
- *  defines for accessing M68340 timer registers
- *
- *  Author:
- *  Geoffroy Montel
- *  France Telecom - CNET/DSM/TAM/CAT
- *  4, rue du Clos Courtel
- *  35512 CESSON-SEVIGNE
- *  FRANCE
- *
- *  e-mail: g_montel@yahoo.com
- *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef __m340timer_H__
-#define __m340timer_H__
-
-extern void Fifo_Full_benchmark_timer_initialize (void);
-
-extern void (*Restart_Fifo_Full_A_Timer)();
-extern void (*Restart_Check_A_Timer)();
-extern void (*Restart_Fifo_Full_B_Timer)();
-extern void (*Restart_Check_B_Timer)();
-
-/*  CR */
-#define m340_SWR		(1<<15)
-#define m340_Polling_Mode	(0<<12)
-#define m340_TC_Enabled		(1<<12)
-#define m340_TG_Enabled		(2<<12)
-#define m340_TG_TC_Enabled	(3<<12)
-#define m340_TO_Enabled		(4<<12)
-#define m340_TO_TC_Enabled	(5<<12)
-#define m340_TG_TG_Enabled	(6<<12)
-#define m340_TO_TG_TG_Enabled	(7<<12)
-#define m340_TGE		(1<<11)
-#define m340_PSE		(1<<10)
-#define m340_CPE		(1<<9)
-#define m340_CLK		(1<<8)
-#define m340_Divide_by_2	(1<<5)
-#define m340_Divide_by_4	(2<<5)
-#define m340_Divide_by_8	(3<<5)
-#define m340_Divide_by_16	(4<<5)
-#define m340_Divide_by_32	(5<<5)
-#define m340_Divide_by_64	(6<<5)
-#define m340_Divide_by_128	(7<<5)
-#define m340_Divide_by_256	(0<<5)
-#define m340_ICOC		(0<<2)
-#define m340_SWG		(1<<2)
-#define m340_VDCSWG		(2<<2)
-#define m340_VWSSPG		(3<<2)
-#define m340_PWM		(4<<2)
-#define m340_PM			(5<<2)
-#define m340_EC			(6<<2)
-#define m340_TB			(7<<2)
-#define m340_Disabled		0
-#define m340_Toggle_Mode	1
-#define m340_Zero_Mode		2
-#define m340_One_Mode		3
-
-/*  SR */
-#define m340_IRQ		(1<<15)
-#define m340_TO			(1<<14)
-#define m340_TG			(1<<13)
-#define m340_TC			(1<<12)
-#define m340_TGL		(1<<11)
-#define m340_ON			(1<<10)
-#define m340_OUT		(1<<9)
-#define m340_COM		(1<<8)
-
-#endif
diff --git a/c/src/lib/libbsp/m68k/gen68340/include/m340uart.h b/c/src/lib/libbsp/m68k/gen68340/include/m340uart.h
deleted file mode 100644
index 619a732a14..0000000000
--- a/c/src/lib/libbsp/m68k/gen68340/include/m340uart.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/**
- * @file
- *
- * @ingroup m68k_gen68340
- *
- * @brief UART console driver definitions.
- */
-
-/*
- *  Header file for console driver
- *  defines for accessing M68340/68349 UART registers
- *
- *  Author:
- *  Geoffroy Montel
- *  France Telecom - CNET/DSM/TAM/CAT
- *  4, rue du Clos Courtel
- *  35512 CESSON-SEVIGNE
- *  FRANCE
- *
- *  e-mail: g_montel@yahoo.com
- *
- *
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef __m340uart_H__
-#define __m340uart_H__
-
-/* UART initialisation */
-#define UART_CHANNEL_A			0
-#define UART_CHANNEL_B			1
-#define UART_NUMBER_OF_CHANNELS		2
-#define UART_CONSOLE_NAME		"/dev/console"
-#define UART_RAW_IO_NAME		"/dev/tty1"
-#define UART_FIFO_FULL			0
-#define UART_CRR			1
-#define UART_INTERRUPTS			0
-#define UART_POLLING			1
-#define UART_TERMIOS_CONSOLE		0
-#define UART_TERMIOS_RAW		1
-#define UART_TERMIOS_MIN_DEFAULT	1
-#define UART_TERMIOS_TIME_DEFAULT	0
-
-void Init_UART_Table(void);
-
-typedef struct {
-		uint8_t        		enable;
-		uint16_t        	rx_buffer_size;	/* NOT IMPLEMENTED */
-		uint16_t        	tx_buffer_size;	/* NOT IMPLEMENTED */
-	       } uart_termios_config;
-
-typedef struct { /* for one channel */
-		uint8_t        		enable;		/* use this channel */
-		char			name[64];	/* use UART_CONSOLE_NAME for console purpose */
-		uint8_t        		parity_mode;	/* parity mode, see MR1 section for defines */
-		uint8_t        		bits_per_char;	/* bits per character, see MR1 section for defines  */
-		float			rx_baudrate;	/* Rx baudrate */
-		float			tx_baudrate;	/* Tx baudrate */
-		uint8_t        		rx_mode;	/* FIFO Full (UART_FIFO_FULL) or ChannelReceiverReady (UART_CRR) */
-		uint8_t        		mode;		/* use interrupts (UART_INTERRUPTS) or polling (UART_POLLING) */
-		uart_termios_config	termios;
-	       } uart_channel_config;
-
-extern uart_channel_config		m340_uart_config[UART_NUMBER_OF_CHANNELS];
-
-typedef  struct {
-		 int	set;	/* number of the m340 baud speed set */
-		 int	rcs;	/* RCS for the needed baud set */
-		 int    tcs;	/* TCS for the needed baud set */
-		} t_baud_speed;
-
-typedef	 struct {
-		 t_baud_speed	baud_speed_table[2];
-		 short		nb;
-		} t_baud_speed_table;
-
-extern t_baud_speed_table
-Find_Right_m340_UART_Config(float ChannelA_ReceiverBaudRate, float ChannelA_TransmitterBaudRate, uint8_t         enableA,
-			    float ChannelB_ReceiverBaudRate, float ChannelB_TransmitterBaudRate, uint8_t         enableB);
-
-extern rtems_isr InterruptHandler (rtems_vector_number v);
-
-extern int dbugRead (int minor);
-extern ssize_t dbugWrite (int minor, const char *buf, size_t len);
-
-extern float m340_Baud_Rates_Table[16][2];
-
-/*  SR */
-#define m340_Rx_RDY		1
-#define m340_FFULL		(1<<1)
-#define m340_Tx_RDY		(1<<2)
-#define m340_TxEMP		(1<<3)
-#define m340_OE			(1<<4)
-#define m340_PE			(1<<5)
-#define m340_FE			(1<<6)
-#define m340_RB			(1<<7)
-
-/*  IER */
-#define m340_TxRDYA		1
-#define m340_RxRDYA		(1<<1)
-#define m340_TxRxRDYA		0x3
-#define m340_TxRDYB		(1<<4)
-#define m340_RxRDYB		(1<<5)
-#define m340_TxRxRDYB		0x30
-
-/*  CR */
-#define m340_Reset_Error_Status	0x40
-#define m340_Reset_Receiver	0x20
-#define m340_Reset_Transmitter	0x30
-#define m340_Transmitter_Enable	(1<<2)
-#define m340_Receiver_Enable	1
-#define m340_Transmitter_Disable (2<<2)
-#define m340_Receiver_Disable	2
-
-/*  ACR */
-#define m340_BRG_Set1		0
-#define m340_BRG_Set2		(1<<7)
-
-/*  OPCR */
-#define m340_OPCR_Gal		0x0
-#define m340_OPCR_Aux		0xFF
-
-/*  ISR */
-#define m340_COS		(1<<7)
-#define m340_DBB		(1<<6)
-#define m340_XTAL_RDY		(1<<3)
-#define m340_DBA		(1<<2)
-
-/*  MR1 */
-#define m340_RxRTS		(1<<7)
-#define m340_R_F		(1<<6)		/* character or block mode */
-#define m340_ERR		(1<<5)
-#define m340_RxRTX		(1<<7)
-#define m340_Even_Parity	0
-#define m340_Odd_Parity		(1<<2)
-#define m340_Low_Parity		(2<<2)
-#define m340_High_Parity	(3<<2)
-#define m340_No_Parity		(4<<2)
-#define m340_Data_Character	(6<<2)
-#define m340_Address_Character	(7<<2)
-#define m340_5bpc		0x0
-#define m340_6bpc		0x1
-#define m340_7bpc		0x2
-#define m340_8bpc		0x3
-
-/*  MR2 */
-#define m340_normal		(0<<6)
-#define m340_automatic_echo	(1<<6)
-#define m340_local_loopback	(2<<6)
-#define m340_remote_loopback	(3<<6)
-#define m340_TxRTS		(1<<5)
-#define m340_TxCTS		(1<<4)
-
-/* Baud rates for Transmitter/Receiver */
-#define SCLK	1		/* put your own SCLK value here */
-
-#endif
diff --git a/c/src/lib/libbsp/m68k/gen68340/include/m68340.h b/c/src/lib/libbsp/m68k/gen68340/include/m68340.h
deleted file mode 100644
index 37440f3098..0000000000
--- a/c/src/lib/libbsp/m68k/gen68340/include/m68340.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/**
- * @file
- *
- * @ingroup m68k_gen68340
- *
- * @brief MC68430 definitions.
- */ 
-
-/**********************************************************************
- *  MC68340 C Header File                                             *
- *                                                                    *
- *  Developed by         : Motorola                                   *
- *                         High Performance Embedded Systems Division *
- *                         Austin, TX                                 *
- *  Rectified by	 : Geoffroy Montel
- *			   g_montel@yahoo.com			      *
- *                                                                    *
- **********************************************************************/
-
-typedef volatile unsigned char *  portb;  /* 8-bit port  */
-typedef volatile unsigned short * portw;  /* 16-bit port */
-typedef volatile unsigned int *   portl;  /* 32-bit port */
-
-#define MBASE 0xEFFFF000             /* Module Base Address          */
-			             /* not EFFFF000 due to a 68349
-					hardware incompatibility     */
-
-#define MBAR   (*(portb) 0x0003FF00) /* Module Base Addr Reg         */
-#define MBAR1  (*(portb) 0x0003FF00) /* Module Base Addr Reg 1 (MSW) */
-#define MBAR2  (*(portb) 0x0003FF02) /* Module Base Addr Reg 2 (LSW) */
-
-/* System Integration Module */
-
-#define SIMMCR    (*(portw) (MBASE+0x0000)) /* SIM Module Config Reg    */
-#define SIMSYNCR  (*(portw) (MBASE+0x0004)) /* SIM Clock Synth Cont Reg */
-#define SIMAVR    (*(portb) (MBASE+0x0006)) /* SIM Autovector Reg       */
-#define SIMRSR    (*(portb) (MBASE+0x0007)) /* SIM Reset Status Reg     */
-#define SIMPORTA  (*(portb) (MBASE+0x0011)) /* SIM Port A Data Reg      */
-#define SIMDDRA   (*(portb) (MBASE+0x0013)) /* SIM Port A Data Dir Reg  */
-#define SIMPPRA1  (*(portb) (MBASE+0x0015)) /* SIM Port A Pin Asm 1 Reg */
-#define SIMPPRA2  (*(portb) (MBASE+0x0017)) /* SIM Port A Pin Asm 2 Reg */
-#define SIMPORTB  (*(portb) (MBASE+0x0019)) /* SIM Port B Data Reg      */
-#define SIMPORTB1 (*(portb) (MBASE+0x001B)) /* SIM Port B Data Reg      */
-#define SIMDDRB   (*(portb) (MBASE+0x001D)) /* SIM Port B Data Dir Reg  */
-#define SIMPPARB  (*(portb) (MBASE+0x001F)) /* SIM Port B Pin Asm Reg   */
-#define SIMSWIV   (*(portb) (MBASE+0x0020)) /* SIM SW Interrupt Vector  */
-#define SIMSYPCR  (*(portb) (MBASE+0x0021)) /* SIM System Prot Cont Reg */
-#define SIMPICR   (*(portw) (MBASE+0x0022)) /* SIM Period Intr Cont Reg */
-#define SIMPITR   (*(portw) (MBASE+0x0024)) /* SIM Period Intr Tmg Reg  */
-#define SIMSWSR   (*(portb) (MBASE+0x0027)) /* SIM Software Service Reg */
-
-#define SIMCS0AM  (*(portl) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk   */
-#define SIMCS0AM1 (*(portw) (MBASE+0x0040)) /* SIM Chp Sel 0 Addr Msk 1 */
-#define SIMCS0AM2 (*(portw) (MBASE+0x0042)) /* SIM Chp Sel 0 Addr Msk 2 */
-#define SIMCS0BA  (*(portl) (MBASE+0x0044)) /* SIM Chp Sel 0 Base Addr  */
-#define SIMCS0BA1 (*(portw) (MBASE+0x0044)) /* SIM Chp Sel 0 Bas Addr 1 */
-#define SIMCS0BA2 (*(portw) (MBASE+0x0046)) /* SIM Chp Sel 0 Bas Addr 2 */
-#define SIMCS1AM  (*(portl) (MBASE+0x0048)) /* SIM Chp Sel 1 Adress Msk */
-#define SIMCS1AM1 (*(portw) (MBASE+0x0048)) /* SIM Chp Sel 1 Addr Msk 1 */
-#define SIMCS1AM2 (*(portw) (MBASE+0x004A)) /* SIM Chp Sel 1 Addr Msk 2 */
-#define SIMCS1BA  (*(portl) (MBASE+0x004C)) /* SIM Chp Sel 1 Base Addr  */
-#define SIMCS1BA1 (*(portw) (MBASE+0x004C)) /* SIM Chp Sel 1 Bas Addr 1 */
-#define SIMCS1BA2 (*(portw) (MBASE+0x004E)) /* SIM Chp Sel 1 Bas Addr 2 */
-#define SIMCS2AM  (*(portl) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk   */
-#define SIMCS2AM1 (*(portw) (MBASE+0x0050)) /* SIM Chp Sel 2 Addr Msk 1 */
-#define SIMCS2AM2 (*(portw) (MBASE+0x0052)) /* SIM Chp Sel 2 Addr Msk 2 */
-#define SIMCS2BA  (*(portl) (MBASE+0x0054)) /* SIM Chp Sel 2 Base Addr  */
-#define SIMCS2BA1 (*(portw) (MBASE+0x0054)) /* SIM Chp Sel 2 Bas Addr 1 */
-#define SIMCS2BA2 (*(portw) (MBASE+0x0056)) /* SIM Chp Sel 2 Bas Addr 2 */
-#define SIMCS3AM  (*(portl) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk   */
-#define SIMCS3AM1 (*(portw) (MBASE+0x0058)) /* SIM Chp Sel 3 Addr Msk 1 */
-#define SIMCS3AM2 (*(portw) (MBASE+0x005A)) /* SIM Chp Sel 3 Addr Msk 2 */
-#define SIMCS3BA  (*(portl) (MBASE+0x005C)) /* SIM Chp Sel 3 Base Addr  */
-#define SIMCS3BA1 (*(portw) (MBASE+0x005C)) /* SIM Chp Sel 3 Bas Addr 1 */
-#define SIMCS3BA2 (*(portw) (MBASE+0x005E)) /* SIM Chp Sel 3 Bas Addr 2 */
-
-/* Dynamic Memory Access (DMA) Module */
-
-#define DMAMCR1   (*(portw) (MBASE+0x0780)) /* DMA Module Config Reg 1  */
-#define DMAINTR1  (*(portw) (MBASE+0x0784)) /* DMA Interrupt Reg 1      */
-#define DMACCR1   (*(portw) (MBASE+0x0788)) /* DMA Channel Cont Reg 1   */
-#define DMACSR1   (*(portb) (MBASE+0x078A)) /* DMA Channel Status Reg 1 */
-#define DMAFCR1   (*(portb) (MBASE+0x078B)) /* DMA Function Code Reg 1  */
-#define DMASAR1   (*(portl) (MBASE+0x078C)) /* DMA DMA Src Addr Reg 1   */
-#define DMADAR1   (*(portl) (MBASE+0x0790)) /* DMA Dest Addr Reg 1      */
-#define DMABTC1   (*(portb) (MBASE+0x079l)) /* DMA Byte Trans Cnt Reg 1 */
-
-#define DMAMCR2   (*(portw) (MBASE+0x07A0)) /* DMA Module Config Reg 2  */
-#define DMAINTR2  (*(portw) (MBASE+0x07A4)) /* DMA Interrupt Reg 2      */
-#define DMACCR2   (*(portw) (MBASE+0x07A8)) /* DMA Channel Cont Reg 2   */
-#define DMACSR2   (*(portb) (MBASE+0x07AA)) /* DMA Channel Status Reg 2 */
-#define DMAFCR2   (*(portb) (MBASE+0x07AB)) /* DMA Function Code Reg 1  */
-#define DMASAR2   (*(portl) (MBASE+0x07AC)) /* DMA Source  Addr Reg 2   */
-#define DMADAR2   (*(portl) (MBASE+0x07B0)) /* DMA Dest Addr Reg 2      */
-#define DMABTC2   (*(portb) (MBASE+0x07B4)) /* DMA Byte Trans Cnt Reg 2 */
-
-/* Dual Serial Module */
-
-#define DUMCRH    (*(portb) (MBASE+0x0700)) /* DUART Module Config Reg  */
-#define DUMCRL    (*(portb) (MBASE+0x0701)) /* DUART Module Config Reg  */
-#define DUILR     (*(portb) (MBASE+0x0704)) /* DUART Interrupt Level    */
-#define DUIVR     (*(portb) (MBASE+0x0705)) /* DUART Interrupt Vector   */
-#define DUMR1A    (*(portb) (MBASE+0x0710)) /* DUART Mode Reg 1A        */
-#define DUSRA     (*(portb) (MBASE+0x0711)) /* DUART Status Reg A       */
-#define DUCSRA    (*(portb) (MBASE+0x0711)) /* DUART Clock Sel Reg A    */
-#define DUCRA     (*(portb) (MBASE+0x0712)) /* DUART Command Reg A      */
-#define DURBA     (*(portb) (MBASE+0x0713)) /* DUART Receiver Buffer A  */
-#define DUTBA     (*(portb) (MBASE+0x0713)) /* DUART Transmitter Buff A */
-#define DUIPCR    (*(portb) (MBASE+0x0714)) /* DUART Input Port Chg Reg */
-#define DUACR     (*(portb) (MBASE+0x0714)) /* DUART Auxiliary Cont Reg */
-#define DUISR     (*(portb) (MBASE+0x0715)) /* DUART Interrupt Stat Reg */
-#define DUIER     (*(portb) (MBASE+0x0715)) /* DUART Interrupt Enb Reg  */
-
-#define DUMR1B    (*(portb) (MBASE+0x0718)) /* DUART Mode Reg 1B        */
-#define DUSRB     (*(portb) (MBASE+0x0719)) /* DUART Status Reg B       */
-#define DUCSRB    (*(portb) (MBASE+0x0719)) /* DUART Clock Sel Reg B    */
-#define DUCRB     (*(portb) (MBASE+0x071A)) /* DUART Command Reg B      */
-#define DURBB     (*(portb) (MBASE+0x071B)) /* DUART Receiver Buffer B  */
-#define DUTBB     (*(portb) (MBASE+0x071B)) /* DUART Transmitter Buff B */
-#define DUIP      (*(portb) (MBASE+0x071D)) /* DUART Input Port Reg     */
-#define DUOPCR    (*(portb) (MBASE+0x071D)) /* DUART Outp Port Cnt Reg  */
-#define DUOPBS    (*(portb) (MBASE+0x071E)) /* DUART Outp Port Bit Set  */
-#define DUOPBR    (*(portb) (MBASE+0x071F)) /* DUART Outp Port Bit Rst  */
-#define DUMR2A    (*(portb) (MBASE+0x0720)) /* DUART Mode Reg 2A        */
-#define DUMR2B    (*(portb) (MBASE+0x0721)) /* DUART Mode Reg 2B        */
-
-/* Dual Timer Module */
-
-#define TMCR1    (*(portw) (MBASE+0x0600)) /* Timer Module Config Reg 1 */
-#define TIR1     (*(portw) (MBASE+0x0604)) /* Timer Interrupt Reg 1     */
-#define TCR1     (*(portw) (MBASE+0x0606)) /* Timer Control Reg 1       */
-#define TSR1     (*(portw) (MBASE+0x0608)) /* Timer Status Reg 1        */
-#define TCNTR1   (*(portw) (MBASE+0x060A)) /* Timer Counter Reg 1       */
-#define WPREL11  (*(portw) (MBASE+0x060C)) /* Timer Preload 1 Reg 1     */
-#define WPREL21  (*(portw) (MBASE+0x060E)) /* Timer Preload 2 Reg 1     */
-#define TCOM1    (*(portw) (MBASE+0x0610)) /* Timer Compare Reg 1       */
-
-#define TMCR2    (*(portw) (MBASE+0x0640)) /* Timer Module Config Reg 2 */
-#define TIR2     (*(portw) (MBASE+0x0644)) /* Timer Interrupt Reg 2     */
-#define TCR2     (*(portw) (MBASE+0x0646)) /* Timer Control Reg 2       */
-#define TSR2     (*(portw) (MBASE+0x0648)) /* Timer Status Reg 2        */
-#define TCNTR2   (*(portw) (MBASE+0x064A)) /* Timer Counter Reg 2       */
-#define WPREL12  (*(portw) (MBASE+0x064C)) /* Timer Preload 1 Reg 2     */
-#define WPREL22  (*(portw) (MBASE+0x064E)) /* Timer Preload 2 Reg 2     */
-#define TCOM2    (*(portw) (MBASE+0x0650)) /* Timer Compare Reg 2       */
diff --git a/c/src/lib/libbsp/m68k/gen68340/include/m68340.inc b/c/src/lib/libbsp/m68k/gen68340/include/m68340.inc
deleted file mode 100644
index 5c1ba36799..0000000000
--- a/c/src/lib/libbsp/m68k/gen68340/include/m68340.inc
+++ /dev/null
@@ -1,148 +0,0 @@
-/*----------------------------------------------------------------------------
-* file name: M68340.INC 				JC RAHUEL CNET/DSM/TAM/CAT
-* 
-* MC68340 BCC  Board Support Package
-*
-* date: 1/12/1993					
-*
-* Copyright 1989, Ready Systems FRANCE
-*
-* Supports: VRTX32 and RTscope
-*
-* Related Board: MOTOROLA BCC M68340
-*
-* Description:	EQUATES FOR 68340 DEVICES
-*
-* Changes:
-*	- Geoffroy Montel (g_montel@yahoo.com) :
-*	  changed EQU syntax for GNU as
-*
-*----------------------------------------------------------------------------*/
-
-/************************************************
- * ATTENTION: must match defs. in C header file *
- ************************************************/
-
-/* -- SIM equates --    system integration module */
-.equ BASE_REG, 0x3FF00	
-.equ BASE_SIM, 0xEFFFF000
-.equ SIM_MCR, 0x000	/* module configuration register */	
-.equ SIM_SYNCR, 0x004	/* clock synthesizer control register */	
-.equ SIM_AVR, 0x006	/* autovector register */	
-.equ SIM_RSR, 0x007	/* reset status register */	
-
-/* -- Port A -- */
-.equ SIM_PORTA, 0x011	/* port A data */	
-.equ SIM_DDRA, 0x013	/* port A direction data */	
-.equ SIM_PPRA1, 0x015	/* Port A pin assignement 1 */	
-.equ SIM_PPRA2, 0x017	/* Port A pin assignement 2 */ 	
-
-/* -- Port B -- */
-.equ SIM_PORTB, 0x019	/* port B data */	
-.equ SIM_PORTB1, 0x01B	/* port B data auxiliary */	
-.equ SIM_DDRB, 0x01D	/* port B direction data */	
-.equ SIM_PPRB, 0x01F	/* Port B pin assignement */
-.equ SIM_SWIV, 0x020	/* SW interrupt vector */	
-.equ SIM_SYPCR, 0x021	/* System protection control register */	
-.equ SIM_PICR, 0x022	/* Periodic interrupt control register */	
-.equ SIM_PITR, 0x024	/* Periodic interrupt timing register */	
-.equ SIM_SWSR, 0x027	/* Sofware service */	
-
-/* -- Chip select -- */
-.equ SIM_MASKH0, 0x040	/* mask register CS0 */	
-.equ SIM_MASKL0, 0x042	/* mask register CS0 */	
-.equ SIM_ADDRH0, 0x044	/* base address CS0 */	
-.equ SIM_ADDRL0, 0x046	/* base address CS0 */	
-.equ SIM_MASKH1, 0x048	/* mask register CS1 */	
-.equ SIM_MASKL1, 0x04A	/* mask register CS1 */	
-.equ SIM_ADDRH1, 0x04C	/* base address CS1 */	
-.equ SIM_ADDRL1, 0x04E	/* base address CS1 */	
-.equ SIM_MASKH2, 0x050	/* mask register CS2 */	
-.equ SIM_MASKL2, 0x052	/* mask register CS2 */	
-.equ SIM_ADDRH2, 0x054	/* base address CS2 */	
-.equ SIM_ADDRL2, 0x056	/* base address CS2 */	
-.equ SIM_MASKH3, 0x058	/* mask register CS3 */	
-.equ SIM_MASKL3, 0x05A	/* mask register CS3 */	
-.equ SIM_ADDRH3, 0x05C	/* base address CS3 */	
-.equ SIM_ADDRL3, 0x05E	/* base address CS3 */	
-
-/* -- TIMERS  equates -- */
-
-/* __ TIMER 0 */
-.equ TIM_MCR0, 0x600	/* Module configuration register */
-.equ TIM_IR0, 0x604	/* interrupt register */
-.equ TIM_CR0, 0x606	/* controle register */
-.equ TIM_SR0, 0x608	/* Status/prescaler register */
-.equ TIM_CNTR0, 0x60A	/* counter register */
-.equ TIM_PREL10, 0x60C	/* Preload register 1 */
-.equ TIM_PREL20, 0x60E	/* Preload register 2 */
-.equ TIM_COM0, 0x610	/* Compare register */
-
-/* __ TIMER 1 */
-
-.equ TIM_MCR1, 0x640	/* Module configuration register */
-.equ TIM_IR1, 0x644	/* interrupt register */
-.equ TIM_CR1, 0x646	/* controle register */
-.equ TIM_SR1, 0x648	/* Status/prescaler register */
-.equ TIM_CNTR1, 0x64A	/* counter register */	
-.equ TIM_PREL11, 0x64C	/* Preload register 1 */	
-.equ TIM_PREL21, 0x64E	/* Preload register 2 */	
-.equ TIM_COM1, 0x650	/* Compare register */	
-
-/* -- U.A.R.T.  equates -- */
-
-.equ UA_MCRH, 0x700	/* module configuration register */	
-.equ UA_MCRL, 0x701	/* module configuration register */	
-.equ UA_ILR, 0x704	/* Interrupt level */	
-.equ UA_IVR, 0x705	/* Interrupt vector */	
-.equ UA_MR1A, 0x710	/* Mode register 1 A */ 
-.equ UA_MR2A, 0x720	/* Mode register 2 A*/ 	
-.equ UA_CSRA, 0x711	/* Clock_select register A */	
-.equ UA_SRA, 0x711	/* status register A */	
-.equ UA_CRA, 0x712	/* command register A */	
-.equ UA_RBA, 0x713	/* receive buffer A */	
-.equ UA_TBA, 0x713	/* transmit buffer A */	
-.equ UA_IPCR, 0x714	/* input port change register */	
-.equ UA_ACR, 0x714	/* auxiliary control register */	
-.equ UA_ISR, 0x715	/* interrupt status register */	
-.equ UA_IER, 0x715	/* interrupt enable register */	
-.equ UA_MR1B, 0x718	/* Mode register 1 B */
-.equ UA_MR2B, 0x721	/* Mode register  2 B */
-.equ UA_CSRB, 0x719	/* Clock_select register B */
-.equ UA_SRB, 0x719	/* status register B */
-.equ UA_CRB, 0x71A	/* command register A */
-.equ UA_RBB, 0x71B	/* receive buffer A */
-.equ UA_TBB, 0x71B	/* transmit buffer A */
-.equ UA_IP, 0x71D	/* Input port register */
-.equ UA_OPCR, 0x71D	/* output port control register */	
-.equ UA_OPS, 0x71E	/* output port bit set */	
-.equ UA_OPR, 0x71F	/* output port bit reset */
-.equ TX_A_EN, 0x01	/* Tx A irq enable */
-.equ TX_B_EN, 0x10	/* Tx B irq enable */
-.equ TX_A_DIS, 0xFE	/* Tx A irq enable */
-.equ TX_B_DIS, 0xEF	/* Tx B irq enable */
-.equ TX_AB_DIS, 0x22
-	
-/* -- DMA equates -- */
-.equ DMA_MCR0, 0x780	/* module configuration register */	
-.equ DMA_IR0, 0x784	/* Interrupt register */	
-.equ DMA_CCR0, 0x788	/* Channel control register */	
-.equ DMA_CSR0, 0x78A	/* Channel status register */	
-.equ DMA_FCR0, 0x78B	/* Function code register */	
-.equ DMA_SARH0, 0x78C	/* Source adresse register */	
-.equ DMA_SARL0, 0x78E	/* Source adresse register */	
-.equ DMA_DARH0, 0x790	/* destination adresse register */	
-.equ DMA_DARL0, 0x792	/* destination adresse register */	
-.equ DMA_BTCH0, 0x794	/* byte transfer register */	
-.equ DMA_BTCL0, 0x796	/* byte transfer register */	
-.equ DMA_MCR1, 0x7A0	/* module configuration register */
-.equ DMA_IR1, 0x7A4	/* Interrupt register */	
-.equ DMA_CCR1, 0x7A8	/* Channel control register */	
-.equ DMA_CSR1, 0x7AA	/* Channel status register */	
-.equ DMA_FCR1, 0x7AB	/* Function code register */	
-.equ DMA_SARH1, 0x7AC	/* Source adresse register */	
-.equ DMA_SARL1, 0x7AE	/* Source adresse register */	
-.equ DMA_DARH1, 0x7B0	/* destination adresse register */	
-.equ DMA_DARL1, 0x7B2	/* destination adresse register */	
-.equ DMA_BTCH1, 0x7B4	/* byte transfer register */	
-.equ DMA_BTCL1, 0x7B6	/* byte transfer register */	
diff --git a/c/src/lib/libbsp/m68k/gen68340/include/m68349.inc b/c/src/lib/libbsp/m68k/gen68340/include/m68349.inc
deleted file mode 100644
index 4e3ce53d29..0000000000
--- a/c/src/lib/libbsp/m68k/gen68340/include/m68349.inc
+++ /dev/null
@@ -1,410 +0,0 @@
-/*----------------------------------------------------------------------------
- * file name: M68349.INC 				P. CADIC CNET/DSM/TAM/CAT
- *
- * MC68349 BCC  Board Support Package
- *
- * date: 31/07/97
- *
- * Description:	EQUATES FOR 68349 DEVICES
- *
- * Modifications:
- * 	- adapted for GNU CC by G.Montel 26/05/98
- *----------------------------------------------------------------------------*/
-
-| -- SIM equates --                   
-
-.equ	BASE_REG, 0x3FF00
-.equ	BASE_SIM, 0xEFFFF000		| pour correction du bug 68349 sur IACK
-
-.equ	SIM_MCR, 0x000    		| module configuration register
-.equ	SIM_IDR, 0x002    		| processor identification register
-.equ	SIM_SYNCR, 0x004    		| clock synthesizer control register
-.equ	SIM_AVR, 0x006    		| autovector register
-.equ	SIM_RSR, 0x007    		| reset status register
-
-| -- Port A
-.equ	SIM_PORTA, 0x011    		| port A data
-.equ	SIM_DDRA, 0x013    		| port A direction data
-.equ	SIM_PPRA1, 0x015    		| Port A pin assignement 1
-.equ	SIM_PPRA2, 0x017    		| Port A pin assignement 2
-
-| -- Port B
-.equ	SIM_PORTB, 0x019    		| port B data
-.equ	SIM_PORTB1, 0x01B    		| port B data auxiliary
-.equ	SIM_DDRB, 0x01D    		| port B direction data
-.equ	SIM_PPRB, 0x01F    		| Port B pin assignement
-
-.equ	SIM_SWIV, 0x020    | SW interrupt vector
-.equ	SIM_SYPCR, 0x021    | System protection control register
-.equ	SIM_PICR, 0x022    | Periodic interrupt control register
-.equ	SIM_PITR, 0x024    | Periodic interrupt timing register
-.equ	SIM_SWSR, 0x027    | Sofware service
-
-| -- Chip select
-.equ	SIM_MASKH0, 0x040    | mask register CS0
-.equ	SIM_MASKL0, 0x042    | mask register CS0
-.equ	SIM_ADDRH0, 0x044    | base address CS0
-.equ	SIM_ADDRL0, 0x046    | base address CS0
-
-.equ	SIM_MASKH1, 0x048    | mask register CS1
-.equ	SIM_MASKL1, 0x04A    | mask register CS1
-.equ	SIM_ADDRH1, 0x04C    | base address CS1
-.equ	SIM_ADDRL1, 0x04E    | base address CS1
-
-.equ	SIM_MASKH2, 0x050    | mask register CS2
-.equ	SIM_MASKL2, 0x052    | mask register CS2
-.equ	SIM_ADDRH2, 0x054    | base address CS2
-.equ	SIM_ADDRL2, 0x056    | base address CS2
-
-.equ	SIM_MASKH3, 0x058    | mask register CS3
-.equ	SIM_MASKL3, 0x05A    | mask register CS3
-.equ	SIM_ADDRH3, 0x05C    | base address CS3
-.equ	SIM_ADDRL3, 0x05E    | base address CS3
-
-| -- TIMERS  equates --
-
-| __ TIMER 0
-
-.equ	TIM_MCR0, 0x600    | Module configuration register
-.equ	TIM_IR0, 0x604    | interrupt register
-.equ	TIM_CR0, 0x606    | controle register
-.equ	TIM_SR0, 0x608    | Status/prescaler register
-.equ	TIM_CNTR0, 0x60A    | counter register
-.equ	TIM_PREL10, 0x60C    | Preload register 1
-.equ	TIM_PREL20, 0x60E    | Preload register 2
-.equ	TIM_COM0, 0x610    | Compare register
-
-| __ TIMER 1
-
-.equ	TIM_MCR1, 0x640    | Module configuration register
-.equ	TIM_IR1, 0x644    | interrupt register
-.equ	TIM_CR1, 0x646    | controle register
-.equ	TIM_SR1, 0x648    | Status/prescaler register
-.equ	TIM_CNTR1, 0x64A    | counter register
-.equ	TIM_PREL11, 0x64C    | Preload register 1
-.equ	TIM_PREL21, 0x64E    | Preload register 2
-.equ	TIM_COM1, 0x650    | Compare register
-
-| -- U.A.R.T.  equates --
-
-.equ	UA_MCRH, 0x700    | module configuration register
-.equ	UA_MCRL, 0x701    | module configuration register
-.equ	UA_ILR, 0x704    | Interrupt level
-.equ	UA_IVR, 0x705    | Interrupt vector
-
-.equ	UA_MR1A, 0x710    | Mode register 1 A
-.equ	UA_MR2A, 0x720    | Mode register 2 A
-.equ	UA_CSRA, 0x711    | Clock_select regiter A
-.equ	UA_SRA, 0x711    | status register A
-.equ	UA_CRA, 0x712    | command register A
-.equ	UA_RBA, 0x713    | receive buffer A
-.equ	UA_TBA, 0x713    | transmit buffer A
-
-.equ	UA_IPCR, 0x714    | input port change register
-.equ	UA_ACR, 0x714    | auxiliary control register
-.equ	UA_ISR, 0x715    | interrupt status register
-.equ	UA_IER, 0x715    | interrupt enable register
-
-.equ	UA_MR1B, 0x718    | Mode register 1 B
-.equ	UA_MR2B, 0x721    | Mode register 2 B
-.equ	UA_CSRB, 0x719    | Clock_select regiter B
-.equ	UA_SRB, 0x719    | status register B
-.equ	UA_CRB, 0x71A    | command register A
-.equ	UA_RBB, 0x71B    | receive buffer A
-.equ	UA_TBB, 0x71B    | transmit buffer A
-
-.equ	UA_IP, 0x71D    | Input port register
-.equ	UA_OPCR, 0x71D    | output port control register
-.equ	UA_OPS, 0x71E    | output port bit set
-.equ	UA_OPR, 0x71F    | output port bit reset
-.equ	TX_A_EN, 0x01     | Tx A irq enable
-.equ	TX_B_EN, 0x10     | Tx B irq enable
-.equ	TX_A_DIS, 0xFE     | Tx A irq enable
-.equ	TX_B_DIS, 0xEF     | Tx B irq enable
-.equ	TX_AB_DIS, 0x22
-
-
-| -- DMA equates
-.equ	DMA_MCR0, 0x780    | module configuration register
-.equ	DMA_IR0, 0x784    | Interrupt register
-.equ	DMA_CCR0, 0x788    | Channel control register
-.equ	DMA_CSR0, 0x78A    | Channel status register
-.equ	DMA_FCR0, 0x78B    | Function code register
-.equ	DMA_SARH0, 0x78C    | Source adresse register
-.equ	DMA_SARL0, 0x78E    | Source adresse register
-.equ	DMA_DARH0, 0x790    | destination adresse register
-.equ	DMA_DARL0, 0x792    | destination adresse register
-.equ	DMA_BTCH0, 0x794    | byte transfer register
-.equ	DMA_BTCL0, 0x796    | byte transfer register
-
-.equ	DMA_MCR1, 0x7A0    | module configuration register
-.equ	DMA_IR1, 0x7A4    | Interrupt register
-.equ	DMA_CCR1, 0x7A8    | Channel control register
-.equ	DMA_CSR1, 0x7AA    | Channel status register
-.equ	DMA_FCR1, 0x7AB    | Function code register
-.equ	DMA_SARH1, 0x7AC    | Source adresse register
-.equ	DMA_SARL1, 0x7AE    | Source adresse register
-.equ	DMA_DARH1, 0x7B0    | destination adresse register
-.equ	DMA_DARL1, 0x7B2    | destination adresse register
-.equ	DMA_BTCH1, 0x7B4    | byte transfer register
-.equ	DMA_BTCL1, 0x7B6    | byte transfer register
-
-| -- cache equates
-.equ	CACHE_MCR, 0xFC0	| cache config reg. (long)
-
-| -- quad data memory module (QDMM) equates
-.equ	QDMM_MCR, 0xC00		| QDMM config reg (long)
-.equ	QDMM_QBAR0, 0xC10	| QDMM base 0 (long)
-.equ	QDMM_QBAR1, 0xC14	| QDMM base 1 (long)
-.equ	QDMM_QBAR2, 0xC18	| QDMM base 2 (long)
-.equ	QDMM_QBAR3, 0xC1C	| QDMM base 3 (long)
-
-
-
-|-----------------------------------------------------
-| AST68349 internal registers
-|-----------------------------------------------------
-.equ	EPLD_SPACE, 3				| "reserved user" space
-.equ	CPU_SPACE, 7				| "CPU" space
-
-||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
-| GLUE EPLD
-||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
-
-.equ	GLUE_EPLD, 0xB0000000
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| configuration of /CS0 :
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		|ena|val|wid| ws|b31|b30|b29|b28|
-| 		+---+---+---+---+---+---+---+---+
-|
-| b[31..28] : base address for decoding /CS[3..0]
-|  the decoding is as follow :
-|
-|  +----------+------------+------+
-|	| a[31..28] | a[27..26]	| /CS  |
-|	+-----------+-----------+------+
-|	| b[31..28] |    00		| /CS0 |	each /CS decodes 64 Mbytes
-|	| b[31..28] |    01		| /CS1 |
-|	| b[31..28] |    10		| /CS2 |
-|	| b[31..28] |    11		| /CS3 |
-|	+-----------------------+------+
-|
-| after /RESET, /CS0 is validated for every cycle, until programmed
-|
-| ws : number of wait-states : 0 => 0 ws
-|                              1 => external /dsackx
-| wid : width of chip-select : 0 => 16 bits
-|                              1 => 32 bits
-| ena : enable chip-select   : 0 => disabled
-|                              1 => enabled
-|
-| val : automatic validation. set after reset
-| cleared when /CS0 is configured
-|
-.equ	REG_CS0, 0
-
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| configuration of /CS1 to /CS3:
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		|ena| x |wid| ws| x | x | x | x |
-| 		+---+---+---+---+---+---+---+---+
-|
-| ws : number of wait-states : 0 => 0 ws
-|                              1 => external /dsackx
-| wid : width of chip-select : 0 => 16 bits
-|                              1 => 32 bits
-| ena : enable chip-select   : 0 => disabled
-|                              1 => enabled
-.equ	REG_CS1, 1
-.equ	REG_CS2, 2
-.equ	REG_CS3, 3
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| I2C register
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+----+
-| 		| x | x | x | x | x | x |clk|data|
-| 		+---+---+---+---+---+---+---+----+
-| bidirecionnal pin, open drain output.
-| set bit to 1 to read external state of pin
-|
-.equ	REG_I2C, 4
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| PDCS register
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		|s12|s11|s14|pd5|pd4|pd3|pd2|pd1|
-| 		+---+---+---+---+---+---+---+---+
-| pd[5..1] : value read on the DRAM module
-| S12, S11 and S14 : "user reserved" configuration switch
-|
-.equ	REG_PDCS, 5
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| timer1 register
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		|ena| x | x | x | x | x | d1| d0|
-| 		+---+---+---+---+---+---+---+---+
-|
-| the timer clock is the 1000Hz clock of the ASTECC platform
-| the timer is reloaded on each write to the register, or if the input
-| TIN1 is set to 0.
-| on overflow, the open drain output TOUT1 is set to 0
-| the timer must be disabled to return TOUT1 to the inactive state
-|
-.equ	REG_TIMER1, 6
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| timer2 register
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		|ena| x | x | x | x | x | d1| d0|
-| 		+---+---+---+---+---+---+---+---+
-| the timer clock is the 1000Hz clock of the ASTECC platform
-| the timer is reloaded on each write to the register, or if the input
-| TIN2 is set to 0.
-| on overflow, the open drain output TOUT2 is set to 0
-| the timer must be disabled to return TOUT2 to the inactive state
-|
-.equ	REG_TIMER2, 7
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| baudrate generator register
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		| x | x | x | x | x | d2| d1| d0|
-| 		+---+---+---+---+---+---+---+---+
-|
-| d[2..0] : divider of a 3.6864 Mhz clock
-|
-| d[2..0]    :     0      1       2       3      4      5      6      7
-| divides by :     2      4       6       8     10     12     14     16
-| SCLK (Mhz) :  1.8432  0.9216  0.6144  0.4608   x    0.3072   x    0.2304
-| baudrate   :  115200   57600  38400    28800   x     19200   x     14400
-|
-.equ	REG_BAUDRATE, 8
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| IO register
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		| x | x | x |io4|io3|io2|io1|io0|
-| 		+---+---+---+---+---+---+---+---+
-|
-| io[4..0] : data written to port
-|
-| maximum current load is about 5 mA per pin
-|
-.equ	REG_IO, 9
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| IO port
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		| x | x | x |io4|io3|io2|io1|io0|
-| 		+---+---+---+---+---+---+---+---+
-|
-| io[4..0] : data read from port
-|
-.equ	REG_IO_PORT, 10
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| IO direction register
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		| x | x | x | x | x |dr2|dr1|dr0|
-| 		+---+---+---+---+---+---+---+---+
-|
-| dr0 : 0 => io port 0 is configured as input (default after /RESET)
-|       1 => io port 0 is configured as output
-|
-| dr1 : 0 => io port 1 is configured as input (default after /RESET)
-|       1 => io port 1 is configured as output
-|
-| dr2 : 0 => io ports 2 to 4 are configured as input (default after /RESET)
-|       1 => io ports 2 to 4 are configured as output
-|
-.equ	REG_DIR_IO, 11
-
-
-
-
-||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
-| DRAM EPLD
-||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
-
-.equ	DRAM_EPLD, 0xA0000000
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| number of wait-state for DRAM
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		| x | x | x | x | x | x |ws1|ws0|
-| 		+---+---+---+---+---+---+---+---+
-|
-| ws[1..0]    : 0   1   2   3
-| wait states : 0   1   2   3
-|
-.equ	REG_WS, 0
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| configuration of refresh for DRAM
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		|ena| x | x | x | x | x |rf1|rf0|
-| 		+---+---+---+---+---+---+---+---+
-|
-|	rf[1..0] :  0   1    2    3
-|	refresh  : 5µs 10µs 15µs 20µs
-|
-| ena == 0 : refresh disabled
-| ena == 1 : refresh enabled
-|
-.equ	REG_REFRESH, 1
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| configuration of DRAM module size
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		| x | x | x | x | x |sz2|sz1|sz0|
-| 		+---+---+---+---+---+---+---+---+
-|
-|  sz[2..0]     : 0   1   2   3   4    5   6   7
-|  size (Mbytes): 4   8   16  32  64  128  0   0
-|
-.equ	REG_CONFIG, 2
-
-|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-| bus width of /CS0 during reset		bw[1..0]  : 0   1   2       3
-|                                   bus width : 32  16  8   ext. /dsackx
-|
-| state of CS_SWITCH  : sel == 0 => CPU chip_selects  (/CS[3..0])
-|                     : sel == 1 => EPLD chip_selects (/CS[3..0])
-|
-|		  7   6   5   4   3   2   1   0
-| 		+---+---+---+---+---+---+---+---+
-| 		|bw1|bw0| x | x | x | x | x |sel|
-| 		+---+---+---+---+---+---+---+---+
-|
-.equ	REG_BUSWIDTH, 3
-
diff --git a/c/src/lib/libbsp/m68k/gen68340/include/tm27.h b/c/src/lib/libbsp/m68k/gen68340/include/tm27.h
deleted file mode 100644
index 0dfa7bf628..0000000000
--- a/c/src/lib/libbsp/m68k/gen68340/include/tm27.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <rtems/tm27-default.h>