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author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2011-02-11 12:30:00 +0000 |
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committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2011-02-11 12:30:00 +0000 |
commit | 3bb06c067131a915e247917079e44c764f7c2877 (patch) | |
tree | 7920ef3841344a616ca5bf4862ff79b18b34a150 /c/src/lib/libbsp/m68k/av5282/startup/bspstart.c | |
parent | 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org> (diff) | |
download | rtems-3bb06c067131a915e247917079e44c764f7c2877.tar.bz2 |
2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>
* startup/bspstart.c, startup/init5282.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
Diffstat (limited to '')
-rw-r--r-- | c/src/lib/libbsp/m68k/av5282/startup/bspstart.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c b/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c index ec48ebd1ab..cf2fb7fef4 100644 --- a/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c @@ -35,8 +35,8 @@ /* * CPU-space access */ -#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) -#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) +#define m68k_set_acr0(_acr0) __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0)) +#define m68k_set_acr1(_acr1) __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1)) /* * Read/write copy of common cache @@ -94,7 +94,7 @@ void _CPU_cache_invalidate_1_instruction_line(const void *addr) * Top half of cache is I-space */ addr = (void *)((int)addr | 0x400); - asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); } void _CPU_cache_enable_data(void) @@ -129,7 +129,7 @@ void _CPU_cache_invalidate_1_data_line(const void *addr) * Bottom half of cache is D-space */ addr = (void *)((int)addr & ~0x400); - asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); + __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); } /* |