2011-08-01 Jennifer Averett <Jennifer.Averett@OARcorp.com>

	PR 1802
	* shared/irq/irq_asm.S, shared/irq/irq_init.c, shared/smp/smp-imps.c,
	shared/smp/smp-imps.h: Add SMP support for i386.
	* shared/smp/getcpuid.c: New file.

2 files changed, 54 insertions, 50 deletions

diff --git a/c/src/lib/libbsp/i386/shared/irq/irq_asm.S b/c/src/lib/libbsp/i386/shared/irq/irq_asm.S
index edd7cea6cb..e644e7587c 100644
--- a/c/src/lib/libbsp/i386/shared/irq/irq_asm.S
+++ b/c/src/lib/libbsp/i386/shared/irq/irq_asm.S
@@ -32,7 +32,7 @@
 #define EBP_OFF 12       /* code restoring ebp/esp relies on */
 #define ESP_OFF 16       /* esp being on top of ebp!         */
 #ifdef __SSE__
-/* need to be on 16 byte boundary for SSE */
+/* need to be on 16 byte boundary for SSE, add 12 to do that */
 #define FRM_SIZ (20+12+512)
 #define SSE_OFF 32
 #else
@@ -46,17 +46,9 @@ SYM (_ISR_Handler):
 	 *  Before this was point is reached the vectors unique
 	 *  entry point did the following:
 	 *
-	 *     1. saved scratch registers registers eax edx ecx"
+	 *     1. saved scratch registers registers eax edx ecx
 	 *     2. put the vector number in ecx.
 	 *
-	 * BEGINNING OF ESTABLISH SEGMENTS
-	 *
-	 *  WARNING: If an interrupt can occur when the segments are
-	 *           not correct, then this is where we should establish
-	 *           the segments.  In addition to establishing the
-	 *           segments, it may be necessary to establish a stack
-	 *           in the current data area on the outermost interrupt.
-	 *
 	 *  NOTE:  If the previous values of the segment registers are
 	 *         pushed, do not forget to adjust SAVED_REGS.
 	 *
@@ -104,9 +96,48 @@ SYM (_ISR_Handler):
 	ldmxcsr ARG_OFF(esp)            /* clean-slate MXCSR              */
 #endif
 
+.check_stack_switch:
+	movl      esp, ebp                  /* ebp = previous stack pointer */
+#if defined(RTEMS_SMP) && defined(BSP_HAS_SMP)
+	movl     $SYM(_Per_CPU_Information_p), ebx
+	call     SYM(bsp_smp_processor_id)
+	mov      (ebx,eax,4), ebx
+        pushl    ecx
+        call     SYM(_ISR_SMP_Enter)
+        popl     ecx
+        cmpl     $0, eax
+        jne      .i8259
+        movl     PER_CPU_INTERRUPT_STACK_HIGH(ebx), esp
+       
+#else
+	movl     $SYM(_Per_CPU_Information), ebx
+
+	/*
+         *  Is this the outermost interrupt?
+	 *  Switch stacks if necessary
+	 */
+	cmpl      $0, PER_CPU_ISR_NEST_LEVEL(ebx)
+	jne       nested                    /* No, then continue */
+	movl      PER_CPU_INTERRUPT_STACK_HIGH(ebx), esp
+
+	/*
+	 *  We want to insure that the old stack pointer is in ebp
+	 *  By saving it on every interrupt, all we have to do is
+	 *  movl ebp->esp near the end of every interrupt.
+	 */
+
+nested:
+	incl      PER_CPU_ISR_NEST_LEVEL(ebx)  /* one nest level deeper */
+	incl      SYM (_Thread_Dispatch_disable_level) /* disable multitasking */
+#endif
+        /*
+         *  i8259 Management
+         */
+
+.i8259:
         /* Do not disable any 8259 interrupts if this isn't from one */
 	cmp       ecx, 16               /* is this a PIC IRQ? */
-	jge       .check_stack_switch
+	jge       .end_of_i8259
 
 	/*
 	 * acknowledge the interrupt
@@ -136,44 +167,7 @@ SYM (_ISR_Handler):
 	outb      $PIC_SLAVE_COMMAND_IO_PORT
 .master:
 	outb      $PIC_MASTER_COMMAND_IO_PORT
-
-	/*
-	 *  Now switch stacks if necessary
-	 */
-
-PUBLIC (ISR_STOP)
-ISR_STOP:
-.check_stack_switch:
-	movl      esp, ebp                  /* ebp = previous stack pointer */
-#if defined(RTEMS_SMP) && defined(BSP_HAS_SMP)
-	movl     $SYM(_Per_CPU_Information_p), ebx
-	call     SYM(bsp_smp_processor_id)
-	mov      (ebx,eax,4), ebx
-#else
-	movl     $SYM(_Per_CPU_Information), ebx
-#endif
-
-	/* is this the outermost interrupt? */
-	cmpl      $0, PER_CPU_ISR_NEST_LEVEL(ebx)
-	jne       nested                    /* No, then continue */
-	movl      PER_CPU_INTERRUPT_STACK_HIGH(ebx), esp
-
-	/*
-	 *  We want to insure that the old stack pointer is in ebp
-	 *  By saving it on every interrupt, all we have to do is
-	 *  movl ebp->esp near the end of every interrupt.
-	 */
-
-nested:
-	incl      PER_CPU_ISR_NEST_LEVEL(ebx)  /* one nest level deeper */
-	incl      SYM (_Thread_Dispatch_disable_level) /* disable multitasking */
-
-        /*
-         * GCC versions starting with 4.3 no longer place the cld
-         * instruction before string operations.  We  need to ensure
-         * it is set correctly for ISR handlers.
-         */
-        cld
+.end_of_i8259:
 
 	/*
 	 * re-enable interrupts at processor level as the current
@@ -216,8 +210,14 @@ nested:
 	outb	  $PIC_MASTER_IMR_IO_PORT
 	movb	  ah, al
 	outb	  $PIC_SLAVE_IMR_IO_PORT
-
 .dont_restore_i8259:
+
+
+#if defined(RTEMS_SMP) && defined(BSP_HAS_SMP)
+        call    SYM(_ISR_SMP_Exit)
+	testl	eax, eax
+	je	.exit
+#else
 	decl      PER_CPU_ISR_NEST_LEVEL(ebx)  /* one less ISR nest level */
 	                                    /* If interrupts are nested, */
 	                                    /*   then dispatching is disabled */
@@ -231,6 +231,7 @@ nested:
 	                                    /* Is task switch necessary? */
 	jne       .schedule                 /* Yes, then call the scheduler */
 	jmp       .exit                     /* No, exit */
+#endif
 
 .schedule:
 	/*
diff --git a/c/src/lib/libbsp/i386/shared/irq/irq_init.c b/c/src/lib/libbsp/i386/shared/irq/irq_init.c
index 798d57a35b..b2b9b92a78 100644
--- a/c/src/lib/libbsp/i386/shared/irq/irq_init.c
+++ b/c/src/lib/libbsp/i386/shared/irq/irq_init.c
@@ -6,6 +6,9 @@
  *  Copyright (c) 2009 embedded brains GmbH
  *  CopyRight (C) 1998 valette@crf.canon.fr
  *
+ *  COPYRIGHT (c) 2011.
+ *  On-Line Applications Research Corporation (OAR).
+ *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.