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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1998-07-23 22:02:34 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1998-07-23 22:02:34 +0000 |
| commit | 67a2288991ce3662a588ee83c0bea9c9efae5f1e (patch) | |
| tree | a8d68b22bfd313619f2a0d0b2e3b4755b8278b9d /c/src/lib/libbsp/i386/shared/irq/irq_asm.h | |
| parent | Patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>: (diff) | |
| download | rtems-67a2288991ce3662a588ee83c0bea9c9efae5f1e.tar.bz2 | |
Patch from Eric VALETTE <valette@crf.canon.fr>:
Here is a enhanced version of my previous patch. This patch enables
to potentially share the new interrupt management code for all Intel targets
(pc386, go32 and force386) bsp.
Note : this patch is complete only for pc386. It still needs to
be completed for go32 and force386. I carrefully checked
that anything needed is in for force386 (only some function
name changes for IDT manipulation and GDT segment
manipulation). But anyway I will not be able to test any
of theses targets...
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libbsp/i386/shared/irq/irq_asm.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/i386/shared/irq/irq_asm.h b/c/src/lib/libbsp/i386/shared/irq/irq_asm.h new file mode 100644 index 0000000000..bf6bb17e8e --- /dev/null +++ b/c/src/lib/libbsp/i386/shared/irq/irq_asm.h @@ -0,0 +1,30 @@ +/* irq_asm.h + * + * This include file has defines to represent some contant used + * to program and manage the Intel 8259 interrupt controller + * + * + * COPYRIGHT (c) 1998 valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ +#ifndef __IRQ_ASM_H__ +#define __IRQ_ASM_H__ + +#define PC386_ASM_IRQ_VECTOR_BASE 0x20 + /* PIC's command and mask registers */ +#define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */ +#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 /* Slave PIC command register */ +#define PIC_MASTER_IMR_IO_PORT 0x21 /* Master PIC Interrupt Mask Register */ +#define PIC_SLAVE_IMR_IO_PORT 0xa1 /* Slave PIC Interrupt Mask Register */ + + /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */ +#define PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */ +#define PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */ + + +#endif |