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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2016-08-31 16:49:15 +0200
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2016-10-02 10:40:34 +0200
commit22cc80783b63df70332ebaf6db2ce8498b932450 (patch)
tree5f4932cd7b954c25ddcdcd0a7fddd5417fb99506 /c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c
parentarm/raspberrypi: use cache manager operations to flush/invalidate all cache l... (diff)
downloadrtems-22cc80783b63df70332ebaf6db2ce8498b932450.tar.bz2
arm/xilinx_zynq: ensure that cache is cleaned and MMU disabled when initialization starts.
The u-boot loader enables the MMU plus the data and instruction caches in some versions which results in RTEMS boot failure. Closes #2774.
Diffstat (limited to '')
-rw-r--r--c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c35
1 files changed, 35 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c
index 58f5ec63ff..5372380c24 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c
@@ -21,6 +21,41 @@
BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
{
+ uint32_t sctlr_val;
+
+ sctlr_val = arm_cp15_get_control();
+
+ /*
+ * Current U-boot loader seems to start kernel image
+ * with I and D caches on and MMU enabled.
+ * If RTEMS application image finds that cache is on
+ * during startup then disable caches.
+ */
+ if ( sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
+ if ( sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
+ /*
+ * If the data cache is on then ensure that it is clean
+ * before switching off to be extra carefull.
+ */
+ arm_cp15_data_cache_clean_all_levels();
+ }
+ arm_cp15_flush_prefetch_buffer();
+ sctlr_val &= ~ ( ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A );
+ arm_cp15_set_control( sctlr_val );
+ }
+ arm_cp15_instruction_cache_invalidate();
+ /*
+ * The care should be taken there that no shared levels
+ * are invalidated by secondary CPUs in SMP case.
+ * It is not problem on Zynq because level of coherency
+ * is L1 only and higher level is not maintained and seen
+ * by CP15. So no special care to limit levels on the secondary
+ * are required there.
+ */
+ arm_cp15_data_cache_invalidate_all_levels();
+ arm_cp15_branch_predictor_invalidate_all();
+ arm_cp15_tlb_invalidate();
+ arm_cp15_flush_prefetch_buffer();
arm_a9mpcore_start_hook_0();
}