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authorChris Johns <chrisj@rtems.org>2016-11-25 09:45:35 +1100
committerChris Johns <chrisj@rtems.org>2016-11-29 08:50:40 +1100
commit8fd465e67e5db00839e7b3a717a816d57b46f198 (patch)
tree6a513d7e9fce8c3a300c2b0860ad9ec6e5ef1275 /c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c
parentsparc: Optimize _ISR_Handler() (diff)
downloadrtems-8fd465e67e5db00839e7b3a717a816d57b46f198.tar.bz2
arm/zynq: Wait for the UART TX FIFO to empty on reset.
Diffstat (limited to '')
-rw-r--r--c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c b/c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c
index aa96eba375..f9a1cf91d5 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c
@@ -226,3 +226,16 @@ const console_fns zynq_uart_fns = {
.deviceSetAttributes = zynq_uart_set_attribues,
.deviceOutputUsesInterrupts = false
};
+
+void zynq_uart_reset_tx_flush(int minor)
+{
+ volatile zynq_uart *regs = zynq_uart_get_regs(minor);
+ int c = 4;
+
+ while (c-- > 0)
+ zynq_uart_write_polled(minor, '\r');
+
+ while ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_TEMPTY) == 0) {
+ /* Wait */
+ }
+}