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author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-07-03 17:26:50 +0200 |
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committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-10-02 10:40:33 +0200 |
commit | a114f99bd28cd534b1446d2d85ea681ef1832955 (patch) | |
tree | 44b9310939d888604b61e59ab1191436ab8f4ffb /c/src/lib/libbsp/arm/shared | |
parent | bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310. (diff) | |
download | rtems-a114f99bd28cd534b1446d2d85ea681ef1832955.tar.bz2 |
bsps/arm: Change code to explicit selection of cache implementation for ARM BSPs.
The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.
The ARM targets equipped by cache should include
appropriate implementation.
Next options are available for now
c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
basic ARM cache integrated on the CPU core directly
which requires only CP15 oparations
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
support for case where ARM L2C-310 cache controller
is used. It is accessible as mmaped peripheral.
c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
Cortex-M specific cache support
Updates #2782
Updates #2783
Diffstat (limited to 'c/src/lib/libbsp/arm/shared')
-rw-r--r-- | c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h | 134 |
1 files changed, 134 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h b/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h new file mode 100644 index 0000000000..bc19cb7cad --- /dev/null +++ b/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h @@ -0,0 +1,134 @@ +/** + * @file + * + * @ingroup arm + * + * @brief ARM cache defines and implementation. + */ + +/* + * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H +#define LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H + +#include <libcpu/arm-cp15.h> + +#define CPU_DATA_CACHE_ALIGNMENT 32 +#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 +#if defined(__ARM_ARCH_7A__) +/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */ +#define CPU_MAXIMAL_CACHE_ALIGNMENT 64 +#endif + +static inline void _CPU_cache_flush_1_data_line(const void *d_addr) +{ + arm_cp15_data_cache_clean_line(d_addr); +} + +static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr) +{ + arm_cp15_data_cache_invalidate_line(d_addr); +} + +static inline void _CPU_cache_freeze_data(void) +{ + /* TODO */ +} + +static inline void _CPU_cache_unfreeze_data(void) +{ + /* TODO */ +} + +static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) +{ + arm_cp15_instruction_cache_invalidate_line(d_addr); +} + +static inline void _CPU_cache_freeze_instruction(void) +{ + /* TODO */ +} + +static inline void _CPU_cache_unfreeze_instruction(void) +{ + /* TODO */ +} + +static inline void _CPU_cache_flush_entire_data(void) +{ + arm_cp15_data_cache_test_and_clean(); +} + +static inline void _CPU_cache_invalidate_entire_data(void) +{ + arm_cp15_data_cache_invalidate(); +} + +static inline void _CPU_cache_enable_data(void) +{ + rtems_interrupt_level level; + uint32_t ctrl; + + rtems_interrupt_disable(level); + ctrl = arm_cp15_get_control(); + ctrl |= ARM_CP15_CTRL_C; + arm_cp15_set_control(ctrl); + rtems_interrupt_enable(level); +} + +static inline void _CPU_cache_disable_data(void) +{ + rtems_interrupt_level level; + uint32_t ctrl; + + rtems_interrupt_disable(level); + arm_cp15_data_cache_test_and_clean_and_invalidate(); + ctrl = arm_cp15_get_control(); + ctrl &= ~ARM_CP15_CTRL_C; + arm_cp15_set_control(ctrl); + rtems_interrupt_enable(level); +} + +static inline void _CPU_cache_invalidate_entire_instruction(void) +{ + arm_cp15_instruction_cache_invalidate(); +} + +static inline void _CPU_cache_enable_instruction(void) +{ + rtems_interrupt_level level; + uint32_t ctrl; + + rtems_interrupt_disable(level); + ctrl = arm_cp15_get_control(); + ctrl |= ARM_CP15_CTRL_I; + arm_cp15_set_control(ctrl); + rtems_interrupt_enable(level); +} + +static inline void _CPU_cache_disable_instruction(void) +{ + rtems_interrupt_level level; + uint32_t ctrl; + + rtems_interrupt_disable(level); + ctrl = arm_cp15_get_control(); + ctrl &= ~ARM_CP15_CTRL_I; + arm_cp15_set_control(ctrl); + rtems_interrupt_enable(level); +} + +#endif /* LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H */ |