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| author | Martin Galvan <martin.galvan@tallertechnologies.com> | 2015-02-20 10:08:01 -0300 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-02-20 18:52:58 +0100 |
| commit | dc9aaf7ced34501d7647a86b4c626c9cc056db01 (patch) | |
| tree | 77107477e04d9849531480f68dd2fae5d8f0aa59 /c/src/lib/libbsp/arm/shared | |
| parent | IMFS: Fix copy on write for linfiles (diff) | |
| download | rtems-dc9aaf7ced34501d7647a86b4c626c9cc056db01.tar.bz2 | |
ARM: Support VFP-D16
This patch allows the existing FPU code to support both VFP-D16 and
VFP-D32. According to ARM, writes to D32DIS are ignored for D16 so
there's no need to enclose the bic instruction with an #ifdef. We tested
it on a TMS570LS3137 using TI initialization code and it works fine.
Signed-off by: Martin Galvan <martin.galvan@tallertechnologies.com>
Diffstat (limited to 'c/src/lib/libbsp/arm/shared')
| -rw-r--r-- | c/src/lib/libbsp/arm/shared/start/start.S | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/c/src/lib/libbsp/arm/shared/start/start.S b/c/src/lib/libbsp/arm/shared/start/start.S index 63b32501f5..f5f0fa4091 100644 --- a/c/src/lib/libbsp/arm/shared/start/start.S +++ b/c/src/lib/libbsp/arm/shared/start/start.S @@ -187,7 +187,7 @@ _start: /* Stay in SVC mode */ -#ifdef ARM_MULTILIB_VFP_D32 +#ifdef ARM_MULTILIB_VFP /* Read CPACR */ mrc p15, 0, r0, c1, c0, 2 @@ -195,7 +195,9 @@ _start: orr r0, r0, #(1 << 20) orr r0, r0, #(1 << 22) - /* Clear ASEDIS and D32DIS */ + /* + * Clear ASEDIS and D32DIS. Writes to D32DIS are ignored for VFP-D16. + */ bic r0, r0, #(3 << 30) /* Write CPACR */ @@ -205,7 +207,7 @@ _start: /* Enable FPU */ mov r0, #(1 << 30) vmsr FPEXC, r0 -#endif +#endif /* ARM_MULTILIB_VFP */ /* * Branch to start hook 0. |