arm/bsps: CP15 and basic cache support entire cache clean for more architecture variants now.

Next cache operations should work on most of cores now

  rtems_cache_flush_entire_data()
  rtems_cache_invalidate_entire_data()
  rtems_cache_invalidate_entire_instruction()

Instruction cache invalidate works on the first level for now only.
Data cacache operations are extended to ensure flush/invalidate
on all cache levels.

The CP15 arm_cp15_data_cache_clean_all_levels() function extended
to continue through unified levels too (ctype = 4).

Updates #2782
Updates #2783

2 files changed, 24 insertions, 4 deletions

diff --git a/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h b/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
index de5fddb5aa..31a69be1fb 100644
--- a/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
+++ b/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
@@ -49,11 +49,14 @@ _CPU_cache_flush_data_range(
 )
 {
   _ARM_Data_synchronization_barrier();
-  arm_cp15_drain_write_buffer();
   arm_cache_l1_flush_data_range(
     d_addr,
     n_bytes
   );
+  #if !defined(__ARM_ARCH_7A__)
+  arm_cp15_drain_write_buffer();
+  #endif
+ _ARM_Data_synchronization_barrier();
 }
 
 static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
@@ -92,6 +95,7 @@ static inline void
 _CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes)
 {
   arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes );
+  _ARM_Instruction_synchronization_barrier();
 }
 
 static inline void _CPU_cache_freeze_instruction(void)
@@ -106,12 +110,23 @@ static inline void _CPU_cache_unfreeze_instruction(void)
 
 static inline void _CPU_cache_flush_entire_data(void)
 {
-  arm_cp15_data_cache_test_and_clean();
+  _ARM_Data_synchronization_barrier();
+  #if defined(__ARM_ARCH_7A__)
+  arm_cp15_data_cache_clean_all_levels();
+  #else
+  arm_cp15_data_cache_clean_and_invalidate();
+  arm_cp15_drain_write_buffer();
+  #endif
+  _ARM_Data_synchronization_barrier();
 }
 
 static inline void _CPU_cache_invalidate_entire_data(void)
 {
+  #if defined(__ARM_ARCH_7A__)
+  arm_cp15_data_cache_invalidate_all_levels();
+  #else
   arm_cp15_data_cache_invalidate();
+  #endif
 }
 
 static inline void _CPU_cache_enable_data(void)
@@ -141,7 +156,8 @@ static inline void _CPU_cache_disable_data(void)
 
 static inline void _CPU_cache_invalidate_entire_instruction(void)
 {
-  arm_cp15_instruction_cache_invalidate();
+  arm_cache_l1_invalidate_entire_instruction();
+  _ARM_Instruction_synchronization_barrier();
 }
 
 static inline void _CPU_cache_enable_instruction(void)
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
index 74a65c5ac7..9caa2685bc 100644
--- a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
+++ b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
@@ -329,9 +329,13 @@ static inline void arm_cache_l1_invalidate_entire_instruction( void )
   arm_cp15_instruction_cache_invalidate();
   #endif /* RTEMS_SMP */
 
-  if ( ( ctrl & ARM_CP15_CTRL_Z ) == 0 ) {
+  if ( ( ctrl & ARM_CP15_CTRL_Z ) != 0 ) {
+    #if defined(__ARM_ARCH_7A__)
     arm_cp15_branch_predictor_inner_shareable_invalidate_all();
+    #endif
+    #if defined(__ARM_ARCH_6KZ__) || defined(__ARM_ARCH_7A__)
     arm_cp15_branch_predictor_invalidate_all();
+    #endif
   }
 }