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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-09-03 01:30:47 +0200 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-10-02 10:40:34 +0200 |
| commit | 00dfdd6b0837a21bd3acaab590d850653f79dfa7 (patch) | |
| tree | e745f510a29d5da29454a7c24dbad1cdc1f5a7bd /c/src/lib/libbsp/arm/shared | |
| parent | bsps/arm: use defines for cache type register format field. (diff) | |
| download | rtems-00dfdd6b0837a21bd3acaab590d850653f79dfa7.tar.bz2 | |
bsps/arm: remove lock in arm_cp15_set_translation_table_entries().
Protection by rtems_interrupt_disable() is incompatible with SMP build.
Actual page table entries manipulation function does not need locking
and disabling cache and can be run concurrently even on multiple
CPUs as long as changes do not modify same region. If the function
is called from more threads/CPUs to modify same region with different
mapping options concurrently then there is problem at another level
of virtual address space management and has to be solved by mutex
or other locking at that level.
Updates #2782
Updates #2783
Diffstat (limited to 'c/src/lib/libbsp/arm/shared')
| -rw-r--r-- | c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c b/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c index f65000959e..c2be0f566e 100644 --- a/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c +++ b/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c @@ -85,13 +85,5 @@ uint32_t arm_cp15_set_translation_table_entries( uint32_t section_flags ) { - rtems_interrupt_level level; - uint32_t section_flags_of_first_entry; - - rtems_interrupt_disable(level); - section_flags_of_first_entry = - set_translation_table_entries(begin, end, section_flags); - rtems_interrupt_enable(level); - - return section_flags_of_first_entry; + return set_translation_table_entries(begin, end, section_flags); } |