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| author | Kevin Kirspel <kevin-kirspel@idexx.com> | 2017-01-24 09:40:31 -0500 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-01-24 15:42:05 +0100 |
| commit | b43c2e895289b20f84fc0c86e25d16ba6e9be29f (patch) | |
| tree | 08edfe056ff9a2ff7f626d5eda7106ace3d365c8 /c/src/lib/libbsp/arm/shared/start/start.S | |
| parent | sptests/sprmsched01: Merge and fix (diff) | |
| download | rtems-b43c2e895289b20f84fc0c86e25d16ba6e9be29f.tar.bz2 | |
Adding ARM VFP V2 support
Diffstat (limited to '')
| -rwxr-xr-x[-rw-r--r--] | c/src/lib/libbsp/arm/shared/start/start.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/shared/start/start.S b/c/src/lib/libbsp/arm/shared/start/start.S index 7adcb443c2..c5263ece7b 100644..100755 --- a/c/src/lib/libbsp/arm/shared/start/start.S +++ b/c/src/lib/libbsp/arm/shared/start/start.S @@ -274,6 +274,7 @@ bsp_start_skip_hyp_svc_switch: /* Stay in SVC mode */ #ifdef ARM_MULTILIB_VFP +#ifdef ARM_MULTILIB_HAS_CPACR /* Read CPACR */ mrc p15, 0, r0, c1, c0, 2 @@ -289,6 +290,7 @@ bsp_start_skip_hyp_svc_switch: /* Write CPACR */ mcr p15, 0, r0, c1, c0, 2 isb +#endif /* Enable FPU */ mov r0, #(1 << 30) @@ -408,6 +410,7 @@ _start: #endif #ifdef ARM_MULTILIB_VFP +#ifdef ARM_MULTILIB_HAS_CPACR /* * Enable CP10 and CP11 coprocessors for privileged and user mode in * CPACR (bits 20-23). Ensure that write to register completes. @@ -418,6 +421,7 @@ _start: str r1, [r0] dsb isb +#endif #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION bl bsp_start_init_registers_vfp |