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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-05-31 13:59:47 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-05-31 15:20:33 +0200 |
| commit | db42c079a0479c17add94e5fb5fb89db1dfa6799 (patch) | |
| tree | 723eb41d04eddb021be998d57e8863806cc0d0a6 /c/src/lib/libbsp/arm/shared/start/start.S | |
| parent | smp: Add ARM support (diff) | |
| download | rtems-db42c079a0479c17add94e5fb5fb89db1dfa6799.tar.bz2 | |
bsps/arm: Add SMP support
Diffstat (limited to 'c/src/lib/libbsp/arm/shared/start/start.S')
| -rw-r--r-- | c/src/lib/libbsp/arm/shared/start/start.S | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/shared/start/start.S b/c/src/lib/libbsp/arm/shared/start/start.S index e79a5fc503..7b59ab4857 100644 --- a/c/src/lib/libbsp/arm/shared/start/start.S +++ b/c/src/lib/libbsp/arm/shared/start/start.S @@ -31,6 +31,14 @@ .extern boot_card .extern bsp_start_hook_0 .extern bsp_start_hook_1 + .extern bsp_stack_irq_end + .extern bsp_stack_fiq_end + .extern bsp_stack_abt_end + .extern bsp_stack_und_end + .extern bsp_stack_svc_end +#ifdef RTEMS_SMP + .extern bsp_stack_all_size +#endif .extern _ARMV4_Exception_undef_default .extern _ARMV4_Exception_swi_default .extern _ARMV4_Exception_data_abort_default @@ -119,6 +127,16 @@ _start: * loader. */ +#ifdef RTEMS_SMP + /* Read MPIDR */ + mrc p15, 0, r0, c0, c0, 5 + + /* Calculate stack offset */ + and r0, #0xff + ldr r1, =bsp_stack_all_size + mul r1, r0 +#endif + /* * Set SVC mode, disable interrupts and enable ARM instructions. */ @@ -131,26 +149,41 @@ _start: mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F) msr cpsr, r0 ldr sp, =bsp_stack_irq_end +#ifdef RTEMS_SMP + add sp, r1 +#endif /* Enter FIQ mode and set up the FIQ stack pointer */ mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F) msr cpsr, r0 ldr sp, =bsp_stack_fiq_end +#ifdef RTEMS_SMP + add sp, r1 +#endif /* Enter ABT mode and set up the ABT stack pointer */ mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F) msr cpsr, r0 ldr sp, =bsp_stack_abt_end +#ifdef RTEMS_SMP + add sp, r1 +#endif /* Enter UND mode and set up the UND stack pointer */ mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F) msr cpsr, r0 ldr sp, =bsp_stack_und_end +#ifdef RTEMS_SMP + add sp, r1 +#endif /* Enter SVC mode and set up the SVC stack pointer */ mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F) msr cpsr, r0 ldr sp, =bsp_stack_svc_end +#ifdef RTEMS_SMP + add sp, r1 +#endif /* Stay in SVC mode */ |