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authorThomas Doerfler <Thomas.Doerfler@embedded-brains.de>2010-04-09 12:22:57 +0000
committerThomas Doerfler <Thomas.Doerfler@embedded-brains.de>2010-04-09 12:22:57 +0000
commit7a6f8d09fe3efe112e8c752d978e4488a1b41d0e (patch)
treef41f7689ef1c4817d6259d82e0d3c149ca07a135 /c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h
parentgcc-4.5.0-RC-20100406. (diff)
downloadrtems-7a6f8d09fe3efe112e8c752d978e4488a1b41d0e.tar.bz2
added dma header
added thumb support to start.S updated documentation
Diffstat (limited to '')
-rw-r--r--c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h57
1 files changed, 56 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h b/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h
index 2adf0bec19..e9cf27a893 100644
--- a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h
+++ b/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h
@@ -1,7 +1,7 @@
/**
* @file
*
- * @ingroup lpc
+ * @ingroup lpc_timer
*
* @brief Timer API.
*/
@@ -28,6 +28,22 @@
extern "C" {
#endif
+/**
+ * @defgroup lpc_timer Timer Support
+ *
+ * @ingroup lpc
+ *
+ * @brief Timer support.
+ *
+ * @{
+ */
+
+/**
+ * @name Interrupt Register Defines
+ *
+ * @{
+ */
+
#define LPC_TIMER_IR_MR0 0x1U
#define LPC_TIMER_IR_MR1 0x2U
#define LPC_TIMER_IR_MR2 0x4U
@@ -38,9 +54,25 @@ extern "C" {
#define LPC_TIMER_IR_CR3 0x80U
#define LPC_TIMER_IR_ALL 0xffU
+/** @} */
+
+/**
+ * @name Timer Control Register Defines
+ *
+ * @{
+ */
+
#define LPC_TIMER_TCR_EN 0x1U
#define LPC_TIMER_TCR_RST 0x2U
+/** @} */
+
+/**
+ * @name Match Control Register Defines
+ *
+ * @{
+ */
+
#define LPC_TIMER_MCR_MR0_INTR 0x1U
#define LPC_TIMER_MCR_MR0_RST 0x2U
#define LPC_TIMER_MCR_MR0_STOP 0x4U
@@ -54,6 +86,14 @@ extern "C" {
#define LPC_TIMER_MCR_MR3_RST 0x400U
#define LPC_TIMER_MCR_MR3_STOP 0x800U
+/** @} */
+
+/**
+ * @name Capture Control Register Defines
+ *
+ * @{
+ */
+
#define LPC_TIMER_CCR_CAP0_RE 0x1U
#define LPC_TIMER_CCR_CAP0_FE 0x2U
#define LPC_TIMER_CCR_CAP0_INTR 0x4U
@@ -67,6 +107,14 @@ extern "C" {
#define LPC_TIMER_CCR_CAP3_FE 0x400U
#define LPC_TIMER_CCR_CAP3_INTR 0x800U
+/** @} */
+
+/**
+ * @name External Match Register Defines
+ *
+ * @{
+ */
+
#define LPC_TIMER_EMR_EM0_RE 0x1U
#define LPC_TIMER_EMR_EM1_FE 0x2U
#define LPC_TIMER_EMR_EM2_INTR 0x4U
@@ -76,6 +124,11 @@ extern "C" {
#define LPC_TIMER_EMR_EMC2_RE 0x40U
#define LPC_TIMER_EMR_EMC3_FE 0x80U
+/** @} */
+
+/**
+ * @brief Timer control block.
+ */
typedef struct {
uint32_t ir;
uint32_t tcr;
@@ -96,6 +149,8 @@ typedef struct {
uint32_t ctcr;
} lpc_timer;
+/** @} */
+
#ifdef __cplusplus
}
#endif /* __cplusplus */