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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-07-17 19:31:33 +0200 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-07-20 16:46:04 +0200 |
| commit | 577e7fb337c8de90d0b5661ef5b901042817366d (patch) | |
| tree | 3449d3b051ff7386ddb8f2d25594e0922dffbea8 /c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | |
| parent | bsps/arm: do not disable MMU during translation table management operations. (diff) | |
| download | rtems-577e7fb337c8de90d0b5661ef5b901042817366d.tar.bz2 | |
arm/bsps: CP15 and basic cache support entire cache clean for more architecture variants now.
Next cache operations should work on most of cores now
rtems_cache_flush_entire_data()
rtems_cache_invalidate_entire_data()
rtems_cache_invalidate_entire_instruction()
Instruction cache invalidate works on the first level for now only.
Data cacache operations are extended to ensure flush/invalidate
on all cache levels.
The CP15 arm_cp15_data_cache_clean_all_levels() function extended
to continue through unified levels too (ctype = 4).
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h index 74a65c5ac7..9caa2685bc 100644 --- a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h +++ b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h @@ -329,9 +329,13 @@ static inline void arm_cache_l1_invalidate_entire_instruction( void ) arm_cp15_instruction_cache_invalidate(); #endif /* RTEMS_SMP */ - if ( ( ctrl & ARM_CP15_CTRL_Z ) == 0 ) { + if ( ( ctrl & ARM_CP15_CTRL_Z ) != 0 ) { + #if defined(__ARM_ARCH_7A__) arm_cp15_branch_predictor_inner_shareable_invalidate_all(); + #endif + #if defined(__ARM_ARCH_6KZ__) || defined(__ARM_ARCH_7A__) arm_cp15_branch_predictor_invalidate_all(); + #endif } } |