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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-06-05 10:01:42 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-06-06 08:02:09 +0200 |
commit | 40599e7e86f29acd422124223e1758fea7beaa63 (patch) | |
tree | 98aefb454d03cc8bf9d157623c87fa698170e58f /c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | |
parent | bsp/altera-cyclone-v: Simplify start hooks (diff) | |
download | rtems-40599e7e86f29acd422124223e1758fea7beaa63.tar.bz2 |
bsps/arm: Change L2 cache initialization
Do not touch the L1 caches since they have been initialized by the start
hooks.
Diffstat (limited to '')
-rw-r--r-- | c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | 47 |
1 files changed, 0 insertions, 47 deletions
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h index 10f680d1ea..139c17182e 100644 --- a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h +++ b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h @@ -352,28 +352,6 @@ static inline void arm_cache_l1_unfreeze_instruction( void ) /* To be implemented as needed, if supported by hardware at all */ } -static inline void arm_cache_l1_enable_data( void ) -{ - uint32_t ctrl; - - arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA ); - - assert( ARM_CACHE_L1_CPU_DATA_ALIGNMENT == arm_cp15_get_data_cache_line_size() ); - - ctrl = arm_cp15_get_control(); - - /* Only enable the cache if it is disabled */ - if ( !( ctrl & ARM_CP15_CTRL_C ) ) { - /* Clean and invalidate the Data cache */ - arm_cache_l1_invalidate_entire_data(); - - /* Enable the Data cache */ - ctrl |= ARM_CP15_CTRL_C; - - arm_cp15_set_control( ctrl ); - } -} - static inline void arm_cache_l1_disable_data( void ) { /* Clean and invalidate the Data cache */ @@ -395,31 +373,6 @@ static inline void arm_cache_l1_disable_instruction( void ) arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_I ); } -static inline void arm_cache_l1_enable_instruction( void ) -{ - uint32_t ctrl; - - arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION ); - - assert( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT - == arm_cp15_get_data_cache_line_size() ); - - /* Enable Instruction cache only if it is disabled */ - ctrl = arm_cp15_get_control(); - - if ( !( ctrl & ARM_CP15_CTRL_I ) ) { - /* Invalidate the Instruction cache */ - arm_cache_l1_invalidate_entire_instruction(); - - /* Enable the Instruction cache */ - ctrl |= ARM_CP15_CTRL_I; - - arm_cp15_set_control( ctrl ); - } - - arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA ); -} - static inline size_t arm_cache_l1_get_data_cache_size( void ) { size_t size; |