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author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2004-04-21 10:43:04 +0000 |
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committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2004-04-21 10:43:04 +0000 |
commit | 6128a4aa5e791ed4e0a655bfd346a52d92da7883 (patch) | |
tree | af53ca3f67ce405b6fbc6c98399c8e0c87e01a9e /c/src/lib/libbsp/arm/shared/comm/uart.h | |
parent | 2004-04-20 Ralf Corsepius <ralf_corsepius@rtems.org> (diff) | |
download | rtems-6128a4aa5e791ed4e0a655bfd346a52d92da7883.tar.bz2 |
Remove stray white spaces.
Diffstat (limited to '')
-rw-r--r-- | c/src/lib/libbsp/arm/shared/comm/uart.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/c/src/lib/libbsp/arm/shared/comm/uart.h b/c/src/lib/libbsp/arm/shared/comm/uart.h index c472d8296e..18322cedee 100644 --- a/c/src/lib/libbsp/arm/shared/comm/uart.h +++ b/c/src/lib/libbsp/arm/shared/comm/uart.h @@ -38,7 +38,7 @@ extern int BSPConsolePort; extern int BSPBaseBaud; /* * Command values for BSP_uart_intr_ctrl(), - * values are strange in order to catch errors + * values are strange in order to catch errors * with assert */ #define BSP_UART_INTR_CTRL_DISABLE (0) @@ -71,20 +71,20 @@ extern int BSPBaseBaud; #define RBR RSRBR /* Rx Buffer Register (read) */ #define THR RSTHR /* Tx Buffer Register (write) */ #define IER RSIER /* Interrupt Enable Register */ - + /* DLAB X */ #define IIR RSIIR /* Interrupt Ident Register (read) */ #define FCR RSFCR /* FIFO Control Register (write) */ #define LCR RSLCR /* Line Control Register */ #define LSR RSLSR /* Line Status Register */ - + /* DLAB 1 */ #define DLL RSDLL /* Divisor Latch, LSB */ #define DLM RSDLH /* Divisor Latch, MSB */ - + /* Uart control */ #define CNT RSCNT /* General Control register */ - + /* * define bit for CNT */ |