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| author | Joel Sherrill <joel@rtems.org> | 2016-07-12 05:44:17 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2016-07-12 05:44:17 -0500 |
| commit | 612297e813795d6f8c09d8b8a5e1dfa712ad3d9d (patch) | |
| tree | 77808013ec7ef5612e190a7af80e4d9e1cb88fbe /c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h | |
| parent | DOSFS - LENGHT -> LENGTH (diff) | |
| download | rtems-612297e813795d6f8c09d8b8a5e1dfa712ad3d9d.tar.bz2 | |
Misc: Spell length correctly
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h b/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h index efca2bb24e..c6e1f834d7 100644 --- a/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h +++ b/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h @@ -29,7 +29,7 @@ #define CPU_DATA_CACHE_ALIGNMENT 32 #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 #if defined(__ARM_ARCH_7A__) -/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */ +/* Some/many ARM Cortex-A cores have L1 data line length 64 bytes */ #define CPU_MAXIMAL_CACHE_ALIGNMENT 64 #endif |