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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-07-04 20:34:39 +0200 |
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committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-10-02 10:40:34 +0200 |
commit | be62c0b02c0747ac2f96d898e51d29556930cf16 (patch) | |
tree | ea0ad59482e848930332105c0b58c52134b0730c /c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h | |
parent | bsps/arm: reorganize CP15 code to allow clean and invalidate ARMv7 cache by l... (diff) | |
download | rtems-be62c0b02c0747ac2f96d898e51d29556930cf16.tar.bz2 |
bsps/arm: Fix basic cache support for SMP
Updates #2782
Updates #2783
Diffstat (limited to 'c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h')
-rw-r--r-- | c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h b/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h index 31a69be1fb..53b0ceb935 100644 --- a/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h +++ b/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h @@ -134,11 +134,11 @@ static inline void _CPU_cache_enable_data(void) rtems_interrupt_level level; uint32_t ctrl; - rtems_interrupt_disable(level); + rtems_interrupt_local_disable(level); ctrl = arm_cp15_get_control(); ctrl |= ARM_CP15_CTRL_C; arm_cp15_set_control(ctrl); - rtems_interrupt_enable(level); + rtems_interrupt_local_enable(level); } static inline void _CPU_cache_disable_data(void) @@ -146,12 +146,12 @@ static inline void _CPU_cache_disable_data(void) rtems_interrupt_level level; uint32_t ctrl; - rtems_interrupt_disable(level); + rtems_interrupt_local_disable(level); arm_cp15_data_cache_test_and_clean_and_invalidate(); ctrl = arm_cp15_get_control(); ctrl &= ~ARM_CP15_CTRL_C; arm_cp15_set_control(ctrl); - rtems_interrupt_enable(level); + rtems_interrupt_local_enable(level); } static inline void _CPU_cache_invalidate_entire_instruction(void) @@ -165,11 +165,11 @@ static inline void _CPU_cache_enable_instruction(void) rtems_interrupt_level level; uint32_t ctrl; - rtems_interrupt_disable(level); + rtems_interrupt_local_disable(level); ctrl = arm_cp15_get_control(); ctrl |= ARM_CP15_CTRL_I; arm_cp15_set_control(ctrl); - rtems_interrupt_enable(level); + rtems_interrupt_local_enable(level); } static inline void _CPU_cache_disable_instruction(void) @@ -177,11 +177,11 @@ static inline void _CPU_cache_disable_instruction(void) rtems_interrupt_level level; uint32_t ctrl; - rtems_interrupt_disable(level); + rtems_interrupt_local_disable(level); ctrl = arm_cp15_get_control(); ctrl &= ~ARM_CP15_CTRL_I; arm_cp15_set_control(ctrl); - rtems_interrupt_enable(level); + rtems_interrupt_local_enable(level); } #endif /* LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H */ |