diff options
| author | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2009-12-15 15:20:47 +0000 |
|---|---|---|
| committer | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2009-12-15 15:20:47 +0000 |
| commit | c468f18bb73a570bf2b3eb279a7dea60b91c3319 (patch) | |
| tree | b181297c2b4a0f8fa3edbb9987fd99a3ecc45a8b /c/src/lib/libbsp/arm/lpc32xx | |
| parent | add support for ARM11, reimplement nested interrupts (diff) | |
| download | rtems-c468f18bb73a570bf2b3eb279a7dea60b91c3319.tar.bz2 | |
add support for LPC32xx
Diffstat (limited to '')
22 files changed, 1819 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/lpc32xx/.cvsignore b/c/src/lib/libbsp/arm/lpc32xx/.cvsignore new file mode 100644 index 0000000000..baba64eafa --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/.cvsignore @@ -0,0 +1,8 @@ +aclocal.m4 +autom4te*.cache +config.cache +config.log +config.status +configure +Makefile +Makefile.in diff --git a/c/src/lib/libbsp/arm/lpc32xx/ChangeLog b/c/src/lib/libbsp/arm/lpc32xx/ChangeLog new file mode 100644 index 0000000000..faa574da80 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/ChangeLog @@ -0,0 +1,9 @@ +2009-12-15 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * bsp_specs, configure.ac, console/console-config.c, include/bsp.h, + include/irq-config.h, include/irq.h, include/lpc32xx.h, + include/lpc-clock-config.h, irq/irq.c, + make/custom/lpc32xx_phycore.cfg, Makefile.am, misc/timer.c, + preinstall.am, README, rtc/rtc-config.c, startup/bspreset.c, + startup/bspstart.c, startup/bspstarthooks.c, + startup/linkcmds.lpc32xx_phycore: New files. diff --git a/c/src/lib/libbsp/arm/lpc32xx/Makefile.am b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am new file mode 100644 index 0000000000..fd866bcdcd --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am @@ -0,0 +1,142 @@ +## +# +# @file +# +# @brief Makefile of LibBSP for the LPC32XX boards. +# + +# $Id$ + +ACLOCAL_AMFLAGS = -I ../../../../aclocal + +include $(top_srcdir)/../../../../automake/compile.am + +include_bspdir = $(includedir)/bsp + +dist_project_lib_DATA = bsp_specs + +############################################################################### +# Header # +############################################################################### + +include_HEADERS = include/bsp.h + +nodist_include_HEADERS = ../../shared/include/coverhd.h \ + include/bspopts.h + +nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h + +include_bsp_HEADERS = +include_bsp_HEADERS += ../../shared/include/utility.h +include_bsp_HEADERS += ../../shared/include/irq-generic.h +include_bsp_HEADERS += ../../shared/include/irq-info.h +include_bsp_HEADERS += ../../shared/include/stackalloc.h +include_bsp_HEADERS += ../../shared/tod.h +include_bsp_HEADERS += ../shared/include/linker-symbols.h +include_bsp_HEADERS += ../shared/include/start.h +include_bsp_HEADERS += ../shared/lpc/include/lpc-timer.h +include_bsp_HEADERS += include/irq-config.h +include_bsp_HEADERS += include/irq.h +include_bsp_HEADERS += include/lpc32xx.h +include_bsp_HEADERS += include/lpc-clock-config.h + +include_HEADERS += ../../shared/include/tm27.h + +############################################################################### +# Data # +############################################################################### + +noinst_LIBRARIES = libbspstart.a + +libbspstart_a_SOURCES = ../shared/start/start.S + +project_lib_DATA = start.$(OBJEXT) + +project_lib_DATA += startup/linkcmds +project_lib_DATA += ../shared/startup/linkcmds.base + +EXTRA_DIST = startup/linkcmds.lpc32xx_phycore + +############################################################################### +# LibBSP # +############################################################################### + +noinst_LIBRARIES += libbsp.a + +libbsp_a_SOURCES = + +# Shared +libbsp_a_SOURCES += ../../shared/bootcard.c \ + ../../shared/bspclean.c \ + ../../shared/bspgetworkarea.c \ + ../../shared/bsplibc.c \ + ../../shared/bsppost.c \ + ../../shared/bsppredriverhook.c \ + ../../shared/bsppretaskinghook.c \ + ../../shared/gnatinstallhandler.c \ + ../../shared/sbrk.c \ + ../../shared/src/stackalloc.c \ + ../shared/abort/simple_abort.c + +# Startup +libbsp_a_SOURCES += startup/bspstart.c \ + startup/bspreset.c + +# IRQ +libbsp_a_SOURCES += ../../shared/src/irq-generic.c \ + ../../shared/src/irq-legacy.c \ + ../../shared/src/irq-info.c \ + ../../shared/src/irq-shell.c \ + ../../shared/src/irq-server.c \ + irq/irq.c + +# Console +libbsp_a_SOURCES += ../../shared/console.c \ + console/console-config.c + +# Clock +libbsp_a_SOURCES += ../shared/lpc/clock/lpc-clock-config.c \ + ../../../shared/clockdrv_shell.h + +# RTC +libbsp_a_SOURCES += ../../shared/tod.c \ + rtc/rtc-config.c + +# Timer +libbsp_a_SOURCES += misc/timer.c + +# SSP + +# I2C + +# Start hooks (FIXME: This is brittle.) +libbsp_a_SOURCES += startup/bspstarthooks.c +bspstarthooks.o: startup/bspstarthooks.c + $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS:-mthumb=) \ + -MT bspstarthooks.o -MD -MP -MF $(DEPDIR)/bspstarthooks.Tpo -c -o bspstarthooks.o \ + `test -f 'startup/bspstarthooks.c' || echo '$(srcdir)/'`startup/bspstarthooks.c + +############################################################################### +# Network # +############################################################################### + +if HAS_NETWORKING + +# noinst_PROGRAMS = network.rel + +# network_rel_SOURCES = network/network.c +# network_rel_CPPFLAGS = $(AM_CPPFLAGS) -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE +# network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) + +# libbsp_a_LIBADD = network.rel + +endif + +############################################################################### +# Special Rules # +############################################################################### + +DISTCLEANFILES = include/bspopts.h + +include $(srcdir)/preinstall.am +include $(top_srcdir)/../../../../automake/local.am diff --git a/c/src/lib/libbsp/arm/lpc32xx/README b/c/src/lib/libbsp/arm/lpc32xx/README new file mode 100644 index 0000000000..97a1546e2d --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/README @@ -0,0 +1,5 @@ +Development board is phyCORE-LPC3250 RDK. Basic initialization via stage 1 +bootloader or U-Boot will be assumed. Drivers: + + o Standard UART 3, 4, 5, 6 (Console = 5, 115200N1) + o Clock uses TIMER 0 diff --git a/c/src/lib/libbsp/arm/lpc32xx/bsp_specs b/c/src/lib/libbsp/arm/lpc32xx/bsp_specs new file mode 100644 index 0000000000..9be7e23eb6 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/bsp_specs @@ -0,0 +1,13 @@ +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*startfile: +%{!qrtems: %(old_startfile)} \ +%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e start}} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N} + +*endfile: +%{!qrtems: *(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s } diff --git a/c/src/lib/libbsp/arm/lpc32xx/configure.ac b/c/src/lib/libbsp/arm/lpc32xx/configure.ac new file mode 100644 index 0000000000..6febd9d350 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/configure.ac @@ -0,0 +1,61 @@ +## +# +# @file +# +# @brief Configure script of LibBSP for the LPC32XX boards. +# + +AC_PREREQ(2.59) +AC_INIT([rtems-c-src-lib-libbsp-arm-lpc32xx],[_RTEMS_VERSION],[rtems-bugs@rtems.com]) +AC_CONFIG_SRCDIR([bsp_specs]) +RTEMS_TOP(../../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.9]) +RTEMS_BSP_CONFIGURE + +RTEMS_PROG_CC_FOR_TARGET +RTEMS_CANONICALIZE_TOOLS +RTEMS_PROG_CCAS + +RTEMS_CHECK_NETWORKING +AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") + +RTEMS_BSPOPTS_SET([LPC32XX_OSCILLATOR_MAIN],[*],[13000000U]) +RTEMS_BSPOPTS_HELP([LPC32XX_OSCILLATOR_MAIN],[main oscillator frequency in Hz]) + +RTEMS_BSPOPTS_SET([LPC32XX_OSCILLATOR_RTC],[*],[32768U]) +RTEMS_BSPOPTS_HELP([LPC32XX_OSCILLATOR_RTC],[RTC oscillator frequency in Hz]) + +RTEMS_BSPOPTS_SET([LPC32XX_ARM_CLK],[*],[208000000U]) +RTEMS_BSPOPTS_HELP([LPC32XX_ARM_CLK],[ARM clock in Hz]) + +RTEMS_BSPOPTS_SET([LPC32XX_HCLK],[*],[104000000U]) +RTEMS_BSPOPTS_HELP([LPC32XX_HCLK],[AHB bus clock in Hz]) + +RTEMS_BSPOPTS_SET([LPC32XX_PERIPH_CLK],[*],[13000000U]) +RTEMS_BSPOPTS_HELP([LPC32XX_PERIPH_CLK],[peripheral clock in Hz]) + +RTEMS_BSPOPTS_SET([LPC32XX_CONFIG_U3CLK],[*],[]) +RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_U3CLK],[clock configuration for UART 3]) + +RTEMS_BSPOPTS_SET([LPC32XX_CONFIG_U4CLK],[*],[]) +RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_U4CLK],[clock configuration for UART 4]) + +RTEMS_BSPOPTS_SET([LPC32XX_CONFIG_U5CLK],[*],[0x00001386U]) +RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_U5CLK],[clock configuration for UART 5]) + +RTEMS_BSPOPTS_SET([LPC32XX_CONFIG_U6CLK],[*],[]) +RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_U6CLK],[clock configuration for UART 6]) + +RTEMS_BSPOPTS_SET([LPC32XX_CONFIG_UART_CLKMODE],[*],[0x00000200U]) +RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_UART_CLKMODE],[clock mode configuration for UARTs]) + +RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) +RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) + +RTEMS_BSP_CLEANUP_OPTIONS(0, 0) +RTEMS_BSP_LINKCMDS + +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT diff --git a/c/src/lib/libbsp/arm/lpc32xx/console/console-config.c b/c/src/lib/libbsp/arm/lpc32xx/console/console-config.c new file mode 100644 index 0000000000..1504919a55 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/console/console-config.c @@ -0,0 +1,139 @@ +/** + * @file + * + * @ingroup lpc32xx + * + * @brief Console configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#include <libchip/serial.h> +#include <libchip/ns16550.h> + +#include <bsp.h> +#include <bsp/lpc32xx.h> +#include <bsp/irq.h> + +static uint8_t lpc32xx_uart_get_register(uint32_t addr, uint8_t i) +{ + volatile uint32_t *reg = (volatile uint32_t *) addr; + + return (uint8_t) reg [i]; +} + +static void lpc32xx_uart_set_register(uint32_t addr, uint8_t i, uint8_t val) +{ + volatile uint32_t *reg = (volatile uint32_t *) addr; + + reg [i] = val; +} + +rtems_device_minor_number Console_Port_Minor = 0; + +/* FIXME: Console selection */ + +console_tbl Console_Port_Tbl [] = { + #ifdef LPC32XX_CONFIG_U5CLK + { + .sDeviceName = "/dev/ttyS5", + .deviceType = SERIAL_NS16550, + .pDeviceFns = &ns16550_fns, + .deviceProbe = NULL, + .pDeviceFlow = NULL, + .ulMargin = 16, + .ulHysteresis = 8, + .pDeviceParams = (void *) 1, + .ulCtrlPort1 = LPC32XX_BASE_UART_5, + .ulCtrlPort2 = 0, + .ulDataPort = LPC32XX_BASE_UART_5, + .getRegister = lpc32xx_uart_get_register, + .setRegister = lpc32xx_uart_set_register, + .getData = NULL, + .setData = NULL, + .ulClock = 16, + .ulIntVector = LPC32XX_IRQ_UART_5 + }, + #endif + #ifdef LPC32XX_CONFIG_U3CLK + { + .sDeviceName = "/dev/ttyS3", + .deviceType = SERIAL_NS16550, + .pDeviceFns = &ns16550_fns, + .deviceProbe = NULL, + .pDeviceFlow = NULL, + .ulMargin = 16, + .ulHysteresis = 8, + .pDeviceParams = (void *) 1, + .ulCtrlPort1 = LPC32XX_BASE_UART_3, + .ulCtrlPort2 = 0, + .ulDataPort = LPC32XX_BASE_UART_3, + .getRegister = lpc32xx_uart_get_register, + .setRegister = lpc32xx_uart_set_register, + .getData = NULL, + .setData = NULL, + .ulClock = 16, + .ulIntVector = LPC32XX_IRQ_UART_3 + }, + #endif + #ifdef LPC32XX_CONFIG_U4CLK + { + .sDeviceName = "/dev/ttyS4", + .deviceType = SERIAL_NS16550, + .pDeviceFns = &ns16550_fns, + .deviceProbe = NULL, + .pDeviceFlow = NULL, + .ulMargin = 16, + .ulHysteresis = 8, + .pDeviceParams = (void *) 1, + .ulCtrlPort1 = LPC32XX_BASE_UART_4, + .ulCtrlPort2 = 0, + .ulDataPort = LPC32XX_BASE_UART_4, + .getRegister = lpc32xx_uart_get_register, + .setRegister = lpc32xx_uart_set_register, + .getData = NULL, + .setData = NULL, + .ulClock = 16, + .ulIntVector = LPC32XX_IRQ_UART_4 + }, + #endif + #ifdef LPC32XX_CONFIG_U6CLK + { + .sDeviceName = "/dev/ttyS6", + .deviceType = SERIAL_NS16550, + .pDeviceFns = &ns16550_fns, + .deviceProbe = NULL, + .pDeviceFlow = NULL, + .ulMargin = 16, + .ulHysteresis = 8, + .pDeviceParams = (void *) 1, + .ulCtrlPort1 = LPC32XX_BASE_UART_6, + .ulCtrlPort2 = 0, + .ulDataPort = LPC32XX_BASE_UART_6, + .getRegister = lpc32xx_uart_get_register, + .setRegister = lpc32xx_uart_set_register, + .getData = NULL, + .setData = NULL, + .ulClock = 16, + .ulIntVector = LPC32XX_IRQ_UART_6 + }, + #endif +}; + +#define LPC32XX_UART_COUNT \ + (sizeof(Console_Port_Tbl) / sizeof(Console_Port_Tbl [0])) + +unsigned long Console_Port_Count = LPC32XX_UART_COUNT; + +console_data Console_Port_Data [LPC32XX_UART_COUNT]; diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h b/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h new file mode 100644 index 0000000000..a42dd7b0be --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h @@ -0,0 +1,99 @@ +/** + * @file + * + * @ingroup lpc32xx + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_BSP_H +#define LIBBSP_ARM_LPC32XX_BSP_H + +#include <bspopts.h> + +#include <rtems.h> +#include <rtems/console.h> +#include <rtems/clockdrv.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#ifndef ASM + +struct rtems_bsdnet_ifconfig; + +/** + * @defgroup lpc32xx LPC32XX Support + * + * @ingroup bsp_kit + * + * @brief LPC32XX support package. + * + * @{ + */ + +/** + * @brief Network driver attach and detach function. + */ +int lpc32xx_eth_attach_detach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +/** + * @brief Standard network driver attach and detach function. + */ +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc32xx_eth_attach_detach + +/** + * @brief Standard network driver name. + */ +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" + +/** + * @brief Optimized idle task. + * + * This idle task sets the power mode to idle. This causes the processor clock + * to be stopped, while on-chip peripherals remain active. Any enabled + * interrupt from a peripheral or an external interrupt source will cause the + * processor to resume execution. + * + * To enable the idle task use the following in the system configuration: + * + * @code + * #include <bsp.h> + * + * #define CONFIGURE_INIT + * + * #define CONFIGURE_IDLE_TASK_BODY lpc32xx_idle + * + * #include <confdefs.h> + * @endcode + */ +void *lpc32xx_idle(uintptr_t ignored); + +/** @} */ + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_BSP_H */ diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in b/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in new file mode 100644 index 0000000000..bcf5f8fa42 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in @@ -0,0 +1,61 @@ +/* include/bspopts.h.in. Generated from configure.ac by autoheader. */ + +/* If defined, then the BSP Framework will put a non-zero pattern into the + RTEMS Workspace and C program heap. This should assist in finding code that + assumes memory starts set to zero. */ +#undef BSP_DIRTY_MEMORY + +/* If defined, print a message and wait until pressed before resetting board + when application exits. */ +#undef BSP_PRESS_KEY_FOR_RESET + +/* If defined, reset the board when the application exits. */ +#undef BSP_RESET_BOARD_AT_EXIT + +/* reset vector address for BSP start */ +#undef BSP_START_RESET_VECTOR + +/* ARM clock in Hz */ +#undef LPC32XX_ARM_CLK + +/* clock configuration for UART 3 */ +#undef LPC32XX_CONFIG_U3CLK + +/* clock configuration for UART 4 */ +#undef LPC32XX_CONFIG_U4CLK + +/* clock configuration for UART 5 */ +#undef LPC32XX_CONFIG_U5CLK + +/* clock configuration for UART 6 */ +#undef LPC32XX_CONFIG_U6CLK + +/* clock mode configuration for UARTs */ +#undef LPC32XX_CONFIG_UART_CLKMODE + +/* AHB bus clock in Hz */ +#undef LPC32XX_HCLK + +/* main oscillator frequency in Hz */ +#undef LPC32XX_OSCILLATOR_MAIN + +/* RTC oscillator frequency in Hz */ +#undef LPC32XX_OSCILLATOR_RTC + +/* peripheral clock in Hz */ +#undef LPC32XX_PERIPH_CLK + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/irq-config.h b/c/src/lib/libbsp/arm/lpc32xx/include/irq-config.h new file mode 100644 index 0000000000..659e2ea56e --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/include/irq-config.h @@ -0,0 +1,27 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief Interrupt support configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_IRQ_CONFIG_H +#define LIBBSP_ARM_LPC32XX_IRQ_CONFIG_H + +#include <bsp/irq.h> + +#endif /* LIBBSP_ARM_LPC32XX_IRQ_CONFIG_H */ diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/irq.h b/c/src/lib/libbsp/arm/lpc32xx/include/irq.h new file mode 100644 index 0000000000..62d28fe7e0 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/include/irq.h @@ -0,0 +1,165 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief Interrupt definitions. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_IRQ_H +#define LIBBSP_ARM_LPC32XX_IRQ_H + +#ifndef ASM + +#include <rtems.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define LPC32XX_IRQ_INDEX(module, subindex) ((module) + (subindex)) + +#define LPC32XX_IRQ_MODULE_MIC 0U +#define LPC32XX_IRQ_MODULE_SIC_1 32U +#define LPC32XX_IRQ_MODULE_SIC_2 64U +#define LPC32XX_IRQ_MODULE_COUNT 3U + +/* MIC interrupts */ +#define LPC32XX_IRQ_SIC_1_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 0) +#define LPC32XX_IRQ_SIC_2_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 1) +#define LPC32XX_IRQ_TIMER_4_OR_MCPWM LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 3) +#define LPC32XX_IRQ_TIMER_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 4) +#define LPC32XX_IRQ_TIMER_HS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 5) +#define LPC32XX_IRQ_WDG LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 6) +#define LPC32XX_IRQ_UART_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 7) +#define LPC32XX_IRQ_UART_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 8) +#define LPC32XX_IRQ_UART_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 9) +#define LPC32XX_IRQ_UART_6 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 10) +#define LPC32XX_IRQ_NAND_FLASH LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 11) +#define LPC32XX_IRQ_SDCARD_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 13) +#define LPC32XX_IRQ_LCD LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 14) +#define LPC32XX_IRQ_SDCARD_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 15) +#define LPC32XX_IRQ_TIMER_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 16) +#define LPC32XX_IRQ_TIMER_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 17) +#define LPC32XX_IRQ_TIMER_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 18) +#define LPC32XX_IRQ_TIMER_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 19) +#define LPC32XX_IRQ_SSP_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 20) +#define LPC32XX_IRQ_SSP_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 21) +#define LPC32XX_IRQ_I2S_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 22) +#define LPC32XX_IRQ_I2S_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 23) +#define LPC32XX_IRQ_UART_7 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 24) +#define LPC32XX_IRQ_UART_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 25) +#define LPC32XX_IRQ_UART_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 26) +#define LPC32XX_IRQ_TIMER_MS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 27) +#define LPC32XX_IRQ_DMA LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 28) +#define LPC32XX_IRQ_ETHERNET LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 29) +#define LPC32XX_IRQ_SIC_1_FIQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 30) +#define LPC32XX_IRQ_SIC_2_FIQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 31) + +/* SIC 1 interrupts */ +#define LPC32XX_IRQ_JTAG_COMM_TX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 1) +#define LPC32XX_IRQ_JTAG_COMM_RX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 2) +#define LPC32XX_IRQ_GPI_28 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 4) +#define LPC32XX_IRQ_TS_P LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 6) +#define LPC32XX_IRQ_TS_IRQ_OR_ADC LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 7) +#define LPC32XX_IRQ_TS_AUX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 8) +#define LPC32XX_IRQ_SPI_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 12) +#define LPC32XX_IRQ_PLL_USB LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 13) +#define LPC32XX_IRQ_PLL_HCLK LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 14) +#define LPC32XX_IRQ_PLL_397 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 17) +#define LPC32XX_IRQ_I2C_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 18) +#define LPC32XX_IRQ_I2C_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 19) +#define LPC32XX_IRQ_RTC LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 20) +#define LPC32XX_IRQ_KEYSCAN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 22) +#define LPC32XX_IRQ_SPI_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 23) +#define LPC32XX_IRQ_SW LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 24) +#define LPC32XX_IRQ_USB_OTG_TIMER LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 25) +#define LPC32XX_IRQ_USB_OTG_ATX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 26) +#define LPC32XX_IRQ_USB_HOST LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 27) +#define LPC32XX_IRQ_USB_DEV_DMA LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 28) +#define LPC32XX_IRQ_USB_DEV_LP LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 29) +#define LPC32XX_IRQ_USB_DEV_HP LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 30) +#define LPC32XX_IRQ_USB_I2C LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 31) + +/* SIC 2 interrupts */ +#define LPC32XX_IRQ_GPIO_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 0) +#define LPC32XX_IRQ_GPIO_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 1) +#define LPC32XX_IRQ_GPIO_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 2) +#define LPC32XX_IRQ_GPIO_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 3) +#define LPC32XX_IRQ_GPIO_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 4) +#define LPC32XX_IRQ_GPIO_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 5) +#define LPC32XX_IRQ_SPI_2_DATAIN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 6) +#define LPC32XX_IRQ_UART_2_HCTS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 7) +#define LPC32XX_IRQ_GPIO_P0_P1_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 8) +#define LPC32XX_IRQ_GPI_8 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 9) +#define LPC32XX_IRQ_GPI_9 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 10) +#define LPC32XX_IRQ_GPI_19 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 11) +#define LPC32XX_IRQ_UART_7_HCTS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 12) +#define LPC32XX_IRQ_GPI_7 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 15) +#define LPC32XX_IRQ_SDIO LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 18) +#define LPC32XX_IRQ_UART_5_RX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 19) +#define LPC32XX_IRQ_SPI_1_DATAIN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 20) +#define LPC32XX_IRQ_GPI_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 22) +#define LPC32XX_IRQ_GPI_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 23) +#define LPC32XX_IRQ_GPI_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 24) +#define LPC32XX_IRQ_GPI_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 25) +#define LPC32XX_IRQ_GPI_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 26) +#define LPC32XX_IRQ_GPI_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 27) +#define LPC32XX_IRQ_GPI_6 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 28) +#define LPC32XX_IRQ_SYSCLK LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 31) + +#define LPC32XX_IRQ_PRIORITY_VALUE_MIN 0U +#define LPC32XX_IRQ_PRIORITY_VALUE_MAX 15U +#define LPC32XX_IRQ_PRIORITY_COUNT (LPC32XX_IRQ_PRIORITY_VALUE_MAX + 1U) +#define LPC32XX_IRQ_PRIORITY_HIGHEST LPC32XX_IRQ_PRIORITY_VALUE_MIN +#define LPC32XX_IRQ_PRIORITY_LOWEST LPC32XX_IRQ_PRIORITY_VALUE_MAX + +#define BSP_INTERRUPT_VECTOR_MIN LPC32XX_IRQ_SIC_1_IRQ +#define BSP_INTERRUPT_VECTOR_MAX LPC32XX_IRQ_SYSCLK + +#define LPC32XX_IRQ_COUNT (BSP_INTERRUPT_VECTOR_MAX + 1) + +void lpc32xx_irq_set_priority(rtems_vector_number vector, unsigned priority); + +unsigned lpc32xx_irq_get_priority(rtems_vector_number vector); + +typedef enum { + LPC32XX_IRQ_ACTIVE_LOW_OR_FALLING_EDGE, + LPC32XX_IRQ_ACTIVE_HIGH_OR_RISING_EDGE +} lpc32xx_irq_activation_polarity; + +void lpc32xx_irq_set_activation_polarity(rtems_vector_number vector, lpc32xx_irq_activation_polarity activation_polarity); + +lpc32xx_irq_activation_polarity lpc32xx_irq_get_activation_polarity(rtems_vector_number vector); + +typedef enum { + LPC32XX_IRQ_LEVEL_SENSITIVE, + LPC32XX_IRQ_EDGE_SENSITIVE +} lpc32xx_irq_activation_type; + +void lpc32xx_irq_set_activation_type(rtems_vector_number vector, lpc32xx_irq_activation_type activation_type); + +lpc32xx_irq_activation_type lpc32xx_irq_get_activation_type(rtems_vector_number vector); + +/** @} */ + +#endif /* ASM */ + +#endif /* LIBBSP_ARM_LPC32XX_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/lpc-clock-config.h b/c/src/lib/libbsp/arm/lpc32xx/include/lpc-clock-config.h new file mode 100644 index 0000000000..c4d7906632 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/include/lpc-clock-config.h @@ -0,0 +1,45 @@ +/** + * @file + * + * @ingroup lpc32xx + * + * @brief Clock driver configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H +#define LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H + +#include <bsp.h> +#include <bsp/irq.h> +#include <bsp/lpc32xx.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define LPC_CLOCK_INTERRUPT LPC32XX_IRQ_TIMER_0 + +#define LPC_CLOCK_TIMER_BASE LPC32XX_BASE_TIMER_0 + +#define LPC_CLOCK_REFERENCE LPC32XX_PERIPH_CLK + +#define LPC_CLOCK_MODULE_ENABLE() + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H */ diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h b/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h new file mode 100644 index 0000000000..2e82d34b80 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h @@ -0,0 +1,94 @@ +/** + * @file + * + * @ingroup lpc32xx + * + * @brief Register base addresses. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http: + */ + +#ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H +#define LIBBSP_ARM_LPC32XX_LPC32XX_H + +#define LPC32XX_BASE_ADC 0x40048000 +#define LPC32XX_BASE_SYSCON 0x40004000 +#define LPC32XX_BASE_DEBUG_CTRL 0x40040000 +#define LPC32XX_BASE_DMA 0x31000000 +#define LPC32XX_BASE_EMC 0x31080000 +#define LPC32XX_BASE_EMC_CS_0 0xe0000000 +#define LPC32XX_BASE_EMC_CS_1 0xe1000000 +#define LPC32XX_BASE_EMC_CS_2 0xe2000000 +#define LPC32XX_BASE_EMC_CS_3 0xe3000000 +#define LPC32XX_BASE_EMC_DYCS_0 0x80000000 +#define LPC32XX_BASE_EMC_DYCS_1 0xa0000000 +#define LPC32XX_BASE_ETB_CFG 0x310c0000 +#define LPC32XX_BASE_ETB_DATA 0x310e0000 +#define LPC32XX_BASE_ETHERNET 0x31060000 +#define LPC32XX_BASE_GPIO 0x40028000 +#define LPC32XX_BASE_I2C_1 0x400a0000 +#define LPC32XX_BASE_I2C_2 0x400a8000 +#define LPC32XX_BASE_I2S_0 0x20094000 +#define LPC32XX_BASE_I2S_1 0x2009c000 +#define LPC32XX_BASE_IRAM 0x08000000 +#define LPC32XX_BASE_IROM 0x0c000000 +#define LPC32XX_BASE_KEYSCAN 0x40050000 +#define LPC32XX_BASE_LCD 0x31040000 +#define LPC32XX_BASE_MCPWM 0x400e8000 +#define LPC32XX_BASE_MIC 0x40008000 +#define LPC32XX_BASE_NAND_MLC 0x200a8000 +#define LPC32XX_BASE_NAND_SLC 0x20020000 +#define LPC32XX_BASE_PWM_1 0x4005c000 +#define LPC32XX_BASE_PWM_2 0x4005c004 +#define LPC32XX_BASE_PWM_3 0x4002c000 +#define LPC32XX_BASE_PWM_4 0x40030000 +#define LPC32XX_BASE_RTC 0x40024000 +#define LPC32XX_BASE_RTC_RAM 0x40024080 +#define LPC32XX_BASE_SDCARD 0x20098000 +#define LPC32XX_BASE_SIC_1 0x4000c000 +#define LPC32XX_BASE_SIC_2 0x40010000 +#define LPC32XX_BASE_SPI_1 0x20088000 +#define LPC32XX_BASE_SPI_2 0x20090000 +#define LPC32XX_BASE_SSP_0 0x20084000 +#define LPC32XX_BASE_SSP_1 0x2008c000 +#define LPC32XX_BASE_TIMER_0 0x40044000 +#define LPC32XX_BASE_TIMER_1 0x4004c000 +#define LPC32XX_BASE_TIMER_2 0x40058000 +#define LPC32XX_BASE_TIMER_3 0x40060000 +#define LPC32XX_BASE_TIMER_5 0x4002c000 +#define LPC32XX_BASE_TIMER_6 0x40030000 +#define LPC32XX_BASE_TIMER_HS 0x40038000 +#define LPC32XX_BASE_TIMER_MS 0x40034000 +#define LPC32XX_BASE_UART_1 0x40014000 +#define LPC32XX_BASE_UART_2 0x40018000 +#define LPC32XX_BASE_UART_3 0x40080000 +#define LPC32XX_BASE_UART_4 0x40088000 +#define LPC32XX_BASE_UART_5 0x40090000 +#define LPC32XX_BASE_UART_6 0x40098000 +#define LPC32XX_BASE_UART_7 0x4001c000 +#define LPC32XX_BASE_USB 0x31020000 +#define LPC32XX_BASE_USB_OTG_I2C 0x31020300 +#define LPC32XX_BASE_WDT 0x4003c000 + +#define LPC32XX_U3CLK (*(volatile uint32_t *) 0x400040d0) +#define LPC32XX_U4CLK (*(volatile uint32_t *) 0x400040d4) +#define LPC32XX_U5CLK (*(volatile uint32_t *) 0x400040d8) +#define LPC32XX_U6CLK (*(volatile uint32_t *) 0x400040dc) +#define LPC32XX_IRDACLK (*(volatile uint32_t *) 0x400040e0) +#define LPC32XX_UART_CTRL (*(volatile uint32_t *) 0x40054000) +#define LPC32XX_UART_CLKMODE (*(volatile uint32_t *) 0x40054004) +#define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008) +#define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8) + +#endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */ diff --git a/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c b/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c new file mode 100644 index 0000000000..187b4b310b --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c @@ -0,0 +1,372 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief Interrupt support. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#include <bsp.h> +#include <bsp/irq.h> +#include <bsp/irq-generic.h> +#include <bsp/lpc32xx.h> + +/* + * Mask out SIC 1 and 2 IRQ request. There is no need to mask out the FIQ, + * since a pending FIQ would be a fatal error. The default handler will be + * invoked in this case. + */ +#define LPC32XX_MIC_STATUS_MASK (~0x3U) + +typedef union { + struct { + uint32_t mic; + uint32_t sic_1; + uint32_t sic_2; + } field; + uint32_t fields_table [LPC32XX_IRQ_MODULE_COUNT]; +} lpc32xx_irq_fields; + +typedef struct { + uint32_t er; + uint32_t rsr; + uint32_t sr; + uint32_t apr; + uint32_t atr; + uint32_t itr; +} lpc32xx_irq_controller; + +static volatile lpc32xx_irq_controller *const lpc32xx_mic = (volatile lpc32xx_irq_controller *) LPC32XX_BASE_MIC; + +static volatile lpc32xx_irq_controller *const lpc32xx_sic_1 = (volatile lpc32xx_irq_controller *) LPC32XX_BASE_SIC_1; + +static volatile lpc32xx_irq_controller *const lpc32xx_sic_2 = (volatile lpc32xx_irq_controller *) LPC32XX_BASE_SIC_2; + +static uint8_t lpc32xx_irq_priority_table [LPC32XX_IRQ_COUNT]; + +static lpc32xx_irq_fields lpc32xx_irq_priority_masks [LPC32XX_IRQ_PRIORITY_COUNT]; + +static lpc32xx_irq_fields lpc32xx_irq_enable; + +static inline bool lpc32xx_irq_is_valid(rtems_vector_number vector) +{ + return vector <= BSP_INTERRUPT_VECTOR_MAX; +} + +static inline bool lpc32xx_irq_priority_is_valid(unsigned priority) +{ + return priority <= LPC32XX_IRQ_PRIORITY_LOWEST; +} + +#define LPC32XX_IRQ_BIT_OPS_DEFINE \ + unsigned bit = index & 0x1fU; \ + unsigned module = index >> 5 + +#define LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE \ + LPC32XX_IRQ_BIT_OPS_DEFINE; \ + unsigned module_offset = module << 14; \ + volatile uint32_t *reg = \ + (volatile uint32_t *) (LPC32XX_BASE_MIC + module_offset + register_offset) + +#define LPC32XX_IRQ_OFFSET_ER 0U +#define LPC32XX_IRQ_OFFSET_RSR 4U +#define LPC32XX_IRQ_OFFSET_SR 8U +#define LPC32XX_IRQ_OFFSET_APR 12U +#define LPC32XX_IRQ_OFFSET_ATR 16U +#define LPC32XX_IRQ_OFFSET_ITR 20U + +static inline bool lpc32xx_irq_is_bit_set_in_register(unsigned index, unsigned register_offset) +{ + LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE; + + return *reg & (1U << bit); +} + +static inline void lpc32xx_irq_set_bit_in_register(unsigned index, unsigned register_offset) +{ + LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE; + + *reg |= 1U << bit; +} + +static inline void lpc32xx_irq_clear_bit_in_register(unsigned index, unsigned register_offset) +{ + LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE; + + *reg &= ~(1U << bit); +} + +static inline void lpc32xx_irq_set_bit_in_field(unsigned index, lpc32xx_irq_fields *fields) +{ + LPC32XX_IRQ_BIT_OPS_DEFINE; + + fields->fields_table [module] |= 1U << bit; +} + +static inline void lpc32xx_irq_clear_bit_in_field(unsigned index, lpc32xx_irq_fields *fields) +{ + LPC32XX_IRQ_BIT_OPS_DEFINE; + + fields->fields_table [module] &= ~bit; +} + +static inline unsigned lpc32xx_irq_get_index(uint32_t val) +{ + uint32_t reg; + + asm volatile ( + THUMB_TO_ARM + "clz %1, %1\n" + "rsb %1, %1, #31\n" + ARM_TO_THUMB + : "=&r" (reg), "=r" (val) + : "1" (val) + ); + + return val; +} + +void lpc32xx_irq_set_priority(rtems_vector_number vector, unsigned priority) +{ + if (lpc32xx_irq_is_valid(vector)) { + rtems_interrupt_level level; + unsigned i = 0; + + if (priority > LPC32XX_IRQ_PRIORITY_LOWEST) { + priority = LPC32XX_IRQ_PRIORITY_LOWEST; + } + + lpc32xx_irq_priority_table [vector] = (uint8_t) priority; + + for (i = LPC32XX_IRQ_PRIORITY_HIGHEST; i <= priority; ++i) { + rtems_interrupt_disable(level); + lpc32xx_irq_clear_bit_in_field(vector, &lpc32xx_irq_priority_masks [i]); + rtems_interrupt_enable(level); + } + + for (i = priority + 1; i <= LPC32XX_IRQ_PRIORITY_LOWEST; ++i) { + rtems_interrupt_disable(level); + lpc32xx_irq_set_bit_in_field(vector, &lpc32xx_irq_priority_masks [i]); + rtems_interrupt_enable(level); + } + } +} + +unsigned lpc32xx_irq_get_priority(rtems_vector_number vector) +{ + if (lpc32xx_irq_is_valid(vector)) { + return lpc32xx_irq_priority_table [vector]; + } else { + return LPC32XX_IRQ_PRIORITY_LOWEST; + } +} + +void lpc32xx_irq_set_activation_polarity(rtems_vector_number vector, lpc32xx_irq_activation_polarity activation_polarity) +{ + if (lpc32xx_irq_is_valid(vector)) { + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + if (activation_polarity == LPC32XX_IRQ_ACTIVE_HIGH_OR_RISING_EDGE) { + lpc32xx_irq_set_bit_in_register(vector, LPC32XX_IRQ_OFFSET_APR); + } else { + lpc32xx_irq_clear_bit_in_register(vector, LPC32XX_IRQ_OFFSET_APR); + } + rtems_interrupt_enable(level); + } +} + +lpc32xx_irq_activation_polarity lpc32xx_irq_get_activation_polarity(rtems_vector_number vector) +{ + if (lpc32xx_irq_is_valid(vector)) { + if (lpc32xx_irq_is_bit_set_in_register(vector, LPC32XX_IRQ_OFFSET_APR)) { + return LPC32XX_IRQ_ACTIVE_HIGH_OR_RISING_EDGE; + } else { + return LPC32XX_IRQ_ACTIVE_LOW_OR_FALLING_EDGE; + } + } else { + return LPC32XX_IRQ_ACTIVE_LOW_OR_FALLING_EDGE; + } +} + +void lpc32xx_irq_set_activation_type(rtems_vector_number vector, lpc32xx_irq_activation_type activation_type) +{ + if (lpc32xx_irq_is_valid(vector)) { + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + if (activation_type == LPC32XX_IRQ_EDGE_SENSITIVE) { + lpc32xx_irq_set_bit_in_register(vector, LPC32XX_IRQ_OFFSET_ATR); + } else { + lpc32xx_irq_clear_bit_in_register(vector, LPC32XX_IRQ_OFFSET_ATR); + } + rtems_interrupt_enable(level); + } +} + +lpc32xx_irq_activation_type lpc32xx_irq_get_activation_type(rtems_vector_number vector) +{ + if (lpc32xx_irq_is_valid(vector)) { + if (lpc32xx_irq_is_bit_set_in_register(vector, LPC32XX_IRQ_OFFSET_ATR)) { + return LPC32XX_IRQ_EDGE_SENSITIVE; + } else { + return LPC32XX_IRQ_LEVEL_SENSITIVE; + } + } else { + return LPC32XX_IRQ_LEVEL_SENSITIVE; + } +} + +void bsp_interrupt_dispatch(void) +{ + uint32_t status = lpc32xx_mic->sr & LPC32XX_MIC_STATUS_MASK; + uint32_t er_mic = lpc32xx_mic->er; + uint32_t er_sic_1 = lpc32xx_sic_1->er; + uint32_t er_sic_2 = lpc32xx_sic_2->er; + uint32_t psr = 0; + lpc32xx_irq_fields *masks = NULL; + rtems_vector_number vector = 0; + unsigned priority = 0; + + if (status != 0) { + vector = lpc32xx_irq_get_index(status); + } else { + status = lpc32xx_sic_1->sr; + if (status != 0) { + vector = lpc32xx_irq_get_index(status) + LPC32XX_IRQ_MODULE_SIC_1; + } else { + status = lpc32xx_sic_2->sr; + if (status != 0) { + vector = lpc32xx_irq_get_index(status) + LPC32XX_IRQ_MODULE_SIC_2; + } else { + return; + } + } + } + + priority = lpc32xx_irq_priority_table [vector]; + + masks = &lpc32xx_irq_priority_masks [priority]; + + lpc32xx_mic->er = er_mic & masks->field.mic; + lpc32xx_sic_1->er = er_sic_1 & masks->field.sic_1; + lpc32xx_sic_2->er = er_sic_2 & masks->field.sic_2; + + psr = arm_status_irq_enable(); + + bsp_interrupt_handler_dispatch(vector); + + arm_status_restore(psr); + + lpc32xx_mic->er = er_mic & lpc32xx_irq_enable.field.mic; + lpc32xx_sic_1->er = er_sic_1 & lpc32xx_irq_enable.field.sic_1; + lpc32xx_sic_2->er = er_sic_2 & lpc32xx_irq_enable.field.sic_2; +} + +rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) +{ + if (lpc32xx_irq_is_valid(vector)) { + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + lpc32xx_irq_set_bit_in_register(vector, LPC32XX_IRQ_OFFSET_ER); + lpc32xx_irq_set_bit_in_field(vector, &lpc32xx_irq_enable); + rtems_interrupt_enable(level); + } + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) +{ + if (lpc32xx_irq_is_valid(vector)) { + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + lpc32xx_irq_clear_bit_in_field(vector, &lpc32xx_irq_enable); + lpc32xx_irq_clear_bit_in_register(vector, LPC32XX_IRQ_OFFSET_ER); + rtems_interrupt_enable(level); + } + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_facility_initialize(void) +{ + size_t i = 0; + + /* Set default priority */ + for (i = 0; i < LPC32XX_IRQ_COUNT; ++i) { + lpc32xx_irq_priority_table [i] = LPC32XX_IRQ_PRIORITY_LOWEST; + } + + /* Enable SIC 1 and 2 at all priorities */ + for (i = 0; i < LPC32XX_IRQ_PRIORITY_COUNT; ++i) { + lpc32xx_irq_priority_masks [i].field.mic = 0xc0000003; + } + + /* Disable all interrupts except SIC 1 and 2 */ + lpc32xx_irq_enable.field.sic_2 = 0x0; + lpc32xx_irq_enable.field.sic_1 = 0x0; + lpc32xx_irq_enable.field.mic = 0xc0000003; + lpc32xx_sic_1->er = 0x0; + lpc32xx_sic_2->er = 0x0; + lpc32xx_mic->er = 0xc0000003; + + /* Set interrupt types to IRQ */ + lpc32xx_mic->itr = 0x0; + lpc32xx_sic_1->itr = 0x0; + lpc32xx_sic_2->itr = 0x0; + + /* Set interrupt activation polarities */ + lpc32xx_mic->apr = 0x3ff0efe0; + lpc32xx_sic_1->apr = 0xfbd27184; + lpc32xx_sic_2->apr = 0x801810c0; + + /* Set interrupt activation types */ + lpc32xx_mic->atr = 0x0; + lpc32xx_sic_1->atr = 0x26000; + lpc32xx_sic_2->atr = 0x0; + + _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL); + + return RTEMS_SUCCESSFUL; +} + +void bsp_interrupt_handler_default(rtems_vector_number vector) +{ + printk("spurious interrupt: %u\n", vector); +} + +static void lpc32xx_irq_dump_controller(volatile lpc32xx_irq_controller *controller) +{ + printk( + "er %08x\nrsr %08x\nsr %08x\napr %08x\natr %08x\nitr %08x\n", + controller->er, + controller->rsr, + controller->sr, + controller->apr, + controller->atr, + controller->itr + ); +} + +void lpc32xx_irq_dump(void) +{ + lpc32xx_irq_dump_controller(lpc32xx_mic); + lpc32xx_irq_dump_controller(lpc32xx_sic_1); + lpc32xx_irq_dump_controller(lpc32xx_sic_2); +} diff --git a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_phycore.cfg b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_phycore.cfg new file mode 100644 index 0000000000..3dbb643ba1 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_phycore.cfg @@ -0,0 +1,14 @@ +# +# Config file for Phycore LPC3250 board. +# +# $Id$ +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = arm + +CPU_CFLAGS = -mcpu=arm926ej-s -mthumb -mstructure-size-boundary=8 \ + -Wextra -Wno-unused -Wpointer-arith -Wcast-qual -Wconversion -Wmissing-prototypes + +CFLAGS_OPTIMIZE_V = -Os -g diff --git a/c/src/lib/libbsp/arm/lpc32xx/misc/timer.c b/c/src/lib/libbsp/arm/lpc32xx/misc/timer.c new file mode 100644 index 0000000000..5c0246133c --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/misc/timer.c @@ -0,0 +1,55 @@ +/** + * @file + * + * @ingroup lpc32xx + * + * @brief Benchmark timer support. + */ + +/* + * Copyright (c) 2008, 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#include <rtems.h> +#include <rtems/timerdrv.h> + +static bool benchmark_timer_find_average_overhead = false; + +static uint32_t benchmark_timer_base; + +/* TODO */ +static uint32_t lpc32xx_timer(void) +{ + return 0; +} + +void benchmark_timer_initialize(void) +{ + benchmark_timer_base = lpc32xx_timer(); +} + +uint32_t benchmark_timer_read(void) +{ + uint32_t delta = lpc32xx_timer() - benchmark_timer_base; + + if (benchmark_timer_find_average_overhead) { + return delta; + } else { + /* TODO */ + return 0; + } +} + +void benchmark_timer_disable_subtracting_average_overhead(bool find_average_overhead) +{ + benchmark_timer_find_average_overhead = find_average_overhead; +} diff --git a/c/src/lib/libbsp/arm/lpc32xx/preinstall.am b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am new file mode 100644 index 0000000000..3f2aa0c774 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am @@ -0,0 +1,119 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES = $(TMPINSTALL_FILES) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) + +$(PROJECT_LIB)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_LIB) + @: > $(PROJECT_LIB)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) + +$(PROJECT_INCLUDE)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE) + @: > $(PROJECT_INCLUDE)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) + +$(PROJECT_INCLUDE)/bsp/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp + @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) + +$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs +PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs + +$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h + +$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h + +$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h + +$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h + +$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h + +$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h + +$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h + +$(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h + +$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h + +$(PROJECT_INCLUDE)/bsp/linker-symbols.h: ../shared/include/linker-symbols.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/linker-symbols.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/linker-symbols.h + +$(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start.h + +$(PROJECT_INCLUDE)/bsp/lpc-timer.h: ../shared/lpc/include/lpc-timer.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-timer.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-timer.h + +$(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h + +$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h + +$(PROJECT_INCLUDE)/bsp/lpc32xx.h: include/lpc32xx.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc32xx.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc32xx.h + +$(PROJECT_INCLUDE)/bsp/lpc-clock-config.h: include/lpc-clock-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-clock-config.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-clock-config.h + +$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h + +$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) +TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) + +$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds + +$(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base +TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base + diff --git a/c/src/lib/libbsp/arm/lpc32xx/rtc/rtc-config.c b/c/src/lib/libbsp/arm/lpc32xx/rtc/rtc-config.c new file mode 100644 index 0000000000..35a2c75be9 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/rtc/rtc-config.c @@ -0,0 +1,93 @@ +/** + * @file + * + * @ingroup lpc32xx + * + * @brief RTC configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#include <libchip/rtc.h> + +#include <bsp/lpc32xx.h> + +#define LPC32XX_RTC_COUNT 1 + +static void lpc32xx_rtc_initialize(int minor) +{ + /* TODO */ +} + +static int lpc32xx_rtc_get_time(int minor, rtems_time_of_day *tod) +{ + /* TODO */ + +#if 0 + tod->ticks = 0; + tod->second = RTC_SEC; + tod->minute = RTC_MIN; + tod->hour = RTC_HOUR; + tod->day = RTC_DOM; + tod->month = RTC_MONTH; + tod->year = RTC_YEAR; +#endif + + return 0; +} + +static int lpc32xx_rtc_set_time(int minor, const rtems_time_of_day *tod) +{ + /* TODO */ + +#if 0 + RTC_SEC = tod->second; + RTC_MIN = tod->minute; + RTC_HOUR = tod->hour; + RTC_DOM = tod->day; + RTC_MONTH = tod->month; + RTC_YEAR = tod->year; +#endif + + return 0; +} + +static bool lpc32xx_rtc_probe(int minor) +{ + return true; +} + +const rtc_fns lpc32xx_rtc_ops = { + .deviceInitialize = lpc32xx_rtc_initialize, + .deviceGetTime = lpc32xx_rtc_get_time, + .deviceSetTime = lpc32xx_rtc_set_time +}; + +unsigned long RTC_Count = LPC32XX_RTC_COUNT; + +rtems_device_minor_number RTC_Minor = 0; + +rtc_tbl RTC_Table [LPC32XX_RTC_COUNT] = { + { + .sDeviceName = "/dev/rtc", + .deviceType = RTC_CUSTOM, + .pDeviceFns = &lpc32xx_rtc_ops, + .deviceProbe = lpc32xx_rtc_probe, + .pDeviceParams = NULL, + .ulCtrlPort1 = 0, + .ulDataPort = 0, + .getRegister = NULL, + .setRegister = NULL + } +}; diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/bspreset.c b/c/src/lib/libbsp/arm/lpc32xx/startup/bspreset.c new file mode 100644 index 0000000000..76534449fd --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/startup/bspreset.c @@ -0,0 +1,31 @@ +/** + * @file + * + * @ingroup lpc32xx + * + * @brief Reset code. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#include <rtems.h> + +#include <bsp/bootcard.h> + +void bsp_reset( void) +{ + while (true) { + /* Do nothing */ + } +} diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c new file mode 100644 index 0000000000..02247bb96c --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c @@ -0,0 +1,123 @@ +/** + * @file + * + * @ingroup lpc32xx + * + * @brief Startup code. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#include <bsp.h> +#include <bsp/bootcard.h> +#include <bsp/irq-generic.h> +#include <bsp/irq.h> +#include <bsp/linker-symbols.h> +#include <bsp/stackalloc.h> +#include <bsp/lpc32xx.h> + +/* FIXME */ +#define CONSOLE_RBR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00)) +#define CONSOLE_THR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00)) +#define CONSOLE_DLL (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00)) +#define CONSOLE_DLM (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x04)) +#define CONSOLE_IER (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x04)) +#define CONSOLE_IIR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x08)) +#define CONSOLE_FCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x08)) +#define CONSOLE_LCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x0C)) +#define CONSOLE_LSR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x14)) +#define CONSOLE_SCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x1C)) +#define CONSOLE_ACR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x20)) +#define CONSOLE_ICR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x24)) +#define CONSOLE_FDR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x28)) +#define CONSOLE_TER (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x30)) + +void bsp_start(void) +{ + #ifdef LPC32XX_CONFIG_U3CLK + LPC32XX_U3CLK = LPC32XX_CONFIG_U3CLK; + #endif + #ifdef LPC32XX_CONFIG_U4CLK + LPC32XX_U4CLK = LPC32XX_CONFIG_U4CLK; + #endif + #ifdef LPC32XX_CONFIG_U5CLK + LPC32XX_U5CLK = LPC32XX_CONFIG_U5CLK; + #endif + #ifdef LPC32XX_CONFIG_U6CLK + LPC32XX_U6CLK = LPC32XX_CONFIG_U6CLK; + #endif + + #ifdef LPC32XX_CONFIG_UART_CLKMODE + LPC32XX_UART_CLKMODE = LPC32XX_CONFIG_UART_CLKMODE; + #endif + + LPC32XX_UART_CTRL = 0x0; + LPC32XX_UART_LOOP = 0x0; + + /* FIXME */ + CONSOLE_LCR = 0x0; + CONSOLE_IER = 0x0; + CONSOLE_LCR = 0x80; + CONSOLE_DLL = 0x1; /* Clock is already set in LPC32XX_U5CLK */ + CONSOLE_DLM = 0x0; + CONSOLE_LCR = 0x3; + CONSOLE_FCR = 0x7; + +#if 0 + /* FIXME */ + printk("LPC32XX_U3CLK %08x\n", LPC32XX_U3CLK); + printk("LPC32XX_U4CLK %08x\n", LPC32XX_U4CLK); + printk("LPC32XX_U5CLK %08x\n", LPC32XX_U5CLK); + printk("LPC32XX_U6CLK %08x\n", LPC32XX_U6CLK); + printk("LPC32XX_IRDACLK %08x\n", LPC32XX_IRDACLK); + printk("LPC32XX_UART_CTRL %08x\n", LPC32XX_UART_CTRL); + printk("LPC32XX_UART_CLKMODE %08x\n", LPC32XX_UART_CLKMODE); + printk("LPC32XX_UART_LOOP %08x\n", LPC32XX_UART_LOOP); +#endif + + /* Interrupts */ + if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) { + _CPU_Fatal_halt(0xe); + } + + /* Task stacks */ + bsp_stack_initialize( + bsp_section_stack_begin, + (uintptr_t) bsp_section_stack_size + ); +} + +#define UART_LSR_THRE 0x00000020U + +static void lpc32xx_console_wait(void) +{ + while ((CONSOLE_LSR & UART_LSR_THRE) == 0) { + /* Wait */ + } +} + +static void lpc32xx_BSP_output_char(char c) +{ + lpc32xx_console_wait(); + + CONSOLE_THR = c; + + if (c == '\n') { + lpc32xx_console_wait(); + + CONSOLE_THR = '\r'; + } +} + +BSP_output_char_function_type BSP_output_char = lpc32xx_BSP_output_char; diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c new file mode 100644 index 0000000000..7f668f83c5 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c @@ -0,0 +1,84 @@ +/** + * @file + * + * @ingroup lpc32xx + * + * @brief Startup code. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#include <stdbool.h> + +#include <bspopts.h> +#include <bsp/start.h> +#include <bsp/lpc32xx.h> +#include <bsp/linker-symbols.h> + +#define BSP_START_SECTION __attribute__((section(".bsp_start"))) + +static void BSP_START_SECTION lpc32xx_clear_bss(void) +{ + const int *end = (const int *) bsp_section_bss_end; + int *out = (int *) bsp_section_bss_begin; + + /* Clear BSS */ + while (out != end) { + *out = 0; + ++out; + } +} + +void BSP_START_SECTION bsp_start_hook_0(void) +{ + /* TODO */ +} + +void BSP_START_SECTION bsp_start_hook_1(void) +{ + /* TODO */ + + /* Copy .text section */ + bsp_start_memcpy_arm( + (int *) bsp_section_text_begin, + (const int *) bsp_section_text_load_begin, + (size_t) bsp_section_text_size + ); + + /* Copy .rodata section */ + bsp_start_memcpy_arm( + (int *) bsp_section_rodata_begin, + (const int *) bsp_section_rodata_load_begin, + (size_t) bsp_section_rodata_size + ); + + /* Copy .data section */ + bsp_start_memcpy_arm( + (int *) bsp_section_data_begin, + (const int *) bsp_section_data_load_begin, + (size_t) bsp_section_data_size + ); + + /* Copy .fast section */ + bsp_start_memcpy_arm( + (int *) bsp_section_fast_begin, + (const int *) bsp_section_fast_load_begin, + (size_t) bsp_section_fast_size + ); + + /* Clear .bss section */ + lpc32xx_clear_bss(); + + /* At this point we can use objects outside the .start section */ +} diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_phycore b/c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_phycore new file mode 100644 index 0000000000..8003ecc996 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_phycore @@ -0,0 +1,60 @@ +/** + * @file + * + * @ingroup lpc32xx_linker_phycore + * + * @brief Memory map. + */ + +/** + * @defgroup lpc32xx_linker_phycore phyCORE-LPC3250 Memory Map + * + * @ingroup bsp_linker + * + * @brief phyCORE-LPC3250 memory map. + * + * <table> + * <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr> + * <tr><td>RAM_INT</td><td>0x08000000</td><td>256k</td></tr> + * <tr><td>RAM_EXT</td><td>0x80000000</td><td>64M</td></tr> + * <tr><td>ROM_EXT</td><td>0xe0000000</td><td>2M</td></tr> + * </table> + * + * <table> + * <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr> + * <tr><td>.start</td><td>RAM_EXT</td><td></td></tr> + * <tr><td>.vector</td><td>RAM_INT</td><td></td></tr> + * <tr><td>.text</td><td>RAM_EXT</td><td>RAM_EXT</td></tr> + * <tr><td>.rodata</td><td>RAM_EXT</td><td>RAM_EXT</td></tr> + * <tr><td>.data</td><td>RAM_EXT</td><td>RAM_EXT</td></tr> + * <tr><td>.fast</td><td>RAM_EXT</td><td>RAM_EXT</td></tr> + * <tr><td>.bss</td><td>RAM_EXT</td><td></td></tr> + * <tr><td>.work</td><td>RAM_EXT</td><td></td></tr> + * <tr><td>.stack</td><td>RAM_INT</td><td></td></tr> + * </table> + */ + +MEMORY { + RAM_INT (AIW) : ORIGIN = 0x08000000, LENGTH = 256k + RAM_EXT (AIW) : ORIGIN = 0x80000000, LENGTH = 64M /* SDRAM on DYCS0 */ + ROM_EXT (RX) : ORIGIN = 0xe0000000, LENGTH = 2M /* NOR flash on CS0 */ + NIRVANA : ORIGIN = 0, LENGTH = 0 +} + +REGION_ALIAS ("REGION_START", RAM_EXT); +REGION_ALIAS ("REGION_VECTOR", RAM_INT); +REGION_ALIAS ("REGION_TEXT", RAM_EXT); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_RODATA", RAM_EXT); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_DATA", RAM_EXT); +REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_FAST", RAM_EXT); +REGION_ALIAS ("REGION_FAST_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_BSS", RAM_EXT); +REGION_ALIAS ("REGION_WORK", RAM_EXT); +REGION_ALIAS ("REGION_STACK", RAM_INT); + +bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096; + +INCLUDE linkcmds.base |