2010-05-20 Sebastian Huber <sebastian.huber@embedded-brains.de>

	* make/custom/lpc32xx.inc, make/custom/lpc32xx_mzx_boot_int.cfg,
	startup/linkcmds.lpc32xx_mzx_boot_int: New files.
	* Makefile.am, configure.ac, preinstall.am, include/bsp.h,
	include/bspopts.h.in, include/lpc32xx.h, irq/irq.c,
	make/custom/lpc32xx_phycore.cfg, startup/bspstart.c,
	startup/bspstarthooks.c: Changes throughout.

3 files changed, 199 insertions, 170 deletions

diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c
index a005054222..c8f0a728ba 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c
+++ b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c
@@ -7,7 +7,7 @@
  */
 
 /*
- * Copyright (c) 2009
+ * Copyright (c) 2009, 2010
  * embedded brains GmbH
  * Obere Lagerstr. 30
  * D-82178 Puchheim
@@ -27,22 +27,6 @@
 #include <bsp/stackalloc.h>
 #include <bsp/lpc32xx.h>
 
-/* FIXME */
-#define CONSOLE_RBR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00))
-#define CONSOLE_THR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00))
-#define CONSOLE_DLL (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00))
-#define CONSOLE_DLM (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x04))
-#define CONSOLE_IER (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x04))
-#define CONSOLE_IIR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x08))
-#define CONSOLE_FCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x08))
-#define CONSOLE_LCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x0C))
-#define CONSOLE_LSR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x14))
-#define CONSOLE_SCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x1C))
-#define CONSOLE_ACR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x20))
-#define CONSOLE_ICR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x24))
-#define CONSOLE_FDR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x28))
-#define CONSOLE_TER (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x30))
-
 static void lpc32xx_timer_initialize(void)
 {
   volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER;
@@ -60,42 +44,6 @@ static void lpc32xx_timer_initialize(void)
 
 void bsp_start(void)
 {
-  uint32_t uartclk_ctrl = 0;
-
-  #ifdef LPC32XX_CONFIG_U3CLK
-    uartclk_ctrl |= 1U << 0;
-    LPC32XX_U3CLK = LPC32XX_CONFIG_U3CLK;
-  #endif
-  #ifdef LPC32XX_CONFIG_U4CLK
-    uartclk_ctrl |= 1U << 1;
-    LPC32XX_U4CLK = LPC32XX_CONFIG_U4CLK;
-  #endif
-  #ifdef LPC32XX_CONFIG_U5CLK
-    uartclk_ctrl |= 1U << 2;
-    LPC32XX_U5CLK = LPC32XX_CONFIG_U5CLK;
-  #endif
-  #ifdef LPC32XX_CONFIG_U6CLK
-    uartclk_ctrl |= 1U << 3;
-    LPC32XX_U6CLK = LPC32XX_CONFIG_U6CLK;
-  #endif
-
-  #ifdef LPC32XX_CONFIG_UART_CLKMODE
-    LPC32XX_UART_CLKMODE = LPC32XX_CONFIG_UART_CLKMODE;
-  #endif
-
-  LPC32XX_UARTCLK_CTRL = uartclk_ctrl;
-  LPC32XX_UART_CTRL = 0x0;
-  LPC32XX_UART_LOOP = 0x0;
-
-  /* FIXME */
-  CONSOLE_LCR = 0x0;
-  CONSOLE_IER = 0x0;
-  CONSOLE_LCR = 0x80;
-  CONSOLE_DLL = 0x1; /* Clock is already set in LPC32XX_U5CLK */
-  CONSOLE_DLM = 0x0;
-  CONSOLE_LCR = 0x3;
-  CONSOLE_FCR = 0x7;
-
   if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
     _CPU_Fatal_halt(0xe);
   }
@@ -107,27 +55,3 @@ void bsp_start(void)
 
   lpc32xx_timer_initialize();
 }
-
-#define UART_LSR_THRE 0x00000020U
-
-static void lpc32xx_console_wait(void)
-{
-  while ((CONSOLE_LSR & UART_LSR_THRE) == 0) {
-    /* Wait */
-  }
-}
-
-static void lpc32xx_BSP_output_char(char c)
-{
-  lpc32xx_console_wait();
-
-  CONSOLE_THR = c;
-
-  if (c == '\n') {
-    lpc32xx_console_wait();
-
-    CONSOLE_THR = '\r';
-  }
-}
-
-BSP_output_char_function_type BSP_output_char = lpc32xx_BSP_output_char;
diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c
index 32c9f1a3d1..7c9c7fec5e 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c
+++ b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c
@@ -26,6 +26,7 @@
 #include <bsp/lpc32xx.h>
 #include <bsp/mmu.h>
 #include <bsp/linker-symbols.h>
+#include <bsp/uart-output-char.h>
 
 #ifdef LPC32XX_DISABLE_READ_WRITE_DATA_CACHE
   #define LPC32XX_MMU_READ_WRITE_DATA LPC32XX_MMU_READ_WRITE
@@ -56,94 +57,118 @@ static void BSP_START_SECTION lpc32xx_clear_bss(void)
   }
 }
 
-typedef struct {
-  uint32_t begin;
-  uint32_t end;
-  uint32_t flags;
-} lpc32xx_mmu_config;
+#ifndef LPC32XX_DISABLE_MMU
+  typedef struct {
+    uint32_t begin;
+    uint32_t end;
+    uint32_t flags;
+  } lpc32xx_mmu_config;
 
-static const BSP_START_DATA_SECTION lpc32xx_mmu_config
-  lpc32xx_mmu_config_table [] = {
+  static const BSP_START_DATA_SECTION lpc32xx_mmu_config
+    lpc32xx_mmu_config_table [] = {
+    {
+      .begin = (uint32_t) bsp_section_start_begin,
+      .end = (uint32_t) bsp_section_start_end,
+      .flags = LPC32XX_MMU_CODE
+    }, {
+      .begin = (uint32_t) bsp_section_vector_begin,
+      .end = (uint32_t) bsp_section_vector_end,
+      .flags = LPC32XX_MMU_READ_WRITE_CACHED
+    }, {
+      .begin = (uint32_t) bsp_section_text_begin,
+      .end = (uint32_t) bsp_section_text_end,
+      .flags = LPC32XX_MMU_CODE
+    }, {
+      .begin = (uint32_t) bsp_section_rodata_begin,
+      .end = (uint32_t) bsp_section_rodata_end,
+      .flags = LPC32XX_MMU_READ_ONLY_DATA
+    }, {
+      .begin = (uint32_t) bsp_section_data_begin,
+      .end = (uint32_t) bsp_section_data_end,
+      .flags = LPC32XX_MMU_READ_WRITE_DATA
+    }, {
+      .begin = (uint32_t) bsp_section_fast_begin,
+      .end = (uint32_t) bsp_section_fast_end,
+      .flags = LPC32XX_MMU_CODE
+    }, {
+      .begin = (uint32_t) bsp_section_bss_begin,
+      .end = (uint32_t) bsp_section_bss_end,
+      .flags = LPC32XX_MMU_READ_WRITE_DATA
+    }, {
+      .begin = (uint32_t) bsp_section_work_begin,
+      .end = (uint32_t) bsp_section_work_end,
+      .flags = LPC32XX_MMU_READ_WRITE_DATA
+    }, {
+      .begin = (uint32_t) bsp_section_stack_begin,
+      .end = (uint32_t) bsp_section_stack_end,
+      .flags = LPC32XX_MMU_READ_WRITE_DATA
+    }, {
+      .begin = 0x0U,
+      .end = 0x100000U,
+      .flags = LPC32XX_MMU_READ_ONLY_CACHED
+    }, {
+      .begin = 0x20000000U,
+      .end = 0x200c0000U,
+      .flags = LPC32XX_MMU_READ_WRITE
+    }, {
+      .begin = 0x30000000U,
+      .end = 0x32000000U,
+      .flags = LPC32XX_MMU_READ_WRITE
+    }, {
+      .begin = 0x40000000U,
+      .end = 0x40100000U,
+      .flags = LPC32XX_MMU_READ_WRITE
+    }
+  };
+
+  static void BSP_START_SECTION lpc32xx_mmu_set_entries(
+    uint32_t *ttb,
+    const lpc32xx_mmu_config *config
+  )
   {
-    .begin = (uint32_t) bsp_section_start_begin,
-    .end = (uint32_t) bsp_section_start_end,
-    .flags = LPC32XX_MMU_CODE
-  }, {
-    .begin = (uint32_t) bsp_section_vector_begin,
-    .end = (uint32_t) bsp_section_vector_end,
-    .flags = LPC32XX_MMU_READ_WRITE_CACHED
-  }, {
-    .begin = (uint32_t) bsp_section_text_begin,
-    .end = (uint32_t) bsp_section_text_end,
-    .flags = LPC32XX_MMU_CODE
-  }, {
-    .begin = (uint32_t) bsp_section_rodata_begin,
-    .end = (uint32_t) bsp_section_rodata_end,
-    .flags = LPC32XX_MMU_READ_ONLY_DATA
-  }, {
-    .begin = (uint32_t) bsp_section_data_begin,
-    .end = (uint32_t) bsp_section_data_end,
-    .flags = LPC32XX_MMU_READ_WRITE_DATA
-  }, {
-    .begin = (uint32_t) bsp_section_fast_begin,
-    .end = (uint32_t) bsp_section_fast_end,
-    .flags = LPC32XX_MMU_CODE
-  }, {
-    .begin = (uint32_t) bsp_section_bss_begin,
-    .end = (uint32_t) bsp_section_bss_end,
-    .flags = LPC32XX_MMU_READ_WRITE_DATA
-  }, {
-    .begin = (uint32_t) bsp_section_work_begin,
-    .end = (uint32_t) bsp_section_work_end,
-    .flags = LPC32XX_MMU_READ_WRITE_DATA
-  }, {
-    .begin = (uint32_t) bsp_section_stack_begin,
-    .end = (uint32_t) bsp_section_stack_end,
-    .flags = LPC32XX_MMU_READ_WRITE_DATA
-  }, {
-    .begin = 0x0U,
-    .end = 0x100000U,
-    .flags = LPC32XX_MMU_READ_ONLY_CACHED
-  }, {
-    .begin = 0x20000000U,
-    .end = 0x200c0000U,
-    .flags = LPC32XX_MMU_READ_WRITE
-  }, {
-    .begin = 0x30000000U,
-    .end = 0x32000000U,
-    .flags = LPC32XX_MMU_READ_WRITE
-  }, {
-    .begin = 0x40000000U,
-    .end = 0x40100000U,
-    .flags = LPC32XX_MMU_READ_WRITE
+    uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin);
+    uint32_t iend =
+      ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end));
+
+    if (config->begin != config->end) {
+      while (i < iend) {
+        ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags;
+        ++i;
+      }
+    }
   }
-};
 
-static void BSP_START_SECTION lpc32xx_mmu_set_entries(
-  uint32_t *ttb,
-  const lpc32xx_mmu_config *config
-)
-{
-  uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin);
-  uint32_t iend = ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end));
+  static void BSP_START_SECTION
+    lpc32xx_setup_translation_table_and_enable_mmu(uint32_t ctrl)
+  {
+    uint32_t const dac =
+      ARM_CP15_DAC_DOMAIN(LPC32XX_MMU_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT);
+    uint32_t *const ttb = (uint32_t *) bsp_section_work_end;
+    size_t const config_entry_count =
+      sizeof(lpc32xx_mmu_config_table) / sizeof(lpc32xx_mmu_config_table [0]);
+    size_t i = 0;
+
+    arm_cp15_set_domain_access_control(dac);
+    arm_cp15_set_translation_table_base(ttb);
 
-  if (config->begin != config->end) {
-    while (i < iend) {
-      ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags;
-      ++i;
+    /* Initialize translation table with invalid entries */
+    for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) {
+      ttb [i] = 0;
     }
+
+    for (i = 0; i < config_entry_count; ++i) {
+      lpc32xx_mmu_set_entries(ttb, &lpc32xx_mmu_config_table [i]);
+    }
+
+    /* Enable MMU and cache */
+    ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
+    arm_cp15_set_control(ctrl);
   }
-}
+#endif
 
 static void BSP_START_SECTION lpc32xx_mmu_and_cache_setup(void)
 {
-  uint32_t const dac =
-    ARM_CP15_DAC_DOMAIN(LPC32XX_MMU_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT);
   uint32_t ctrl = 0;
-  uint32_t *const ttb = (uint32_t *) bsp_section_work_end;
-  size_t const config_entry_count =
-    sizeof(lpc32xx_mmu_config_table) / sizeof(lpc32xx_mmu_config_table [0]);
-  size_t i = 0;
 
   /* Disable MMU and cache, basic settings */
   ctrl = arm_cp15_get_control();
@@ -155,21 +180,9 @@ static void BSP_START_SECTION lpc32xx_mmu_and_cache_setup(void)
   arm_cp15_cache_invalidate();
   arm_cp15_tlb_invalidate();
 
-  arm_cp15_set_domain_access_control(dac);
-  arm_cp15_set_translation_table_base(ttb);
-
-  /* Initialize translation table with invalid entries */
-  for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) {
-    ttb [i] = 0;
-  }
-
-  for (i = 0; i < config_entry_count; ++i) {
-    lpc32xx_mmu_set_entries(ttb, &lpc32xx_mmu_config_table [i]);
-  }
-
-  /* Enable MMU and cache */
-  ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
-  arm_cp15_set_control(ctrl);
+  #ifndef LPC32XX_DISABLE_MMU
+    lpc32xx_setup_translation_table_and_enable_mmu(ctrl);
+  #endif
 }
 
 void BSP_START_SECTION bsp_start_hook_0(void)
@@ -177,9 +190,44 @@ void BSP_START_SECTION bsp_start_hook_0(void)
   lpc32xx_mmu_and_cache_setup();
 }
 
+static void BSP_START_SECTION bsp_start_config_uarts(void)
+{
+  uint32_t uartclk_ctrl = 0;
+
+  #ifdef LPC32XX_CONFIG_U3CLK
+    uartclk_ctrl |= 1U << 0;
+    LPC32XX_U3CLK = LPC32XX_CONFIG_U3CLK;
+  #endif
+  #ifdef LPC32XX_CONFIG_U4CLK
+    uartclk_ctrl |= 1U << 1;
+    LPC32XX_U4CLK = LPC32XX_CONFIG_U4CLK;
+  #endif
+  #ifdef LPC32XX_CONFIG_U5CLK
+    uartclk_ctrl |= 1U << 2;
+    LPC32XX_U5CLK = LPC32XX_CONFIG_U5CLK;
+  #endif
+  #ifdef LPC32XX_CONFIG_U6CLK
+    uartclk_ctrl |= 1U << 3;
+    LPC32XX_U6CLK = LPC32XX_CONFIG_U6CLK;
+  #endif
+
+  #ifdef LPC32XX_CONFIG_UART_CLKMODE
+    LPC32XX_UART_CLKMODE = LPC32XX_CONFIG_UART_CLKMODE;
+  #endif
+
+  LPC32XX_UARTCLK_CTRL = uartclk_ctrl;
+  LPC32XX_UART_CTRL = 0x0;
+  LPC32XX_UART_LOOP = 0x0;
+
+  #ifdef LPC32XX_CONFIG_U5CLK
+    /* Clock is already set in LPC32XX_U5CLK */
+    BSP_CONSOLE_UART_INIT(0x01);
+  #endif
+}
+
 void BSP_START_SECTION bsp_start_hook_1(void)
 {
-  /* TODO */
+  bsp_start_config_uarts();
 
   /* Copy .text section */
   arm_cp15_instruction_cache_invalidate();
diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_mzx_boot_int b/c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_mzx_boot_int
new file mode 100644
index 0000000000..54aef5364c
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_mzx_boot_int
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx_linker_boot
+ *
+ * @brief Memory map.
+ */
+
+/**
+ * @defgroup lpc32xx_linker_boot Boot Memory Map
+ *
+ * @ingroup bsp_linker
+ *
+ * @brief Boot memory map.
+ *
+ * <table>
+ *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
+ *   <tr><td>RAM_INT</td><td>0x08000000</td><td>256k</td></tr>
+ * </table>
+ *
+ * <table>
+ *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
+ *   <tr><td>.start</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.text</td><td>RAM_INT</td><td>RAM_INT</td></tr>
+ *   <tr><td>.rodata</td><td>RAM_INT</td><td>RAM_INT</td></tr>
+ *   <tr><td>.data</td><td>RAM_INT</td><td>RAM_INT</td></tr>
+ *   <tr><td>.fast</td><td>RAM_INT</td><td>RAM_INT</td></tr>
+ *   <tr><td>.bss</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.work</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.stack</td><td>RAM_INT</td><td></td></tr>
+ * </table>
+ */
+
+MEMORY {
+        RAM_INT (AIW) : ORIGIN = 0x08000000, LENGTH = 256k
+        NIRVANA : ORIGIN = 0, LENGTH = 0
+}
+
+REGION_ALIAS ("REGION_START", RAM_INT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_TEXT_LOAD", RAM_INT);
+REGION_ALIAS ("REGION_RODATA", RAM_INT);
+REGION_ALIAS ("REGION_RODATA_LOAD", RAM_INT);
+REGION_ALIAS ("REGION_DATA", RAM_INT);
+REGION_ALIAS ("REGION_DATA_LOAD", RAM_INT);
+REGION_ALIAS ("REGION_FAST", RAM_INT);
+REGION_ALIAS ("REGION_FAST_LOAD", RAM_INT);
+REGION_ALIAS ("REGION_BSS", RAM_INT);
+REGION_ALIAS ("REGION_WORK", RAM_INT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+
+bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
+bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
+
+INCLUDE linkcmds.base