2011-03-29 Sebastian Huber <sebastian.huber@embedded-brains.de>

	* configure.ac, include/bspopts.h.in: New BSP option
	LPC32XX_SCRATCH_AREA_SIZE.  Disable BSP option
	LPC32XX_DISABLE_READ_ONLY_PROTECTION for all BSPs.
	* include/boot.h: Removed application specific defines.
	* include/nand-mlc.h, misc/nand-mlc.c: Changed configuration layout.
	* include/mmu.h, misc/mmu.c: Documentation.  Bugfix.
	* include/bsp.h, startup/bspstarthooks.c, misc/restart.c,
	startup/linkcmds.lpc32xx_mzx, startup/linkcmds.lpc32xx_mzx_stage_1,
	startup/linkcmds.lpc32xx_mzx_stage_2,
	startup/linkcmds.lpc32xx_phycore: Support for scratch area.  Moved
	code into macros for reusability.

5 files changed, 101 insertions, 26 deletions

diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/boot.h b/c/src/lib/libbsp/arm/lpc32xx/include/boot.h
index cb8ab5c392..3d11da47d1 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/include/boot.h
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/boot.h
@@ -55,9 +55,8 @@ extern "C" {
  * @{
  */
 
-#define LPC32XX_BOOT_STAGE_1_BLOCK_0 0
-#define LPC32XX_BOOT_STAGE_1_BLOCK_1 1
-#define LPC32XX_BOOT_STAGE_2_BLOCK_0 2
+#define LPC32XX_BOOT_BLOCK_0 0
+#define LPC32XX_BOOT_BLOCK_1 1
 
 #define LPC32XX_BOOT_ICR_SP_3AC_8IF 0xf0
 #define LPC32XX_BOOT_ICR_SP_4AC_8IF 0xd2
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h b/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h
index 29dd08e5eb..886c0385fb 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h
@@ -135,6 +135,71 @@ extern uint32_t lpc32xx_magic_zero_end [];
  */
 extern uint32_t lpc32xx_magic_zero_size [];
 
+#ifdef LPC32XX_SCRATCH_AREA_SIZE
+  /**
+   * @rief Scratch area.
+   *
+   * The usage is application specific.
+   */
+  extern uint8_t lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE];
+#endif
+
+#define LPC32XX_DO_STOP_GPDMA \
+  do { \
+    if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { \
+      if ((lpc32xx.dma.cfg & LPC_DMA_CFG_EN) != 0) { \
+        int i = 0; \
+        for (i = 0; i < 8; ++i) { \
+          lpc32xx.dma.channels [i].cfg = 0; \
+        } \
+        lpc32xx.dma.cfg &= ~LPC_DMA_CFG_EN; \
+      } \
+      LPC32XX_DMACLK_CTRL = 0; \
+    } \
+  } while (0)
+
+#define LPC32XX_DO_STOP_ETHERNET \
+  do { \
+    if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { \
+      lpc32xx.eth.command = 0x38; \
+      lpc32xx.eth.mac1 = 0xcf00; \
+      lpc32xx.eth.mac1 = 0; \
+      LPC32XX_MAC_CLK_CTRL = 0; \
+    } \
+  } while (0)
+
+#define LPC32XX_DO_STOP_USB \
+  do { \
+    if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { \
+      LPC32XX_OTG_CLK_CTRL = 0; \
+      LPC32XX_USB_CTRL = 0x80000; \
+    } \
+  } while (0)
+
+#define LPC32XX_DO_RESTART(addr) \
+  do { \
+    ARM_SWITCH_REGISTERS; \
+    rtems_interrupt_level level; \
+    uint32_t ctrl = 0; \
+  \
+    rtems_interrupt_disable(level); \
+  \
+    arm_cp15_data_cache_test_and_clean(); \
+    arm_cp15_instruction_cache_invalidate(); \
+  \
+    ctrl = arm_cp15_get_control(); \
+    ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); \
+    arm_cp15_set_control(ctrl); \
+  \
+    __asm__ volatile ( \
+      ARM_SWITCH_TO_ARM \
+      "mov pc, %[addr]\n" \
+      ARM_SWITCH_BACK \
+      : ARM_SWITCH_OUTPUT \
+      : [addr] "r" (addr) \
+    ); \
+  } while (0)
+
 /** @} */
 
 /**
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in b/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in
index c408b8b28f..849aaa27f1 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in
@@ -63,6 +63,9 @@
 /* peripheral clock in Hz */
 #undef LPC32XX_PERIPH_CLK
 
+/* size of scratch area */
+#undef LPC32XX_SCRATCH_AREA_SIZE
+
 /* stop Ethernet controller at start-up to avoid DMA interference */
 #undef LPC32XX_STOP_ETHERNET
 
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/mmu.h b/c/src/lib/libbsp/arm/lpc32xx/include/mmu.h
index 679be89666..eeebe59d20 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/include/mmu.h
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/mmu.h
@@ -7,12 +7,13 @@
  */
 
 /*
- * Copyright (c) 2009
- * embedded brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * <rtems@embedded-brains.de>
+ * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
@@ -55,7 +56,12 @@ extern "C" {
 #define LPC32XX_MMU_READ_WRITE_CACHED \
   (LPC32XX_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
 
-void lpc32xx_set_translation_table_entries(
+/**
+ * @brief Sets the @a section_flags for the address range [@a begin, @a end).
+ *
+ * @return Previous section flags of the first modified entry.
+ */
+uint32_t lpc32xx_set_translation_table_entries(
   const void *begin,
   const void *end,
   uint32_t section_flags
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/nand-mlc.h b/c/src/lib/libbsp/arm/lpc32xx/include/nand-mlc.h
index b783e08736..4e70345716 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/include/nand-mlc.h
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/nand-mlc.h
@@ -181,22 +181,7 @@ extern "C" {
  * @brief MLC NAND controller configuration.
  */
 typedef struct {
-  /**
-   * @brief Selects small pages (512 Bytes user data and 16 Bytes spare data)
-   * or large pages (2048 Bytes user data and 64 Bytes spare data).
-   */
-  bool small_pages;
-
-  /**
-   * @brief Selects 3/4 address cycles for small pages/large pages or 4/5
-   * address cycles.
-   */
-  bool many_address_cycles;
-
-  /**
-   * @brief Selects 64 or 128 pages per block in case of large pages.
-   */
-  bool normal_blocks;
+  uint32_t flags;
 
   uint32_t block_count;
 
@@ -207,6 +192,23 @@ typedef struct {
 } lpc32xx_mlc_config;
 
 /**
+ * @brief Selects small pages (512 Bytes user data and 16 Bytes spare data)
+ * or large pages (2048 Bytes user data and 64 Bytes spare data).
+ */
+#define MLC_SMALL_PAGES 0x1U
+
+/**
+ * @Brief Selects 3/4 address cycles for small pages/large pages or 4/5
+ * address cycles.
+ */
+#define MLC_MANY_ADDRESS_CYCLES 0x2U
+
+/**
+ * @brief Selects 64 or 128 pages per block in case of large pages.
+ */
+#define MLC_NORMAL_BLOCKS 0x4U
+
+/**
  * @brief Initializes the MLC NAND controller according to @a cfg.
  */
 void lpc32xx_mlc_init(const lpc32xx_mlc_config *cfg);