add support for LPC32xx

6 files changed, 491 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h b/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h
new file mode 100644
index 0000000000..a42dd7b0be
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h
@@ -0,0 +1,99 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx
+ *
+ * @brief Global BSP definitions.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_LPC32XX_BSP_H
+#define LIBBSP_ARM_LPC32XX_BSP_H
+
+#include <bspopts.h>
+
+#include <rtems.h>
+#include <rtems/console.h>
+#include <rtems/clockdrv.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+#ifndef ASM
+
+struct rtems_bsdnet_ifconfig;
+
+/**
+ * @defgroup lpc32xx LPC32XX Support
+ *
+ * @ingroup bsp_kit
+ *
+ * @brief LPC32XX support package.
+ *
+ * @{
+ */
+
+/**
+ * @brief Network driver attach and detach function.
+ */
+int lpc32xx_eth_attach_detach(
+  struct rtems_bsdnet_ifconfig *config,
+  int attaching
+);
+
+/**
+ * @brief Standard network driver attach and detach function.
+ */
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH	lpc32xx_eth_attach_detach
+
+/**
+ * @brief Standard network driver name.
+ */
+#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
+
+/**
+ * @brief Optimized idle task.
+ *
+ * This idle task sets the power mode to idle.  This causes the processor clock
+ * to be stopped, while on-chip peripherals remain active.  Any enabled
+ * interrupt from a peripheral or an external interrupt source will cause the
+ * processor to resume execution.
+ *
+ * To enable the idle task use the following in the system configuration:
+ *
+ * @code
+ * #include <bsp.h>
+ *
+ * #define CONFIGURE_INIT
+ *
+ * #define CONFIGURE_IDLE_TASK_BODY lpc32xx_idle
+ *
+ * #include <confdefs.h>
+ * @endcode
+ */
+void *lpc32xx_idle(uintptr_t ignored);
+
+/** @} */
+
+#endif /* ASM */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_LPC32XX_BSP_H */
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in b/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in
new file mode 100644
index 0000000000..bcf5f8fa42
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in
@@ -0,0 +1,61 @@
+/* include/bspopts.h.in.  Generated from configure.ac by autoheader.  */
+
+/* If defined, then the BSP Framework will put a non-zero pattern into the
+   RTEMS Workspace and C program heap. This should assist in finding code that
+   assumes memory starts set to zero. */
+#undef BSP_DIRTY_MEMORY
+
+/* If defined, print a message and wait until pressed before resetting board
+   when application exits. */
+#undef BSP_PRESS_KEY_FOR_RESET
+
+/* If defined, reset the board when the application exits. */
+#undef BSP_RESET_BOARD_AT_EXIT
+
+/* reset vector address for BSP start */
+#undef BSP_START_RESET_VECTOR
+
+/* ARM clock in Hz */
+#undef LPC32XX_ARM_CLK
+
+/* clock configuration for UART 3 */
+#undef LPC32XX_CONFIG_U3CLK
+
+/* clock configuration for UART 4 */
+#undef LPC32XX_CONFIG_U4CLK
+
+/* clock configuration for UART 5 */
+#undef LPC32XX_CONFIG_U5CLK
+
+/* clock configuration for UART 6 */
+#undef LPC32XX_CONFIG_U6CLK
+
+/* clock mode configuration for UARTs */
+#undef LPC32XX_CONFIG_UART_CLKMODE
+
+/* AHB bus clock in Hz */
+#undef LPC32XX_HCLK
+
+/* main oscillator frequency in Hz */
+#undef LPC32XX_OSCILLATOR_MAIN
+
+/* RTC oscillator frequency in Hz */
+#undef LPC32XX_OSCILLATOR_RTC
+
+/* peripheral clock in Hz */
+#undef LPC32XX_PERIPH_CLK
+
+/* Define to the address where bug reports for this package should be sent. */
+#undef PACKAGE_BUGREPORT
+
+/* Define to the full name of this package. */
+#undef PACKAGE_NAME
+
+/* Define to the full name and version of this package. */
+#undef PACKAGE_STRING
+
+/* Define to the one symbol short name of this package. */
+#undef PACKAGE_TARNAME
+
+/* Define to the version of this package. */
+#undef PACKAGE_VERSION
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/irq-config.h b/c/src/lib/libbsp/arm/lpc32xx/include/irq-config.h
new file mode 100644
index 0000000000..659e2ea56e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/irq-config.h
@@ -0,0 +1,27 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief Interrupt support configuration.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_LPC32XX_IRQ_CONFIG_H
+#define LIBBSP_ARM_LPC32XX_IRQ_CONFIG_H
+
+#include <bsp/irq.h>
+
+#endif /* LIBBSP_ARM_LPC32XX_IRQ_CONFIG_H */
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/irq.h b/c/src/lib/libbsp/arm/lpc32xx/include/irq.h
new file mode 100644
index 0000000000..62d28fe7e0
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/irq.h
@@ -0,0 +1,165 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief Interrupt definitions.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_LPC32XX_IRQ_H
+#define LIBBSP_ARM_LPC32XX_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+#define LPC32XX_IRQ_INDEX(module, subindex) ((module) + (subindex))
+
+#define LPC32XX_IRQ_MODULE_MIC 0U
+#define LPC32XX_IRQ_MODULE_SIC_1 32U
+#define LPC32XX_IRQ_MODULE_SIC_2 64U
+#define LPC32XX_IRQ_MODULE_COUNT 3U
+
+/* MIC interrupts */
+#define LPC32XX_IRQ_SIC_1_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 0)
+#define LPC32XX_IRQ_SIC_2_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 1)
+#define LPC32XX_IRQ_TIMER_4_OR_MCPWM LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 3)
+#define LPC32XX_IRQ_TIMER_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 4)
+#define LPC32XX_IRQ_TIMER_HS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 5)
+#define LPC32XX_IRQ_WDG LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 6)
+#define LPC32XX_IRQ_UART_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 7)
+#define LPC32XX_IRQ_UART_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 8)
+#define LPC32XX_IRQ_UART_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 9)
+#define LPC32XX_IRQ_UART_6 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 10)
+#define LPC32XX_IRQ_NAND_FLASH LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 11)
+#define LPC32XX_IRQ_SDCARD_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 13)
+#define LPC32XX_IRQ_LCD LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 14)
+#define LPC32XX_IRQ_SDCARD_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 15)
+#define LPC32XX_IRQ_TIMER_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 16)
+#define LPC32XX_IRQ_TIMER_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 17)
+#define LPC32XX_IRQ_TIMER_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 18)
+#define LPC32XX_IRQ_TIMER_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 19)
+#define LPC32XX_IRQ_SSP_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 20)
+#define LPC32XX_IRQ_SSP_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 21)
+#define LPC32XX_IRQ_I2S_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 22)
+#define LPC32XX_IRQ_I2S_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 23)
+#define LPC32XX_IRQ_UART_7 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 24)
+#define LPC32XX_IRQ_UART_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 25)
+#define LPC32XX_IRQ_UART_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 26)
+#define LPC32XX_IRQ_TIMER_MS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 27)
+#define LPC32XX_IRQ_DMA LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 28)
+#define LPC32XX_IRQ_ETHERNET LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 29)
+#define LPC32XX_IRQ_SIC_1_FIQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 30)
+#define LPC32XX_IRQ_SIC_2_FIQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 31)
+
+/* SIC 1 interrupts */
+#define LPC32XX_IRQ_JTAG_COMM_TX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 1)
+#define LPC32XX_IRQ_JTAG_COMM_RX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 2)
+#define LPC32XX_IRQ_GPI_28 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 4)
+#define LPC32XX_IRQ_TS_P LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 6)
+#define LPC32XX_IRQ_TS_IRQ_OR_ADC LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 7)
+#define LPC32XX_IRQ_TS_AUX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 8)
+#define LPC32XX_IRQ_SPI_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 12)
+#define LPC32XX_IRQ_PLL_USB LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 13)
+#define LPC32XX_IRQ_PLL_HCLK LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 14)
+#define LPC32XX_IRQ_PLL_397 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 17)
+#define LPC32XX_IRQ_I2C_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 18)
+#define LPC32XX_IRQ_I2C_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 19)
+#define LPC32XX_IRQ_RTC LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 20)
+#define LPC32XX_IRQ_KEYSCAN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 22)
+#define LPC32XX_IRQ_SPI_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 23)
+#define LPC32XX_IRQ_SW LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 24)
+#define LPC32XX_IRQ_USB_OTG_TIMER LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 25)
+#define LPC32XX_IRQ_USB_OTG_ATX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 26)
+#define LPC32XX_IRQ_USB_HOST LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 27)
+#define LPC32XX_IRQ_USB_DEV_DMA LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 28)
+#define LPC32XX_IRQ_USB_DEV_LP LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 29)
+#define LPC32XX_IRQ_USB_DEV_HP LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 30)
+#define LPC32XX_IRQ_USB_I2C LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 31)
+
+/* SIC 2 interrupts */
+#define LPC32XX_IRQ_GPIO_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 0)
+#define LPC32XX_IRQ_GPIO_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 1)
+#define LPC32XX_IRQ_GPIO_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 2)
+#define LPC32XX_IRQ_GPIO_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 3)
+#define LPC32XX_IRQ_GPIO_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 4)
+#define LPC32XX_IRQ_GPIO_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 5)
+#define LPC32XX_IRQ_SPI_2_DATAIN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 6)
+#define LPC32XX_IRQ_UART_2_HCTS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 7)
+#define LPC32XX_IRQ_GPIO_P0_P1_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 8)
+#define LPC32XX_IRQ_GPI_8 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 9)
+#define LPC32XX_IRQ_GPI_9 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 10)
+#define LPC32XX_IRQ_GPI_19 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 11)
+#define LPC32XX_IRQ_UART_7_HCTS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 12)
+#define LPC32XX_IRQ_GPI_7 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 15)
+#define LPC32XX_IRQ_SDIO LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 18)
+#define LPC32XX_IRQ_UART_5_RX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 19)
+#define LPC32XX_IRQ_SPI_1_DATAIN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 20)
+#define LPC32XX_IRQ_GPI_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 22)
+#define LPC32XX_IRQ_GPI_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 23)
+#define LPC32XX_IRQ_GPI_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 24)
+#define LPC32XX_IRQ_GPI_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 25)
+#define LPC32XX_IRQ_GPI_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 26)
+#define LPC32XX_IRQ_GPI_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 27)
+#define LPC32XX_IRQ_GPI_6 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 28)
+#define LPC32XX_IRQ_SYSCLK LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 31)
+
+#define LPC32XX_IRQ_PRIORITY_VALUE_MIN 0U
+#define LPC32XX_IRQ_PRIORITY_VALUE_MAX 15U
+#define LPC32XX_IRQ_PRIORITY_COUNT (LPC32XX_IRQ_PRIORITY_VALUE_MAX + 1U)
+#define LPC32XX_IRQ_PRIORITY_HIGHEST LPC32XX_IRQ_PRIORITY_VALUE_MIN
+#define LPC32XX_IRQ_PRIORITY_LOWEST LPC32XX_IRQ_PRIORITY_VALUE_MAX
+
+#define BSP_INTERRUPT_VECTOR_MIN LPC32XX_IRQ_SIC_1_IRQ
+#define BSP_INTERRUPT_VECTOR_MAX LPC32XX_IRQ_SYSCLK
+
+#define LPC32XX_IRQ_COUNT (BSP_INTERRUPT_VECTOR_MAX + 1)
+
+void lpc32xx_irq_set_priority(rtems_vector_number vector, unsigned priority);
+
+unsigned lpc32xx_irq_get_priority(rtems_vector_number vector);
+
+typedef enum {
+  LPC32XX_IRQ_ACTIVE_LOW_OR_FALLING_EDGE,
+  LPC32XX_IRQ_ACTIVE_HIGH_OR_RISING_EDGE
+} lpc32xx_irq_activation_polarity;
+
+void lpc32xx_irq_set_activation_polarity(rtems_vector_number vector, lpc32xx_irq_activation_polarity activation_polarity);
+
+lpc32xx_irq_activation_polarity lpc32xx_irq_get_activation_polarity(rtems_vector_number vector);
+
+typedef enum {
+  LPC32XX_IRQ_LEVEL_SENSITIVE,
+  LPC32XX_IRQ_EDGE_SENSITIVE
+} lpc32xx_irq_activation_type;
+
+void lpc32xx_irq_set_activation_type(rtems_vector_number vector, lpc32xx_irq_activation_type activation_type);
+
+lpc32xx_irq_activation_type lpc32xx_irq_get_activation_type(rtems_vector_number vector);
+
+/** @} */
+
+#endif /* ASM */
+
+#endif /* LIBBSP_ARM_LPC32XX_IRQ_H */
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/lpc-clock-config.h b/c/src/lib/libbsp/arm/lpc32xx/include/lpc-clock-config.h
new file mode 100644
index 0000000000..c4d7906632
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/lpc-clock-config.h
@@ -0,0 +1,45 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx
+ *
+ * @brief Clock driver configuration.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H
+#define LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/lpc32xx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define LPC_CLOCK_INTERRUPT LPC32XX_IRQ_TIMER_0
+
+#define LPC_CLOCK_TIMER_BASE LPC32XX_BASE_TIMER_0
+
+#define LPC_CLOCK_REFERENCE LPC32XX_PERIPH_CLK
+
+#define LPC_CLOCK_MODULE_ENABLE()
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H */
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h b/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h
new file mode 100644
index 0000000000..2e82d34b80
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h
@@ -0,0 +1,94 @@
+/**
+ * @file
+ *
+ * @ingroup lpc32xx
+ *
+ * @brief Register base addresses.
+ */
+
+/*
+ * Copyright (c) 2009
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http:
+ */
+
+#ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H
+#define LIBBSP_ARM_LPC32XX_LPC32XX_H
+
+#define LPC32XX_BASE_ADC 0x40048000
+#define LPC32XX_BASE_SYSCON 0x40004000
+#define LPC32XX_BASE_DEBUG_CTRL 0x40040000
+#define LPC32XX_BASE_DMA 0x31000000
+#define LPC32XX_BASE_EMC 0x31080000
+#define LPC32XX_BASE_EMC_CS_0 0xe0000000
+#define LPC32XX_BASE_EMC_CS_1 0xe1000000
+#define LPC32XX_BASE_EMC_CS_2 0xe2000000
+#define LPC32XX_BASE_EMC_CS_3 0xe3000000
+#define LPC32XX_BASE_EMC_DYCS_0 0x80000000
+#define LPC32XX_BASE_EMC_DYCS_1 0xa0000000
+#define LPC32XX_BASE_ETB_CFG 0x310c0000
+#define LPC32XX_BASE_ETB_DATA 0x310e0000
+#define LPC32XX_BASE_ETHERNET 0x31060000
+#define LPC32XX_BASE_GPIO 0x40028000
+#define LPC32XX_BASE_I2C_1 0x400a0000
+#define LPC32XX_BASE_I2C_2 0x400a8000
+#define LPC32XX_BASE_I2S_0 0x20094000
+#define LPC32XX_BASE_I2S_1 0x2009c000
+#define LPC32XX_BASE_IRAM 0x08000000
+#define LPC32XX_BASE_IROM 0x0c000000
+#define LPC32XX_BASE_KEYSCAN 0x40050000
+#define LPC32XX_BASE_LCD 0x31040000
+#define LPC32XX_BASE_MCPWM 0x400e8000
+#define LPC32XX_BASE_MIC 0x40008000
+#define LPC32XX_BASE_NAND_MLC 0x200a8000
+#define LPC32XX_BASE_NAND_SLC 0x20020000
+#define LPC32XX_BASE_PWM_1 0x4005c000
+#define LPC32XX_BASE_PWM_2 0x4005c004
+#define LPC32XX_BASE_PWM_3 0x4002c000
+#define LPC32XX_BASE_PWM_4 0x40030000
+#define LPC32XX_BASE_RTC 0x40024000
+#define LPC32XX_BASE_RTC_RAM 0x40024080
+#define LPC32XX_BASE_SDCARD 0x20098000
+#define LPC32XX_BASE_SIC_1 0x4000c000
+#define LPC32XX_BASE_SIC_2 0x40010000
+#define LPC32XX_BASE_SPI_1 0x20088000
+#define LPC32XX_BASE_SPI_2 0x20090000
+#define LPC32XX_BASE_SSP_0 0x20084000
+#define LPC32XX_BASE_SSP_1 0x2008c000
+#define LPC32XX_BASE_TIMER_0 0x40044000
+#define LPC32XX_BASE_TIMER_1 0x4004c000
+#define LPC32XX_BASE_TIMER_2 0x40058000
+#define LPC32XX_BASE_TIMER_3 0x40060000
+#define LPC32XX_BASE_TIMER_5 0x4002c000
+#define LPC32XX_BASE_TIMER_6 0x40030000
+#define LPC32XX_BASE_TIMER_HS 0x40038000
+#define LPC32XX_BASE_TIMER_MS 0x40034000
+#define LPC32XX_BASE_UART_1 0x40014000
+#define LPC32XX_BASE_UART_2 0x40018000
+#define LPC32XX_BASE_UART_3 0x40080000
+#define LPC32XX_BASE_UART_4 0x40088000
+#define LPC32XX_BASE_UART_5 0x40090000
+#define LPC32XX_BASE_UART_6 0x40098000
+#define LPC32XX_BASE_UART_7 0x4001c000
+#define LPC32XX_BASE_USB 0x31020000
+#define LPC32XX_BASE_USB_OTG_I2C 0x31020300
+#define LPC32XX_BASE_WDT 0x4003c000
+
+#define LPC32XX_U3CLK (*(volatile uint32_t *) 0x400040d0)
+#define LPC32XX_U4CLK (*(volatile uint32_t *) 0x400040d4)
+#define LPC32XX_U5CLK (*(volatile uint32_t *) 0x400040d8)
+#define LPC32XX_U6CLK (*(volatile uint32_t *) 0x400040dc)
+#define LPC32XX_IRDACLK (*(volatile uint32_t *) 0x400040e0)
+#define LPC32XX_UART_CTRL (*(volatile uint32_t *) 0x40054000)
+#define LPC32XX_UART_CLKMODE (*(volatile uint32_t *) 0x40054004)
+#define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008)
+#define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8)
+
+#endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */