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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2016-07-03 09:30:20 +0200
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2016-10-02 10:40:33 +0200
commit886b962e7b8c7c15f7d849925d7ca48482a05bca (patch)
tree3df5ec7dddbfb186c1f6af4cdfc1257689227346 /c/src/lib/libbsp/arm/lpc32xx/Makefile.am
parentrtems+bsps/cache: Define cache manager operations for code synchronization an... (diff)
downloadrtems-886b962e7b8c7c15f7d849925d7ca48482a05bca.tar.bz2
bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.
Updates #2782 Updates #2783
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