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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-09-26 07:31:29 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-09-26 07:31:58 +0200 |
| commit | 4bf2ce3115a532a173cb34f20bedf186d897db8b (patch) | |
| tree | acd3b163ee2489468735124b79c3d61ebb5d7e80 /c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_i2creg.h | |
| parent | posix shm: Add oflag to Shm_Control (diff) | |
| download | rtems-4bf2ce3115a532a173cb34f20bedf186d897db8b.tar.bz2 | |
bsp/imx: Add register headers
Update #3090.
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_i2creg.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_i2creg.h b/c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_i2creg.h new file mode 100644 index 0000000000..52201c7033 --- /dev/null +++ b/c/src/lib/libbsp/arm/imx/include/arm/freescale/imx/imx_i2creg.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IMX_I2CREG_H +#define IMX_I2CREG_H + +#include <bsp/utility.h> + +typedef struct { + uint32_t iadr; +#define IMX_I2C_IADR_ADR(val) BSP_FLD32(val, 1, 7) +#define IMX_I2C_IADR_ADR_GET(reg) BSP_FLD32GET(reg, 1, 7) +#define IMX_I2C_IADR_ADR_SET(reg, val) BSP_FLD32SET(reg, val, 1, 7) + uint32_t ifdr; +#define IMX_I2C_IFDR_IC(val) BSP_FLD32(val, 0, 5) +#define IMX_I2C_IFDR_IC_GET(reg) BSP_FLD32GET(reg, 0, 5) +#define IMX_I2C_IFDR_IC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) + uint32_t i2cr; +#define IMX_I2C_I2CR_IEN BSP_BIT32(7) +#define IMX_I2C_I2CR_IIEN BSP_BIT32(6) +#define IMX_I2C_I2CR_MSTA BSP_BIT32(5) +#define IMX_I2C_I2CR_MTX BSP_BIT32(4) +#define IMX_I2C_I2CR_TXAK BSP_BIT32(3) +#define IMX_I2C_I2CR_RSTA BSP_BIT32(2) + uint32_t i2sr; +#define IMX_I2C_I2SR_ICF BSP_BIT32(7) +#define IMX_I2C_I2SR_IAAS BSP_BIT32(6) +#define IMX_I2C_I2SR_IBB BSP_BIT32(5) +#define IMX_I2C_I2SR_IAL BSP_BIT32(4) +#define IMX_I2C_I2SR_SRW BSP_BIT32(2) +#define IMX_I2C_I2SR_IIF BSP_BIT32(1) +#define IMX_I2C_I2SR_RXAK BSP_BIT32(0) + uint32_t i2dr; +#define IMX_I2C_I2DR_DATA(val) BSP_FLD32(val, 0, 7) +#define IMX_I2C_I2DR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define IMX_I2C_I2DR_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) +} imx_i2c; + +#endif /* IMX_I2CREG_H */ |