diff options
| author | Jay Monkman <jtm@smoothsmoothie.com> | 2005-03-11 07:27:56 +0000 |
|---|---|---|
| committer | Jay Monkman <jtm@smoothsmoothie.com> | 2005-03-11 07:27:56 +0000 |
| commit | e8c785c68aeb6565c1cd56fcefd8edb1163f4894 (patch) | |
| tree | dd3954615862f25cf1a9e81e455f37f730af7074 /c/src/lib/libbsp/arm/gp32/startup/memmap.c | |
| parent | 2005-03-11 Philippe Simons <loki_666@fastmail.fm> (diff) | |
| download | rtems-e8c785c68aeb6565c1cd56fcefd8edb1163f4894.tar.bz2 | |
2005-03-11 Philippe Simons <loki_666@fastmail.fm>
* acinclude.m4: Added gp32 BSP.
* gp32/.cvsignore, gp32/Makefile.am, gp32/README, gp32/bsp_specs,
gp32/configure.ac, gp32/console/.cvsignore, gp32/console/conio.c,
gp32/console/console.c, gp32/console/defaultfont.c,
gp32/include/.cvsignore, gp32/include/bsp.h, gp32/include/conio.h,
gp32/include/tm27.h, gp32/start/.cvsignore, gp32/start/start.S,
gp32/startup/.cvsignore, gp32/startup/bspstart.c,
gp32/startup/exit.c, gp32/startup/linkcmds, gp32/startup/memmap.c: New files.
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libbsp/arm/gp32/startup/memmap.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/gp32/startup/memmap.c b/c/src/lib/libbsp/arm/gp32/startup/memmap.c new file mode 100644 index 0000000000..50492c56b4 --- /dev/null +++ b/c/src/lib/libbsp/arm/gp32/startup/memmap.c @@ -0,0 +1,28 @@ +/* + * GP32 Memory Map + * + * Copyright (c) 2004 by Cogent Computer Systems + * Written by Jay Monkman <jtm@lopingdog.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ +#include <rtems.h> +#include <libcpu/mmu.h> + +/* Remember, the ARM920 has 64 TLBs. If you have more 1MB sections than + * that, you'll have TLB lookups, which could hurt performance. + */ +mmu_sect_map_t mem_map[] = { +/* <phys addr> <virt addr> <size> <flags> */ + {0x0c000000, 0x00000000, 1, MMU_CACHE_NONE}, /* SDRAM for vectors */ + {0x0c000000, 0x0c000000, 7, MMU_CACHE_WTHROUGH}, /* SDRAM W cache */ + {0x0c700000, 0x0c700000, 1, MMU_CACHE_NONE}, /* SDRAM W/O cache */ + {0x14000000, 0x14000000, 16, MMU_CACHE_NONE}, /* Internals Regs - */ + {0x15000000, 0x15000000, 16, MMU_CACHE_NONE}, /* Internal Regs - */ + {0x00000000, 0x00000000, 0, 0} /* The end */ +}; |