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| author | Chris Johns <chrisj@rtems.org> | 2017-12-23 18:18:56 +1100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-01-25 08:45:26 +0100 |
| commit | 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 (patch) | |
| tree | 44759efe9374f13200a97e96d91bd9a2b7e5ce2a /c/src/lib/libbsp/arm/csb337 | |
| parent | MAINTAINERS: Add myself to Write After Approval. (diff) | |
| download | rtems-2afb22b7e1ebcbe40373ff7e0efae7d207c655a9.tar.bz2 | |
Remove make preinstall
A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.
This has at least seven problems:
* The make preinstall step itself needs time and disk space.
* Errors in header files show up in the build tree copy. This makes it
hard for editors to open the right file to fix the error.
* There is no clear relationship between source and build tree header
files. This makes an audit of the build process difficult.
* The visibility of all header files in the build tree makes it
difficult to enforce API barriers. For example it is discouraged to
use BSP-specifics in the cpukit.
* An introduction of a new build system is difficult.
* Include paths specified by the -B option are system headers. This
may suppress warnings.
* The parallel build had sporadic failures on some hosts.
This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.
The new cpukit include directories are:
* cpukit/include
* cpukit/score/cpu/@RTEMS_CPU@/include
* cpukit/libnetworking
The new BSP include directories are:
* bsps/include
* bsps/@RTEMS_CPU@/include
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include
There are build tree include directories for generated files.
The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.
The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.
Update #3254.
Diffstat (limited to 'c/src/lib/libbsp/arm/csb337')
18 files changed, 10 insertions, 6031 deletions
diff --git a/c/src/lib/libbsp/arm/csb337/Makefile.am b/c/src/lib/libbsp/arm/csb337/Makefile.am index 6999c0250e..a2d448c3e9 100644 --- a/c/src/lib/libbsp/arm/csb337/Makefile.am +++ b/c/src/lib/libbsp/arm/csb337/Makefile.am @@ -4,47 +4,21 @@ EXTRA_DIST = include $(top_srcdir)/../../../../automake/compile.am include $(top_srcdir)/../../bsp.am -include_bspdir = $(includedir)/bsp - -dist_project_lib_DATA = bsp_specs - -include_HEADERS = include/bsp.h -include_HEADERS += include/tm27.h -include_HEADERS += include/at91rm9200_dbgu.h -include_HEADERS += include/at91rm9200_emac.h -include_HEADERS += include/at91rm9200_gpio.h -include_HEADERS += include/at91rm9200.h -include_HEADERS += include/at91rm9200_mem.h -include_HEADERS += include/at91rm9200_pmc.h -include_HEADERS += include/at91rm9200_usart.h -include_HEADERS += include/bits.h +dist_project_lib_DATA = startup/bsp_specs if ENABLE_LCD -include_HEADERS += include/sed1356.h endif -include_bsp_HEADERS = -libbsp_a_CPPFLAGS = +libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) if ENABLE_UMON -include_umondir = $(includedir)/umon -include_umon_HEADERS = ../../shared/umon/cli.h -include_umon_HEADERS += ../../shared/umon/monlib.h -include_umon_HEADERS += ../../shared/umon/tfs.h - -include_rtemsdir = $(includedir)/rtems -include_rtems_HEADERS = ../../shared/umon/umon.h endif -nodist_include_HEADERS = include/bspopts.h -nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h DISTCLEANFILES = include/bspopts.h noinst_PROGRAMS = if ENABLE_LCD -nodist_include_HEADERS += console/sed1356_16bit.h -nodist_include_HEADERS += console/font8x16.h endif EXTRA_DIST += start/start.S @@ -52,9 +26,10 @@ start.$(OBJEXT): start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -project_lib_DATA += startup/linkcmds -EXTRA_DIST += startup/linkcmds.csb337 -EXTRA_DIST += startup/linkcmds.csb637 +project_lib_DATA += linkcmds +dist_project_lib_DATA += startup/linkcmds.csb337 +dist_project_lib_DATA += startup/linkcmds.csb637 + EXTRA_DIST += README EXTRA_DIST += README.kit637_v6 @@ -80,9 +55,6 @@ libbsp_a_SOURCES += ../../shared/console.c console/uarts.c \ libbsp_a_SOURCES += console/dbgu.c libbsp_a_SOURCES += console/usart.c # IRQ -include_bsp_HEADERS += ../../shared/include/irq-generic.h \ - ../../shared/include/irq-info.h -include_bsp_HEADERS += include/bsp/irq.h libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c libbsp_a_SOURCES += ../../shared/src/irq-generic.c libbsp_a_SOURCES += ../../shared/src/irq-info.c @@ -122,5 +94,5 @@ if HAS_NETWORKING libbsp_a_LIBADD += network.rel endif -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../../automake/local.am +include $(srcdir)/../../../../../../bsps/arm/csb337/headers.am diff --git a/c/src/lib/libbsp/arm/csb337/configure.ac b/c/src/lib/libbsp/arm/csb337/configure.ac index 5567bf06f4..066d425e56 100644 --- a/c/src/lib/libbsp/arm/csb337/configure.ac +++ b/c/src/lib/libbsp/arm/csb337/configure.ac @@ -4,6 +4,9 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libbsp-arm-csb337],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([make/custom/csb337.cfg]) RTEMS_TOP(../../../../../..) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP +RTEMS_BSP_LINKCMDS RTEMS_CANONICAL_TARGET_CPU AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) @@ -63,7 +66,6 @@ RTEMS_BSPOPTS_HELP([ENABLE_USART3], AM_CONDITIONAL(ENABLE_USART3,test "$ENABLE_USART3" = "1") RTEMS_BSP_CLEANUP_OPTIONS -RTEMS_BSP_LINKCMDS # Explicitly list all Makefiles here AC_CONFIG_FILES([Makefile]) diff --git a/c/src/lib/libbsp/arm/csb337/console/font8x16.h b/c/src/lib/libbsp/arm/csb337/console/font8x16.h deleted file mode 100644 index 0445b67668..0000000000 --- a/c/src/lib/libbsp/arm/csb337/console/font8x16.h +++ /dev/null @@ -1,3615 +0,0 @@ -/** - * @file - * - * @ingroup arm_csb337 - * - * @brief Simple 8 x 16 font, printable characters only. - */ - -/** - * @defgroup csb337_font Simple 8 x 16 font - * - * @ingroup arm_csb337 - * - * @brief Simple 8 x 16 font, printable characters only. - */ - -/* - * font8x16.h - * - * Simple 8 x 16 font printable Characters only. To lookup, subtract - * FIRST_CHAR from the Character, multiply x FONT_HEIGHT and get the next - * FONT_WIDTH bytes. - * - * Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ - * which includes this notice: - * - ************************************************************************** - * General notice: - * This code is part of a boot-monitor package developed as a generic base - * platform for embedded system designs. As such, it is likely to be - * distributed to various projects beyond the control of the original - * author. Please notify the author of any enhancements made or bugs found - * so that all may benefit from the changes. In addition, notification back - * to the author will allow the new user to pick up changes that may have - * been made by other users after this version of the code was distributed. - * - * Note1: the majority of this code was edited with 4-space tabs. - * Note2: as more and more contributions are accepted, the term "author" - * is becoming a mis-representation of credit. - * - * Original author: Ed Sutter - * Email: esutter@alcatel-lucent.com - * Phone: 908-582-2351 - ************************************************************************** - * - * Ed Sutter has been informed that this code is being used in RTEMS. - * - * This code was reformatted by Joel Sherrill from OAR Corporation and - * Fernando Nicodemos <fgnicodemos@terra.com.br> from NCB - Sistemas - * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding - * standards and to eliminate C++ style comments. - */ - -#define FONT_WIDTH 8 -#define FONT_HEIGHT 16 -#define FIRST_CHAR 0x20 -#define LAST_CHAR 0x7F -#define CURSOR_ON 0x7F -#define CURSOR_OFF 0x20 - -const uint8_t font8x16[] = { - - -/* Character (0x20): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, - -/* Character ! (0x21): - ht=16, width=8 - +--------+ - | | - | | - | ** | - | **** | - | **** | - | **** | - | **** | - | ** | - | ** | - | | - | ** | - | ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x18, -0x3C, -0x3C, -0x3C, -0x3C, -0x18, -0x18, -0x00, -0x18, -0x18, -0x00, -0x00, -0x00, -0x00, - -/* Character " (0x22): - ht=16, width=8 - +--------+ - | | - | | - | ** ** | - | ** ** | - | ** ** | - | ** ** | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - +--------+ */ -0x00, -0x36, -0x36, -0x36, -0x36, -0x14, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, - -/* Character # (0x23): - ht=16, width=8 - +--------+ - | | - | | - | ** ** | - | ** ** | - | ** ** | - |******* | - | ** ** | - | ** ** | - |******* | - | ** ** | - | ** ** | - | ** ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x6C, -0x6C, -0x6C, -0xFE, -0x6C, -0x6C, -0xFE, -0x6C, -0x6C, -0x6C, -0x00, -0x00, -0x00, -0x00, - -/* Character $ (0x24): - ht=16, width=8 - +--------+ - | | - | | - | ** | - | ** | - | ***** | - |** ** | - |** * | - | **** | - | **** | - | * ** | - |** ** | - | ***** | - | ** | - | ** | - | | - | | - +--------+ */ -0x00, -0x00, -0x18, -0x18, -0x7C, -0xC6, -0xC0, -0x78, -0x3C, -0x06, -0xC6, -0x7C, -0x18, -0x18, -0x00, -0x00, - -/* Character % (0x25): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - | ** * | - | ** ** | - | ** | - | ** | - | ** | - | ** ** | - |** ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0x62, -0x66, -0x0C, -0x18, -0x30, -0x66, -0xC6, -0x00, -0x00, -0x00, -0x00, - -/* Character & (0x26): - ht=16, width=8 - +--------+ - | | - | | - | *** | - | ** ** | - | *** | - | ** | - | *** ** | - | ****** | - |** ** | - |** ** | - |** ** | - | *** ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x38, -0x6C, -0x38, -0x30, -0x76, -0x7E, -0xCC, -0xCC, -0xCC, -0x76, -0x00, -0x00, -0x00, -0x00, - -/* Character ' (0x27): - ht=16, width=8 - +--------+ - | | - | ** | - | ** | - | ** | - | ** | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - +--------+ */ -0x00, -0x0C, -0x0C, -0x0C, -0x18, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, - -/* Character ( (0x28): - ht=16, width=8 - +--------+ - | | - | | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x0C, -0x18, -0x30, -0x30, -0x30, -0x30, -0x30, -0x30, -0x18, -0x0C, -0x00, -0x00, -0x00, -0x00, - -/* Character ) (0x29): - ht=16, width=8 - +--------+ - | | - | | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x30, -0x18, -0x0C, -0x0C, -0x0C, -0x0C, -0x0C, -0x0C, -0x18, -0x30, -0x00, -0x00, -0x00, -0x00, - -/* Character * (0x2A): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - | ** ** | - | *** | - |******* | - | *** | - | ** ** | - | | - | | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0x6C, -0x38, -0xFE, -0x38, -0x6C, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, - -/* Character (0x2B): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - | ** | - | ** | - | ****** | - | ** | - | ** | - | | - | | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0x18, -0x18, -0x7E, -0x18, -0x18, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, - -/* Character , (0x2C): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - | | - | | - | | - | | - | ** | - | ** | - | ** | - | ** | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x0C, -0x0C, -0x0C, -0x18, -0x00, -0x00, -0x00, - -/* Character - (0x2D): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - | | - | | - | ****** | - | | - | | - | | - | | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0xFE, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, - -/* Character . (0x2E): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | ** | - | ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x18, -0x18, -0x00, -0x00, -0x00, -0x00, - -/* Character / (0x2F): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | * | - | ** | - | ** | - | ** | - | ** | - | ** | - | * | - | | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x02, -0x06, -0x0C, -0x18, -0x30, -0x60, -0xC0, -0x80, -0x00, -0x00, -0x00, -0x00, - -/* Character 0 (0x30): - ht=16, width=8 - +--------+ - | | - | | - | ***** | - |** ** | - |** ** | - |** *** | - |** **** | - |**** ** | - |*** ** | - |** ** | - |** ** | - | ***** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x7C, -0xC6, -0xC6, -0xCE, -0xDE, -0xF6, -0xE6, -0xC6, -0xC6, -0x7C, -0x00, -0x00, -0x00, -0x00, - -/* Character 1 (0x31): - ht=16, width=8 - +--------+ - | | - | | - | ** | - | **** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ****** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x18, -0x78, -0x18, -0x18, -0x18, -0x18, -0x18, -0x18, -0x18, -0x7E, -0x00, -0x00, -0x00, -0x00, - -/* Character 2 (0x32): - ht=16, width=8 - +--------+ - | | - | | - | ***** | - |** ** | - |** ** | - | ** | - | ** | - | ** | - | ** | - | ** | - |** ** | - |******* | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x7C, -0xC6, -0xC6, -0x06, -0x0C, -0x18, -0x30, -0x60, -0xC6, -0xFE, -0x00, -0x00, -0x00, -0x00, - -/* Character 3 (0x33): - ht=16, width=8 - +--------+ - | | - | | - | ***** | - |** ** | - | ** | - | ** | - | **** | - | ** | - | ** | - | ** | - |** ** | - | ***** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x7C, -0xC6, -0x06, -0x06, -0x3C, -0x06, -0x06, -0x06, -0xC6, -0x7C, -0x00, -0x00, -0x00, -0x00, - -/* Character 4 (0x34): - ht=16, width=8 - +--------+ - | | - | | - | ** | - | *** | - | **** | - | ** ** | - |** ** | - |** ** | - |******* | - | ** | - | ** | - | **** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x0C, -0x1C, -0x3C, -0x6C, -0xCC, -0xCC, -0xFE, -0x0C, -0x0C, -0x1E, -0x00, -0x00, -0x00, -0x00, - -/* Character 5 (0x35): - ht=16, width=8 - +--------+ - | | - | | - |******* | - |** | - |** | - |** | - |****** | - | ** | - | ** | - | ** | - |** ** | - | ***** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0xFE, -0xC0, -0xC0, -0xC0, -0xFC, -0x06, -0x06, -0x06, -0xC6, -0x7C, -0x00, -0x00, -0x00, -0x00, - -/* Character 6 (0x36): - ht=16, width=8 - +--------+ - | | - | | - | ***** | - |** ** | - |** | - |** | - |****** | - |** ** | - |** ** | - |** ** | - |** ** | - | ***** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x7C, -0xC6, -0xC0, -0xC0, -0xFC, -0xC6, -0xC6, -0xC6, -0xC6, -0x7C, -0x00, -0x00, -0x00, -0x00, - -/* Character 7 (0x37): - ht=16, width=8 - +--------+ - | | - | | - |******* | - |** ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0xFE, -0xC6, -0x06, -0x0C, -0x18, -0x30, -0x30, -0x30, -0x30, -0x30, -0x00, -0x00, -0x00, -0x00, - -/* Character 8 (0x38): - ht=16, width=8 - +--------+ - | | - | | - | ***** | - |** ** | - |** ** | - |** ** | - | ***** | - |** ** | - |** ** | - |** ** | - |** ** | - | ***** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x7C, -0xC6, -0xC6, -0xC6, -0x7C, -0xC6, -0xC6, -0xC6, -0xC6, -0x7C, -0x00, -0x00, -0x00, -0x00, - -/* Character 9 (0x39): - ht=16, width=8 - +--------+ - | | - | | - | ***** | - |** ** | - |** ** | - |** ** | - |** ** | - | ****** | - | ** | - | ** | - |** ** | - | ***** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x7C, -0xC6, -0xC6, -0xC6, -0xC6, -0x7E, -0x06, -0x06, -0xC6, -0x7C, -0x00, -0x00, -0x00, -0x00, - -/* Character : (0x3A): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - | ** | - | ** | - | | - | | - | ** | - | ** | - | | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0x0C, -0x0C, -0x00, -0x00, -0x0C, -0x0C, -0x00, -0x00, -0x00, -0x00, -0x00, - -/* Character ; (0x3B): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - | ** | - | ** | - | | - | | - | ** | - | ** | - | ** | - | ** | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0x0C, -0x0C, -0x00, -0x00, -0x0C, -0x0C, -0x0C, -0x18, -0x00, -0x00, -0x00, - -/* Character < (0x3C): - ht=16, width=8 - +--------+ - | | - | | - | | - | ** | - | ** | - | ** | - | ** | - |** | - | ** | - | ** | - | ** | - | ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x0C, -0x18, -0x30, -0x60, -0xC0, -0x60, -0x30, -0x18, -0x0C, -0x00, -0x00, -0x00, -0x00, - -/* Character = (0x3D): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - | | - |******* | - | | - |******* | - | | - | | - | | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0xFE, -0x00, -0xFE, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, - -/* Character > (0x3E): - ht=16, width=8 - +--------+ - | | - | | - | | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x60, -0x30, -0x18, -0x0C, -0x06, -0x0C, -0x18, -0x30, -0x60, -0x00, -0x00, -0x00, -0x00, - -/* Character ? (0x3F): - ht=16, width=8 - +--------+ - | | - | | - | ***** | - |** ** | - |** ** | - | ** | - | ** | - | ** | - | ** | - | | - | ** | - | ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x7C, -0xC6, -0xC6, -0x0C, -0x18, -0x18, -0x18, -0x00, -0x18, -0x18, -0x00, -0x00, -0x00, -0x00, - -/* Character @ (0x40): - ht=16, width=8 - +--------+ - | | - | | - | ***** | - |** ** | - |** ** | - |** ** | - |** **** | - |** **** | - |** **** | - |** *** | - |** | - | ****** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x7C, -0xC6, -0xC6, -0xC6, -0xDE, -0xDE, -0xDE, -0xDC, -0xC0, -0x7E, -0x00, -0x00, -0x00, -0x00, - -/* Character A (0x41): - ht=16, width=8 - +--------+ - | | - | | - | *** | - | ** ** | - |** ** | - |** ** | - |** ** | - |******* | - |** ** | - |** ** | - |** ** | - |** ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x38, -0x6C, -0xC6, -0xC6, -0xC6, -0xFE, -0xC6, -0xC6, -0xC6, -0xC6, -0x00, -0x00, -0x00, -0x00, - -/* Character B (0x42): - ht=16, width=8 - +--------+ - | | - | | - |****** | - | ** ** | - | ** ** | - | ** ** | - | ***** | - | ** ** | - | ** ** | - | ** ** | - | ** ** | - |****** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0xFC, -0x66, -0x66, -0x66, -0x7C, -0x66, -0x66, -0x66, -0x66, -0xFC, -0x00, -0x00, -0x00, -0x00, - -/* Character C (0x43): - ht=16, width=8 - +--------+ - | | - | | - | **** | - | ** ** | - |** * | - |** | - |** | - |** | - |** | - |** * | - | ** ** | - | **** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x3C, -0x66, -0xC2, -0xC0, -0xC0, -0xC0, -0xC0, -0xC2, -0x66, -0x3C, -0x00, -0x00, -0x00, -0x00, - -/* Character D (0x44): - ht=16, width=8 - +--------+ - | | - | | - |***** | - | ** ** | - | ** ** | - | ** ** | - | ** ** | - | ** ** | - | ** ** | - | ** ** | - | ** ** | - |***** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0xF8, -0x6C, -0x66, -0x66, -0x66, -0x66, -0x66, -0x66, -0x6C, -0xF8, -0x00, -0x00, -0x00, -0x00, - -/* Character E (0x45): - ht=16, width=8 - +--------+ - | | - | | - |******* | - | ** ** | - | ** | - | ** * | - | ***** | - | ** * | - | ** | - | ** | - | ** ** | - |******* | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0xFE, -0x66, -0x60, -0x64, -0x7C, -0x64, -0x60, -0x60, -0x66, -0xFE, -0x00, -0x00, -0x00, -0x00, - -/* Character F (0x46): - ht=16, width=8 - +--------+ - | | - | | - |******* | - | ** ** | - | ** | - | ** * | - | ***** | - | ** * | - | ** | - | ** | - | ** | - |**** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0xFE, -0x66, -0x60, -0x64, -0x7C, -0x64, -0x60, -0x60, -0x60, -0xF0, -0x00, -0x00, -0x00, -0x00, - -/* Character G (0x47): - ht=16, width=8 - +--------+ - | | - | | - | ***** | - |** ** | - |** ** | - |** | - |** | - |** | - |** *** | - |** ** | - |** ** | - | ***** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x7C, -0xC6, -0xC6, -0xC0, -0xC0, -0xC0, -0xCE, -0xC6, -0xC6, -0x7C, -0x00, -0x00, -0x00, -0x00, - -/* Character H (0x48): - ht=16, width=8 - +--------+ - | | - | | - |** ** | - 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-/* Character x (0x78): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - |** ** | - |** ** | - | ** ** | - | *** | - | ** ** | - |** ** | - |** ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0xC6, -0xC6, -0x6C, -0x38, -0x6C, -0xC6, -0xC6, -0x00, -0x00, -0x00, -0x00, - -/* Character y (0x79): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - |** ** | - |** ** | - |** ** | - |** ** | - |** *** | - | *** ** | - | ** | - |** ** | - | ***** | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0xC6, -0xC6, -0xC6, -0xC6, -0xCE, -0x76, -0x06, -0xC6, -0x7C, -0x00, -0x00, - -/* Character z (0x7A): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - |******* | - |* ** | - | ** | - | ** | - | ** | - | ** * | - |******* | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0xFE, -0x86, -0x0C, -0x18, -0x30, -0x62, -0xFE, -0x00, -0x00, -0x00, -0x00, - -/* Character { (0x7B): - ht=16, width=8 - +--------+ - | | - | | - | *** | - | ** | - | ** | - | ** | - | *** | - | ** | - | ** | - | ** | - | ** | - | *** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x0E, -0x18, -0x18, -0x18, -0x70, -0x18, -0x18, -0x18, -0x18, -0x0E, -0x00, -0x00, -0x00, -0x00, - -/* Character | (0x7C): - ht=16, width=8 - +--------+ - | | - | | - | ** | - | ** | - | ** | - | ** | - | | - | ** | - | ** | - | ** | - | ** | - | ** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x18, -0x18, -0x18, -0x18, -0x00, -0x18, -0x18, -0x18, -0x18, -0x18, -0x00, -0x00, -0x00, -0x00, - -/* Character } (0x7D): - ht=16, width=8 - +--------+ - | | - | | - | *** | - | ** | - | ** | - | ** | - | *** | - | ** | - | ** | - | ** | - | ** | - | *** | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x70, -0x18, -0x18, -0x18, -0x0E, -0x18, -0x18, -0x18, -0x18, -0x70, -0x00, -0x00, -0x00, -0x00, - -/* Character ~ (0x7E): - ht=16, width=8 - +--------+ - | | - | | - | *** ** | - |** *** | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x76, -0xDC, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, -0x00, - -/* Character DELTA (0x7F): - ht=16, width=8 - +--------+ - | | - | | - | | - | | - | | - | * | - | *** | - | *** | - | ** ** | - | ** ** | - |******* | - | | - | | - | | - | | - | | - +--------+ */ -0x00, -0x00, -0x00, -0x00, -0x00, -0x10, -0x38, -0x38, -0x6C, -0x6C, -0xFE, -0x00, -0x00, -0x00, -0x00, -0x00, -}; diff --git a/c/src/lib/libbsp/arm/csb337/console/sed1356_16bit.h b/c/src/lib/libbsp/arm/csb337/console/sed1356_16bit.h deleted file mode 100644 index 5ccf85d01c..0000000000 --- a/c/src/lib/libbsp/arm/csb337/console/sed1356_16bit.h +++ /dev/null @@ -1,566 +0,0 @@ -/** - * @file - * - * @ingroup arm_csb337 - * - * @brief SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) - * 16-Bit access mode - */ - -/** - * @defgroup csb337_sed1356 SED Video Controller. - * - * @ingroup arm_csb337 - * - * @brief SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) - * 16-Bit access mode - */ - -/* - * sed1356.h: SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) - * 16-Bit access mode - * - * Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ - * which includes this notice: - * - ************************************************************************** - * General notice: - * This code is part of a boot-monitor package developed as a generic base - * platform for embedded system designs. As such, it is likely to be - * distributed to various projects beyond the control of the original - * author. Please notify the author of any enhancements made or bugs found - * so that all may benefit from the changes. In addition, notification back - * to the author will allow the new user to pick up changes that may have - * been made by other users after this version of the code was distributed. - * - * Note1: the majority of this code was edited with 4-space tabs. - * Note2: as more and more contributions are accepted, the term "author" - * is becoming a mis-representation of credit. - * - * Original author: Ed Sutter - * Email: esutter@alcatel-lucent.com - * Phone: 908-582-2351 - ************************************************************************** - * - * Ed Sutter has been informed that this code is being used in RTEMS. - * - * The code has been reformatted by Joel Sherrill from OAR Corporation and - * Fernando Nicodemos <fgnicodemos@terra.com.br> from NCB - Sistemas - * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding standards - * and to eliminate C++ style comments. - */ - -#ifndef __sed1356_16bit_h -#define __sed1356_16bit_h - -#include "bits.h" -/*------------------------------------------------------------------------ - * cpu specific code must define the following board specific macros. - * in cpuio.h. These examples assume the SED135x has been placed in - * the correct endian mode via hardware. - * #define SED_MEM_BASE 0xf0600000 <-- just example addresses, - * #define SED_REG_BASE 0xf0400000 <-- define for each board - * #define SED_STEP 1 <-- 1 = device is on 16-bit boundry, 2 = 32-bit boundry, 4 = 64-bit boundry - * #define SED_REG16(_x_) *(vushortr *)(SED_REG_BASE + (_x_ * SED_STEP)) // Control/Status Registers - * #define RD_FB16(_reg_,_val_) ((_val_) = *((vushort *)((SED_MEM_BASE + (_reg_ * SED_STEP))))) - * #define WR_FB16(_reg_,_val_) (*((vushort *)((SED_MEM_BASE + (_reg_ * 2)))) = (_val_)) - * Big endian processors - * #define H2SED(_x_) ((((x) & 0xff00U) >> 8) | (((x) & 0x00ffU) << 8)) - * Little endian - * #define H2SED(_x_) (_x_) - * - */ - -/* - * SED1356 registers - 16-Bit Access Mode. The first register - * referenced is the even addressed register. The byte offsets - * of the odd registers are shown in the comments - */ -#define SED1356_REG_REV_and_MISC SED_REG16(0x00) -#define SED1356_REG_GPIO_CFG SED_REG16(0x04) -#define SED1356_REG_GPIO_CTL SED_REG16(0x08) -#define SED1356_REG_MD_CFG_RD_LO_and_HI SED_REG16(0x0c) -#define SED1356_REG_MCLK_CFG SED_REG16(0x10) -#define SED1356_REG_LCD_PCLK_CFG SED_REG16(0x14) -#define SED1356_REG_CRT_PCLK_CFG SED_REG16(0x18) -#define SED1356_REG_MEDIA_PCLK_CFG SED_REG16(0x1c) -#define SED1356_REG_WAIT_STATE SED_REG16(0x1e) -#define SED1356_REG_MEM_CFG_and_REF_RATE SED_REG16(0x20) -#define SED1356_REG_MEM_TMG0_and_1 SED_REG16(0x2a) -#define SED1356_REG_PANEL_TYPE_and_MOD_RATE SED_REG16(0x30) -/* LCD Control registers */ -#define SED1356_REG_LCD_HOR_DISP SED_REG16(0x32) -#define SED1356_REG_LCD_HOR_NONDISP_and_START SED_REG16(0x34) -#define SED1356_REG_LCD_HOR_PULSE SED_REG16(0x36) -#define SED1356_REG_LCD_VER_DISP_HT_LO_and_HI SED_REG16(0x38) -#define SED1356_REG_LCD_VER_NONDISP_and_START SED_REG16(0x3a) -#define SED1356_REG_LCD_VER_PULSE SED_REG16(0x3c) -#define SED1356_REG_LCD_DISP_MODE_and_MISC SED_REG16(0x40) -#define SED1356_REG_LCD_DISP_START_LO_and_MID SED_REG16(0x42) -#define SED1356_REG_LCD_DISP_START_HI SED_REG16(0x44) -#define SED1356_REG_LCD_ADD_OFFSET_LO_and_HI SED_REG16(0x46) -#define SED1356_REG_LCD_PIXEL_PAN SED_REG16(0x48) -#define SED1356_REG_LCD_FIFO_THRESH_LO_and_HI SED_REG16(0x4a) -/* CRT/TV Control registers */ -#define SED1356_REG_CRT_HOR_DISP SED_REG16(0x50) -#define SED1356_REG_CRT_HOR_NONDISP_and_START SED_REG16(0x52) -#define SED1356_REG_CRT_HOR_PULSE SED_REG16(0x54) -#define SED1356_REG_CRT_VER_DISP_HT_LO_and_HI SED_REG16(0x56) -#define SED1356_REG_CRT_VER_NONDISP_and_START SED_REG16(0x58) -#define SED1356_REG_CRT_VER_PULSE_and_OUT_CTL SED_REG16(0x5a) -#define SED1356_REG_CRT_DISP_MODE SED_REG16(0x60) -#define SED1356_REG_CRT_DISP_START_LO_and_MID SED_REG16(0x62) -#define SED1356_REG_CRT_DISP_START_HI SED_REG16(0x64) -#define SED1356_REG_CRT_ADD_OFFSET_LO_and_HI SED_REG16(0x66) -#define SED1356_REG_CRT_PIXEL_PAN SED_REG16(0x68) -#define SED1356_REG_CRT_FIFO_THRESH_LO_and_HI SED_REG16(0x6a) -/* LCD Cursor Control Registers */ -#define SED1356_REG_LCD_CURSOR_CTL_and_START_ADD SED_REG16(0x70) -#define SED1356_REG_LCD_CURSOR_X_POS_LO_and_HI SED_REG16(0x72) -#define SED1356_REG_LCD_CURSOR_Y_POS_LO_and_HI SED_REG16(0x74) -#define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x76) -#define SED1356_REG_LCD_CURSOR_RED_CLR_0 SED_REG16(0x78) -#define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x7a) -#define SED1356_REG_LCD_CURSOR_RED_CLR_1 SED_REG16(0x7c) -#define SED1356_REG_LCD_CURSOR_FIFO_THRESH SED_REG16(0x7e) -/* CRT Cursor Control Registers */ -#define SED1356_REG_CRT_CURSOR_CTL_and_START_ADD SED_REG16(0x80) -#define SED1356_REG_CRT_CURSOR_X_POS_LO_and_HI SED_REG16(0x82) -#define SED1356_REG_CRT_CURSOR_Y_POS_LO_and_HI SED_REG16(0x84) -#define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x86) -#define SED1356_REG_CRT_CURSOR_RED_CLR_0 SED_REG16(0x88) -#define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x8a) -#define SED1356_REG_CRT_CURSOR_RED_CLR_1 SED_REG16(0x8c) -#define SED1356_REG_CRT_CURSOR_FIFO_THRESH SED_REG16(0x8e) -/* BitBlt Control Registers */ -#define SED1356_REG_BLT_CTL_0_and_1 SED_REG16(0x100) -#define SED1356_REG_BLT_ROP_CODE_and_BLT_OP SED_REG16(0x102) -#define SED1356_REG_BLT_SRC_START_LO_and_MID SED_REG16(0x104) -#define SED1356_REG_BLT_SRC_START_HI SED_REG16(0x106) -#define SED1356_REG_BLT_DEST_START_LO_and_MID SED_REG16(0x108) -#define SED1356_REG_BLT_DEST_START_HI SED_REG16(0x10a) -#define SED1356_REG_BLT_ADD_OFFSET_LO_and_HI SED_REG16(0x10c) -#define SED1356_REG_BLT_WID_LO_and_HI SED_REG16(0x110) -#define SED1356_REG_BLT_HGT_LO_and_HI SED_REG16(0x112) -#define SED1356_REG_BLT_BG_CLR_LO_and_HI SED_REG16(0x114) -#define SED1356_REG_BLT_FG_CLR_LO_and_HI SED_REG16(0x118) -/* Look-Up Table Control Registers */ -#define SED1356_REG_LUT_MODE SED_REG16(0x1e0) -#define SED1356_REG_LUT_ADD SED_REG16(0x1e2) -#define SED1356_REG_LUT_DATA SED_REG16(0x1e4) -/* Power and Miscellaneous Control Registers */ -#define SED1356_REG_PWR_CFG_and_STAT SED_REG16(0x1f0) -#define SED1356_REG_WATCHDOG_CTL SED_REG16(0x1f4) -#define SED1356_REG_DISP_MODE SED_REG16(0x1fc) - -/* - * Bit Assignments - Little Endian, Use H2SED() macro to access - * - * SED1356_REG_REV_and_MISC - even - */ -#define SED1356_REV_ID_MASK 0xfc /* ID bits - masks off the rev bits */ -#define SED1356_REV_ID_1356 BIT4 -#define SED1356_REV_ID_1355 BIT3 - -/* SED1356_REG_REV_and_MISC - odd */ -#define SED1356_MISC_HOST_DIS BIT7 << 8 /* 0 = enable host access, 1 = disable */ - -/* SED1356_REG_GPIO_CFG and SED1356_REG_GPIO_STAT */ -#define SED1356_GPIO_GPIO3 BIT3 /* 0 = input, 1 = output, if configured as GPIO */ -#define SED1356_GPIO_GPIO2 BIT2 -#define SED1356_GPIO_GPIO1 BIT1 - -/* SED1356_REG_MCLK_CFG */ -#define SED1356_MCLK_DIV2 BIT4 -#define SED1356_MCLK_SRC_BCLK BIT0 -#define SED1356_MCLK_SRC_CLKI 0x00 - -/* SED1356_REG_LCD_PCLK_CFG, SED1356_REG_CRT_PCLK_CFG - * and SED1356_REG_MEDIA_PCLK_CFG - */ -#define SED1356_PCLK_X2 BIT7 /* SED1356_REG_CRT_PCLK_CFG only */ -#define SED1356_PCLK_DIV1 0x00 << 4 -#define SED1356_PCLK_DIV2 0x01 << 4 -#define SED1356_PCLK_DIV3 0x02 << 4 -#define SED1356_PCLK_DIV4 0x03 << 4 -#define SED1356_PCLK_SRC_CLKI 0x00 -#define SED1356_PCLK_SRC_BCLK 0x01 -#define SED1356_PCLK_SRC_CLKI2 0x02 -#define SED1356_PCLK_SRC_MCLK 0x03 - -/* SED1356_REG_MEM_CFG_and_REF_RATE - even */ -#define SED1356_MEM_CFG_2CAS_EDO 0x00 -#define SED1356_MEM_CFG_2CAS_FPM 0x01 -#define SED1356_MEM_CFG_2WE_EDO 0x02 -#define SED1356_MEM_CFG_2WE_FPM 0x03 -#define SED1356_MEM_CFG_MASK 0x03 - -/* SED1356_REG_MEM_CFG_and_REF_RATE - odd */ -#define SED1356_REF_TYPE_CBR 0x00 << 6 << 8 -#define SED1356_REF_TYPE_SELF 0x01 << 6 << 8 -#define SED1356_REF_TYPE_NONE 0x02 << 6 << 8 -#define SED1356_REF_TYPE_MASK 0x03 << 6 << 8 -#define SED1356_REF_RATE_64 0x00 << 0 << 8 /* MCLK / 64 */ -#define SED1356_REF_RATE_128 0x01 << 0 << 8 /* MCLK / 128 */ -#define SED1356_REF_RATE_256 0x02 << 0 << 8 /* MCLK / 256 */ -#define SED1356_REF_RATE_512 0x03 << 0 << 8 /* MCLK / 512 */ -#define SED1356_REF_RATE_1024 0x04 << 0 << 8 /* MCLK / 1024 */ -#define SED1356_REF_RATE_2048 0x05 << 0 << 8 /* MCLK / 2048 */ -#define SED1356_REF_RATE_4096 0x06 << 0 << 8 /* MCLK / 4096 */ -#define SED1356_REF_RATE_8192 0x07 << 0 << 8 /* MCLK / 8192 */ -#define SED1356_REF_RATE_MASK 0x07 << 0 << 8 /* MCLK / 8192 */ - -/* SED1356_REG_MEM_TMG0_and_1 - even */ -#define SED1356_MEM_TMG0_EDO50_MCLK40 0x01 -#define SED1356_MEM_TMG0_EDO50_MCLK33 0x01 -#define SED1356_MEM_TMG0_EDO60_MCLK33 0x01 -#define SED1356_MEM_TMG0_EDO50_MCLK30 0x12 -#define SED1356_MEM_TMG0_EDO60_MCLK30 0x01 -#define SED1356_MEM_TMG0_EDO70_MCLK30 0x00 -#define SED1356_MEM_TMG0_EDO50_MCLK25 0x12 -#define SED1356_MEM_TMG0_EDO60_MCLK25 0x12 -#define SED1356_MEM_TMG0_EDO70_MCLK25 0x01 -#define SED1356_MEM_TMG0_EDO80_MCLK25 0x00 -#define SED1356_MEM_TMG0_EDO50_MCLK20 0x12 -#define SED1356_MEM_TMG0_EDO60_MCLK20 0x12 -#define SED1356_MEM_TMG0_EDO70_MCLK20 0x12 -#define SED1356_MEM_TMG0_EDO80_MCLK20 0x01 -#define SED1356_MEM_TMG0_FPM50_MCLK25 0x12 -#define SED1356_MEM_TMG0_FPM60_MCLK25 0x01 -#define SED1356_MEM_TMG0_FPM50_MCLK20 0x12 -#define SED1356_MEM_TMG0_FPM60_MCLK20 0x12 -#define SED1356_MEM_TMG0_FPM70_MCLK20 0x11 -#define SED1356_MEM_TMG0_FPM80_MCLK20 0x01 - -/* SED1356_REG_MEM_TMG0_and_1 - odd */ -#define SED1356_MEM_TMG1_EDO50_MCLK40 0x01 << 8 -#define SED1356_MEM_TMG1_EDO50_MCLK33 0x01 << 8 -#define SED1356_MEM_TMG1_EDO60_MCLK33 0x01 << 8 -#define SED1356_MEM_TMG1_EDO50_MCLK30 0x02 << 8 -#define SED1356_MEM_TMG1_EDO60_MCLK30 0x01 << 8 -#define SED1356_MEM_TMG1_EDO70_MCLK30 0x00 << 8 -#define SED1356_MEM_TMG1_EDO50_MCLK25 0x02 << 8 -#define SED1356_MEM_TMG1_EDO60_MCLK25 0x02 << 8 -#define SED1356_MEM_TMG1_EDO70_MCLK25 0x01 << 8 -#define SED1356_MEM_TMG1_EDO80_MCLK25 0x01 << 8 -#define SED1356_MEM_TMG1_EDO50_MCLK20 0x02 << 8 -#define SED1356_MEM_TMG1_EDO60_MCLK20 0x02 << 8 -#define SED1356_MEM_TMG1_EDO70_MCLK20 0x02 << 8 -#define SED1356_MEM_TMG1_EDO80_MCLK20 0x01 << 8 -#define SED1356_MEM_TMG1_FPM50_MCLK25 0x02 << 8 -#define SED1356_MEM_TMG1_FPM60_MCLK25 0x01 << 8 -#define SED1356_MEM_TMG1_FPM50_MCLK20 0x02 << 8 -#define SED1356_MEM_TMG1_FPM60_MCLK20 0x02 << 8 -#define SED1356_MEM_TMG1_FPM70_MCLK20 0x02 << 8 -#define SED1356_MEM_TMG1_FPM80_MCLK20 0x01 << 8 - - -/* Bit definitions - * - * SED1356_REG_PANEL_TYPE_AND_MOD_RATE - even - */ -#define SED1356_PANEL_TYPE_EL BIT7 -#define SED1356_PANEL_TYPE_4_9 (0x00 << 4) /* Passive 4-Bit, TFT 9-Bit */ -#define SED1356_PANEL_TYPE_8_12 (0x01 << 4) /* Passive 8-Bit, TFT 12-Bit */ -#define SED1356_PANEL_TYPE_16 (0x02 << 4) /* Passive 16-Bit, or TFT 18-Bit */ -#define SED1356_PANEL_TYPE_MASK (0x03 << 4) -#define SED1356_PANEL_TYPE_FMT BIT3 /* 0 = Passive Format 1, 1 = Passive Format 2 */ -#define SED1356_PANEL_TYPE_CLR BIT2 /* 0 = Passive Mono, 1 = Passive Color */ -#define SED1356_PANEL_TYPE_DUAL BIT1 /* 0 = Passive Single, 1 = Passive Dual */ -#define SED1356_PANEL_TYPE_TFT BIT0 /* 0 = Passive, 1 = TFT (DUAL, FMT & CLR are don't cares) */ - -/* SED1356_REG_CRT_HOR_PULSE, SED1356_REG_CRT_VER_PULSE, - * SED1356_REG_LCD_HOR_PULSE and SED1356_REG_LCD_VER_PULSE - */ -#define SED1356_PULSE_POL_HIGH BIT7 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */ -#define SED1356_PULSE_POL_LOW 0x00 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */ -#define SED1356_PULSE_WID(_x_) (_x_ & 0x0f) /* Pulse Width in Pixels */ - -/* SED1356_LCD_DISP_MODE_and_MISC - even */ -#define SED1356_LCD_DISP_BLANK BIT7 /* 1 = Blank LCD Display */ -#define SED1356_LCD_DISP_SWIV_NORM (0x00 << 4) /* Used with SED1356_REG_DISP_MODE Bit 6 */ -#define SED1356_LCD_DISP_SWIV_90 (0x00 << 4) -#define SED1356_LCD_DISP_SWIV_180 (0x01 << 4) -#define SED1356_LCD_DISP_SWIV_270 (0x01 << 4) -#define SED1356_LCD_DISP_SWIV_MASK (0x01 << 4) -#define SED1356_LCD_DISP_16BPP 0x05 /* Bit Per Pixel Selection */ -#define SED1356_LCD_DISP_15BPP 0x04 -#define SED1356_LCD_DISP_8BPP 0x03 -#define SED1356_LCD_DISP_4BPP 0x02 -#define SED1356_LCD_DISP_BPP_MASK 0x07 - -/* SED1356_LCD_DISP_MODE_and_MISC - odd */ -#define SED1356_LCD_MISC_DITH BIT1 << 8 /* 1 = Dither Disable, Passive Panel Only */ -#define SED1356_LCD_MISC_DUAL BIT0 << 8 /* 1 = Dual Panel Disable, Passive Panel Only */ - -/* SED1356_REG_CRT_VER_PULSE_and_OUT_CTL - odd */ -#define SED1356_CRT_OUT_CHROM BIT5 << 8 /* 1 = TV Chrominance Filter Enable */ -#define SED1356_CRT_OUT_LUM BIT4 << 8 /* 1 = TV Luminance Filter Enable */ -#define SED1356_CRT_OUT_DAC_LVL BIT3 << 8 /* 1 = 4.6ma IREF, 0 = 9.2 IREF */ -#define SED1356_CRT_OUT_SVIDEO BIT1 << 8 /* 1 = S-Video Output, 0 = Composite Video Output */ -#define SED1356_CRT_OUT_PAL BIT0 << 8 /* 1 = PAL Format Output, 0 = NTSC Format Output */ - -/* SED1356_REG_CRT_DISP_MODE */ -#define SED1356_CRT_DISP_BLANK BIT7 /* 1 = Blank CRT Display */ -#define SED1356_CRT_DISP_16BPP 0x05 /* Bit Per Pixel Selection */ -#define SED1356_CRT_DISP_15BPP 0x04 -#define SED1356_CRT_DISP_8BPP 0x03 -#define SED1356_CRT_DISP_4BPP 0x02 -#define SED1356_CRT_DISP_BPP_MASK 0x07 - -/* SED1356_DISP_MODE */ -#define SED1356_DISP_SWIV_NORM (0x00 << 6) /* Used with SED1356_LCD_DISP_MODE Bit 4 */ -#define SED1356_DISP_SWIV_90 (0x01 << 6) -#define SED1356_DISP_SWIV_180 (0x00 << 6) -#define SED1356_DISP_SWIV_270 (0x01 << 6) -#define SED1356_DISP_MODE_OFF 0x00 /* All Displays Off */ -#define SED1356_DISP_MODE_LCD 0x01 /* LCD Only */ -#define SED1356_DISP_MODE_CRT 0x02 /* CRT Only */ -#define SED1356_DISP_MODE_LCD_CRT 0x03 /* Simultaneous LCD and CRT */ -#define SED1356_DISP_MODE_TV 0x04 /* TV Only, Flicker Filter Off */ -#define SED1356_DISP_MODE_TV_LCD 0x05 /* Simultaneous LCD and TV, Flicker Filter Off */ -#define SED1356_DISP_MODE_TV_FLICK 0x06 /* TV Only, Flicker Filter On */ -#define SED1356_DISP_MODE_TV_LCD_FLICK 0x07 /* Simultaneous LCD and TV, Flicker Filter On */ - -/* SED1356_REG_PWR_CFG and SED1356_REG_PWR_STAT */ -#define SED1356_PWR_PCLK BIT1 /* SED1356_REG_PWR_STAT only */ -#define SED1356_PWR_MCLK BIT0 - -/* SED1356_REG_VER_NONDISP */ -#define SED1356_VER_NONDISP BIT7 /* vertical retrace status 1 = in retrace */ - -/* Display size defines */ -extern long PIXELS_PER_ROW; -extern long PIXELS_PER_COL; -#define BYTES_PER_PIXEL 2 -extern long COLS_PER_SCREEN; -extern long ROWS_PER_SCREEN; - -/* 16-bit pixels are RGB 565 - LSB of RED and BLUE are tied low at the */ -/* LCD Interface, while the LSB of GREEN is loaded as 0 */ -#define RED_SUBPIXEL(n) ((n & 0x1f) << 11) -#define GREEN_SUBPIXEL(n) ((n & 0x1f) << 5) -#define BLUE_SUBPIXEL(n) ((n & 0x1f) << 0) - -/* define a simple VGA style 16-color pallette */ -#if 0 -#define LU_BLACK (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)) -#define LU_BLUE (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f)) -#define LU_GREEN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00)) -#define LU_CYAN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f)) -#define LU_RED (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)) -#define LU_VIOLET (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f)) -#define LU_YELLOW (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00)) -#define LU_GREY (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f)) -#define LU_WHITE (RED_SUBPIXEL(0x17) | GREEN_SUBPIXEL(0x17) | BLUE_SUBPIXEL(0x17)) -#define LU_BRT_BLUE (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f)) -#define LU_BRT_GREEN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00)) -#define LU_BRT_CYAN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f)) -#define LU_BRT_RED (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)) -#define LU_BRT_VIOLET (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f)) -#define LU_BRT_YELLOW (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00)) -#define LU_BRT_WHITE (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f)) -/* RED, GREEN, BLUE Entry */ - { 0x00, 0x00, 0x00, }, /* LU_BLACK */ - { 0x00, 0x00, 0xA0, }, /* LU_BLUE */ - { 0x00, 0xA0, 0x00, }, /* LU_GREEN */ - { 0x00, 0xA0, 0xA0, }, /* LU_CYAN */ - { 0xA0, 0x00, 0x00, }, /* LU_RED */ - { 0xA0, 0x00, 0xA0, }, /* LU_VIOLET */ - { 0xA0, 0xA0, 0x00, }, /* LU_YELLOW */ - { 0xA0, 0xA0, 0xA0, }, /* LU_WHITE */ - { 0x50, 0x50, 0x50, }, /* LU_GREY */ - { 0x50, 0x50, 0xF0, }, /* LU_BRT_BLUE */ - { 0x50, 0xF0, 0x50, }, /* LU_BRT_GREEN */ - { 0x50, 0xF0, 0xF0, }, /* LU_BRT_CYAN */ - { 0xF0, 0x50, 0x50, }, /* LU_BRT_RED */ - { 0xF0, 0x50, 0xF0, }, /* LU_BRT_VIOLET */ - { 0xF0, 0xF0, 0x50, }, /* LU_BRT_YELLOW */ - { 0xF0, 0xF0, 0xF0, }, /* LU_BRT_WHITE */ -#endif - -#define BLUE (0x14 << 0) -#define GREEN (0x14 << 6) -#define RED (0x14 << 11) - -#define HALF_BLUE (0x0a << 0) -#define HALF_GREEN (0x0a << 6) -#define HALF_RED (0x0a << 11) - - -#define BRT_BLUE (0x1e << 0) -#define BRT_GREEN (0x1e << 6) -#define BRT_RED (0x1e << 11) - -#define LU_BLACK 0 -#define LU_BLUE (BLUE) -#define LU_GREEN (GREEN) -#define LU_CYAN (GREEN | BLUE) -#define LU_RED (RED) -#define LU_VIOLET (RED | BLUE) -#define LU_YELLOW (RED | GREEN) -#define LU_WHITE (RED | GREEN | BLUE) -#define LU_GREY (HALF_RED | HALF_GREEN | HALF_BLUE) -#define LU_BRT_BLUE (HALF_RED | HALF_GREEN | BRT_BLUE) -#define LU_BRT_GREEN (HALF_RED | BRT_GREEN | HALF_BLUE) -#define LU_BRT_CYAN (HALF_RED | BRT_GREEN | BRT_BLUE) -#define LU_BRT_RED (BRT_RED | HALF_GREEN | HALF_BLUE) -#define LU_BRT_VIOLET (BRT_RED | HALF_GREEN | BRT_BLUE) -#define LU_BRT_YELLOW (BRT_RED | BRT_GREEN | HALF_BLUE) -#define LU_BRT_WHITE (BRT_RED | BRT_GREEN | BRT_BLUE) - -const ushort vga_lookup[] = { -LU_BLACK, /* 0 */ -LU_BLUE, /* 1 */ -LU_GREEN, /* 2 */ -LU_CYAN, /* 3 */ -LU_RED, /* 4 */ -LU_VIOLET, /* 5 */ -LU_YELLOW, /* 6 */ -LU_WHITE, /* 7 */ -LU_GREY, /* 8 */ -LU_BRT_BLUE, /* 9 */ -LU_BRT_GREEN, /* 10 */ -LU_BRT_CYAN, /* 11 */ -LU_BRT_RED, /* 12 */ -LU_BRT_VIOLET, /* 13 */ -LU_BRT_YELLOW, /* 14 */ -LU_BRT_WHITE /* 15 */ -}; - -/* default foreground and background colors */ -#define SED_BG_DEF 1 -#define SED_FG_DEF 14 - -/* Draw defines */ -#define TOP 0 -#define BOTTOM (PIXELS_PER_COL-1) -#define LEFT 0 -#define RIGHT (PIXELS_PER_ROW-1) -#define CENTER_X (PIXELS_PER_ROW/2) -#define CENTER_Y (PIXELS_PER_COL/2) - - -/* Vertical and Horizontal Pulse, Start and Non-Display values vary depending - * upon the mode. The following section gives some insight into how the - * values are arrived at. - * ms = milliseconds, us = microseconds, ns = nanoseconds - * Mhz = Megaherz, Khz = Kiloherz, Hz = Herz - * - * *************************************************************************************************** - * CRT Mode is 640x480 @ 72Hz VESA compatible timing. PCLK = 31.5Mhz (31.75ns) - * *************************************************************************************************** - * - * CRT MODE HORIZONTAL TIMING PARAMETERS - * - * |<-------Tha------->| - * |___________________| ______ - * Display Enable _____________________| |____________________| - * | | - * Horizontal Pulse __ ________|___________________|________ __________ - * |_________| | | |________| - * |<- Thp ->| | | | - * | |<-Thbp->| | | - * | |<-Thfp->| - * |<----------------------Tht-------------------->| - * - * Tha - Active Display Time = 640 pixels - * Thp - Horizontal Pulse = 1.27us/31.75ns = 40 pixels - * Thbp - Horizontal Front Porch = 1.016us/31.75ns = 32 pixels - * Thfp - Horizontal Back Porch = 3.8us/31.75ns = 120 pixels - * Tht - Total Horizontal Time = 832 pixels x 32.75ns/pixel = 26.416us or 38.785Khz - * - * Correlation between horizontal timing parameters and SED registers - */ -#define SED_HOR_PULSE_WIDTH_CRT 0x07 /* Horizontal Pulse Width Register = (Thp/8) - 1 */ -#define SED_HOR_PULSE_START_CRT 0x02 /* Horizontal Pulse Start Position Register = ((Thfp + 2)/8) - 1 */ -#define SED_HOR_NONDISP_CRT 0x17 /* Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1 */ -/* - * CRT MODE VERTICAL TIMING PARAMTERS - * - * |<-------Tva------->| - * |___________________| ______ - * Display Enable _____________________| |_____________________| - * | | - * Vertical Pulse __ ________|___________________|________ __________ - * |_________| | | |________| - * |<- Tvp ->| | | | - * | |<-Tvbp->| | | - * | |<-Tvfp->| - * |<----------------------Tvt-------------------->| - * - * Tva - Active Display Time = 480 lines - * Tvp - Vertical Pulse = 3 lines - * Tvfp - Vertical Front Porch = 9 lines - * Tvbp - Vertical Back Porch = 28 lines - * Tvt - Total Horizontal Time = 520 lines x 26.416us/line = 13.73632ms or 72.8Hz - * - * Correlation between vertical timing parameters and SED registers - */ -#define SED_VER_PULSE_WIDTH_CRT 0x02 // VRTC/FPFRAME Pulse Width Register = Tvp - 1 -#define SED_VER_PULSE_START_CRT 0x08 // VRTC/FPFRAME Start Position Register = Tvfp - 1 -#define SED_VER_NONDISP_CRT 0x27 // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1 -/* - ***************************************************************************************************** - * DUAL LCD Mode is 640x480 @ 60Hz VGA compatible timing. PCLK = 25.175Mhz (39.722ns) - ***************************************************************************************************** - * - * LCD MODE HORIZONTAL TIMING PARAMTERS - * - * |<-------Tha------->| - * |___________________| ______ - * Display Enable _____________________| |____________________| - * | | - * Horizontal Pulse __ ________|___________________|________ __________ - * |_________| | | |________| - * |<- Thp ->| | | | - * | |<-Thbp->| | | - * | |<-Thfp->| - * |<----------------------Tht-------------------->| - * - * Tha - Active Display Time = 640 pixels - * Thp - Horizontal Pulse = 3.8us/39.72ns = 96 pixels - * Thfp - Horizontal Front Porch = .595us/39.72ns = 16 pixels - * Thbp - Horizontal Backporch = 1.9us/39.72ns = 48 pixels - * Tht - Total Horizontal Time = = 800 pixels @ 39.72ns/pixel = 31.776us or 31.47Khz - * - * Correlation between horizontal timing parameters and SED registers - *#define SED_HOR_PULSE_WIDTH_LCD 0x0b // HRTC/FPLINE Pulse Width Register = (Thp/8) - 1 - *#define SED_HOR_PULSE_START_LCD 0x02 // HRTC/FPLINE Start Position Register = (Thfp/8) - 2 - *#define SED_HOR_NONDISP_LCD 0x13 // Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1 - */ -extern long SED_HOR_PULSE_WIDTH_LCD; -extern long SED_HOR_PULSE_START_LCD; -extern long SED_HOR_NONDISP_LCD; - -/* - * - * LCD MODE VERTICAL TIMING PARAMTERS - * - * |<-------Tva------->| - * |___________________| ______ - * Display Enable _____________________| |_____________________| - * | | - * Vertical Pulse __ ________|___________________|________ __________ - * |_________| | | |________| - * |<- Tvp ->| | | | - * | |<-Tvbp->| | | - * | |<-Tvfp->| - * |<----------------------Tvt-------------------->| - * - * Tva - Active Display Time = 480 lines - * Tvp - Vertical Pulse = 2 lines - * Tvfp - Vertical Front Porch = 10 lines - * Tvbp - Vertical Backporch = 33 lines - * Tvt - Total Horizontal Time = 525 lines @ 31.776us/line = 16.682ms or 60Hz - * - * Correlation between vertical timing parameters and SED registers - *#define SED_VER_PULSE_WIDTH_LCD 0x01 // VRTC/FPFRAME Pulse Width Register = Tvp - 1 - *#define SED_VER_PULSE_START_LCD 0x09 // VRTC/FPFRAME Start Position Register = Tvfp - 1 - *#define SED_VER_NONDISP_LCD 0x2c // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1 - */ -extern long SED_VER_PULSE_WIDTH_LCD; -extern long SED_VER_PULSE_START_LCD; -extern long SED_VER_NONDISP_LCD; - -#endif diff --git a/c/src/lib/libbsp/arm/csb337/include/at91rm9200.h b/c/src/lib/libbsp/arm/csb337/include/at91rm9200.h deleted file mode 100644 index 3ed64c7073..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/at91rm9200.h +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Atmel AT91RM9200 Register definitions, used in KIT637_V6 (CSB637) - * - * Copyright (c) 2003 by Cogent Computer Systems - * Written by Mike Kelly <mike@cogcomp.com> - * - * Modified by Fernando Nicodemos <fgnicodemos@terra.com.br> - * from NCB - Sistemas Embarcados Ltda. (Brazil) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. -*/ - - -#ifndef __AT91RM9200_H__ -#define __AT91RM9200_H__ - -#include "bits.h" - -typedef volatile unsigned long vulong; - -/* Source Mode Register - 32 of them */ -#define AIC_SMR_BASE 0xFFFFF000 -#define AIC_SMR_REG(_x_) *(vulong *)(AIC_SMR_BASE + (_x_ & 0x7c)) - -/* Source Vector Register - 32 of them */ -#define AIC_SVR_BASE 0xFFFFF080 -#define AIC_SVR_REG(_x_) *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c)) - -/* Control Register - 32 of them */ -#define AIC_CTL_BASE 0xFFFFF100 -#define AIC_CTL_REG(_x_) *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f)) - -/* Register Offsets */ -/* offsets from AIC_SMR_BASE and AIC_SVR_BASE */ -#define AIC_SMR_FIQ 0x00 /* Advanced Interrupt Controller FIQ */ -#define AIC_SMR_SYSIRQ 0x04 /* Advanced Interrupt Controller SYSIRQ */ -#define AIC_SMR_PIOA 0x08 /* Parallel I/O Controller A */ -#define AIC_SMR_PIOB 0x0c /* Parallel I/O Controller B */ -#define AIC_SMR_PIOC 0x10 /* Parallel I/O Controller C */ -#define AIC_SMR_PIOD 0x14 /* Parallel I/O Controller D */ -#define AIC_SMR_US0 0x18 /* USART 0 */ -#define AIC_SMR_US1 0x1c /* USART 1 */ -#define AIC_SMR_US2 0x20 /* USART 2 */ -#define AIC_SMR_US3 0x24 /* USART 3 */ -#define AIC_SMR_MCI 0x28 /* Multimedia Card Interface */ -#define AIC_SMR_UDP 0x2c /* USB Device Port */ -#define AIC_SMR_TWI 0x30 /* Two-wire Interface */ -#define AIC_SMR_SPI 0x34 /* Serial Peripheral Interface */ -#define AIC_SMR_SSC0 0x38 /* Synchronous Serial Controller 0 */ -#define AIC_SMR_SSC1 0x3c /* Synchronous Serial Controller 1 */ -#define AIC_SMR_SSC2 0x40 /* Synchronous Serial Controller 2 */ -#define AIC_SMR_TC0 0x44 /* Timer/Counter 0 */ -#define AIC_SMR_TC1 0x48 /* Timer/Counter 1 */ -#define AIC_SMR_TC2 0x4c /* Timer/Counter 2 */ -#define AIC_SMR_TC3 0x50 /* Timer/Counter 3 */ -#define AIC_SMR_TC4 0x54 /* Timer/Counter 4 */ -#define AIC_SMR_TC5 0x58 /* Timer/Counter 5 */ -#define AIC_SMR_UHP 0x5c /* USB Host Port */ -#define AIC_SMR_EMAC 0x60 /* Ethernet MAC */ -#define AIC_SMR_IRQ0 0x64 /* Advanced Interrupt Controller IRQ0 */ -#define AIC_SMR_IRQ1 0x68 /* Advanced Interrupt Controller IRQ1 */ -#define AIC_SMR_IRQ2 0x6c /* Advanced Interrupt Controller IRQ2 */ -#define AIC_SMR_IRQ3 0x70 /* Advanced Interrupt Controller IRQ3 */ -#define AIC_SMR_IRQ4 0x74 /* Advanced Interrupt Controller IRQ4 */ -#define AIC_SMR_IRQ5 0x78 /* Advanced Interrupt Controller IRQ5 */ -#define AIC_SMR_IRQ6 0x7c /* Advanced Interrupt Controller IRQ6 */ - -/* from AIC_CTL_BASE */ -#define AIC_IVR 0x00 /* IRQ Vector Register */ -#define AIC_FVR 0x04 /* FIQ Vector Register */ -#define AIC_ISR 0x08 /* Interrupt Status Register */ -#define AIC_IPR 0x0C /* Interrupt Pending Register */ -#define AIC_IMR 0x10 /* Interrupt Mask Register */ -#define AIC_CISR 0x14 /* Core Interrupt Status Register */ -#define AIC_IECR 0x20 /* Interrupt Enable Command Register */ -#define AIC_IDCR 0x24 /* Interrupt Disable Command Register */ -#define AIC_ICCR 0x28 /* Interrupt Clear Command Register */ -#define AIC_ISCR 0x2C /* Interrupt Set Command Register */ -#define AIC_EOICR 0x30 /* End of Interrupt Command Register */ -#define AIC_SPU 0x34 /* Spurious Vector Register */ -#define AIC_DCR 0x38 /* Debug Control Register (Protect) */ -#define AIC_FFER 0x40 /* Fast Forcing Enable Register */ -#define AIC_FFDR 0x44 /* Fast Forcing Disable Register */ -#define AIC_FFSR 0x48 /* Fast Forcing Status Register */ - -/* Bit Defines */ -/* AIC_ISR - Interrupt Status Register */ -#define AIC_ISR_IRQID_MASK 0x1f /* current interrupt ID */ - -/* AIC_CISR - Core Interrupt Status Register */ -#define AIC_CISR_IRQ BIT1 /* 1 = Core IRQ is active */ -#define AIC_CISR_FIQ BIT0 /* 1 = Core FIQ is active */ - -/* AIC_DCR - Debug Control Register (Protect) */ -#define AIC_DCR_GMSK BIT1 /* 0 = AIC controls IRQ and FIQ */ -#define AIC_DCR_PROT BIT0 /* 1 = enable protection mode */ - -/* AIC_SMR */ -#define AIC_SMR_PRIOR(_x_) ((_x_ & 0x07) << 0) -#define AIC_SMR_SRC_LVL_LOW (0 << 5) /* Are these right? docs don't say which is high/low */ -#define AIC_SMR_SRC_EDGE_LOW (1 << 5) -#define AIC_SMR_SRC_LVL_HI (2 << 5) -#define AIC_SMR_SRC_EDGE_HI (3 << 5) - -/**************************************************************************/ -/* Debug Unit */ -/**************************************************************************/ -#define DBGU_BASE 0xFFFFF200 -#define DBGU_REG(_x_) *(vulong *)(DBGU_BASE + _x_) - -/* Register Offsets */ -#define DBGU_CR 0x00 /* Control Register */ -#define DBGU_MR 0x04 /* Mode Register */ -#define DBGU_IER 0x08 /* Interrupt Enable Register */ -#define DBGU_IDR 0x0C /* Interrupt Disable Register */ -#define DBGU_IMR 0x10 /* Interrupt Mask Register */ -#define DBGU_CSR 0x14 /* Channel Status Register */ -#define DBGU_RHR 0x18 /* Receiver Holding Register */ -#define DBGU_THR 0x1C /* Transmitter Holding Register */ -#define DBGU_BRGR 0x20 /* Baud Rate Generator Register */ -#define DBGU_C1R 0x40 /* Chip ID1 Register */ -#define DBGU_C2R 0x44 /* Chip ID2 Register */ -#define DBGU_FNTR 0x48 /* Force NTRST Register */ - -/**************************************************************************/ -/* USART 0-3 */ -/**************************************************************************/ -#define USART0_BASE 0xFFFC0000 -#define USART1_BASE 0xFFFC4000 -#define USART2_BASE 0xFFFC8000 -#define USART3_BASE 0xFFFCC000 -/* - * WARNING: The USART3_BASE at the AT91RM9200 Manual is wrong!!! - * Manual revision: Rev. 1768H-ATARM–16-Jun-09 - * USART3_BASE is NOT 0xFFECC000 - */ - -/****************/ -/* System Timer */ -/****************/ -#define ST_BASE 0xFFFFFD00 -#define ST_REG(_x_) *(vulong *)(ST_BASE + _x_) - -/* Register Offsets */ -#define ST_CR 0x00 /* Control Register */ -#define ST_PIMR 0x04 /* Period Interval Mode Register */ -#define ST_WDMR 0x08 /* Watchdog Mode Register */ -#define ST_RTMR 0x0C /* Real-time Mode Register */ -#define ST_SR 0x10 /* Status Register */ -#define ST_IER 0x14 /* Interrupt Enable Register */ -#define ST_IDR 0x18 /* Interrupt Disable Register */ -#define ST_IMR 0x1C /* Interrupt Mask Register */ -#define ST_RTAR 0x20 /* Real-time Alarm Register */ -#define ST_CRTR 0x24 /* Current Real-time Register */ - -/* Bit Defines */ -/* ST_CR - Control Register */ -#define ST_CR_WDRST BIT0 /* write 1 to reload WD counter */ - -/* ST_PIMR - Period Interval Mode Register */ -#define ST_PIMR_PIV_MASK 0x0000ffff - -/* ST_WDMR - Watchdog Mode Register */ -#define ST_WDMR_EXTEN BIT17 /* WDOVF is not implemented on AT91RM9200 */ -#define ST_WDMR_RSTEN BIT16 /* 1 = reset the AT91RM9200 when WD overflows */ -#define ST_WDMR_WDV_MASK 0x0000ffff /* WD counter is in the lower 16-bits */ - -/* ST_RTMR - Real-time Mode Register */ -#define ST_RTMR_RTPRES_MASK 0x0000ffff /* Real-Time Prescaler */ - -/* ST_SR - Status Register - Read Only */ -/* ST_IER - Interrupt Enable Register - Write Only */ -/* ST_IDR - Interrupt Disable Register - Write Only */ -/* ST_IMR - Interrupt Mask Register - Read Only */ -#define ST_SR_ALMS BIT3 -#define ST_SR_RTTINC BIT2 -#define ST_SR_WDOVF BIT1 -#define ST_SR_PITS BIT0 - -/* ST_RTAR - Real-time Alarm Register */ -#define ST_RTAR_ALMV_MASK 0x000fffff - -/* ST_CRTR - Current Real-time Register */ -#define ST_CRTR_CRTV_MASK 0x000fffff - - -/************************************************************************** - * Peripheral Data Control (DMA) - * Note that each of the following peripherals has it's own - * set of these registers starting at offset 0x100 from it's - * base address: DBGU, SPI, USART and SSC - * To access the DMA for a peripheral, use the macro for that - * peripheral but with these register offsets - **************************************************************************/ -/* Register Offsets */ -#define PDC_RPR 0x100 /* Receive Pointer Register */ -#define PDC_RCR 0x104 /* Receive Counter Register */ -#define PDC_TPR 0x108 /* Transmit Pointer Register */ -#define PDC_TCR 0x10c /* Transmit Counter Register */ -#define PDC_RNPR 0x110 /* Receive Next Pointer Register */ -#define PDC_RNCR 0x114 /* Receive Next Counter Register */ -#define PDC_TNPR 0x118 /* Transmit Next Pointer Register */ -#define PDC_TNCR 0x11c /* Transmit Next Counter Register */ -#define PDC_PTCR 0x120 /* PDC Transfer Control Register */ -#define PDC_PTSR 0x124 /* PDC Transfer Status Register */ - -/************************************************************************** - * Parallel I/O Unit - * There are four PIO blocks - A, B, C and D. They all have the - * same register set, but different base addresses - **************************************************************************/ -/* Port A */ -#define PIOA_BASE 0xFFFFF400 -#define PIOA_REG(_x_) *(vulong *)(PIOA_BASE + _x_) - -/* Port B */ -#define PIOB_BASE 0xFFFFF600 -#define PIOB_REG(_x_) *(vulong *)(PIOB_BASE + _x_) - -/* Port C */ -#define PIOC_BASE 0xFFFFF800 -#define PIOC_REG(_x_) *(vulong *)(PIOC_BASE + _x_) - -/* Port D */ -#define PIOD_BASE 0xFFFFFA00 -#define PIOD_REG(_x_) *(vulong *)(PIOD_BASE + _x_) - -/************************************************************************** - * Power Management and Clock Control - *************************************************************************/ -#define PMC_BASE 0xFFFFFC00 -#define PMC_REG(_x_) *(vulong *)(PMC_BASE + _x_) - -/************************************************************************** - * MAC Unit - *************************************************************************/ -#define EMAC_BASE 0xFFFBC000 -#define EMAC_REG(_x_) *(vulong *)(EMAC_BASE + _x_) - -/************************************************************************** - * Timer/Counter Unit - **************************************************************************/ -#define TC_BASE 0xFFFA0000 -#define TC_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_) -#define TC_TC0_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_) -#define TC_TC1_REG(_x_) *(vulong *)(TC_BASE + 0x40 + _x_) -#define TC_TC2_REG(_x_) *(vulong *)(TC_BASE + 0x80 + _x_) - -/* Offsets from TC_TC?_REG */ -#define TC_CCR 0x00 /* Channel Control Register */ -#define TC_CMR 0x04 /* Channel Mode Register */ -#define TC_CV 0x10 /* Counter Value */ -#define TC_RA 0x14 /* Register A */ -#define TC_RB 0x18 /* Register B */ -#define TC_RC 0x1C /* Register C */ -#define TC_SR 0x20 /* Status Register */ -#define TC_IER 0x24 /* Interrupt Enable Register */ -#define TC_IDR 0x28 /* Interrupt Disable Register */ -#define TC_IMR 0x2C /* Interrupt Mask Register */ - -/* Offsets from TC_BASE */ -#define TC_BCR 0xc0 /* Channel Control Register */ -#define TC_BMR 0xc4 /* Channel Control Register */ - -/* Block control register */ -#define TC_BCR_SYNC BIT1 /* Set to syncronize channels */ - -/* Block mode register */ -#define TC_BMR_TC0(_x_) ((_x_ & 0x3) << 0) /* TC0 clock source */ -#define TC_BMR_TC1(_x_) ((_x_ & 0x3) << 2) /* TC1 clock source */ -#define TC_BMR_TC2(_x_) ((_x_ & 0x3) << 4) /* TC2 clock source */ - -/* Channel Control register */ -#define TC_CCR_CLKEN BIT0 /* Enable clock */ -#define TC_CCR_CLKDIS BIT1 /* Disable clock */ -#define TC_CCR_SWTRG BIT2 /* Software trigger command */ - -/* Channel mode register */ -#define TC_CMR_TCCLKS(_x_) ((_x_ & 0x7) << 0) /* Clock source */ -#define TC_CMR_CLKI BIT3 /* Clock invert */ -#define TC_BURST(_x_) ((_x_ & 0x3 << 4) /* Burst signal selection */ -#define TC_WAVE BIT15 /* 0 for catpure, 1 for wave */ - -/* Channel mode register - capture mode (TC_WAVE = 0) */ -#define TC_CMR_LDBSTOP BIT6 /* Set to stop clock when RB loads */ -#define TC_CMR_LDBDIS BIT7 /* Set to disable clock when RB loads */ -#define TC_CMR_ETRGEDG(_x_) ((_x_ & 0x3) << 8) /* Select edge triggering mode */ -#define TC_CMR_ABETRG BIT10 /* Select ext trigger source */ -#define TC_CMR_CPCTRG BIT14 /* RC Compare trigger enable */ -#define TC_CMR_LDRA(_x_) ((_x_ & 0x3) << 16) /* RA loading selection */ -#define TC_CMR_LDRB(_x_) ((_x_ & 0x3) << 18) /* RB loading selection */ - -/* Channel mode register - wave mode (TC_WAVE = 1) */ -#define TC_CMR_CPCSTOP BIT6 /* Clock stopped w/ RC compare */ -#define TC_CMR_CPCDIS BIT7 /* Clock disabled w/ RC compare */ -#define TC_CMR_EEVTEDG(_x_) ((_x_ & 0x3) << 8) /* Ext event edge selection */ -#define TC_CMR_EEVT(_x_) ((_x_ & 0x3) << 10) /* Ext event selection */ -#define TC_CMR_ENETRG BIT12 /* Ext event trigger enable */ -#define TC_CMR_WAVESEL(_x_) ((_x_ & 0x3) << 13) /* Waveform selection */ -#define TC_CMR_ACPA(_x_) ((_x_ & 0x3) << 16) /* RA compare effect on TIOA */ -#define TC_CMR_ACPC(_x_) ((_x_ & 0x3) << 18) /* RC compare effect on TIOA */ -#define TC_CMR_AEEVT(_x_) ((_x_ & 0x3) << 20) /* Ext event effect on TIOA */ -#define TC_CMR_ASWTRG(_x_) ((_x_ & 0x3) << 22) /* SW trigger effect on TIOA */ -#define TC_CMR_BCPB(_x_) ((_x_ & 0x3) << 24) /* RB compare effect on TIOB */ -#define TC_CMR_BCPC(_x_) ((_x_ & 0x3) << 26) /* RC compare effect on TIOB */ -#define TC_CMR_BEEVT(_x_) ((_x_ & 0x3) << 28) /* Ext event effect on TIOB */ -#define TC_CMR_BSWTRG(_x_) ((_x_ & 0x3) << 30) /* SW trigger effect on TIOB */ - -/* Counter value */ -#define TC_CV_MASK 0xffff /* Timer counter mask */ - -/* Status, Interrupt enable, Interrupt disable, and Interrupt mask registers */ -#define TC_SR_COVFS BIT0 /* Counter overflow status */ -#define TC_SR_LOVRS BIT1 /* Load overrun status */ -#define TC_SR_CPAS BIT2 /* RA compare status */ -#define TC_SR_CPBS BIT3 /* RB compare status */ -#define TC_SR_CPCS BIT4 /* RC compare status */ -#define TC_SR_LDRAS BIT5 /* RA loading status */ -#define TC_SR_LDRBS BIT6 /* RB loading status */ -#define TC_SR_ETRGS BIT7 /* External trigger status */ -#define TC_SR_CLKSTA BIT16 /* Clock enabling status */ -#define TC_SR_MTIOA BIT17 /* TIOA Mirror */ -#define TC_SR_MTIOB BIT18 /* TIOB Mirror */ - -/*************************************************************************** - * External Bus Interface Unit - **************************************************************************/ -#define EBI_BASE 0xFFFFFF60 -#define EBI_REG(_x_) *(vulong *)(EBI_BASE + _x_) - -/*************************************************************************** - * Static Memory Interface Unit - ***************************************************************************/ -#define SMC_REG(_x_) *(vulong *)(EBI_BASE + 0x10 + _x_) - -/************************************************************************** - * SDRAM Memory Interface Unit - **************************************************************************/ -#define SDRC_REG(_x_) *(vulong *)(EBI_BASE + 0x30 + _x_) - -#endif /* __AT91RM9200_H__ */ - diff --git a/c/src/lib/libbsp/arm/csb337/include/at91rm9200_dbgu.h b/c/src/lib/libbsp/arm/csb337/include/at91rm9200_dbgu.h deleted file mode 100644 index 9a65483db0..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/at91rm9200_dbgu.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Atmel AT91RM9200_DBGU Register definitions - * - * Copyright (c) 2003 by Cogent Computer Systems - * Written by Mike Kelly <mike@cogcomp.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef __AT91RM9200_DBGU_H__ -#define __AT91RM9200_DBGU_H__ - -#include "bits.h" - -/* Register Offsets */ -#define DBGU_CR 0x00 /* Control Register */ -#define DBGU_MR 0x04 /* Mode Register */ -#define DBGU_IER 0x08 /* Interrupt Enable Register */ -#define DBGU_IDR 0x0C /* Interrupt Disable Register */ -#define DBGU_IMR 0x10 /* Interrupt Mask Register */ -#define DBGU_SR 0x14 /* Channel Status Register */ -#define DBGU_RHR 0x18 /* Receiver Holding Register */ -#define DBGU_THR 0x1C /* Transmitter Holding Register */ -#define DBGU_BRGR 0x20 /* Baud Rate Generator Register */ -#define DBGU_C1R 0x40 /* Chip ID1 Register */ -#define DBGU_C2R 0x44 /* Chip ID2 Register */ -#define DBGU_FNTR 0x48 /* Force NTRST Register */ - -/* Bit Defines */ -/* Control Register, DBGU_CR, Offset 0x00 */ -#define DBGU_CR_RSTRX BIT2 /* 1 = Reset and disable receiver */ -#define DBGU_CR_RSTTX BIT3 /* 1 = Reset and disable transmitter */ -#define DBGU_CR_RXEN BIT4 /* 1 = Receiver enable */ -#define DBGU_CR_RXDIS BIT5 /* 1 = Receiver disable */ -#define DBGU_CR_TXEN BIT6 /* 1 = Transmitter enable */ -#define DBGU_CR_TXDIS BIT7 /* 1 = Transmitter disable */ -#define DBGU_CR_RSTSTA BIT8 /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */ - -/* Mode Register. DBGU_MR. Offset 0x04 */ -#define DBGU_MR_PAR_EVEN (0x0 << 9) /* Even Parity */ -#define DBGU_MR_PAR_ODD (0x1 << 9) /* Odd Parity */ -#define DBGU_MR_PAR_SPACE (0x2 << 9) /* Parity forced to 0 (Space) */ -#define DBGU_MR_PAR_MARK (0x3 << 9) /* Parity forced to 1 (Mark) */ -#define DBGU_MR_PAR_NONE (0x4 << 9) /* No Parity */ -#define DBGU_MR_PAR_MDROP (0x6 << 9) /* Multi-drop mode */ -#define DBGU_MR_CHMODE_NORM (0x0 << 14) /* Normal Mode */ -#define DBGU_MR_CHMODE_AUTO (0x1 << 14) /* Auto Echo: RXD drives TXD */ -#define DBGU_MR_CHMODE_LOC (0x2 << 14) /* Local Loopback: TXD drives RXD */ -#define DBGU_MR_CHMODE_REM (0x3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */ - -/* Interrupt Enable Register, DBGU_IER, Offset 0x08 */ -/* Interrupt Disable Register, DBGU_IDR, Offset 0x0C */ -/* Interrupt Mask Register, DBGU_IMR, Offset 0x10 */ -/* Channel Status Register, DBGU_SR, Offset 0x14 */ -#define DBGU_INT_RXRDY BIT0 /* RXRDY Interrupt */ -#define DBGU_INT_TXRDY BIT1 /* TXRDY Interrupt */ -#define DBGU_INT_ENDRX BIT3 /* End of Receive Transfer Interrupt */ -/*efine DBGU_INT_ENDTX BIT4 /* End of Transmit Interrupt */ -#define DBGU_INT_OVRE BIT5 /* Overrun Interrupt */ -#define DBGU_INT_FRAME BIT6 /* Framing Error Interrupt */ -#define DBGU_INT_PARE BIT7 /* Parity Error Interrupt */ -#define DBGU_INT_TXEMPTY BIT9 /* TXEMPTY Interrupt */ -#define DBGU_INT_TXBUFE BIT11 /* TXBUFE Interrupt */ -#define DBGU_INT_RXBUFF BIT12 /* RXBUFF Interrupt */ -#define DBGU_INT_COMM_TX BIT30 /* COMM_TX Interrupt */ -#define DBGU_INT_COMM_RX BIT31 /* COMM_RX Interrupt */ -#define DBGU_INT_ALL 0xC0001AFB /* all assigned bits */ - -/* FORCE_NTRST Register, DBGU_FNTR, Offset 0x48 */ -#define DBGU_FNTR_NTRST BIT0 /* 1 = Force NTRST low in JTAG */ - -typedef struct { - volatile uint32_t cr; - volatile uint32_t mr; - volatile uint32_t ier; - volatile uint32_t idr; - volatile uint32_t imr; - volatile uint32_t sr; - volatile uint32_t rhr; - volatile uint32_t thr; - volatile uint32_t brgr; - volatile uint32_t _res0[7]; - volatile uint32_t cidr; - volatile uint32_t exid; - volatile uint32_t fnr; -} at91rm9200_dbgu_regs_t; - -#endif /* __AT91RM9200_DBGU_H__ */ diff --git a/c/src/lib/libbsp/arm/csb337/include/at91rm9200_emac.h b/c/src/lib/libbsp/arm/csb337/include/at91rm9200_emac.h deleted file mode 100644 index 77c42d1526..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/at91rm9200_emac.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Atmel AT91RM9200 EMAC Register definitions - * - * Copyright (c) 2003 by Cogent Computer Systems - * Written by Mike Kelly <mike@cogcomp.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef __AT91RM9200_EMAC_H__ -#define __AT91RM9200_EMAC_H__ - -#include <bits.h> - -/*Register offsets */ -#define EMAC_CTL 0x00 /* Network Control Register */ -#define EMAC_CFG 0x04 /* Network Configuration Register */ -#define EMAC_SR 0x08 /* Network Status Register */ -#define EMAC_TAR 0x0C /* Transmit Address Register */ -#define EMAC_TCR 0x10 /* Transmit Control Register */ -#define EMAC_TSR 0x14 /* Transmit Status Register */ -#define EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ -#define EMAC_RSR 0x20 /* Receive Status Register */ -#define EMAC_ISR 0x24 /* Interrupt Enable Register */ -#define EMAC_IER 0x28 /* Interrupt Enable Register */ -#define EMAC_IDR 0x2C /* Interrupt Disable Register */ -#define EMAC_IMR 0x30 /* Interrupt Mask Register */ -#define EMAC_MAN 0x34 /* PHY Maintenance Register */ -#define EMAC_FRA 0x40 /* Frames Transmitted OK Register */ -#define EMAC_SCOL 0x44 /* Single Collision Frame Register */ -#define EMAC_MCOL 0x48 /* Multiple Collision Frame Register */ -#define EMAC_OK 0x4C /* Frames Received OK Register */ -#define EMAC_SEQE 0x50 /* Frame Check Sequence Error Register */ -#define EMAC_ALE 0x54 /* Alignment Error Register */ -#define EMAC_DTE 0x58 /* Deferred Transmission Frame Register */ -#define EMAC_LCOL 0x5C /* Late Collision Register */ -#define EMAC_ECOL 0x60 /* Excessive Collision Register */ -#define EMAC_CSE 0x64 /* Carrier Sense Error Register */ -#define EMAC_TUE 0x68 /* Transmit Underrun Error Register */ -#define EMAC_CDE 0x6C /* Code Error Register */ -#define EMAC_ELR 0x70 /* Excessive Length Error Register */ -#define EMAC_RJB 0x74 /* Receive Jabber Register */ -#define EMAC_USF 0x78 /* Undersize Frame Register */ -#define EMAC_SQEE 0x7C /* SQE Test Error Register */ -#define EMAC_DRFC 0x80 /* Discarded RX Frame Register */ -#define EMAC_HSH 0x90 /* Hash Address High[63:32] */ -#define EMAC_HSL 0x94 /* Hash Address Low[31:0] */ -#define EMAC_SA1L 0x98 /* Specific Addr 1 Low, First 4 bytes */ -#define EMAC_SA1H 0x9C /* Specific Addr 1 High, Last 2 bytes */ -#define EMAC_SA2L 0xA0 /* Specific Addr 2 Low, First 4 bytes */ -#define EMAC_SA2H 0xA4 /* Specific Addr 2 High, Last 2 bytes */ -#define EMAC_SA3L 0xA8 /* Specific Addr 3 Low, First 4 bytes */ -#define EMAC_SA3H 0xAC /* Specific Addr 3 High, Last 2 bytes */ -#define EMAC_SA4L 0xB0 /* Specific Addr 4 Low, First 4 bytes */ -#define EMAC_SA4H 0xB4 /* Specific Addr 4 High, Last 2 bytesr */ - -/* Control Register, EMAC_CTL, Offset 0x0 */ -#define EMAC_CTL_LB BIT0 /* 1 = Set Loopback output signal */ -#define EMAC_CTL_LBL BIT1 /* 1 = Loopback local. */ -#define EMAC_CTL_RE BIT2 /* 1 = Receive enable. */ -#define EMAC_CTL_TE BIT3 /* 1 = Transmit enable. */ -#define EMAC_CTL_MPE BIT4 /* 1 = Management port enable. */ -#define EMAC_CTL_CSR BIT5 /* Write 1 to clear stats registers. */ -#define EMAC_CTL_ISR BIT6 /* Write to increment stats registers */ -#define EMAC_CTL_WES BIT7 /* 1 = Enable writing to stats regs */ -#define EMAC_CTL_BP BIT8 /* 1 = Force collision on all RX frames */ - -/* Configuration Register, EMAC_CFG, Offset 0x4 */ -#define EMAC_CFG_SPD BIT0 /* 1 = 10/100 Speed (not functional?) */ -#define EMAC_CFG_FD BIT1 /* 1 = Full duplex. */ -#define EMAC_CFG_BR BIT2 /* write 0 */ -#define EMAC_CFG_CAF BIT4 /* 1 = accept all frames */ -#define EMAC_CFG_NBC BIT5 /* 1 = disable reception of bcast frms */ -#define EMAC_CFG_MTI BIT6 /* 1 = Multicast hash enable */ -#define EMAC_CFG_UNI BIT7 /* 1 = Unicast hash enable. */ -#define EMAC_CFG_BIG BIT8 /* 1 = enable reception 1522 byte frms */ -#define EMAC_CFG_EAE BIT9 /* write 0 */ -#define EMAC_CFG_CLK_8 (0 << 10) /* MII Clock = HCLK divided by 8 */ -#define EMAC_CFG_CLK_16 (1 << 10) /* MII Clock = HCLK divided by 16 */ -#define EMAC_CFG_CLK_32 (2 << 10) /* MII Clock = HCLK divided by 32 */ -#define EMAC_CFG_CLK_64 (3 << 10) /* MII Clock = HCLK divided by 64 */ -#define EMAC_CFG_CLK_MASK (3 << 10) /* MII Clock mask */ -#define EMAC_CFG_RTY BIT12 /* Retry Test Mode - Must be 0 */ -#define EMAC_CFG_RMII BIT13 /* Reduced MII Mode Enable */ - -/* Status Register, EMAC_SR, Offset 0x8 */ -#define EMAC_LINK BIT0 /* Link pin */ -#define EMAC_MDIO BIT1 /* Real Time state of MDIO pin */ -#define EMAC_IDLE BIT2 /* 0 = PHY Logic is idle */ - -/* Transmit Control Register, EMAC_TCR, Offset 0x10 */ -#define EMAC_TCR_LEN(_x_) ((_x_ & 0x7FF) << 0) /* Tx frame len minus CRC */ -#define EMAC_TCR_NCRC BIT15 /* Do'nt append CRC on Tx */ - -/* Transmit Status Register, EMAC_TSR, Offset 0x14 */ -#define EMAC_TSR_OVR BIT0 /* 1 = Transmit buffer overrun */ -#define EMAC_TSR_COL BIT1 /* 1 = Collision occured */ -#define EMAC_TSR_RLE BIT2 /* 1 = Retry lmimt exceeded */ -#define EMAC_TSR_TXIDLE BIT3 /* 1 = Transmitter is idle */ -#define EMAC_TSR_BNQ BIT4 /* 1 = Transmit buffer not queued */ -#define EMAC_TSR_COMP BIT5 /* 1 = Transmit complete */ -#define EMAC_TSR_UND BIT6 /* 1 = Transmit underrun */ - -/* Receive Status Register, EMAC_RSR, Offset 0x20 */ -#define EMAC_RSR_BNA BIT0 /* 1 = Buffer not available */ -#define EMAC_RSR_REC BIT1 /* 1 = Frame received */ -#define EMAC_RSR_OVR BIT2 /* 1 = Receive overrun */ - -/* - * Interrupt Status Register, EMAC_ISR, Offsen 0x24 - * Interrupt Enable Register, EMAC_IER, Offset 0x28 - * Interrupt Disable Register, EMAC_IDR, Offset 0x2c - * Interrupt Mask Register, EMAC_IMR, Offset 0x30 - */ -#define EMAC_INT_DONE BIT0 /* Phy management done */ -#define EMAC_INT_RCOM BIT1 /* Receive complete */ -#define EMAC_INT_RBNA BIT2 /* Receive buffer not available */ -#define EMAC_INT_TOVR BIT3 /* Transmit buffer overrun */ -#define EMAC_INT_TUND BIT4 /* Transmit buffer underrun */ -#define EMAC_INT_RTRY BIT5 /* Transmit Retry limt */ -#define EMAC_INT_TBRE BIT6 /* Transmit buffer register empty */ -#define EMAC_INT_TCOM BIT7 /* Transmit complete */ -#define EMAC_INT_TIDLE BIT8 /* Transmit idle */ -#define EMAC_INT_LINK BIT9 /* Link pin changed value */ -#define EMAC_INT_ROVR BIT10 /* Receive overrun */ -#define EMAC_INT_ABT BIT11 /* Abort on DMA transfer */ - -/* PHY Maintenance Register, EMAC_MAN, Offset 0x34 */ -#define EMAC_MAN_DATA(_x_) ((_x_ & 0xFFFF) << 0)/* PHY data register */ -#define EMAC_MAN_CODE (0x2 << 16) /* IEEE Code */ -#define EMAC_MAN_REGA(_x_) ((_x_ & 0x1F) << 18) /* PHY register address */ -#define EMAC_MAN_PHYA(_x_) ((_x_ & 0x1F) << 23) /* PHY address */ -#define EMAC_MAN_WRITE (0x1 << 28) /* Transfer is a write */ -#define EMAC_MAN_READ (0x2 << 28) /* Transfer is a read */ -#define EMAC_MAN_HIGH BIT30 /* Must be set */ -#define EMAC_MAN_LOW BIT31 - -/* - * Bit assignments for Receive Buffer Descriptor - * Address - Word 0 - */ -#define RXBUF_ADD_BASE_MASK 0xfffffffc /* Base addr of the rx buf */ -#define RXBUF_ADD_WRAP BIT1 /* set indicates last buf */ -#define RXBUF_ADD_OWNED BIT0 /* 1 = SW owns the pointer */ - -/* Status - Word 1 */ -#define RXBUF_STAT_BCAST BIT31 /* Global bcast addr detected */ -#define RXBUF_STAT_MULTI BIT30 /* Multicast hash match */ -#define RXBUF_STAT_UNI BIT29 /* Unicast hash match */ -#define RXBUF_STAT_EXT BIT28 /* External address (optional) */ -#define RXBUF_STAT_UNK BIT27 /* Unknown source address */ -#define RXBUF_STAT_LOC1 BIT26 /* Local address 1 match */ -#define RXBUF_STAT_LOC2 BIT25 /* Local address 2 match */ -#define RXBUF_STAT_LOC3 BIT24 /* Local address 3 match */ -#define RXBUF_STAT_LOC4 BIT23 /* Local address 4 match */ -#define RXBUF_STAT_LEN_MASK 0x7ff /* Len of frame including FCS */ - -#endif /* __AT91RM9200_EMAC_H__ */ - diff --git a/c/src/lib/libbsp/arm/csb337/include/at91rm9200_gpio.h b/c/src/lib/libbsp/arm/csb337/include/at91rm9200_gpio.h deleted file mode 100644 index 9fa18ad476..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/at91rm9200_gpio.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * AT91RM9200 GPIO definitions - * - * Copyright (c) 2002 by Cogent Computer Systems - * Written by Mike Kelly <mike@cogcomp.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef AT91RM9200_GPIO_H -#define AT91RM9200_GPIO_H - -#include <bits.h> - -/* Register Offsets */ -#define PIO_PER 0x00 /* PIO Enable Register */ -#define PIO_PDR 0x04 /* PIO Disable Register */ -#define PIO_PSR 0x08 /* PIO Status Register */ -#define PIO_OER 0x10 /* Output Enable Register */ -#define PIO_ODR 0x14 /* Output Disable Registerr */ -#define PIO_OSR 0x18 /* Output Status Register */ -#define PIO_IFER 0x20 /* Input Filter Enable Register */ -#define PIO_IFDR 0x24 /* Input Filter Disable Register */ -#define PIO_IFSR 0x28 /* Input Filter Status Register */ -#define PIO_SODR 0x30 /* Set Output Data Register */ -#define PIO_CODR 0x34 /* Clear Output Data Register */ -#define PIO_ODSR 0x38 /* Output Data Status Register */ -#define PIO_PDSR 0x3c /* Pin Data Status Register */ -#define PIO_IER 0x40 /* Interrupt Enable Register */ -#define PIO_IDR 0x44 /* Interrupt Disable Register */ -#define PIO_IMR 0x48 /* Interrupt Mask Register */ -#define PIO_ISR 0x4c /* Interrupt Status Register */ -#define PIO_MDER 0x50 /* Multi-driver Enable Register */ -#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ -#define PIO_MDSR 0x58 /* Multi-driver Status Register */ -#define PIO_PUDR 0x60 /* Pull-up Disable Register */ -#define PIO_PUER 0x64 /* Pull-up Enable Register */ -#define PIO_PUSR 0x68 /* Pad Pull-up Status Register */ -#define PIO_ASR 0x70 /* Select A Register */ -#define PIO_BSR 0x74 /* Select B Register */ -#define PIO_ABSR 0x78 /* AB Select Status Register */ -#define PIO_OWER 0xA0 /* Output Write Enable Register */ -#define PIO_OWDR 0xA4 /* Output Write Disable Register */ -#define PIO_OWSR 0xA8 /* Output Write Status Register */ - - -/* - * The AT91RM9200 GPIO's are spread across four 32-bit ports A-D. - * To make it easier to interface with them and to eliminate the need - * to track which GPIO is in which port, we convert the Port x, Bit y - * into a single GPIO number 0 - 127. - * - * Board specific defines will assign the board level signal to a - * virutal GPIO. - * - * PORT A - */ -#define GPIO_0 BIT0 -#define GPIO_1 BIT1 -#define GPIO_2 BIT2 -#define GPIO_3 BIT3 -#define GPIO_4 BIT4 -#define GPIO_5 BIT5 -#define GPIO_6 BIT6 -#define GPIO_7 BIT7 -#define GPIO_8 BIT8 -#define GPIO_9 BIT9 -#define GPIO_10 BIT10 -#define GPIO_11 BIT11 -#define GPIO_12 BIT12 -#define GPIO_13 BIT13 -#define GPIO_14 BIT14 -#define GPIO_15 BIT15 -#define GPIO_16 BIT16 -#define GPIO_17 BIT17 -#define GPIO_18 BIT18 -#define GPIO_19 BIT19 -#define GPIO_20 BIT20 -#define GPIO_21 BIT21 -#define GPIO_22 BIT22 -#define GPIO_23 BIT23 -#define GPIO_24 BIT24 -#define GPIO_25 BIT25 -#define GPIO_26 BIT26 -#define GPIO_27 BIT27 -#define GPIO_28 BIT28 -#define GPIO_29 BIT29 -#define GPIO_30 BIT30 -#define GPIO_31 BIT31 -/* PORT B */ -#define GPIO_32 BIT0 -#define GPIO_33 BIT1 -#define GPIO_34 BIT2 -#define GPIO_35 BIT3 -#define GPIO_36 BIT4 -#define GPIO_37 BIT5 -#define GPIO_38 BIT6 -#define GPIO_39 BIT7 -#define GPIO_40 BIT8 -#define GPIO_41 BIT9 -#define GPIO_42 BIT10 -#define GPIO_43 BIT11 -#define GPIO_44 BIT12 -#define GPIO_45 BIT13 -#define GPIO_46 BIT14 -#define GPIO_47 BIT15 -#define GPIO_48 BIT16 -#define GPIO_49 BIT17 -#define GPIO_50 BIT18 -#define GPIO_51 BIT19 -#define GPIO_52 BIT20 -#define GPIO_53 BIT21 -#define GPIO_54 BIT22 -#define GPIO_55 BIT23 -#define GPIO_56 BIT24 -#define GPIO_57 BIT25 -#define GPIO_58 BIT26 -#define GPIO_59 BIT27 -#define GPIO_60 BIT28 -#define GPIO_61 BIT29 -#define GPIO_62 BIT30 -#define GPIO_63 BIT31 -/* PORT C */ -#define GPIO_64 BIT0 -#define GPIO_65 BIT1 -#define GPIO_66 BIT2 -#define GPIO_67 BIT3 -#define GPIO_68 BIT4 -#define GPIO_69 BIT5 -#define GPIO_70 BIT6 -#define GPIO_71 BIT7 -#define GPIO_72 BIT8 -#define GPIO_73 BIT9 -#define GPIO_74 BIT10 -#define GPIO_75 BIT11 -#define GPIO_76 BIT12 -#define GPIO_77 BIT13 -#define GPIO_78 BIT14 -#define GPIO_79 BIT15 -#define GPIO_80 BIT16 -#define GPIO_81 BIT17 -#define GPIO_82 BIT18 -#define GPIO_83 BIT19 -#define GPIO_84 BIT20 -#define GPIO_85 BIT21 -#define GPIO_86 BIT22 -#define GPIO_87 BIT23 -#define GPIO_88 BIT24 -#define GPIO_89 BIT25 -#define GPIO_90 BIT26 -#define GPIO_91 BIT27 -#define GPIO_92 BIT28 -#define GPIO_93 BIT29 -#define GPIO_94 BIT30 -#define GPIO_95 BIT31 -/* PORT D */ -#define GPIO_96 BIT0 -#define GPIO_97 BIT1 -#define GPIO_98 BIT2 -#define GPIO_99 BIT3 -#define GPIO_100 BIT4 -#define GPIO_101 BIT5 -#define GPIO_102 BIT6 -#define GPIO_103 BIT7 -#define GPIO_104 BIT8 -#define GPIO_105 BIT9 -#define GPIO_106 BIT10 -#define GPIO_107 BIT11 -#define GPIO_108 BIT12 -#define GPIO_109 BIT13 -#define GPIO_110 BIT14 -#define GPIO_111 BIT15 -#define GPIO_112 BIT16 -#define GPIO_113 BIT17 -#define GPIO_114 BIT18 -#define GPIO_115 BIT19 -#define GPIO_116 BIT20 -#define GPIO_117 BIT21 -#define GPIO_118 BIT22 -#define GPIO_119 BIT23 -#define GPIO_120 BIT24 -#define GPIO_121 BIT25 -#define GPIO_122 BIT26 -#define GPIO_123 BIT27 -#define GPIO_124 BIT28 -#define GPIO_125 BIT29 -#define GPIO_126 BIT30 -#define GPIO_127 BIT31 - -/* - * Most of the GPIO pins can have one of two alternate functions - * in addition to being GPIO - * - * Port A, Alternate Function A - */ -#define PIOA_ASR_MISO BIT0 /* SPI Master In (RX), Slave out */ -#define PIOA_ASR_MOSI BIT1 /* SPI Master Out (TX), Slave In */ -#define PIOA_ASR_SPCK BIT2 /* SPI Clock */ -#define PIOA_ASR_NPCS0 BIT3 /* SPI Chip Select 0 */ -#define PIOA_ASR_NPCS1 BIT4 /* SPI Chip Select 1 */ -#define PIOA_ASR_NPCS2 BIT5 /* SPI Chip Select 2 */ -#define PIOA_ASR_NPCS3 BIT6 /* SPI Chip Select 3 */ -#define PIOA_ASR_ETXCK BIT7 /* EMAC TX Clock */ -#define PIOA_ASR_ETXEN BIT8 /* EMAC TXEN */ -#define PIOA_ASR_ETX0 BIT9 /* EMAC TXD0 */ -#define PIOA_ASR_ETX1 BIT10 /* EMAC TXD1 */ -#define PIOA_ASR_ECRS BIT11 /* EMAC CRS */ -#define PIOA_ASR_ERX0 BIT12 /* EMAC RXD0 */ -#define PIOA_ASR_ERX1 BIT13 /* EMAC RXD1 */ -#define PIOA_ASR_ERXER BIT14 /* EMAC RXER */ -#define PIOA_ASR_EMDC BIT15 /* EMAC MDC */ -#define PIOA_ASR_EMDIO BIT16 /* EMAC MDIO */ -#define PIOA_ASR_TXD0 BIT17 /* USART 0 Receive */ -#define PIOA_ASR_RXD0 BIT18 /* USART 0 Transmit */ -#define PIOA_ASR_SCK0 BIT19 /* USART 0 Clock */ -#define PIOA_ASR_CTS0 BIT20 /* USART 0 CTS */ -#define PIOA_ASR_RTS0 BIT21 /* USART 0 RTS */ -#define PIOA_ASR_RXD2 BIT22 /* USART 2 Receive */ -#define PIOA_ASR_TXD2 BIT23 /* USART 2 Transmit */ -#define PIOA_ASR_SCK2 BIT24 /* USART 2 Clock */ -#define PIOA_ASR_TWD BIT25 /* Two-Wire (I2C) Data */ -#define PIOA_ASR_TWCK BIT26 /* Two-Wire (I2C) Clock */ -#define PIOA_ASR_MCCK BIT27 /* MMC/SD Card Clock */ -#define PIOA_ASR_MCCDA BIT28 /* MMC/SD Card A Command */ -#define PIOA_ASR_MCDA0 BIT29 /* MMC/SD Card A Data 0 */ -#define PIOA_ASR_DRXD BIT30 /* Debug Uart Receive */ -#define PIOA_ASR_DTXD BIT31 /* Debug Uart Transmit */ - -/* Port A, Alternate Function B */ -#define PIOA_BSR_PCK3 BIT0 /* Peripheral Clock 3 */ -#define PIOA_BSR_PCK0 BIT1 /* Peripheral Clock 0 */ -#define PIOA_BSR_IRQ4 BIT2 /* IRQ4 */ -#define PIOA_BSR_IRQ5 BIT3 /* IRQ5 */ -/*#define PIOA_BSR_PCK1 BIT4 Peripheral Clock 1 ***DUPLICATED at BIT24 ??? */ -#define PIOA_BSR_TXD3 BIT5 /* USART 3 Transmit */ -#define PIOA_BSR_RXD3 BIT6 /* USART 3 Receive */ -#define PIOA_BSR_PCK2 BIT7 /* Peripheral Clock 2 */ -#define PIOA_BSR_MCCDB BIT8 /* MMC/SD Card B Command */ -#define PIOA_BSR_MCDB0 BIT9 /* MMC/SD Card B Data 0 */ -#define PIOA_BSR_MCDB1 BIT10 /* MMC/SD Card B Data 1 */ -#define PIOA_BSR_MCDB2 BIT11 /* MMC/SD Card B Data 2 */ -#define PIOA_BSR_MCDB3 BIT12 /* MMC/SD C ard B Data 3 */ -#define PIOA_BSR_TCLK0 BIT13 /* Timer 0 Clock */ -#define PIOA_BSR_TCLK1 BIT14 /* Timer 1 Clck */ -#define PIOA_BSR_TCLK2 BIT15 /* Timer 2 Clock */ -#define PIOA_BSR_IRQ6 BIT16 /* IRQ6 */ -#define PIOA_BSR_TIOA0 BIT17 /* Timer 0 I/O A */ -#define PIOA_BSR_TIOB0 BIT18 /* Timer 0 I/O B */ -#define PIOA_BSR_TIOA1 BIT19 /* Timer 1 I/O A */ -#define PIOA_BSR_TIOB1 BIT20 /* Timer 1 I/O B */ -#define PIOA_BSR_TIOA2 BIT21 /* Timer 2 I/O A */ -#define PIOA_BSR_TIOB2 BIT22 /* Timer 2 I/O B */ -#define PIOA_BSR_IRQ3 BIT23 /* IRQ3 */ -#define PIOA_BSR_PCK1 BIT24 /* Peripheral Clock 1 */ -#define PIOA_BSR_IRQ2 BIT25 /* IRQ2 */ -#define PIOA_BSR_IRQ1 BIT26 /* IRQ1 */ -#define PIOA_BSR_TCLK3 BIT27 /* Timer Block Clock 3 (docs only show 0-2?) */ -#define PIOA_BSR_TCLK4 BIT28 /* Timer Block Clock 4 */ -#define PIOA_BSR_TCLK5 BIT29 /* Timer Block Clock 5 */ -#define PIOA_BSR_CTS2 BIT30 /* USART 2 CTS */ -#define PIOA_BSR_RTS2 BIT31 /* USART 2 RTS */ - -/* Port B, Function A */ -#define PIOB_ASR_TF0 BIT0 /* AC'97/I2S 0 Transmit Frame */ -#define PIOB_ASR_TK0 BIT1 /* AC'97/I2S 0 Transmit Clock */ -#define PIOB_ASR_TD0 BIT2 /* AC'97/I2S 0 Transmit Data */ -#define PIOB_ASR_RD0 BIT3 /* AC'97/I2S 0 Receive Data */ -#define PIOB_ASR_RK0 BIT4 /* AC'97/I2S 0 Receive Clock */ -#define PIOB_ASR_RF0 BIT5 /* AC'97/I2S 0 Receive Frame */ -#define PIOB_ASR_TF1 BIT6 /* AC'97/I2S 1 Transmit Frame */ -#define PIOB_ASR_TK1 BIT7 /* AC'97/I2S 1 Transmit Clock */ -#define PIOB_ASR_TD1 BIT8 /* AC'97/I2S 1 Transmit Data */ -#define PIOB_ASR_RD1 BIT9 /* AC'97/I2S 1 Receive Data */ -#define PIOB_ASR_RK1 BIT10 /* AC'97/I2S 1 Receive Clock */ -#define PIOB_ASR_RF1 BIT11 /* AC'97/I2S 1 Receive Frame */ -#define PIOB_ASR_TF2 BIT12 /* AC'97/I2S 1 Transmit Frame */ -#define PIOB_ASR_TK2 BIT13 /* AC'97/I2S 1 Transmit Clock */ -#define PIOB_ASR_TD2 BIT14 /* AC'97/I2S 1 Transmit Data */ -#define PIOB_ASR_RD2 BIT15 /* AC'97/I2S 1 Receive Data */ -#define PIOB_ASR_RK2 BIT16 /* AC'97/I2S 1 Receive Clock */ -#define PIOB_ASR_RF2 BIT17 /* AC'97/I2S 1 Receive Frame */ -#define PIOB_ASR_RI1 BIT18 /* USART 1 RI */ -#define PIOB_ASR_DTR1 BIT19 /* USART 1 DTR */ -#define PIOB_ASR_TXD1 BIT20 /* USART 1 TXD */ -#define PIOB_ASR_RXD1 BIT21 /* USART 1 RXD */ -#define PIOB_ASR_SCK1 BIT22 /* USART 1 SCK */ -#define PIOB_ASR_DCD1 BIT23 /* USART 1 DCD */ -#define PIOB_ASR_CTS1 BIT24 /* USART 1 CTS */ -#define PIOB_ASR_DSR1 BIT25 /* USART 1 DSR */ -#define PIOB_ASR_RTS1 BIT26 /* USART 1 RTS */ -#define PIOB_ASR_PCK0 BIT27 /* Peripheral Clock 0 */ -#define PIOB_ASR_FIQ BIT28 /* FIQ */ -#define PIOB_ASR_IRQ0 BIT29 /* IRQ0 */ - -/* Port B, Function B */ -#define PIOB_BSR_RTS3 BIT0 /* USART 3 */ -#define PIOB_BSR_CTS3 BIT1 /* USART 3 */ -#define PIOB_BSR_SCK3 BIT2 /* USART 3 */ -#define PIOB_BSR_MCDA1 BIT3 /* MMC/SD Card A, Data 1 */ -#define PIOB_BSR_MCDA2 BIT4 /* MMC/SD Card A, Data 2 */ -#define PIOB_BSR_MCDA3 BIT5 /* MMC/SD Card A, Data 3 */ -#define PIOB_BSR_TIOA3 BIT6 /* Timer 3 IO A */ -#define PIOB_BSR_TIOB3 BIT7 /* Timer 3 IO B */ -#define PIOB_BSR_TIOA4 BIT8 /* Timer 4 IO A */ -#define PIOB_BSR_TIOB4 BIT9 /* Timer 4 IO B */ -#define PIOB_BSR_TIOA5 BIT10 /* Timer 5 IO A */ -#define PIOB_BSR_TIOB5 BIT11 /* Timer 5 IO B */ -#define PIOB_BSR_ETX2 BIT12 /* EMAC TXD2 */ -#define PIOB_BSR_ETX3 BIT13 /* EMAC TXD3 */ -#define PIOB_BSR_ETXER BIT14 /* EMAC TXER */ -#define PIOB_BSR_ERX2 BIT15 /* EMAC RXD2 */ -#define PIOB_BSR_ERX3 BIT16 /* EMAC RXD3 */ -#define PIOB_BSR_ERXDV BIT17 /* EMAC RXDV */ -#define PIOB_BSR_ECOL BIT18 /* EMAC COL */ -#define PIOB_BSR_ERXCK BIT19 /* EMAC RX Clock */ -#define PIOB_BSR_EF100 BIT25 /* EMAC Speed 100 (RMII Only) */ - -/* Port C, Alternate Function A */ -#define PIOC_ASR_BFCK BIT0 /* Burst Flash Clock */ -#define PIOC_ASR_BFRDY BIT1 /* Burst Flash Ready or SMC Card OE */ -#define PIOC_ASR_BFAVD BIT2 /* Burst Flash Address Valid */ -#define PIOC_ASR_BFBAA BIT3 /* Burst Flash Address Advance or SMC Card WE */ -#define PIOC_ASR_BFOE BIT4 /* Burst Flash OE */ -#define PIOC_ASR_BFWE BIT5 /* Burst Flash WE */ -#define PIOC_ASR_NWAIT BIT6 /* WAIT Input */ -#define PIOC_ASR_A23 BIT7 /* A23 */ -#define PIOC_ASR_A24 BIT8 /* A24 */ -#define PIOC_ASR_A25 BIT9 /* A25 or Compact Flash R/W */ -#define PIOC_ASR_NCS4 BIT10 /* CS4 or Compact Flash CS */ -#define PIOC_ASR_NCS5 BIT11 /* CS5 or Compact Flash CE1 */ -#define PIOC_ASR_NCS6 BIT12 /* CS6 or Compact Flash CE2 */ -#define PIOC_ASR_NCS7 BIT13 /* CS7 */ -#define PIOC_ASR_D16 BIT16 /* Databus Bit 16 */ -#define PIOC_ASR_D17 BIT17 /* Databus Bit 17 */ -#define PIOC_ASR_D18 BIT18 /* Databus Bit 18 */ -#define PIOC_ASR_D19 BIT19 /* Databus Bit 19 */ -#define PIOC_ASR_D20 BIT20 /* Databus Bit 20 */ -#define PIOC_ASR_D21 BIT21 /* Databus Bit 21 */ -#define PIOC_ASR_D22 BIT22 /* Databus Bit 22 */ -#define PIOC_ASR_D23 BIT23 /* Databus Bit 23 */ -#define PIOC_ASR_D24 BIT24 /* Databus Bit 24 */ -#define PIOC_ASR_D25 BIT25 /* Databus Bit 25 */ -#define PIOC_ASR_D26 BIT26 /* Databus Bit 26 */ -#define PIOC_ASR_D27 BIT27 /* Databus Bit 27 */ -#define PIOC_ASR_D28 BIT28 /* Databus Bit 28 */ -#define PIOC_ASR_D29 BIT29 /* Databus Bit 29 */ -#define PIOC_ASR_D30 BIT30 /* Databus Bit 30 */ -#define PIOC_ASR_D31 BIT31 /* Databus Bit 31 */ - -/* Port C, Alternate Function B - None */ - -/* Port D, Alternate Function A */ -#define PIOD_ASR_ETX0 BIT0 /* EMAC TXD0 */ -#define PIOD_ASR_ETX1 BIT1 /* EMAC TXD1 */ -#define PIOD_ASR_ETX2 BIT2 /* EMAC TXD2 */ -#define PIOD_ASR_ETX3 BIT3 /* EMAC TXD3 */ -#define PIOD_ASR_ETXEN BIT4 /* EMAC TXEN */ -#define PIOD_ASR_ETXER BIT5 /* EMAC TXER */ -#define PIOD_ASR_DTXD BIT6 /* Debug UART Transmit */ -#define PIOD_ASR_PCK0 BIT7 /* Peripheral Clock 0 */ -#define PIOD_ASR_PCK1 BIT8 /* Peripheral Clock 1 */ -#define PIOD_ASR_PCK2 BIT9 /* Peripheral Clock 2 */ -#define PIOD_ASR_PCK3 BIT10 /* Peripheral Clock 3 */ -#define PIOD_ASR_TD0 BIT15 /* AC'97/I2S 0 Transmit Data */ -#define PIOD_ASR_TD1 BIT16 /* AC'97/I2S 1 Transmit Data */ -#define PIOD_ASR_TD2 BIT17 /* AC'97/I2S 2 Transmit Data */ -#define PIOD_ASR_NPCS1 BIT18 /* SPI Chip Select 1 */ -#define PIOD_ASR_NPCS2 BIT19 /* SPI Chip Select 2 */ -#define PIOD_ASR_NPCS3 BIT20 /* SPI Chip Select 3 */ -#define PIOD_ASR_RTS0 BIT21 /* USART 0 RTS */ -#define PIOD_ASR_RTS1 BIT22 /* USART 1 RTS */ -#define PIOD_ASR_RTS2 BIT23 /* USART 2 RTS */ -#define PIOD_ASR_RTS3 BIT24 /* USART 3 RTS */ -#define PIOD_ASR_DTR1 BIT25 /* USART 1 DTR */ - -/* Port D, Alternate Function B */ - -#define PIOC_ASR_TSYNC BIT7 /* ETM Sync */ -#define PIOC_ASR_TCLK BIT8 /* ETM Clock */ -#define PIOC_ASR_TPS0 BIT9 /* ETM Processor Status 0 */ -#define PIOC_ASR_TPS1 BIT10 /* ETM Processor Status 1 */ -#define PIOC_ASR_TPS2 BIT11 /* ETM Processor Status 2 */ -#define PIOC_ASR_TPK0 BIT12 /* ETM Packet Data 0 */ -#define PIOC_ASR_TPK1 BIT13 /* ETM Packet Data 1 */ -#define PIOC_ASR_TPK2 BIT14 /* ETM Packet Data 2 */ -#define PIOC_ASR_TPK3 BIT15 /* ETM Packet Data 3 */ -#define PIOC_ASR_TPK4 BIT16 /* ETM Packet Data 4 */ -#define PIOC_ASR_TPK5 BIT17 /* ETM Packet Data 5 */ -#define PIOC_ASR_TPK6 BIT18 /* ETM Packet Data 6 */ -#define PIOC_ASR_TPK7 BIT19 /* ETM Packet Data 7 */ -#define PIOC_ASR_TPK8 BIT20 /* ETM Packet Data 8 */ -#define PIOC_ASR_TPK9 BIT21 /* ETM Packet Data 9 */ -#define PIOC_ASR_TPK10 BIT22 /* ETM Packet Data 10 */ -#define PIOC_ASR_TPK11 BIT23 /* ETM Packet Data 11 */ -#define PIOC_ASR_TPK12 BIT24 /* ETM Packet Data 12 */ -#define PIOC_ASR_TPK13 BIT25 /* ETM Packet Data 13 */ -#define PIOC_ASR_TPK14 BIT26 /* ETM Packet Data 14 */ -#define PIOC_ASR_TPK15 BIT27 /* ETM Packet Data 15 */ - -#endif diff --git a/c/src/lib/libbsp/arm/csb337/include/at91rm9200_mem.h b/c/src/lib/libbsp/arm/csb337/include/at91rm9200_mem.h deleted file mode 100644 index fafb18f6e8..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/at91rm9200_mem.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * AT91RM9200 Memory Controller definitions - * - * Copyright (c) 2002 by Cogent Computer Systems - * Written by Mike Kelly <mike@cogcomp.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef AT91RM9200_MEM_H -#define AT91RM9200_MEM_H - -/********************************************************************** - * External Bus Interface Unit - **********************************************************************/ -#define EBI_CSA 0x00 /* Chip Select Assignment Register */ -#define EBI_CFGR 0x04 /* Configuration Register */ - -/* Bit Defines */ -/* EBI_CSA - Chip Select Assignment Register */ -#define EBI_CSA_CS4_CF BIT4 /* 1 = CS4-6 are assigned to Compact Flash, 0 = Chip Selects */ -#define EBI_CSA_CS3_SMM BIT3 /* 1 = CS3 is assigned to SmartMedia, 0 = Chip Select */ -#define EBI_CSA_CS1_SDRAM BIT1 /* 1 = CS1 is assigned to SDRAM, 0 = Chip Select */ -#define EBI_CSA_CS0_BF BIT0 /* 1 = CS0 is assigned to Burst Flash, 0 = Chip Select */ - -/* EBI_CFGR - Configuration Register */ -#define EBI_CFGR_DBPU BIT0 /* 1 = Disable D0-15 pullups */ - -/*************************************************************************** - * Static Memory Interface Unit - ***************************************************************************/ -#define SMC_CSR0 0x00 /* Chip Select Register 0 */ -#define SMC_CSR1 0x04 /* Chip Select Register 1 */ -#define SMC_CSR2 0x08 /* Chip Select Register 2 */ -#define SMC_CSR3 0x0C /* Chip Select Register 3 */ -#define SMC_CSR4 0x10 /* Chip Select Register 4 */ -#define SMC_CSR5 0x14 /* Chip Select Register 5 */ -#define SMC_CSR6 0x18 /* Chip Select Register 6 */ -#define SMC_CSR7 0x1C /* Chip Select Register 7 */ - -/* Bit Defines */ -/* SMC_CSR0 -7 - Chip Selects 0 - 7 Register */ -#define SMC_CSR_RWHOLD(_x_) ((_x_ & 0x3) << 28) /* Hold CS after R/W strobes */ -#define SMC_CSR_RWSETUP(_x_) ((_x_ & 0x3) << 24) /* Setup CS before R/W strobes */ -#define SMC_CSR_ACSS_0 (0 << 16) /* Setup/Hold Address 0 clocks before/after CS */ -#define SMC_CSR_ACSS_1 (1 << 16) /* Setup/Hold Address 1 clock before/after CS */ -#define SMC_CSR_ACSS_2 (2 << 16) /* Setup/Hold Address 2 clocks before/after CS */ -#define SMC_CSR_ACSS_3 (3 << 16) /* Setup/Hold Address 3 clocks before/after CS */ -#define SMC_CSR_DRP_NORMAL 0 /* 0 = normal read protocol */ -#define SMC_CSR_DRP_EARLY BIT15 /* 1 = early read protocol */ -#define SMC_CSR_DBW_16 (1 << 13) /* CS DataBus Width = 16-Bits */ -#define SMC_CSR_DBW_8 (2 << 13) /* CS DataBus Width = 8 Bits */ -#define SMC_CSR_BAT_16_1 0 /* Single 16-Bit device (when DBW is 16) */ -#define SMC_CSR_BAT_16_2 BIT12 /* Dual 8-Bit devices (when DBW is 16) */ -#define SMC_CSR_TDF(_x_) ((_x_ & 0xf) << 8) /* Intercycle Data Float Time */ -#define SMC_CSR_WSEN BIT7 /* 1 = wait states are enabled */ -#define SMC_CSR_NWS(_x_) ((_x_ & 0x7f) << 0) /* Wait States + 1 */ - -/* ***************************************************************************** */ -/* SDRAM Memory Interface Unit */ -/* ***************************************************************************** */ -#define SDRC_MR 0x00 /* Mode Register */ -#define SDRC_TR 0x04 /* Refresh Timer Register */ -#define SDRC_CR 0x08 /* Configuration Register */ -#define SDRC_SRR 0x0C /* Self Refresh Register */ -#define SDRC_LPR 0x10 /* Low Power Register */ -#define SDRC_IER 0x14 /* Interrupt Enable Register */ -#define SDRC_IDR 0x18 /* Interrupt Disable Register */ -#define SDRC_IMR 0x1C /* Interrupt Mask Register */ -#define SDRC_ISR 0x20 /* Interrupt Status Register */ - -/* Bit Defines */ -/* SDRC_MR - Mode Register */ -#define SDRC_MR_DBW_16 BIT4 /* 1 = SDRAM is 16-bits wide, 0 = 32-bits */ -#define SDRC_MR_NORM (0 << 0) /* Normal Mode - All accesses to SDRAM are decoded normally */ -#define SDRC_MR_NOP (1 << 0) /* NOP Command is sent to SDRAM */ -#define SDRC_MR_PRE (2 << 0) /* Precharge All Command is sent to SDRAM */ -#define SDRC_MR_MRS (3 << 0) /* Mode Register Set Command is sent to SDRAM */ -#define SDRC_MR_REF (4 << 0) /* Refresh Command is sent to SDRAM */ - -/* SDRC_TR - Refresh Timer Register */ -#define SDRC_TR_COUNT(_x_) ((_x_ & 0xfff) << 0) - -/* SDRC_CR - Configuration Register */ -#define SDRC_CR_TXSR(_x_) ((_x_ & 0xf) << 27) /* CKE to ACT Time */ -#define SDRC_CR_TRAS(_x_) ((_x_ & 0xf) << 23) /* ACT to PRE Time */ -#define SDRC_CR_TRCD(_x_) ((_x_ & 0xf) << 19) /* RAS to CAS Time */ -#define SDRC_CR_TRP(_x_) ((_x_ & 0xf) << 15) /* PRE to ACT Time */ -#define SDRC_CR_TRC(_x_) ((_x_ & 0xf) << 11) /* REF to ACT Time */ -#define SDRC_CR_TWR(_x_) ((_x_ & 0xf) << 7) /* Write Recovery Time */ -#define SDRC_CR_CAS_2 (2 << 5) /* Cas Delay = 2, this is the only supported value */ -#define SDRC_CR_NB_2 0 /* 2 Banks per device */ -#define SDRC_CR_NB_4 BIT4 /* 4 Banks per device */ -#define SDRC_CR_NR_11 (0 << 2) /* Number of rows = 11 */ -#define SDRC_CR_NR_12 (1 << 2) /* Number of rows = 12 */ -#define SDRC_CR_NR_13 (2 << 2) /* Number of rows = 13 */ -#define SDRC_CR_NC_8 (0 << 0) /* Number of columns = 8 */ -#define SDRC_CR_NC_9 (1 << 0) /* Number of columns = 9 */ -#define SDRC_CR_NC_10 (2 << 0) /* Number of columns = 10 */ -#define SDRC_CR_NC_11 (3 << 0) /* Number of columns = 11 */ - -/* SDRC_SRR - Self Refresh Register */ -#define SDRC_SRR_SRCB BIT0 /* 1 = Enter Self Refresh */ - -/* SDRC_LPR - Low Power Register */ -#define SDRC_LPR_LPCB BIT0 /* 1 = De-assert CKE between accesses */ - -/* SDRC_IER - Interrupt Enable Register */ -/* SDRC_IDR - Interrupt Disable Register */ -/* SDRC_ISR - Interrupt Mask Register */ -/* SDRC_IMR - Interrupt Mask Register */ -#define SDRC_INT_RES BIT0 /* Refresh Error Status */ - -#endif diff --git a/c/src/lib/libbsp/arm/csb337/include/at91rm9200_pmc.h b/c/src/lib/libbsp/arm/csb337/include/at91rm9200_pmc.h deleted file mode 100644 index 70cf77fc5a..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/at91rm9200_pmc.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * AT91RM9200 Power Management and Clock definitions - * - * Copyright (c) 2002 by Cogent Computer Systems - * Written by Mike Kelly <mike@cogcomp.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef __AT91RM9200_PMC_H__ -#define __AT91RM9200_PMC_H__ - -#include <bits.h> - -/*********************************************************************** - * Power Management and Clock Control Register Offsets - ***********************************************************************/ -int at91rm9200_get_mainclk(void); -int at91rm9200_get_slck(void); -int at91rm9200_get_mck(void); - - -#define PMC_SCER 0x00 /* System Clock Enable Register */ -#define PMC_SCDR 0x04 /* System Clock Disable Register */ -#define PMC_SCSR 0x08 /* System Clock Status Register */ -#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */ -#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ -#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */ -#define PMC_MOR 0x20 /* Main Oscillator Register */ -#define PMC_MCFR 0x24 /* Main Clock Frequency Register */ -#define PMC_PLLAR 0x28 /* PLL A Register */ -#define PMC_PLLBR 0x2C /* PLL B Register */ -#define PMC_MCKR 0x30 /* Master Clock Register */ -#define PMC_PCKR0 0x40 /* Programmable Clock Register 0 */ -#define PMC_PCKR1 0x44 /* Programmable Clock Register 1 */ -#define PMC_PCKR2 0x48 /* Programmable Clock Register 2 */ -#define PMC_PCKR3 0x4C /* Programmable Clock Register 3 */ -#define PMC_PCKR4 0x50 /* Programmable Clock Register 4 */ -#define PMC_PCKR5 0x54 /* Programmable Clock Register 5 */ -#define PMC_PCKR6 0x58 /* Programmable Clock Register 6 */ -#define PMC_PCKR7 0x5C /* Programmable Clock Register 7 */ -#define PMC_IER 0x60 /* Interrupt Enable Register */ -#define PMC_IDR 0x64 /* Interrupt Disable Register */ -#define PMC_SR 0x68 /* Status Register */ -#define PMC_IMR 0x6C /* Interrupt Mask Register */ - -/* Bit Defines */ - -/* PMC_SCDR - System Clock Disable Register */ -/* PMC_SCSR - System Clock Status Register */ -/* PMC_SCER - System Clock Enable Register */ -#define PMC_SCR_PCK7 BIT15 -#define PMC_SCR_PCK6 BIT14 -#define PMC_SCR_PCK5 BIT13 -#define PMC_SCR_PCK4 BIT12 -#define PMC_SCR_PCK3 BIT11 -#define PMC_SCR_PCK2 BIT10 -#define PMC_SCR_PCK1 BIT9 -#define PMC_SCR_PCK0 BIT8 -#define PMC_SCR_UHP BIT4 -#define PMC_SCR_MCKUDP BIT2 -#define PMC_SCR_UDP BIT1 -#define PMC_SCR_PCK BIT0 - -/* PMC_PCER - Peripheral Clock Enable Register */ -/* PMC_PCDR - Peripheral Clock Disable Register */ -/* PMC_PCSR - Peripheral Clock Status Register */ -#define PMC_PCR_PID_EMAC BIT24 /* Ethernet Peripheral Clock */ -#define PMC_PCR_PID_UHP BIT23 /* USB Host Ports Peripheral Clock */ -#define PMC_PCR_PID_TC5 BIT22 /* Timer/Counter 5 Peripheral Clock */ -#define PMC_PCR_PID_TC4 BIT21 /* Timer/Counter 4 Peripheral Clock */ -#define PMC_PCR_PID_TC3 BIT20 /* Timer/Counter 3 Peripheral Clock */ -#define PMC_PCR_PID_TC2 BIT19 /* Timer/Counter 2 Peripheral Clock */ -#define PMC_PCR_PID_TC1 BIT18 /* Timer/Counter 1 Peripheral Clock */ -#define PMC_PCR_PID_TC0 BIT17 /* Timer/Counter 0 Peripheral Clock */ -#define PMC_PCR_PID_SSC2 BIT16 /* Synchronous Serial 2 Peripheral Clock */ -#define PMC_PCR_PID_SSC1 BIT15 /* Synchronous Serial 1 Peripheral Clock */ -#define PMC_PCR_PID_SSC0 BIT14 /* Synchronous Serial 0 Peripheral Clock */ -#define PMC_PCR_PID_SPI BIT13 /* Serial Peripheral Interface Peripheral Clock */ -#define PMC_PCR_PID_TWI BIT12 /* Two-Wire Interface Peripheral Clock */ -#define PMC_PCR_PID_UDP BIT11 /* USB Device Port Peripheral Clock */ -#define PMC_PCR_PID_MCI BIT10 /* MMC/SD Card Peripheral Clock */ -#define PMC_PCR_PID_US3 BIT9 /* USART 3 Peripheral Clock */ -#define PMC_PCR_PID_US2 BIT8 /* USART 2 Peripheral Clock */ -#define PMC_PCR_PID_US1 BIT7 /* USART 1 Peripheral Clock */ -#define PMC_PCR_PID_US0 BIT6 /* USART 0 Peripheral Clock */ -#define PMC_PCR_PID_PIOD BIT5 /* Parallel I/O D Peripheral Clock */ -#define PMC_PCR_PID_PIOC BIT4 /* Parallel I/O C Peripheral Clock */ -#define PMC_PCR_PID_PIOB BIT3 /* Parallel I/O B Peripheral Clock */ -#define PMC_PCR_PID_PIOA BIT2 /* Parallel I/O A Peripheral Clock */ - -/* PMC_MOR - Main Oscillator Register */ -#define PMC_MOR_MOSCEN BIT0 - -/* PMC_MCFR - Main Clock Frequency Register */ -#define PMC_MCFR_MAINRDY BIT16 - -/* PMC_PLLAR - PLL A Register */ -#define PMC_PLLAR_MUST_SET BIT29 /* This bit must be set according to the docs */ -#define PMC_PLLAR_MUL(_x_) ((_x_ & 0x7ff) << 16) /* Multiplier */ -#define PMC_PLLAR_MUL_MASK (0x7ff << 16) /* Multiplier mask */ - -#define PMC_PLLAR_OUT_80_160 (0 << 14) /* select when PLL frequency is 80-160 Mhz */ -#define PMC_PLLAR_OUT_150_240 (2 << 14) /* select when PLL frequency is 150-240 Mhz */ -#define PMC_PLLAR_DIV(_x_) ((_x_ & 0xff) << 0) /* Divider */ -#define PMC_PLLAR_DIV_MASK (0xff) /* Divider mask */ - -/* PMC_PLLBR - PLL B Register */ -#define PMC_PLLBR_USB_96M BIT28 /* Set when PLL is 96Mhz to divide it by 2 for USB */ -#define PMC_PLLBR_MUL(_x_) ((_x_ & 0x7ff) << 16) /* Multiplier */ -#define PMC_PLLBR_MUL_MASK (0x7ff << 16) /* Multiplier mask */ -#define PMC_PLLBR_OUT_80_160 (0 << 14) /* select when PLL frequency is 80-160 Mhz */ -#define PMC_PLLBR_OUT_150_240 (2 << 14) /* select when PLL frequency is 150-240 Mhz */ -#define PMC_PLLBR_DIV(_x_) ((_x_ & 0xff) << 0) /* Divider */ -#define PMC_PLLBR_DIV_MASK (0xff) /* Divider mask */ - -/* PMC_MCKR - Master Clock Register */ -#define PMC_MCKR_MDIV_MASK (3 << 8) /* for masking out the MDIV field */ -#define PMC_MCKR_MDIV_1 (0 << 8) /* MCK = Core/1 */ -#define PMC_MCKR_MDIV_2 (1 << 8) /* MCK = Core/2 */ -#define PMC_MCKR_MDIV_3 (2 << 8) /* MCK = Core/3 */ -#define PMC_MCKR_MDIV_4 (3 << 8) /* MCK = Core/4 */ -#define PMC_MCKR_PRES_MASK (7 << 2) /* for masking out the PRES field */ -#define PMC_MCKR_PRES_1 (0 << 2) /* Core = CSS/1 */ -#define PMC_MCKR_PRES_2 (1 << 2) /* Core = CSS/2 */ -#define PMC_MCKR_PRES_4 (2 << 2) /* Core = CSS/4 */ -#define PMC_MCKR_PRES_8 (3 << 2) /* Core = CSS/8 */ -#define PMC_MCKR_PRES_16 (4 << 2) /* Core = CSS/16 */ -#define PMC_MCKR_PRES_32 (5 << 2) /* Core = CSS/32 */ -#define PMC_MCKR_PRES_64 (6 << 2) /* Core = CSS/64 */ -#define PMC_MCKR_CSS_MASK (3 << 0) /* for masking out the CSS field */ -#define PMC_MCKR_CSS_SLOW (0 << 0) /* Core Source = Slow Clock */ -#define PMC_MCKR_CSS_MAIN (1 << 0) /* Core Source = Main Oscillator */ -#define PMC_MCKR_CSS_PLLA (2 << 0) /* Core Source = PLL A */ -#define PMC_MCKR_CSS_PLLB (3 << 0) /* Core Source = PLL B */ - -/* PMC_PCKR0 - 7 - Programmable Clock Register 0 */ -#define PMC_PCKR_PRES_1 (0 << 2) /* Peripheral Clock = CSS/1 */ -#define PMC_PCKR_PRES_2 (1 << 2) /* Peripheral Clock = CSS/2 */ -#define PMC_PCKR_PRES_4 (2 << 2) /* Peripheral Clock = CSS/4 */ -#define PMC_PCKR_PRES_8 (3 << 2) /* Peripheral Clock = CSS/8 */ -#define PMC_PCKR_PRES_16 (4 << 2) /* Peripheral Clock = CSS/16 */ -#define PMC_PCKR_PRES_32 (5 << 2) /* Peripheral Clock = CSS/32 */ -#define PMC_PCKR_PRES_64 (6 << 2) /* Peripheral Clock = CSS/64 */ -#define PMC_PCKR_CSS_SLOW (0 << 0) /* Peripheral Clock Source = Slow Clock */ -#define PMC_PCKR_CSS_MAIN (1 << 0) /* Peripheral Clock Source = Main Oscillator */ -#define PMC_PCKR_CSS_PLLA (2 << 0) /* Peripheral Clock Source = PLL A */ -#define PMC_PCKR_CSS_PLLB (3 << 0) /* Peripheral Clock Source = PLL B */ - -/* PMC_IER - Interrupt Enable Register */ -/* PMC_IDR - Interrupt Disable Register */ -/* PMC_SR - Status Register */ -/* PMC_IMR - Interrupt Mask Register */ -#define PMC_INT_PCK7_RDY BIT15 -#define PMC_INT_PCK6_RDY BIT14 -#define PMC_INT_PCK5_RDY BIT13 -#define PMC_INT_PCK4_RDY BIT12 -#define PMC_INT_PCK3_RDY BIT11 -#define PMC_INT_PCK2_RDY BIT10 -#define PMC_INT_PCK1_RDY BIT9 -#define PMC_INT_PCK0_RDY BIT8 -#define PMC_INT_MCK_RDY BIT3 -#define PMC_INT_LOCKB BIT2 -#define PMC_INT_LCKA BIT1 -#define PMC_INT_MOSCS BIT0 - - -#endif diff --git a/c/src/lib/libbsp/arm/csb337/include/at91rm9200_usart.h b/c/src/lib/libbsp/arm/csb337/include/at91rm9200_usart.h deleted file mode 100644 index 387f353992..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/at91rm9200_usart.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Atmel AT91RM9200_USART Register definitions, used in KIT637_V6 (CSB637) - * - * Copyright (c) 2003 by Cogent Computer Systems - * Written by Mike Kelly <mike@cogcomp.com> - * - * Modified by Fernando Nicodemos <fgnicodemos@terra.com.br> - * from NCB - Sistemas Embarcados Ltda. (Brazil) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. -*/ - -#ifndef __AT91RM9200_USART_H__ -#define __AT91RM9200_USART_H__ - -#include <bits.h> - -/* Register Offsets */ -#define US_CR 0x00 /* Control Register */ -#define US_MR 0x04 /* Mode Register */ -#define US_IER 0x08 /* Interrupt Enable Register */ -#define US_IDR 0x0C /* Interrupt Disable Register */ -#define US_IMR 0x10 /* Interrupt Mask Register */ -#define US_SR 0x14 /* Channel Status Register */ -#define US_RHR 0x18 /* Receiver Holding Register */ -#define US_THR 0x1C /* Transmitter Holding Register */ -#define US_BRGR 0x20 /* Baud Rate Generator Register */ -#define US_RTOR 0x24 /* Receiver Time-out Register */ -#define US_TTGR 0x28 /* Transmitter Timeguard Register */ -#define US_C1R 0x40 /* Chip ID1 Register - FI DI Ratio Register */ -#define US_C2R 0x44 /* Chip ID2 Register - Number of Erros Register */ -#define US_FNTR 0x48 /* Force NTRST Register */ -#define US_IF 0x4C /* IrDA Filter Register */ - -/* Bit Defines */ -/* Control Register, US_CR, Offset 0x00 */ -#define US_CR_RSTRX BIT2 /* 1 = Reset and disable receiver */ -#define US_CR_RSTTX BIT3 /* 1 = Reset and disable transmitter */ -#define US_CR_RXEN BIT4 /* 1 = Receiver enable */ -#define US_CR_RXDIS BIT5 /* 1 = Receiver disable */ -#define US_CR_TXEN BIT6 /* 1 = Transmitter enable */ -#define US_CR_TXDIS BIT7 /* 1 = Transmitter disable */ -#define US_CR_RSTSTA BIT8 /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */ -#define US_CR_STTBRK BIT9 /* 1 = Start transmission of a Break */ -#define US_CR_STPBRK BIT10 /* 1 = Stop transmission of a Break */ -#define US_CR_STTTO BIT11 /* 1 = Start Time-out */ -#define US_CR_SENDA BIT12 /* 1 = Send Address - MDROP mode only */ -#define US_CR_RSTIT BIT13 /* 1 = Reset Iteration */ -#define US_CR_RSTNACK BIT14 /* 1 = Reset Non Acknowledge */ -#define US_CR_RETTO BIT15 /* 1 = Restart Time-out */ -#define US_CR_DTREN BIT16 /* 1 = Data Terminal Ready Enable - AT91RM9200 only */ -#define US_CR_DTRDIS BIT17 /* 1 = Data Terminal Ready Disable - AT91RM9200 only */ -#define US_CR_RTSEN BIT18 /* 1 = Request To Send Enable */ -#define US_CR_RTSDIS BIT19 /* 1 = Request To Send Disable */ - - -/* Mode Register. US_MR. Offset 0x04 */ -#define US_MR_USMODE (0xF << 0) /* Mode of the USART */ -#define US_MR_USMODE_NORMAL 0 -#define US_MR_USMODE_RS485 1 -#define US_MR_USMODE_HWHS 2 -#define US_MR_USMODE_MODEM 3 -#define US_MR_USMODE_ISO7816_T0 4 -#define US_MR_USMODE_ISO7816_T1 6 -#define US_MR_USMODE_IRDA 8 -#define US_MR_USCLKS (3 << 4) /* Clock Selection */ -#define US_MR_USCLKS_MCK (0 << 4) -#define US_MR_USCLKS_MCK_DIV8 (1 << 4) -#define US_MR_USCLKS_SCK (3 << 4) -#define US_MR_CHRL (3 << 6) /* Character Length */ -#define US_MR_CHRL_5 (0 << 6) -#define US_MR_CHRL_6 (1 << 6) -#define US_MR_CHRL_7 (2 << 6) -#define US_MR_CHRL_8 (3 << 6) -#define US_MR_SYNC (1 << 8) /* Synchronous Mode Select */ -#define US_MR_PAR (7 << 9) /* Parity Type */ -#define US_MR_PAR_EVEN (0 << 9) /* Even Parity */ -#define US_MR_PAR_ODD (1 << 9) /* Odd Parity */ -#define US_MR_PAR_SPACE (2 << 9) /* Parity forced to 0 (Space) */ -#define US_MR_PAR_MARK (3 << 9) /* Parity forced to 1 (Mark) */ -#define US_MR_PAR_NONE (4 << 9) /* No Parity */ -#define US_MR_PAR_MDROP (6 << 9) /* Multi-drop mode */ -#define US_MR_NBSTOP (3 << 12) /* Number of Stop Bits */ -#define US_MR_NBSTOP_1 (0 << 12) -#define US_MR_NBSTOP_1_5 (1 << 12) -#define US_MR_NBSTOP_2 (2 << 12) -#define US_MR_CHMODE (3 << 14) /* Channel Mode */ -#define US_MR_CHMODE_NORM (0 << 14) /* Normal Mode */ -#define US_MR_CHMODE_AUTO (1 << 14) /* Auto Echo: RXD drives TXD */ -#define US_MR_CHMODE_LOC (2 << 14) /* Local Loopback: TXD drives RXD */ -#define US_MR_CHMODE_REM (3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */ -#define US_MR_MSBF (1 << 16) /* Bit Order */ -#define US_MR_MODE9 (1 << 17) /* 9-bit Character Length */ -#define US_MR_CLKO (1 << 18) /* Clock Output Select */ -#define US_MR_OVER (1 << 19) /* Oversampling Mode */ -#define US_MR_INACK (1 << 20) /* Inhibit Non Acknowledge */ -#define US_MR_DSNACK (1 << 21) /* Disable Successive NACK */ -#define US_MR_MAX_ITER (7 << 24) /* Max Iterations */ -#define US_MR_FILTER (1 << 28) /* Infrared Receive Line Filter */ - -/* Interrupt Enable Register, US_IER, Offset 0x08 */ -/* Interrupt Disable Register, US_IDR, Offset 0x0C */ -/* Interrupt Mask Register, US_IMR, Offset 0x10 */ -/* Channel Status Register, US_SR, Offset 0x14 */ -#define US_IER_RXRDY BIT0 /* RXRDY Interrupt */ -#define US_IER_TXRDY BIT1 /* TXRDY Interrupt */ -#define US_IER_RXBRK BIT2 /* End of Receive Transfer Interrupt */ -#define US_IER_ENDRX BIT3 /* End of Receiver Transfer */ -//#define US_IER_ENDTX BIT4 /* End of Transmit Interrupt */ -#define US_IER_OVRE BIT5 /* Overrun Interrupt */ -#define US_IER_FRAME BIT6 /* Framing Error Interrupt */ -#define US_IER_PARE BIT7 /* Parity Error */ -#define US_IER_TIMEOUT BIT8 /* Receiver Time-out */ -#define US_IER_TXEMPTY BIT9 /* Transmitter Empty */ -#define US_IER_ITERATION BIT10 /* Max number of Repetitions Reached */ -#define US_IER_TXBUFE BIT11 /* Transmission Buffer Empty */ -#define US_IER_RXBUFF BIT12 /* Reception Buffer Full */ -#define US_IER_NACK BIT13 /* Non Acknowledge */ -#define US_IER_RIIC BIT16 /* Ring Indicator Input Change [AT91RM9200 only] */ -#define US_IER_DSRIC BIT17 /* Data Set Ready Input Change [AT91RM9200 only] */ -#define US_IER_DCDIC BIT18 /* Data Carrier Detect Input Change [AT91RM9200 only] */ -#define US_IER_CTSIC BIT19 /* Clear to Send Input Change */ -#define US_IER_ALL 0xC0001AFB /* all assigned bits */ - -/* FORCE_NTRST Register, US_FNTR, Offset 0x48 */ -#define US_FNTR_NTRST BIT0 /* 1 = Force NTRST low in JTAG */ - -typedef struct { - volatile uint32_t cr; - volatile uint32_t mr; - volatile uint32_t ier; - volatile uint32_t idr; - volatile uint32_t imr; - volatile uint32_t sr; - volatile uint32_t rhr; - volatile uint32_t thr; - volatile uint32_t brgr; - volatile uint32_t _res0[7]; - volatile uint32_t cidr; - volatile uint32_t exid; - volatile uint32_t fnr; -} at91rm9200_usart_regs_t; - -#endif /* __AT91RM9200_USART_H__ */ diff --git a/c/src/lib/libbsp/arm/csb337/include/bits.h b/c/src/lib/libbsp/arm/csb337/include/bits.h deleted file mode 100644 index 6f2c4036b6..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/bits.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Bit position definitions - * - * Copyright (c) 2002 by Cogent Computer Systems - * Written by Mike Kelly <mike@cogcomp.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef __BITS_H__ -#define __BITS_H__ - -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -#endif /* __BITS_H__ */ - diff --git a/c/src/lib/libbsp/arm/csb337/include/bsp.h b/c/src/lib/libbsp/arm/csb337/include/bsp.h deleted file mode 100644 index c99de2fd0a..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/bsp.h +++ /dev/null @@ -1,78 +0,0 @@ -/** - * @file - * - * @ingroup arm_csb337 - * - * @brief Global BSP definitions. - */ - -/* - * CSB337 BSP header file - * - * Copyright (c) 2004 by Cogent Computer Systems - * Writtent by Jay Monkman <jtm@lopingdog.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef LIBBSP_ARM_CSB337_BSP_H -#define LIBBSP_ARM_CSB337_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup arm_csb337 CSB337 Support - * - * @ingroup bsp_arm - * - * @brief CSB337 support package. - * - * @{ - */ - -#define BSP_FEATURE_IRQ_EXTENSION - -/* What is the input clock freq in hertz? */ -#define BSP_MAIN_FREQ 3686400 /* 3.6864 MHz */ -#define BSP_SLCK_FREQ 32768 /* 32.768 KHz */ - -/* What is the last interrupt? */ -#define BSP_MAX_INT AT91RM9200_MAX_INT - -/* - * forward reference the type to avoid conflicts between libchip serial - * and libchip rtc get and set register types. - */ -typedef struct _console_tbl console_tbl; -console_tbl *BSP_get_uart_from_minor(int minor); - -static inline int32_t BSP_get_baud(void) {return 38400;} - -#define ST_PIMR_PIV 33 /* 33 ticks of the 32.768Khz clock ~= 1msec */ - -/** - * @brief Network driver configuration - */ -extern struct rtems_bsdnet_ifconfig *config; - -/* Change these to match your board */ -int rtems_at91rm9200_emac_attach(struct rtems_bsdnet_ifconfig *config, int attaching); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_at91rm9200_emac_attach - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* _BSP_H */ - diff --git a/c/src/lib/libbsp/arm/csb337/include/bsp/irq.h b/c/src/lib/libbsp/arm/csb337/include/bsp/irq.h deleted file mode 100644 index 771059a3e4..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/bsp/irq.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Interrupt handler Header file - * - * Copyright (c) 2010 embedded brains GmbH. - * - * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __IRQ_H__ -#define __IRQ_H__ - -#ifndef __asm__ - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#endif /* __asm__ */ - -/* possible interrupt sources on the AT91RM9200 */ -#define AT91RM9200_INT_FIQ 0 -#define AT91RM9200_INT_SYSIRQ 1 -#define AT91RM9200_INT_PIOA 2 -#define AT91RM9200_INT_PIOB 3 -#define AT91RM9200_INT_PIOC 4 -#define AT91RM9200_INT_PIOD 5 -#define AT91RM9200_INT_US0 6 -#define AT91RM9200_INT_US1 7 -#define AT91RM9200_INT_US2 8 -#define AT91RM9200_INT_US3 9 -#define AT91RM9200_INT_MCI 10 -#define AT91RM9200_INT_UDP 11 -#define AT91RM9200_INT_TWI 12 -#define AT91RM9200_INT_SPI 13 -#define AT91RM9200_INT_SSC0 14 -#define AT91RM9200_INT_SSC1 15 -#define AT91RM9200_INT_SSC2 16 -#define AT91RM9200_INT_TC0 17 -#define AT91RM9200_INT_TC1 18 -#define AT91RM9200_INT_TC2 19 -#define AT91RM9200_INT_TC3 20 -#define AT91RM9200_INT_TC4 21 -#define AT91RM9200_INT_TC5 22 -#define AT91RM9200_INT_UHP 23 -#define AT91RM9200_INT_EMAC 24 -#define AT91RM9200_INT_IRQ0 25 -#define AT91RM9200_INT_IRQ1 26 -#define AT91RM9200_INT_IRQ2 27 -#define AT91RM9200_INT_IRQ3 28 -#define AT91RM9200_INT_IRQ4 28 -#define AT91RM9200_INT_IRQ5 30 -#define AT91RM9200_INT_IRQ6 31 -#define AT91RM9200_MAX_INT 32 - -#define BSP_INTERRUPT_VECTOR_MIN 0 - -#define BSP_INTERRUPT_VECTOR_MAX (AT91RM9200_MAX_INT - 1) - -#endif /* __IRQ_H__ */ diff --git a/c/src/lib/libbsp/arm/csb337/include/sed1356.h b/c/src/lib/libbsp/arm/csb337/include/sed1356.h deleted file mode 100644 index d4451ab7e1..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/sed1356.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * @file - * - * @ingroup arm_csb337 - * - * @brief Public Interface for SED Video Controller Operations. - */ - -/** - * @defgroup csb337_sed1356 SED Video Controller - * - * @ingroup arm_csb337 - * - * @brief Public Interface for SED Video Controller Operations. - */ - -/* - * Public Interface for SED Video Controller Operations - * - * COPYRIGHT (c) 1989-2009. - * On-Line Applications Research Corporation (OAR). - * - * Modified by Fernando Nicodemos <fgnicodemos@terra.com.br> - * from NCB - Sistemas Embarcados Ltda. (Brazil) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __SED1356_h -#define __SED1356_h - -void sed_init(void); - -int sed_frame_buffer_size(void); - -void sed_clr_row(int char_row); - -void sed_putchar(char c); - -void sed_putstring(char *s); - -void sed_clearscreen(void); - -void sed_write_frame_buffer( - uint32_t i, - uint16_t wr16 -); - -#endif -/* end of file */ diff --git a/c/src/lib/libbsp/arm/csb337/include/tm27.h b/c/src/lib/libbsp/arm/csb337/include/tm27.h deleted file mode 100644 index 0dfa7bf628..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/tm27.h +++ /dev/null @@ -1 +0,0 @@ -#include <rtems/tm27-default.h> diff --git a/c/src/lib/libbsp/arm/csb337/preinstall.am b/c/src/lib/libbsp/arm/csb337/preinstall.am deleted file mode 100644 index 57ab234874..0000000000 --- a/c/src/lib/libbsp/arm/csb337/preinstall.am +++ /dev/null @@ -1,148 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - -$(PROJECT_LIB)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_LIB) - @: > $(PROJECT_LIB)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) - -$(PROJECT_INCLUDE)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE) - @: > $(PROJECT_INCLUDE)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) - -$(PROJECT_INCLUDE)/bsp/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp - @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) - -$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs -PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs - -$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h - -$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h - -$(PROJECT_INCLUDE)/at91rm9200_dbgu.h: include/at91rm9200_dbgu.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200_dbgu.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200_dbgu.h - -$(PROJECT_INCLUDE)/at91rm9200_emac.h: include/at91rm9200_emac.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200_emac.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200_emac.h - -$(PROJECT_INCLUDE)/at91rm9200_gpio.h: include/at91rm9200_gpio.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200_gpio.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200_gpio.h - -$(PROJECT_INCLUDE)/at91rm9200.h: include/at91rm9200.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200.h - -$(PROJECT_INCLUDE)/at91rm9200_mem.h: include/at91rm9200_mem.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200_mem.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200_mem.h - -$(PROJECT_INCLUDE)/at91rm9200_pmc.h: include/at91rm9200_pmc.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200_pmc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200_pmc.h - -$(PROJECT_INCLUDE)/at91rm9200_usart.h: include/at91rm9200_usart.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200_usart.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200_usart.h - -$(PROJECT_INCLUDE)/bits.h: include/bits.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bits.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bits.h - -if ENABLE_LCD -$(PROJECT_INCLUDE)/sed1356.h: include/sed1356.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/sed1356.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/sed1356.h -endif -if ENABLE_UMON -$(PROJECT_INCLUDE)/umon/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/umon - @: > $(PROJECT_INCLUDE)/umon/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/umon/$(dirstamp) - -$(PROJECT_INCLUDE)/umon/cli.h: ../../shared/umon/cli.h $(PROJECT_INCLUDE)/umon/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/umon/cli.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/umon/cli.h - -$(PROJECT_INCLUDE)/umon/monlib.h: ../../shared/umon/monlib.h $(PROJECT_INCLUDE)/umon/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/umon/monlib.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/umon/monlib.h - -$(PROJECT_INCLUDE)/umon/tfs.h: ../../shared/umon/tfs.h $(PROJECT_INCLUDE)/umon/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/umon/tfs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/umon/tfs.h - -$(PROJECT_INCLUDE)/rtems/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems - @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) - -$(PROJECT_INCLUDE)/rtems/umon.h: ../../shared/umon/umon.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/umon.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/umon.h -endif -$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h - -$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h - -if ENABLE_LCD -$(PROJECT_INCLUDE)/sed1356_16bit.h: console/sed1356_16bit.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/sed1356_16bit.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/sed1356_16bit.h - -$(PROJECT_INCLUDE)/font8x16.h: console/font8x16.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/font8x16.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/font8x16.h -endif -$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) -TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) - -$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds -TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds - -$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h - -$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h - -$(PROJECT_INCLUDE)/bsp/irq.h: include/bsp/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h - diff --git a/c/src/lib/libbsp/arm/csb337/bsp_specs b/c/src/lib/libbsp/arm/csb337/startup/bsp_specs index 47dd31d46b..47dd31d46b 100644 --- a/c/src/lib/libbsp/arm/csb337/bsp_specs +++ b/c/src/lib/libbsp/arm/csb337/startup/bsp_specs |