diff options
| author | Pavel Pisa <ppisa@pikron.com> | 2013-08-09 01:22:06 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-08-14 16:25:58 +0200 |
| commit | 2a2f559957c0e14fdfa012dd453316d87a8b7fd7 (patch) | |
| tree | 75a888e16047ba12706cfc084095244b0a89872c /c/src/lib/libbsp/arm/csb336 | |
| parent | bsp/lm3s69xx: add macros for UART CTS/RTS pin configuration (diff) | |
| download | rtems-2a2f559957c0e14fdfa012dd453316d87a8b7fd7.tar.bz2 | |
bsp/csb336: Memory map update and jump to start at image start provided.
CSB336 i.MX1/i.MXS memory map organization
- SDRAM starts at address 0x08000000 but 2 MB are reserved
for boot-block/loader (or other use) before RTEMS image
origin/load address (that is kept from previous setup)
- Caching of 30 MB of SDRAM used for RTEMS (start at 0x08200000)
is changed to writeback mode which provides higher throughput.
- The first 1 MB of RTEMS dedicated SDRAM is remapped to address 0
to provide area for ARM CPU exceptions table.
- Internal registers and rest of the Flash (above 1 MB) are mapped
one to one. Registers region is extended to 2 MB to cover
eSRAM found on i.MX1 chip variant.
- The first two megabytes of SDRAM unused by RTEMS are mapped
with attributes to allow specific purposes.
- the first MB (at address 0x08000000) is nocached to allow
directly set some values read by booot-block after warm reset
- the second MB (at address 0x08100000) is set for write-through
caching. That allows to use memory for LCD frame-buffer without
need to flush cache after each redraw.
Jump to start provided at address 0x08200000 allows
to load application image even as plain binary file
and start it by jump to image start address.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
Diffstat (limited to 'c/src/lib/libbsp/arm/csb336')
| -rw-r--r-- | c/src/lib/libbsp/arm/csb336/start/start.S | 7 | ||||
| -rw-r--r-- | c/src/lib/libbsp/arm/csb336/startup/memmap.c | 10 |
2 files changed, 14 insertions, 3 deletions
diff --git a/c/src/lib/libbsp/arm/csb336/start/start.S b/c/src/lib/libbsp/arm/csb336/start/start.S index d24db37d6b..07f0fd3562 100644 --- a/c/src/lib/libbsp/arm/csb336/start/start.S +++ b/c/src/lib/libbsp/arm/csb336/start/start.S @@ -23,6 +23,13 @@ .equ PSR_F, 0x40 .equ PSR_T, 0x20 +.section .bsp_start_text,"ax" + .code 32 +_start_jump_at_origin: + ldr pc, _start_address +_start_address: + .word _start + .text .globl _start _start: diff --git a/c/src/lib/libbsp/arm/csb336/startup/memmap.c b/c/src/lib/libbsp/arm/csb336/startup/memmap.c index 4feb63d2b2..3fe8bbee8d 100644 --- a/c/src/lib/libbsp/arm/csb336/startup/memmap.c +++ b/c/src/lib/libbsp/arm/csb336/startup/memmap.c @@ -16,10 +16,14 @@ */ mmu_sect_map_t mem_map[] = { /* <phys addr> <virt addr> <size> <flags> */ - {0x08200000, 0x00000000, 1, MMU_CACHE_NONE}, /* Mirror of SDRAM */ + {0x08200000, 0x00000000, 1, MMU_CACHE_WBACK}, /* Mirror of SDRAM */ {0x00100000, 0x00100000, 1, MMU_CACHE_NONE}, /* Bootstrap ROM */ - {0x00200000, 0x00200000, 1, MMU_CACHE_NONE}, /* Internal Regs */ - {0x08000000, 0x08000000, 32, MMU_CACHE_WTHROUGH}, /* SDRAM */ + {0x00200000, 0x00200000, 2, MMU_CACHE_NONE}, /* Internal Regs + eSRAM */ + + {0x08000000, 0x08000000, 1, MMU_CACHE_NONE}, /* SDRAM */ + {0x08100000, 0x08100000, 1, MMU_CACHE_WTHROUGH}, /* SDRAM */ + {0x08200000, 0x08200000, 30, MMU_CACHE_WBACK}, /* SDRAM */ + {0x10000000, 0x10000000, 8, MMU_CACHE_NONE}, /* CS0 - Flash */ {0x12000000, 0x12000000, 1, MMU_CACHE_NONE}, /* CS1 - enet */ {0x13000000, 0x13000000, 1, MMU_CACHE_NONE}, /* CS2 - */ |