Ada95, gnat, go32

18 files changed, 677 insertions, 394 deletions

diff --git a/c/src/exec/libcsupport/src/newlibc.c b/c/src/exec/libcsupport/src/newlibc.c
index 39dea67775..c3e886266d 100644
--- a/c/src/exec/libcsupport/src/newlibc.c
+++ b/c/src/exec/libcsupport/src/newlibc.c
@@ -282,7 +282,7 @@ exit(int status)
  *
  */
 
-#ifndef RTEMS_UNIX
+#if !defined(RTEMS_UNIX) && !defined(__GO32__)
 void _exit(int status)
 {
     rtems_shutdown_executive(status);
diff --git a/c/src/exec/sapi/headers/sptables.h b/c/src/exec/sapi/headers/sptables.h
index db7fc487d3..01addc6118 100644
--- a/c/src/exec/sapi/headers/sptables.h
+++ b/c/src/exec/sapi/headers/sptables.h
@@ -42,7 +42,7 @@ const rtems_multiprocessing_table
  */
 
 const char _RTEMS_version[] =
-  "RTEMS RELEASE V3.2.0 (" CPU_NAME "/" RTEMS_MODEL_NAME ")";
+  "RTEMS RELEASE V3.2.01 (" CPU_NAME "/" RTEMS_MODEL_NAME ")";
 
 
 /*
diff --git a/c/src/exec/sapi/include/rtems/sptables.h b/c/src/exec/sapi/include/rtems/sptables.h
index db7fc487d3..01addc6118 100644
--- a/c/src/exec/sapi/include/rtems/sptables.h
+++ b/c/src/exec/sapi/include/rtems/sptables.h
@@ -42,7 +42,7 @@ const rtems_multiprocessing_table
  */
 
 const char _RTEMS_version[] =
-  "RTEMS RELEASE V3.2.0 (" CPU_NAME "/" RTEMS_MODEL_NAME ")";
+  "RTEMS RELEASE V3.2.01 (" CPU_NAME "/" RTEMS_MODEL_NAME ")";
 
 
 /*
diff --git a/c/src/exec/score/cpu/hppa1.1/cpu.c b/c/src/exec/score/cpu/hppa1.1/cpu.c
index 027ed07333..7dd3ecb3b3 100644
--- a/c/src/exec/score/cpu/hppa1.1/cpu.c
+++ b/c/src/exec/score/cpu/hppa1.1/cpu.c
@@ -108,7 +108,27 @@ void _CPU_Initialize(
     _CPU_Table = *cpu_table;
 }
 
-/*  _CPU_ISR_install_vector
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  /*
+   *  This is unsupported.
+   */
+
+  _CPU_Fatal_halt( 0xdeaddead );
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_vector
  *
  *  This kernel routine installs the RTEMS handler for the
  *  specified vector.
diff --git a/c/src/exec/score/cpu/hppa1.1/cpu.h b/c/src/exec/score/cpu/hppa1.1/cpu.h
index 887cbc6c01..e7016a2d29 100644
--- a/c/src/exec/score/cpu/hppa1.1/cpu.h
+++ b/c/src/exec/score/cpu/hppa1.1/cpu.h
@@ -493,6 +493,19 @@ void _CPU_Initialize(
 );
 
 /*
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  This routine installs a "raw" interrupt handler directly into the 
+ *  processor's vector table.
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
  *  _CPU_ISR_install_vector
  *
  *  This routine installs an interrupt vector.
diff --git a/c/src/exec/score/cpu/i386/asm.h b/c/src/exec/score/cpu/i386/asm.h
index 16cf6c3235..adf92f935a 100644
--- a/c/src/exec/score/cpu/i386/asm.h
+++ b/c/src/exec/score/cpu/i386/asm.h
@@ -40,6 +40,15 @@
  *  have to define these as appropriate.
  */
 
+/*
+ *  Go32 suffers the same bug as __REGISTER_PREFIX__ 
+ */
+ 
+#if __GO32__
+#undef  __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__ _
+#endif
+
 #ifndef __USER_LABEL_PREFIX__
 #define __USER_LABEL_PREFIX__ _
 #endif
diff --git a/c/src/exec/score/cpu/i386/cpu.c b/c/src/exec/score/cpu/i386/cpu.c
index 05a836f7e3..f2859230e2 100644
--- a/c/src/exec/score/cpu/i386/cpu.c
+++ b/c/src/exec/score/cpu/i386/cpu.c
@@ -67,7 +67,60 @@ void _CPU_Initialize(
   }
 }
 
-/*  _CPU_ISR_install_vector
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ */
+ 
+#if __GO32__
+#include <cpu.h>
+#include <go32.h>
+#include <dpmi.h>
+#endif /* __GO32__ */
+
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+#if __GO32__
+    _go32_dpmi_seginfo handler_info;
+ 
+    *old_handler =  0;    /* XXX not supported */
+
+    handler_info.pm_offset = new_handler;
+    handler_info.pm_selector = _go32_my_cs();
+
+    /* install the IDT entry */
+    _go32_dpmi_set_protected_mode_interrupt_vector( vector, &handler_info );
+#else
+  i386_IDT_slot idt;
+  unsigned32    handler;
+
+  *old_handler =  0;    /* XXX not supported */
+
+  handler = (unsigned32) new_handler;
+
+  /* build the IDT entry */
+  idt.offset_0_15      = handler & 0xffff;
+  idt.segment_selector = i386_get_cs();
+  idt.reserved         = 0x00;
+  idt.p_dpl            = 0x8e;         /* present, ISR */
+  idt.offset_16_31     = handler >> 16;
+
+  /* install the IDT entry */
+  i386_Install_idt(
+    (unsigned32) &idt,
+    _CPU_Table.interrupt_table_segment,
+    (unsigned32) _CPU_Table.interrupt_table_offset + (8 * vector)
+  );
+#endif
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_vector
  *
  *  This kernel routine installs the RTEMS handler for the
  *  specified vector.
@@ -95,27 +148,15 @@ void _CPU_ISR_install_vector(
   proc_ptr   *old_handler
 )
 {
-  i386_IDT_slot idt;
+  proc_ptr      ignored;
   unsigned32    unique_handler;
 
+  *old_handler = _ISR_Vector_table[ vector ];
+
   /* calculate the unique entry point for this vector */
   unique_handler = _Interrupt_Handler_entry( vector );
 
-  /* build the IDT entry */
-  idt.offset_0_15      = ((unsigned32) unique_handler) & 0xffff;
-  idt.segment_selector = i386_get_cs();
-  idt.reserved         = 0x00;
-  idt.p_dpl            = 0x8e;         /* present, ISR */
-  idt.offset_16_31     = ((unsigned32) unique_handler) >> 16;
-
-  /* install the IDT entry */
-  i386_Install_idt(
-    (unsigned32) &idt,
-    _CPU_Table.interrupt_table_segment,
-    (unsigned32) _CPU_Table.interrupt_table_offset + (8 * vector)
-  );
+  _CPU_ISR_install_raw_handler( vector, (void *)unique_handler, &ignored );
 
-  /* "portable" part */
-  *old_handler = _ISR_Vector_table[ vector ];
   _ISR_Vector_table[ vector ] = new_handler;
 }
diff --git a/c/src/exec/score/cpu/i386/cpu.h b/c/src/exec/score/cpu/i386/cpu.h
index 04518e1daf..2af0096fc6 100644
--- a/c/src/exec/score/cpu/i386/cpu.h
+++ b/c/src/exec/score/cpu/i386/cpu.h
@@ -309,6 +309,19 @@ void _CPU_Initialize(
 );
 
 /*
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  This routine installs a "raw" interrupt handler directly into the 
+ *  processor's vector table.
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
  *  _CPU_ISR_install_vector
  *
  *  This routine installs an interrupt vector.
diff --git a/c/src/exec/score/cpu/i386/cpu_asm.s b/c/src/exec/score/cpu/i386/cpu_asm.s
index 121b4409d9..7030361d46 100644
--- a/c/src/exec/score/cpu/i386/cpu_asm.s
+++ b/c/src/exec/score/cpu/i386/cpu_asm.s
@@ -547,6 +547,11 @@ SYM (_ISR_Dispatch):
         popa                                # restore general registers
         iret                                # return to interrupted thread
 
+/*
+ *  GO32 does not require these segment related routines.
+ */
+
+#ifndef __GO32__
 /*PAGE
  *
  *  void i386_Install_idt(
@@ -648,6 +653,7 @@ SYM (i386_Physical_to_logical):
         subl    eax,ecx                # ecx = logical address equivalent
         movl    ecx,eax                # eax = ecx
         ret
+#endif /* __GO32__ */
 
 END_CODE
 
diff --git a/c/src/exec/score/cpu/i386/i386.h b/c/src/exec/score/cpu/i386/i386.h
index f85f0777cf..3ebde48ed3 100644
--- a/c/src/exec/score/cpu/i386/i386.h
+++ b/c/src/exec/score/cpu/i386/i386.h
@@ -31,7 +31,7 @@ extern "C" {
 #ifdef i386
 #undef i386
 #endif
-#define i386
+#define i386 1
 
 #ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
 #undef REPLACE_THIS_WITH_THE_CPU_MODEL
diff --git a/c/src/exec/score/cpu/i960/cpu.c b/c/src/exec/score/cpu/i960/cpu.c
index 68ecb0525c..d5acebd225 100644
--- a/c/src/exec/score/cpu/i960/cpu.c
+++ b/c/src/exec/score/cpu/i960/cpu.c
@@ -47,7 +47,41 @@ void _CPU_Initialize(
 
 }
 
-/*  _CPU__ISR_Install_vector
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ */
+ 
+#define _Is_vector_caching_enabled( _prcb ) \
+   ((_prcb)->control_tbl->icon & 0x2000)
+
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  i960ca_PRCB *prcb = _CPU_Table.Prcb;
+  proc_ptr    *cached_intr_tbl = NULL;
+
+  /*  The i80960CA does not support vectors 0-7.  The first 9 entries
+   *  in the Interrupt Table are used to manage pending interrupts.
+   *  Thus vector 8, the first valid vector number, is actually in
+   *  slot 9 in the table.
+   */
+
+  *old_handler = prcb->intr_tbl[ vector + 1 ];
+
+  prcb->intr_tbl[ vector + 1 ] = new_handler;
+
+  if ( _Is_vector_caching_enabled( prcb ) )
+    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
+      cached_intr_tbl[ vector >> 4 ] = new_handler;
+}
+
+/*PAGE
+ *
+ *  _CPU__ISR_install_vector
  *
  *  Install the RTEMS vector wrapper in the CPU's interrupt table.
  *
@@ -60,32 +94,19 @@ void _CPU_Initialize(
  *
  */
 
-#define _Is_vector_caching_enabled( _prcb ) \
-   ((_prcb)->control_tbl->icon & 0x2000)
-
 void _CPU_ISR_install_vector(
   unsigned32  vector,
   proc_ptr    new_handler,
   proc_ptr   *old_handler
 )
 {
-  i960ca_PRCB *prcb = _CPU_Table.Prcb;
-  proc_ptr    *cached_intr_tbl = NULL;
-
-/*  The i80960CA does not support vectors 0-7.  The first 9 entries
- *  in the Interrupt Table are used to manage pending interrupts.
- *  Thus vector 8, the first valid vector number, is actually in
- *  slot 9 in the table.
- */
+  proc_ptr ignored;
 
   *old_handler = _ISR_Vector_table[ vector ];
 
-  _ISR_Vector_table[ vector ] = new_handler;
+  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
 
-  prcb->intr_tbl[ vector + 1 ] = _ISR_Handler;
-  if ( _Is_vector_caching_enabled( prcb ) )
-    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
-      cached_intr_tbl[ vector >> 4 ] = _ISR_Handler;
+  _ISR_Vector_table[ vector ] = new_handler;
 }
 
 /*PAGE
diff --git a/c/src/exec/score/cpu/i960/cpu.h b/c/src/exec/score/cpu/i960/cpu.h
index 3d48d32672..4e8e82e9de 100644
--- a/c/src/exec/score/cpu/i960/cpu.h
+++ b/c/src/exec/score/cpu/i960/cpu.h
@@ -358,6 +358,19 @@ void _CPU_Initialize(
 );
 
 /*
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  This routine installs a "raw" interrupt handler directly into the 
+ *  processor's vector table.
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
  *  _CPU_ISR_install_vector
  *
  *  This routine installs an interrupt vector.
diff --git a/c/src/exec/score/cpu/m68k/cpu.c b/c/src/exec/score/cpu/m68k/cpu.c
index 662a0440f4..a97698372a 100644
--- a/c/src/exec/score/cpu/m68k/cpu.c
+++ b/c/src/exec/score/cpu/m68k/cpu.c
@@ -40,7 +40,29 @@ void _CPU_Initialize(
 
 }
 
-/*  _CPU_ISR_install_vector
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  proc_ptr *interrupt_table = NULL;
+
+  m68k_get_vbr( interrupt_table );
+
+  *old_handler = interrupt_table[ vector ];
+
+  interrupt_table[ vector ] = new_handler;
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_vector
  *
  *  This kernel routine installs the RTEMS handler for the
  *  specified vector.
@@ -51,15 +73,6 @@ void _CPU_Initialize(
  *    old_handler - former ISR for this vector number
  *
  *  Output parameters:  NONE
- *
- *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  This material may be reproduced by or for the U.S. Government pursuant
- *  to the copyright license under the clause at DFARS 252.227-7013.  This
- *  notice must appear in all copies of this file and its derivatives.
- *
- *  $Id$
  */
 
 void _CPU_ISR_install_vector(
@@ -68,14 +81,13 @@ void _CPU_ISR_install_vector(
   proc_ptr   *old_handler
 )
 {
-  proc_ptr *interrupt_table = NULL;
-
-  m68k_get_vbr( interrupt_table );
+  proc_ptr ignored;
 
   *old_handler = _ISR_Vector_table[ vector ];
 
+  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
+
   _ISR_Vector_table[ vector ] = new_handler;
-  interrupt_table[ vector ] = _ISR_Handler;
 }
 
 
@@ -100,21 +112,21 @@ void _CPU_Install_interrupt_stack( void )
  * Returns log2(x)  0<x<256
  */
 const unsigned char __log2table[256] = {
-    0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
-    4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
-    5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-    5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-    6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
-    6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
-    6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
-    6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
-    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
-    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+    0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
+    4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0
 };
 #endif
diff --git a/c/src/exec/score/cpu/m68k/cpu.h b/c/src/exec/score/cpu/m68k/cpu.h
index 0b36533562..566e479f3a 100644
--- a/c/src/exec/score/cpu/m68k/cpu.h
+++ b/c/src/exec/score/cpu/m68k/cpu.h
@@ -328,20 +328,18 @@ EXTERN void               *_CPU_Interrupt_stack_high;
   { \
     extern const unsigned char __log2table[256]; \
     \
-    (_output) = 0;  /* avoids warnings */ \
-    asm         (  "move.w     %1,%0\n"\
-     "\tandi.w     #0xff00,%0\n"\
-     "\tjbne       0f\n"\
-     "\tmoveq.l    #0,%0\n"\
-     "\tmove.b     (%2,%1.w),%0\n"\
-     "\tjbra       1f\n"\
-     "0:\tmoveq.l    #8,%0\n"\
-     "\tlsr.w      #8,%1\n"\
-     "\tadd.b      (%2,%1.w),%0\n"\
-     "1:"\
-     : "=&d" ((_output)) \
-     : "d" ((_value)), "ao" (__log2table) \
-     : "cc" ) ; \
+    asm     ( "   tst.b   %1\n"           /* check for bits in ls byte */ \
+              "   beq.s   0f\n"           /* branch if no bits set */ \
+              "   moveq.l #0,%0\n"        /* set up for bits 0..7 */ \
+              "   andi.w  #0x00ff,%1\n"   /* clear ms byte for add inst */ \
+              "   bra.s   1f\n"           /* go add */ \
+              "0: moveq.l #8,%0\n"        /* set up for bits 8..15 */ \
+              "   lsr.w   #8,%1\n"        /* shift ms byte to ls byte, */ \
+                                          /*   filling ms byte with 0s */ \
+              "1: add.b   (%2,%1.w),%0\n" /* add offset for bit pattern */ \
+               : "=&d" ((_output)) \
+               : "d" ((_value)), "ao" (__log2table) \
+               : "cc" ) ; \
   }
 
 #endif
@@ -385,6 +383,19 @@ void _CPU_Initialize(
 );
 
 /*
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  This routine installs a "raw" interrupt handler directly into the 
+ *  processor's vector table.
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
  *  _CPU_ISR_install_vector
  *
  *  This routine installs an interrupt vector.
diff --git a/c/src/exec/score/cpu/no_cpu/cpu.c b/c/src/exec/score/cpu/no_cpu/cpu.c
index 4d14d231d7..f95c435eae 100644
--- a/c/src/exec/score/cpu/no_cpu/cpu.c
+++ b/c/src/exec/score/cpu/no_cpu/cpu.c
@@ -61,7 +61,26 @@ void _CPU_Initialize(
   _CPU_Table = *cpu_table;
 }
 
-/*  _CPU_ISR_install_vector
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  /*
+   *  This is where we install the interrupt handler into the "raw" interrupt
+   *  table used by the CPU to dispatch interrupt handlers.
+   */
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_vector
  *
  *  This kernel routine installs the RTEMS handler for the
  *  specified vector.
@@ -75,7 +94,6 @@ void _CPU_Initialize(
  *
  */
 
-
 void _CPU_ISR_install_vector(
   unsigned32  vector,
   proc_ptr    new_handler,
@@ -90,6 +108,8 @@ void _CPU_ISR_install_vector(
     *  handler for this vector number.
     */
 
+   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
+
    /*
     *  We put the actual user ISR address in '_ISR_vector_table'.  This will
     *  be used by the _ISR_Handler so the user gets control.
diff --git a/c/src/exec/score/cpu/no_cpu/cpu.h b/c/src/exec/score/cpu/no_cpu/cpu.h
index 5bd0f69c8c..29a6960ea2 100644
--- a/c/src/exec/score/cpu/no_cpu/cpu.h
+++ b/c/src/exec/score/cpu/no_cpu/cpu.h
@@ -702,6 +702,19 @@ void _CPU_Initialize(
 );
 
 /*
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  This routine installs a "raw" interrupt handler directly into the 
+ *  processor's vector table.
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
  *  _CPU_ISR_install_vector
  *
  *  This routine installs an interrupt vector.
diff --git a/c/src/exec/score/cpu/unix/cpu.c b/c/src/exec/score/cpu/unix/cpu.c
index 68397a4e29..acd53e3fd2 100644
--- a/c/src/exec/score/cpu/unix/cpu.c
+++ b/c/src/exec/score/cpu/unix/cpu.c
@@ -17,20 +17,7 @@
  */
 
 #include <rtems/system.h>
-#include <rtems/fatal.h>
 #include <rtems/isr.h>
-#include <rtems/wkspace.h>
-/*
- *  In order to get the types and prototypes used in this file under
- *  Solaris 2.3, it is necessary to pull the following magic.
- */ 
-
-#if defined(solaris)
-#warning "Ignore the undefining __STDC__ warning"
-#undef __STDC__
-#define __STDC__ 0
-#undef  _POSIX_C_SOURCE
-#endif
 
 #include <stdio.h>
 #include <stdlib.h>
@@ -38,22 +25,17 @@
 #include <signal.h>
 #include <time.h>
 
-extern void           set_vector(proc_ptr, int, int);
-extern void           _Thread_Dispatch(void);
-
-extern unsigned32 _Thread_Dispatch_disable_level;
-extern unsigned32 _SYSTEM_ID;
-extern boolean    _Context_Switch_necessary;
-
+#ifndef SA_RESTART
+#define SA_RESTART 0
+#endif
 
-rtems_status_code signal_initialize(void);
-void         Stray_signal(int);
-void         signal_enable(unsigned32);
-void         signal_disable(unsigned32);
-void         interrupt_handler();
+void  _CPU_Signal_initialize(void);
+void  _CPU_Stray_signal(int);
+void  _CPU_ISR_Handler(int);
 
-sigset_t   UNIX_SIGNAL_MASK;
-jmp_buf    default_context;
+sigset_t         _CPU_Signal_mask;
+Context_Control  _CPU_Context_Default_with_ISRs_enabled;
+Context_Control  _CPU_Context_Default_with_ISRs_disabled;
 
 /*
  * Which cpu are we? Used by libcpu and libbsp.
@@ -61,6 +43,144 @@ jmp_buf    default_context;
 
 int cpu_number;
 
+/*PAGE
+ *
+ *  _CPU_ISR_From_CPU_Init
+ */
+
+void _CPU_ISR_From_CPU_Init()
+{
+  unsigned32        i;
+  proc_ptr          old_handler;
+
+
+  /*
+   * Block all the signals except SIGTRAP for the debugger
+   * and SIGABRT for fatal errors.
+   */
+
+  _CPU_ISR_Enable(1);
+
+  (void) sigfillset(&_CPU_Signal_mask);
+  (void) sigdelset(&_CPU_Signal_mask, SIGTRAP);
+  (void) sigdelset(&_CPU_Signal_mask, SIGABRT);
+  (void) sigdelset(&_CPU_Signal_mask, SIGIOT);
+  (void) sigdelset(&_CPU_Signal_mask, SIGCONT);
+
+  sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
+
+  /*
+   * Set the handler for all signals to be signal_handler
+   * which will then vector out to the correct handler
+   * for whichever signal actually happened. Initially
+   * set the vectors to the stray signal handler.
+   */
+
+  for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++)
+      (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler);
+
+  _CPU_Signal_initialize();
+}
+
+void _CPU_Signal_initialize( void )
+{
+  struct sigaction  act;
+  sigset_t          mask;
+
+  /* mark them all active except for TraceTrap  and Abort */
+
+  sigfillset(&mask);
+  sigdelset(&mask, SIGTRAP);
+  sigdelset(&mask, SIGABRT);
+  sigdelset(&mask, SIGIOT);
+  sigdelset(&mask, SIGCONT);
+  sigprocmask(SIG_UNBLOCK, &mask, 0);
+
+  act.sa_handler = _CPU_ISR_Handler;
+  act.sa_mask = mask;
+  act.sa_flags = SA_RESTART;
+
+  sigaction(SIGHUP, &act, 0);
+  sigaction(SIGINT, &act, 0);
+  sigaction(SIGQUIT, &act, 0);
+  sigaction(SIGILL, &act, 0);
+  sigaction(SIGEMT, &act, 0);
+  sigaction(SIGFPE, &act, 0);
+  sigaction(SIGKILL, &act, 0);
+  sigaction(SIGBUS, &act, 0);
+  sigaction(SIGSEGV, &act, 0);
+  sigaction(SIGSYS, &act, 0);
+  sigaction(SIGPIPE, &act, 0);
+  sigaction(SIGALRM, &act, 0);
+  sigaction(SIGTERM, &act, 0);
+  sigaction(SIGUSR1, &act, 0);
+  sigaction(SIGUSR2, &act, 0);
+  sigaction(SIGCHLD, &act, 0);
+  sigaction(SIGCLD, &act, 0);
+  sigaction(SIGPWR, &act, 0);
+  sigaction(SIGVTALRM, &act, 0);
+  sigaction(SIGPROF, &act, 0);
+  sigaction(SIGIO, &act, 0);
+  sigaction(SIGWINCH, &act, 0);
+  sigaction(SIGSTOP, &act, 0);
+  sigaction(SIGTTIN, &act, 0);
+  sigaction(SIGTTOU, &act, 0);
+  sigaction(SIGURG, &act, 0);
+/*
+ *  XXX: Really should be on HPUX.
+ */
+
+#if defined(hppa1_1)
+    sigaction(SIGLOST, &act, 0);
+#endif
+
+}
+
+/*PAGE
+ *
+ *  _CPU_Context_From_CPU_Init
+ */
+
+void _CPU_Context_From_CPU_Init()
+{
+
+#if defined(hppa1_1) && defined(RTEMS_UNIXLIB)
+    /*
+     * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
+     * will handle the full 32 floating point registers.
+     * 
+     *  NOTE:  Is this a bug in HPUX9?
+     */
+
+    {
+      extern unsigned32 _SYSTEM_ID;
+
+      _SYSTEM_ID = 0x20c;
+    }
+#endif
+
+  /*
+   *  get default values to use in _CPU_Context_Initialize()
+   */
+
+  _CPU_ISR_Set_level( 0 );
+  setjmp( _CPU_Context_Default_with_ISRs_enabled.regs );
+  sigprocmask(
+    SIG_SETMASK,    /* ignored when second arg is NULL */
+    0,
+    &_CPU_Context_Default_with_ISRs_enabled.isr_level
+  );
+
+  _CPU_ISR_Set_level( 1 );
+  setjmp( _CPU_Context_Default_with_ISRs_disabled.regs );
+  sigprocmask(
+    SIG_SETMASK,    /* ignored when second arg is NULL */
+    0,
+    &_CPU_Context_Default_with_ISRs_disabled.isr_level
+  );
+
+}
+
 /*  _CPU_Initialize
  *
  *  This routine performs processor dependent initialization.
@@ -76,10 +196,8 @@ void _CPU_Initialize(
   void      (*thread_dispatch)      /* ignored on this CPU */
 )
 {
-  unsigned32  i;
-
   if ( cpu_table == NULL )
-    rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED );
+    _CPU_Fatal_halt( RTEMS_NOT_CONFIGURED );
 
   /*
    *  The thread_dispatch argument is the address of the entry point
@@ -105,52 +223,29 @@ void _CPU_Initialize(
 
   _CPU_Table = *cpu_table;
 
-#if defined(hppa1_1) && defined(RTEMS_UNIXLIB)
-    /*
-     * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
-     * will handle the full 32 floating point registers.
-     * 
-     *  NOTE:  Is this a bug in HPUX9?
-     */
+  _CPU_ISR_From_CPU_Init();
 
-    _SYSTEM_ID = 0x20c;
-#endif
+  _CPU_Context_From_CPU_Init();
 
-  /*
-   *  get default values to use in _CPU_Context_Initialize()
-   */
-
-   setjmp(default_context);
-
-  /*
-   * Block all the signals except SIGTRAP for the debugger
-   * and SIGABRT for fatal errors.
-   */
-
-  _CPU_ISR_Set_signal_level(1);
-
-  sigfillset(&UNIX_SIGNAL_MASK);
-  sigdelset(&UNIX_SIGNAL_MASK, SIGTRAP);
-  sigdelset(&UNIX_SIGNAL_MASK, SIGABRT);
-  sigdelset(&UNIX_SIGNAL_MASK, SIGIOT);
-  sigdelset(&UNIX_SIGNAL_MASK, SIGCONT);
-
-  sigprocmask(SIG_BLOCK, &UNIX_SIGNAL_MASK, 0);
-
-  /*
-   * Set the handler for all signals to be signal_handler
-   * which will then vector out to the correct handler
-   * for whichever signal actually happened. Initially
-   * set the vectors to the stray signal handler.
-   */
+}
 
-  for (i = 0; i < 32; i++)
-      (void)set_vector(Stray_signal, i, 1);
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ */
 
-  signal_initialize();
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  _CPU_Fatal_halt( 0xdeaddead );
 }
 
-/*  _CPU_ISR_install_vector
+/*PAGE
+ *
+ *  _CPU_ISR_install_vector
  *
  *  This kernel routine installs the RTEMS handler for the
  *  specified vector.
@@ -181,7 +276,7 @@ void _CPU_ISR_install_vector(
 
    /*
     *  We put the actual user ISR address in '_ISR_vector_table'.  This will
-    *  be used by the _ISR_Handler so the user gets control.
+    *  be used by the _CPU_ISR_Handler so the user gets control.
     */
 
     _ISR_Vector_table[ vector ] = new_handler;
@@ -215,10 +310,15 @@ void _CPU_Install_interrupt_stack( void )
 
 void _CPU_Internal_threads_Idle_thread_body( void )
 {
-    while (1)
-        pause();
+  while (1)
+    pause();
 }
 
+/*PAGE
+ * 
+ *  _CPU_Context_Initialize
+ */
+
 void _CPU_Context_Initialize(
   Context_Control  *_the_context,
   unsigned32       *_stack_base,
@@ -227,100 +327,114 @@ void _CPU_Context_Initialize(
   void             *_entry_point
 )
 {
-    unsigned32  *addr;
-    unsigned32   jmp_addr;
-    unsigned32   _stack_low;   /* lowest "stack aligned" address */
-    unsigned32   _stack_high;  /* highest "stack aligned" address */
-    unsigned32   _the_size;
+  void        *source;
+  unsigned32  *addr;
+  unsigned32   jmp_addr;
+  unsigned32   _stack_low;   /* lowest "stack aligned" address */
+  unsigned32   _stack_high;  /* highest "stack aligned" address */
+  unsigned32   _the_size;
 
-    jmp_addr = (unsigned32) _entry_point;
+  jmp_addr = (unsigned32) _entry_point;
 
-    /*
-     *  On CPUs with stacks which grow down, we build the stack
-     *  based on the _stack_high address.  On CPUs with stacks which 
-     *  grow up, we build the stack based on the _stack_low address.  
-     */
+  /*
+   *  On CPUs with stacks which grow down, we build the stack
+   *  based on the _stack_high address.  On CPUs with stacks which 
+   *  grow up, we build the stack based on the _stack_low address.  
+   */
 
-    _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT);
-    _stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
+  _stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT);
+  _stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
 
-    _stack_high = ((unsigned32)(_stack_base) + _size);
-    _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
+  _stack_high = ((unsigned32)(_stack_base) + _size);
+  _stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
 
-    _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1);
+  _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1);
 
-    /*
-     * Slam our jmp_buf template into the context we are creating
-     */
+  /*
+   * Slam our jmp_buf template into the context we are creating
+   */
 
-    memcpy(_the_context, default_context, sizeof(jmp_buf));
+  if ( _new_level == 0 )
+    source = _CPU_Context_Default_with_ISRs_enabled.regs;
+  else
+    source = _CPU_Context_Default_with_ISRs_disabled.regs;
+      
+  memcpy(_the_context, source, sizeof(jmp_buf));
 
-    addr = (unsigned32 *)_the_context;
+  addr = (unsigned32 *)_the_context;
 
 #if defined(hppa1_1)
-    *(addr + RP_OFF) = jmp_addr;
-    *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
+  *(addr + RP_OFF) = jmp_addr;
+  *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
 
-    /*
-     * See if we are using shared libraries by checking
-     * bit 30 in 24 off of newp. If bit 30 is set then
-     * we are using shared libraries and the jump address
-     * is at what 24 off of newp points to so shove that
-     * into 24 off of newp instead.
-     */
+  /*
+   * See if we are using shared libraries by checking
+   * bit 30 in 24 off of newp. If bit 30 is set then
+   * we are using shared libraries and the jump address
+   * is at what 24 off of newp points to so shove that
+   * into 24 off of newp instead.
+   */
 
-    if (jmp_addr & 0x40000000) {
-       jmp_addr &= 0xfffffffc;
-       *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr;
-    }
+  if (jmp_addr & 0x40000000) {
+    jmp_addr &= 0xfffffffc;
+     *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr;
+  }
 #elif defined(sparc)
 
-    /*
-     *  See /usr/include/sys/stack.h in Solaris 2.3 for a nice
-     *  diagram of the stack.
-     */
+  /*
+   *  See /usr/include/sys/stack.h in Solaris 2.3 for a nice
+   *  diagram of the stack.
+   */
 
-    asm ("ta  0x03");            /* flush registers */
+  asm ("ta  0x03");            /* flush registers */
 
-    *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
-    *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
-    *(addr + FP_OFF) = (unsigned32)(_stack_high);
+  *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
+  *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
+  *(addr + FP_OFF) = (unsigned32)(_stack_high);
 #else
 #error "UNKNOWN CPU!!!"
 #endif
 
-    if (_new_level)
-        _CPU_ISR_Set_signal_level(1);
-    else
-        _CPU_ISR_Set_signal_level(0);
-
 }
 
+/*PAGE
+ *
+ *  _CPU_Context_restore
+ */
+
 void _CPU_Context_restore(
   Context_Control  *next
 )
 {
-    longjmp(next->regs, 0);
+  sigprocmask( SIG_SETMASK, &next->isr_level, 0 );
+  longjmp( next->regs, 0 );
 }
 
+/*PAGE
+ *
+ *  _CPU_Context_switch
+ */
+
 void _CPU_Context_switch(
   Context_Control  *current,
   Context_Control  *next
 )
 {
-    /*
-     * Save the current context
-     */
-
-    if (setjmp(current->regs) == 0) {
+  /*
+   *  Switch levels in one operation
+   */
 
-       /*
-        * Switch to the new context
-        */
+  sigprocmask( SIG_SETMASK, &next->isr_level, &current->isr_level );
 
-       longjmp(next->regs, 0);
-    }
+  if (setjmp(current->regs) == 0) {    /* Save the current context */
+     longjmp(next->regs, 0);           /* Switch to the new context */
+  }
 }
+ 
+/*PAGE
+ *
+ *  _CPU_Save_float_context
+ */
 
 void _CPU_Save_float_context(
   Context_Control_fp *fp_context
@@ -328,211 +442,157 @@ void _CPU_Save_float_context(
 {
 }
 
+/*PAGE
+ *
+ *  _CPU_Restore_float_context
+ */
+
 void _CPU_Restore_float_context(
   Context_Control_fp *fp_context
 )
 {
 }
 
-void _CPU_ISR_Set_signal_level(unsigned32 level)
-{
-    if (level)
-        _CPU_Disable_signal();
-    else
-        _CPU_Enable_signal(0);
-}
-
+/*PAGE
+ *
+ *  _CPU_ISR_Disable_support
+ */
 
-unsigned32 _CPU_Disable_signal(void)
+unsigned32 _CPU_ISR_Disable_support(void)
 {
-    sigset_t  old_mask;
-    sigset_t  empty_mask;
+  sigset_t  old_mask;
+  sigset_t  empty_mask;
 
-    sigemptyset(&empty_mask);
-    sigemptyset(&old_mask);
-    sigprocmask(SIG_BLOCK, &UNIX_SIGNAL_MASK, &old_mask);
+  sigemptyset(&empty_mask);
+  sigemptyset(&old_mask);
+  sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask);
 
-    if (memcmp((char *)&empty_mask, (char *)&old_mask, sizeof(sigset_t)) != 0)
-        return 1;
+  if (memcmp((char *)&empty_mask, (char *)&old_mask, sizeof(sigset_t)) != 0)
+    return 1;
 
-    return 0;
+  return 0;
 }
 
+/*PAGE
+ *
+ *  _CPU_ISR_Enable
+ */
 
-void _CPU_Enable_signal(unsigned32 level)
+void _CPU_ISR_Enable(
+  unsigned32 level
+)
 {
-    if (level == 0)
-        sigprocmask(SIG_UNBLOCK, &UNIX_SIGNAL_MASK, 0);
+  if (level == 0)
+    sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0);
+  else
+    sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
 }
 
-
-/*
- * Support for external and spurious interrupts on HPPA
+/*PAGE
  *
- *  TODO:
- *    delete interrupt.c etc.
- *    Count interrupts
- *    make sure interrupts disabled properly
- *    should handler check again for more interrupts before exit?
- *    How to enable interrupts from an interrupt handler?
- *    Make sure there is an entry for everything in ISR_Vector_Table
- */
-
-/*
- * Init the external interrupt scheme
- * called by bsp_start()
+ *  _CPU_ISR_Handler
+ *
+ *  External interrupt handler.
+ *  This is installed as a UNIX signal handler.
+ *  It vectors out to specific user interrupt handlers.
  */
 
-rtems_status_code
-signal_initialize(void)
+void _CPU_ISR_Handler(int vector)
 {
-    struct sigaction act;
-    sigset_t         mask;
-
-    /* mark them all active except for TraceTrap  and Abort */
-
-    sigfillset(&mask);
-    sigdelset(&mask, SIGTRAP);
-    sigdelset(&mask, SIGABRT);
-    sigdelset(&mask, SIGIOT);
-    sigdelset(&mask, SIGCONT);
-    sigprocmask(SIG_UNBLOCK, &mask, 0);
-
-    act.sa_handler = interrupt_handler;
-    act.sa_mask = mask;
-#if defined(solaris)
-    act.sa_flags = SA_RESTART;
-#else
-    act.sa_flags = 0;
-#endif
+  extern void        _Thread_Dispatch(void);
+  extern unsigned32  _Thread_Dispatch_disable_level;
+  extern boolean     _Context_Switch_necessary;
 
-    sigaction(SIGHUP, &act, 0);
-    sigaction(SIGINT, &act, 0);
-    sigaction(SIGQUIT, &act, 0);
-    sigaction(SIGILL, &act, 0);
-    sigaction(SIGEMT, &act, 0);
-    sigaction(SIGFPE, &act, 0);
-    sigaction(SIGKILL, &act, 0);
-    sigaction(SIGBUS, &act, 0);
-    sigaction(SIGSEGV, &act, 0);
-    sigaction(SIGSYS, &act, 0);
-    sigaction(SIGPIPE, &act, 0);
-    sigaction(SIGALRM, &act, 0);
-    sigaction(SIGTERM, &act, 0);
-    sigaction(SIGUSR1, &act, 0);
-    sigaction(SIGUSR2, &act, 0);
-    sigaction(SIGCHLD, &act, 0);
-    sigaction(SIGCLD, &act, 0);
-    sigaction(SIGPWR, &act, 0);
-    sigaction(SIGVTALRM, &act, 0);
-    sigaction(SIGPROF, &act, 0);
-    sigaction(SIGIO, &act, 0);
-    sigaction(SIGWINCH, &act, 0);
-    sigaction(SIGSTOP, &act, 0);
-    sigaction(SIGTTIN, &act, 0);
-    sigaction(SIGTTOU, &act, 0);
-    sigaction(SIGURG, &act, 0);
-/*
- *  XXX: Really should be on HPUX.
- */
 
-#if defined(hppa1_1)
-    sigaction(SIGLOST, &act, 0);
-#endif
-
-    return RTEMS_SUCCESSFUL;
-}
+  if (_ISR_Nest_level++ == 0) {
+      /* switch to interrupt stack */
+  }
 
+  _Thread_Dispatch_disable_level++;
 
-/*
- * External interrupt handler.
- * This is installed as cpu interrupt handler.
- * It vectors out to specific external interrupt handlers.
- */
+  if (_ISR_Vector_table[vector]) {
+     _ISR_Vector_table[vector](vector);
+  } else {
+     _CPU_Stray_signal(vector);
+  }
 
-void
-interrupt_handler(int vector)
-{
-    if (_ISR_Nest_level++ == 0) {
-        /* switch to interrupt stack */
-    }
+  if (_ISR_Nest_level-- == 0) {
+      /* switch back to original stack */
+  }
 
-    _Thread_Dispatch_disable_level++;
+  _Thread_Dispatch_disable_level--;
 
-    if (_ISR_Vector_table[vector]) {
-       _ISR_Vector_table[vector](vector);
-    }
-    else {
-       Stray_signal(vector);
-    }
-
-    if (_ISR_Nest_level-- == 0) {
-        /* switch back to original stack */
-    }
-
-    _Thread_Dispatch_disable_level--;
-
-    if (_Thread_Dispatch_disable_level == 0 &&
-        (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) {
-        _CPU_Enable_signal(0);
-        _Thread_Dispatch();
-    }
+  if (_Thread_Dispatch_disable_level == 0 &&
+      (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) {
+      _CPU_ISR_Enable(0);
+      _Thread_Dispatch();
+  }
 }
 
+/*PAGE
+ *
+ *  _CPU_Stray_signal
+ */
 
-void
-Stray_signal(int sig_num)
+void _CPU_Stray_signal(int sig_num)
 {
-    char buffer[ 80 ];   
+  char buffer[ 80 ];   
 
-    /* 
-     *  We avoid using the stdio section of the library.
-     *  The following is generally safe.
-     */
+  /* 
+   *  We avoid using the stdio section of the library.
+   *  The following is generally safe.
+   */
 
-    write( 
-      2,
-      buffer, 
-      sprintf( buffer, "Stray signal %d\n", sig_num )
-    );
+  write( 
+    2,
+    buffer, 
+    sprintf( buffer, "Stray signal %d\n", sig_num )
+  );
  
-    /*
-     * If it was a "fatal" signal, then exit here
-     * If app code has installed a hander for one of these, then
-     * we won't call Stray_signal, so this is ok.
-     */
+  /*
+   * If it was a "fatal" signal, then exit here
+   * If app code has installed a hander for one of these, then
+   * we won't call _CPU_Stray_signal, so this is ok.
+   */
  
-    switch (sig_num)
-    {
-        case SIGINT:
-        case SIGHUP:
-        case SIGQUIT:
-        case SIGILL:
-        case SIGEMT:
-        case SIGKILL:
-        case SIGBUS:
-        case SIGSEGV:
-        case SIGTERM:
-            _CPU_Fatal_error(0x100 + sig_num);
-    }
+  switch (sig_num) {
+      case SIGINT:
+      case SIGHUP:
+      case SIGQUIT:
+      case SIGILL:
+      case SIGEMT:
+      case SIGKILL:
+      case SIGBUS:
+      case SIGSEGV:
+      case SIGTERM:
+          _CPU_Fatal_error(0x100 + sig_num);
+  }
 }
 
+/*PAGE
+ *
+ *  _CPU_Fatal_error
+ */
 
-void
-_CPU_Fatal_error(unsigned32 error)
+void _CPU_Fatal_error(unsigned32 error)
 {
-    setitimer(ITIMER_REAL, 0, 0);
+  setitimer(ITIMER_REAL, 0, 0);
 
-    _exit(error);
+  _exit(error);
 }
 
-int
-_CPU_ffs(unsigned32 value)
+/*PAGE
+ *
+ *  _CPU_ffs
+ */
+
+int _CPU_ffs(unsigned32 value)
 {
-    int output;
+  int output;
+  extern int ffs( int );
 
-    output = ffs(value);
-    output = output - 1;
+  output = ffs(value);
+  output = output - 1;
 
-    return(output);
+  return output;
 }
diff --git a/c/src/exec/score/cpu/unix/cpu.h b/c/src/exec/score/cpu/unix/cpu.h
index 4a016e5879..091f0915b6 100644
--- a/c/src/exec/score/cpu/unix/cpu.h
+++ b/c/src/exec/score/cpu/unix/cpu.h
@@ -26,12 +26,37 @@
 extern "C" {
 #endif
 
-#include <setjmp.h>
 #include <rtems/unix.h>
 #ifndef ASM
 #include <rtems/unixtypes.h>
 #endif
 
+#if defined(solaris2)
+#undef  _POSIX_C_SOURCE
+#define _POSIX_C_SOURCE 3
+#undef  __STRICT_ANSI__
+#define __STRICT_ANSI__
+#endif
+
+#if 0
+
+/*
+ *  In order to get the types and prototypes used in this file under
+ *  Solaris 2.3, it is necessary to pull the following magic.
+ */ 
+
+#if defined(solaris2)
+#warning "Ignore the undefining __STDC__ warning"
+#undef __STDC__
+#define __STDC__ 0
+#undef  _POSIX_C_SOURCE
+#endif
+
+#endif
+
+#include <setjmp.h>
+#include <signal.h>
+
 /* conditional compilation parameters */
 
 /*
@@ -397,7 +422,9 @@ extern "C" {
  */
 
 typedef struct {
-    jmp_buf   regs;
+  jmp_buf   regs;
+  sigset_t  isr_level;
+  int       junk;
 } Context_Control;
 
 typedef struct {
@@ -567,9 +594,11 @@ EXTERN void           (*_CPU_Thread_dispatch_pointer)();
  *  level is returned in _level.
  */
 
+extern unsigned32 _CPU_ISR_Disable_support(void);
+
 #define _CPU_ISR_Disable( _level ) \
     do { \
-      (_level) = _CPU_Disable_signal(); \
+      (_level) = _CPU_ISR_Disable_support(); \
     } while ( 0 )
 
 /*
@@ -578,10 +607,7 @@ EXTERN void           (*_CPU_Thread_dispatch_pointer)();
  *  _level is not modified.
  */
 
-#define _CPU_ISR_Enable( _level )  \
-    do { \
-      _CPU_Enable_signal( (_level) ); \
-    } while ( 0 )
+void _CPU_ISR_Enable(unsigned32 level);
 
 /*
  *  This temporarily restores the interrupt to _level before immediately
@@ -610,10 +636,8 @@ EXTERN void           (*_CPU_Thread_dispatch_pointer)();
 
 #define _CPU_ISR_Set_level( new_level ) \
   { \
-      if ( new_level ) \
-          (void) _CPU_Disable_signal(); \
-      else \
-          _CPU_Enable_signal( 0 ); \
+    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
+    else                  _CPU_ISR_Enable( 1 ); \
   }
 
 /* end of ISR handler macros */
@@ -793,6 +817,19 @@ void _CPU_Initialize(
 );
 
 /*
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  This routine installs a "raw" interrupt handler directly into the 
+ *  processor's vector table.
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
  *  _CPU_ISR_install_vector
  *
  *  This routine installs an interrupt vector.
@@ -875,12 +912,6 @@ void _CPU_ISR_Set_signal_level(
   unsigned32 level
 );
 
-unsigned32 _CPU_Disable_signal( void );
-
-void _CPU_Enable_signal(
-  unsigned32 level
-);
-
 void _CPU_Fatal_error(
   unsigned32 _error
 );