updates from Tony Bennett for PA and UNIX ports

15 files changed, 258 insertions, 174 deletions

diff --git a/c/src/exec/score/cpu/hppa1.1/cpu.c b/c/src/exec/score/cpu/hppa1.1/cpu.c
index a6cddbc804..48e09b908a 100644
--- a/c/src/exec/score/cpu/hppa1.1/cpu.c
+++ b/c/src/exec/score/cpu/hppa1.1/cpu.c
@@ -24,29 +24,16 @@ void hppa_external_interrupt_initialize(void);
 void hppa_external_interrupt_enable(unsigned32);
 void hppa_external_interrupt_disable(unsigned32);
 void hppa_external_interrupt(unsigned32, CPU_Interrupt_frame *);
+void hppa_cpu_halt(unsigned32);
 
 /*
- * Our interrupt handlers take a 2nd argument:
- *   a pointer to a CPU_Interrupt_frame
- * So we use our own prototype instead of rtems_isr_entry
+ * The first level interrupt handler for first 32 interrupts/traps.
+ * Indexed by vector; generally each entry is _Generic_ISR_Handler.
+ * Some TLB traps may have their own first level handler.
  */
 
-typedef void ( *hppa_rtems_isr_entry )(
-    ISR_Vector_number,
-    CPU_Interrupt_frame *
- );
-
-
-/*
- * who are we?  cpu number
- * Not used by executive proper, just kept (or not) as a convenience
- * for libcpu and libbsp stuff that wants it.
- *
- * Defaults to 0.  If the BSP doesn't like it, it can change it.
- */
-
-int cpu_number;                 /* from 0; cpu number in a multi cpu system */
-
+extern void _Generic_ISR_Handler(void);
+unsigned32 HPPA_first_level_interrupt_handler[HPPA_INTERNAL_INTERRUPTS];
 
 /*  _CPU_Initialize
  *
@@ -86,6 +73,20 @@ void _CPU_Initialize(
     asm volatile( "stw   %%r27,%0" : "=m" (_CPU_Default_gr27): );
 
     /*
+     * Init the first level interrupt handlers
+     */
+
+    for (i=0; i <= HPPA_INTERNAL_INTERRUPTS; i++)
+        HPPA_first_level_interrupt_handler[i] = (unsigned32) _Generic_ISR_Handler;
+
+    /*
+     * Init the 2nd level interrupt handlers
+     */
+
+    for (i=0; i <= CPU_INTERRUPT_NUMBER_OF_VECTORS; i++)
+        _ISR_Vector_table[i] = (ISR_Handler_entry) hppa_cpu_halt;
+
+    /*
      * Stabilize the interrupt stuff
      */
 
@@ -96,6 +97,33 @@ void _CPU_Initialize(
      */
 
     iva_table = (unsigned32) IVA_Table;
+#if defined(hppa1_1)
+    /*
+     * HACK:  (from PA72000 TRM, page 4-19)
+     * "The hardware TLB miss handler will never attempt to service
+     *  a non-access TLB miss or a TLB protection violation.  It
+     *  will only attempt to service TLB accesses that would cause
+     *  Trap Numbers 6 (Instruction TLB miss) and 15 (Data TLB miss)."
+     *
+     * The LPA instruction is used to translate a virtual address to
+     * a physical address, however, if the requested virtual address
+     * is not currently resident in the TLB, the hardware TLB miss
+     * handler will NOT insert it.  In this situation Trap Number
+     * #17 is invoked (Non-access Data TLB miss fault).
+     *
+     * To work around this, a dummy data access is first performed
+     * to the virtual address prior to the LPA.  The dummy access
+     * causes the TLB entry to be inserted (if not already present)
+     * and then the following LPA instruction will not generate
+     * a non-access data TLB miss fault.
+     *
+     * It is unclear whether or not this behaves the same way for
+     * the PA8000.
+     * 
+     */
+    iva = *(volatile unsigned32 *)iva_table;  /* dummy access */
+#endif
+
     HPPA_ASM_LPA(0, iva_table, iva);
     set_iva(iva);
 
@@ -112,8 +140,8 @@ unsigned32 _CPU_ISR_Get_level(void)
     int level;
     HPPA_ASM_SSM(0, level);	/* change no bits; just get copy */
     if (level & HPPA_PSW_I)
-        return 1;
-    return 0;
+        return 0;
+    return 1;
 }
 
 /*PAGE
@@ -184,12 +212,8 @@ void _CPU_ISR_install_vector(
  * Support for external and spurious interrupts on HPPA
  *
  *  TODO:
- *    delete interrupt.c etc.
  *    Count interrupts
  *    make sure interrupts disabled properly
- *    should handler check again for more interrupts before exit?
- *    How to enable interrupts from an interrupt handler?
- *    Make sure there is an entry for everything in ISR_Vector_Table
  */
 
 #define DISMISS(mask)           set_eirr(mask)
@@ -208,16 +232,14 @@ hppa_external_interrupt_initialize(void)
     proc_ptr ignore;
 
     /* mark them all unused */
-
     DISABLE(~0);
     DISMISS(~0);
 
     /* install the external interrupt handler */
-  _CPU_ISR_install_vector(
-    HPPA_INTERRUPT_EXTERNAL_INTERRUPT,
-    (proc_ptr)hppa_external_interrupt,
-    &ignore
-  );
+    _CPU_ISR_install_vector(
+        HPPA_INTERRUPT_EXTERNAL_INTERRUPT,
+	(proc_ptr)hppa_external_interrupt, &ignore
+);
 }
 
 /*
@@ -256,19 +278,21 @@ hppa_external_interrupt_spurious_handler(unsigned32           vector,
     printf("spurious external interrupt: %d at pc 0x%x; disabling\n",
        vector, iframe->Interrupt.pcoqfront);
 */
-    DISMISS(VECTOR_TO_MASK(vector));
-    DISABLE(VECTOR_TO_MASK(vector));
 }
 
 void
-hppa_external_interrupt_report_spurious(unsigned32           spurious,
+hppa_external_interrupt_report_spurious(unsigned32           spurious_mask,
                                         CPU_Interrupt_frame *iframe)
 {
     int v;
     for (v=0; v < HPPA_EXTERNAL_INTERRUPTS; v++)
-        if (VECTOR_TO_MASK(v) & spurious)
+        if (VECTOR_TO_MASK(v) & spurious_mask)
+        {
+            DISMISS(VECTOR_TO_MASK(v));
+            DISABLE(VECTOR_TO_MASK(v));
             hppa_external_interrupt_spurious_handler(v, iframe);
-    DISMISS(spurious);
+        }
+    DISMISS(spurious_mask);
 }
 
 
@@ -304,18 +328,18 @@ hppa_external_interrupt(unsigned32           vector,
             {
                 DISMISS(m);
                 mask &= ~m;
-                (*handler)(global_vector, iframe);
+                handler(global_vector, iframe);
             }
         }
 
         if (mask != 0) {
             if ( _CPU_Table.spurious_handler )
-              (*((hppa_rtems_isr_entry) _CPU_Table.spurious_handler))(
-                  mask,
-                  iframe
-                );
+            {
+                handler = (hppa_rtems_isr_entry) _CPU_Table.spurious_handler;
+                handler(mask, iframe);
+            }
             else
-              hppa_external_interrupt_report_spurious(mask, iframe);
+                hppa_external_interrupt_report_spurious(mask, iframe);
         }
     }
 }
@@ -330,13 +354,12 @@ hppa_external_interrupt(unsigned32           vector,
  */
 
 void
-hppa_cpu_halt(unsigned32 type_of_halt,
-              unsigned32 the_error)
+hppa_cpu_halt(unsigned32 the_error)
 {
     unsigned32 isrlevel;
 
     _CPU_ISR_Disable(isrlevel);
 
-    asm volatile( "copy %0,%%r1" : : "r" (the_error) );
+    HPPA_ASM_LABEL("_hppa_cpu_halt");
     HPPA_ASM_BREAK(1, 0);
 }
diff --git a/c/src/exec/score/cpu/hppa1.1/cpu.h b/c/src/exec/score/cpu/hppa1.1/cpu.h
index 095a03735f..a2b430ca28 100644
--- a/c/src/exec/score/cpu/hppa1.1/cpu.h
+++ b/c/src/exec/score/cpu/hppa1.1/cpu.h
@@ -196,6 +196,17 @@ typedef struct {
 } CPU_Interrupt_frame;
 
 /*
+ * Our interrupt handlers take a 2nd argument:
+ *   a pointer to a CPU_Interrupt_frame
+ * So we use our own prototype instead of rtems_isr_entry
+ */
+
+typedef void ( *hppa_rtems_isr_entry )(
+    unsigned32,
+    CPU_Interrupt_frame *
+ );
+
+/*
  * The following table contains the information required to configure
  * the HPPA specific parameters.
  */
@@ -226,7 +237,7 @@ typedef struct {
   unsigned32   external_interrupts;   /* # of external interrupts we use */
   unsigned32   external_interrupt[HPPA_EXTERNAL_INTERRUPTS];
 
-  void       (*spurious_handler)( unsigned32 mask, CPU_Interrupt_frame *);
+  hppa_rtems_isr_entry spurious_handler;
 
   unsigned32   itimer_clicks_per_microsecond; /* for use by Clock driver */
 }   rtems_cpu_table;
@@ -238,14 +249,18 @@ EXTERN unsigned32          _CPU_Default_gr27;
 EXTERN void               *_CPU_Interrupt_stack_low;
 EXTERN void               *_CPU_Interrupt_stack_high;
 
+/* entry points */
+void hppa_external_interrupt_spurious_handler(unsigned32, CPU_Interrupt_frame *);
+
 #endif          /* ! ASM */
 
 /*
- *  context size area for floating point
+ *  context sizes
  */
 
 #ifndef ASM
-#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
+#define CPU_CONTEXT_SIZE     sizeof( Context_Control )
+#define CPU_CONTEXT_FP_SIZE  sizeof( Context_Control_fp )
 #endif
 
 /*
@@ -439,9 +454,9 @@ unsigned32 _CPU_ISR_Get_level( void );
  *    + disable interrupts and halt the CPU
  */
 
-void    hppa_cpu_halt(unsigned32 type_of_halt, unsigned32 the_error);
+void    hppa_cpu_halt(unsigned32 the_error);
 #define _CPU_Fatal_halt( _error ) \
-    hppa_cpu_halt(0, _error)
+    hppa_cpu_halt(_error)
 
 /* end of Fatal Error manager macros */
 
diff --git a/c/src/exec/score/cpu/hppa1.1/cpu_asm.s b/c/src/exec/score/cpu/hppa1.1/cpu_asm.s
index 3832385ccd..36650e7733 100644
--- a/c/src/exec/score/cpu/hppa1.1/cpu_asm.s
+++ b/c/src/exec/score/cpu/hppa1.1/cpu_asm.s
@@ -49,6 +49,7 @@
 
 isr_arg0           .reg    %cr24
 isr_r9             .reg    %cr25
+isr_r8             .reg    %cr26
 
 #
 # Interrupt stack frame looks like this
@@ -105,30 +106,25 @@ isr_r9             .reg    %cr25
 #
 #  The following macro and the 32 instantiations of the macro
 #  are necessary to determine which interrupt vector occurred.
-#  The following macro allows a unique entry point to be defined
-#  for each vector.
 #
-# r9 was loaded with the vector before branching here
-#   scratch registers available:   gr1, gr8, gr9, gr16, gr17, gr24
+#  r9 is loaded with the vector number and then we jump to
+#    the first level interrupt handler.  In most cases this
+#    is _Generic_ISR_Handler.  In a few cases (such as TLB misc)
+#    it may be to some other entry point.
 #
-# NOTE:
-#  .align 32   doesn not seem to work in the continuation below
-#  so just have to count 8 instructions
-#
-# NOTE:
-#    this whole scheme needs to be rethought for TLB traps which
-#    have requirements about what tlb faults they can incur.
-#    ref:  TLB Operation Requirements in 1.1 arch book
+
+# table for first level interrupt handlers
+        .import   HPPA_first_level_interrupt_handler, data
 
 #define THANDLER(vector) \
-        mtctl   %r9,  isr_r9 !         \
-        b       _Generic_ISR_Handler!        \
-        ldi     vector, %r9!       \
-        nop ! \
-        nop ! \
-        nop ! \
-        nop ! \
-        nop
+        mtctl   %r9,  isr_r9 ! \
+        mtctl   %r8,  isr_r8 ! \
+        ldi     vector, %r9  ! \
+        ldil    L%HPPA_first_level_interrupt_handler,%r8 ! \
+        ldo     R%HPPA_first_level_interrupt_handler(%r8),%r8 ! \
+        ldwx,s  %r9(%r8),%r8 ! \
+        bv      0(%r8) ! \
+        mfctl   isr_r8, %r8
 
         .align 4096
 	.EXPORT IVA_Table,ENTRY,PRIV_LEV=0
@@ -210,10 +206,6 @@ _Generic_ISR_Handler:
 	.CALLINFO FRAME=0,NO_CALLS
 	.ENTRY
 
-# Turn on the D bit in psw so we can start saving stuff on stack
-# (interrupt context pieces that need to be saved before the RFI)
-
-        ssm       HPPA_PSW_D, %r0
         mtctl     arg0, isr_arg0
 
 # save interrupt state
@@ -236,31 +228,6 @@ _Generic_ISR_Handler:
         mfctl     %sar, arg0
         stw       arg0, SAR_OFFSET(sp)
 
-# Prepare to re-enter virtual mode
-# We need Q in case the interrupt handler enables interrupts
-#
-
-        ldil      L%CPU_PSW_DEFAULT, arg0
-        ldo       R%CPU_PSW_DEFAULT(arg0), arg0
-        mtctl     arg0, ipsw
-
-# Now jump to "rest_of_isr_handler" with the rfi
-# We are assuming the space queues are all correct already
-
-	ldil 	  L%rest_of_isr_handler, arg0
-	ldo	  R%rest_of_isr_handler(arg0), arg0
-	mtctl	  arg0, pcoq
-	ldo	  4(arg0), arg0
-	mtctl	  arg0, pcoq
-
-        rfi
-	nop
-
-# At this point we are back in virtual mode and all our
-#  normal addressing is once again ok.
-
-rest_of_isr_handler:
-
 #
 # Build an interrupt frame to hold the contexts we will need.
 # We have already saved the interrupt items on the stack
@@ -281,7 +248,7 @@ rest_of_isr_handler:
         stw         %r6,R6_OFFSET(sp)
         stw         %r7,R7_OFFSET(sp)
         stw         %r8,R8_OFFSET(sp)
-        stw         %r9,R9_OFFSET(sp)
+# skip r9
         stw         %r10,R10_OFFSET(sp)
         stw         %r11,R11_OFFSET(sp)
         stw         %r12,R12_OFFSET(sp)
@@ -298,7 +265,7 @@ rest_of_isr_handler:
         stw         %r23,R23_OFFSET(sp)
         stw         %r24,R24_OFFSET(sp)
         stw         %r25,R25_OFFSET(sp)
-        stw         %r26,R26_OFFSET(sp)
+# skip arg0
         stw         %r27,R27_OFFSET(sp)
         stw         %r28,R28_OFFSET(sp)
         stw         %r29,R29_OFFSET(sp)
@@ -324,7 +291,33 @@ rest_of_isr_handler:
 #
 # At this point we are done with isr_arg0, and isr_r9 control registers
 #
+# Prepare to re-enter virtual mode
+# We need Q in case the interrupt handler enables interrupts
+#
+
+        ldil      L%CPU_PSW_DEFAULT, arg0
+        ldo       R%CPU_PSW_DEFAULT(arg0), arg0
+        mtctl     arg0, ipsw
+
+# Now jump to "rest_of_isr_handler" with the rfi
+# We are assuming the space queues are all correct already
+
+	ldil 	  L%rest_of_isr_handler, arg0
+	ldo	  R%rest_of_isr_handler(arg0), arg0
+	mtctl	  arg0, pcoq
+	ldo	  4(arg0), arg0
+	mtctl	  arg0, pcoq
+
+        rfi
+	nop
+
+# At this point we are back in virtual mode and all our
+#  normal addressing is once again ok.
+#
+#  It is now ok to take an exception or trap
+#
 
+rest_of_isr_handler:
 
 # Point to beginning of float context and
 # save the floating point context -- doing whatever patches are necessary
@@ -408,7 +401,7 @@ post_user_interrupt_handler:
 # have turned them on) and return to the interrupted task stack (assuming
 # (_ISR_Nest_level == 0)
 
-        rsm        HPPA_PSW_I, %r0
+        rsm        HPPA_PSW_I + HPPA_PSW_R, %r0
         ldw        -4(sp), sp
 
 #    r3  -- &_ISR_Nest_level
@@ -448,6 +441,7 @@ post_user_interrupt_handler:
 	ldw	   R%_ISR_Signals_to_thread_executing(%r8),%r8
 	comibt,=,n 0,%r8,isr_restore
 
+
 # OK, something happened while in ISR and we need to switch to a task
 # other than the one which was interrupted or the
 #    ISR_Signals_to_thread_executing case
@@ -465,10 +459,11 @@ ISR_dispatch:
 
         ldo        -128(sp),sp
 
-        rsm        HPPA_PSW_I, %r0
-
 isr_restore:
 
+# enable interrupts during most of restore
+        ssm        HPPA_PSW_I, %r0
+
 # Get a pointer to beginning of our stack frame
         ldo        -CPU_INTERRUPT_FRAME_SIZE(sp), %arg1
 
@@ -489,21 +484,6 @@ isr_restore:
 	.EXPORT _CPU_Context_restore
 _CPU_Context_restore:
 
-# Turn off Q & I so we can write pcoq
-        rsm        HPPA_PSW_Q + HPPA_PSW_I, %r0
-
-        ldw        IPSW_OFFSET(arg0), %r8
-        mtctl      %r8, ipsw
-
-        ldw        SAR_OFFSET(arg0), %r9
-        mtctl      %r9, sar
-
-        ldw        PCOQFRONT_OFFSET(arg0), %r10
-        mtctl      %r10, pcoq
-
-        ldw        PCOQBACK_OFFSET(arg0), %r11
-        mtctl      %r11, pcoq
-
 #
 # restore integer state
 #
@@ -531,15 +511,32 @@ _CPU_Context_restore:
         ldw         R22_OFFSET(arg0),%r22
         ldw         R23_OFFSET(arg0),%r23
         ldw         R24_OFFSET(arg0),%r24
-        ldw         R25_OFFSET(arg0),%r25
-# skipping r26 (aka arg0) until we are done with it
+# skipping r25; used as scratch register below
+# skipping r26 (arg0) until we are done with it
         ldw         R27_OFFSET(arg0),%r27
         ldw         R28_OFFSET(arg0),%r28
         ldw         R29_OFFSET(arg0),%r29
         ldw         R30_OFFSET(arg0),%r30
         ldw         R31_OFFSET(arg0),%r31
 
-# Must load r26 last since it is arg0
+# Turn off Q & R & I so we can write interrupt control registers
+        rsm        HPPA_PSW_Q + HPPA_PSW_R + HPPA_PSW_I, %r0
+
+        ldw        IPSW_OFFSET(arg0), %r25
+        mtctl      %r25, ipsw
+
+        ldw        SAR_OFFSET(arg0), %r25
+        mtctl      %r25, sar
+
+        ldw        PCOQFRONT_OFFSET(arg0), %r25
+        mtctl      %r25, pcoq
+
+        ldw        PCOQBACK_OFFSET(arg0), %r25
+        mtctl      %r25, pcoq
+
+# Load r25 with interrupts off
+        ldw         R25_OFFSET(arg0),%r25
+# Must load r26 (arg0) last
         ldw         R26_OFFSET(arg0),%r26
 
 isr_exit:
diff --git a/c/src/exec/score/cpu/hppa1.1/hppa.h b/c/src/exec/score/cpu/hppa1.1/hppa.h
index f8bb55c74c..55c2a63aee 100644
--- a/c/src/exec/score/cpu/hppa1.1/hppa.h
+++ b/c/src/exec/score/cpu/hppa1.1/hppa.h
@@ -1,6 +1,6 @@
 /*
- *	@(#)hppa.h	1.13 - 95/09/21
- *	
+ * @(#)hppa.h	1.17 - 95/12/13
+ * 
  *
  *  Description:
  *		
@@ -209,6 +209,7 @@ extern "C" {
 
 #define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER         HPPA_INTERRUPT_EXTERNAL_0
 #define HPPA_EXTERNAL_INTERRUPTS                       32
+#define HPPA_INTERNAL_INTERRUPTS                       32
 
 /* BSP defined interrupts begin here */
 
@@ -646,7 +647,11 @@ extern "C" {
 #define HPPA_BREAK(i5,i13)      (((i5) & 0x1F) | (((i13) & 0x1FFF) << 13))
 
 
-#ifndef ASM
+/*
+ * this won't work in ASM or non-GNU compilers
+ */
+
+#if !defined(ASM) && defined(__GNUC__)
 
 /*
  * static inline utility functions to get at control registers
@@ -699,21 +704,15 @@ EMIT_CONTROLS(tr5, HPPA_TR5);                /* CR29 */
 EMIT_CONTROLS(tr6, HPPA_TR6);                /* CR30 */
 EMIT_CONTROLS(tr7, HPPA_CR31);               /* CR31 */
 
+#endif /* ASM and GNU */
+
 /*
  * If and How to invoke the debugger (a ROM debugger generally)
  */
-
-#ifdef SIMHPPA_ROM
-/* invoke the pflow debugger */
-#define CPU_INVOKE_DEBUGGER  \
+#define CPU_INVOKE_DEBUGGER \
     do { \
-        extern void debugger_break(void); \
-        debugger_break(); \
+        HPPA_ASM_BREAK(1,1); \
     } while (0)
-#endif
-
-
-#endif /* ASM */
 
 #ifdef __cplusplus
 }
diff --git a/c/src/exec/score/cpu/unix/cpu.c b/c/src/exec/score/cpu/unix/cpu.c
index c77276020b..de3e6a7118 100644
--- a/c/src/exec/score/cpu/unix/cpu.c
+++ b/c/src/exec/score/cpu/unix/cpu.c
@@ -87,7 +87,7 @@ void _CPU_ISR_From_CPU_Init()
    */
 
   sigemptyset(&posix_empty_mask);
- 
+
   /*
    * Block all the signals except SIGTRAP for the debugger
    * and SIGABRT for fatal errors.
@@ -602,7 +602,6 @@ void _CPU_ISR_Handler(int vector)
   extern unsigned32  _Thread_Dispatch_disable_level;
   extern boolean     _Context_Switch_necessary;
 
-
   if (_ISR_Nest_level++ == 0) {
       /* switch to interrupt stack */
   }
@@ -635,19 +634,34 @@ void _CPU_ISR_Handler(int vector)
 
 void _CPU_Stray_signal(int sig_num)
 {
-  char buffer[ 4 ];   
-
-  /* 
-   *  We avoid using the stdio section of the library.
-   *  The following is generally safe.
+  char buffer[ 4 ];
+ 
+  /*
+   * print "stray" msg about ones which that might mean something
+   * Avoid using the stdio section of the library.
+   * The following is generally safe.
    */
-
-  buffer[ 0 ] = (sig_num >> 4) + 0x30;
-  buffer[ 1 ] = (sig_num & 0xf) + 0x30;
-  buffer[ 2 ] = '\n';
-
-  write( 2, "Stray signal 0x", 12 );
-  write( 2, buffer, 3 );
+ 
+  switch (sig_num)
+  {
+      case SIGCLD:
+          break;
+ 
+      default:
+      {
+          /*
+           *  We avoid using the stdio section of the library.
+           *  The following is generally safe.
+           */
+ 
+          buffer[ 0 ] = (sig_num >> 4) + 0x30;
+          buffer[ 1 ] = (sig_num & 0xf) + 0x30;
+          buffer[ 2 ] = '\n';
+ 
+          write( 2, "Stray signal 0x", 12 );
+          write( 2, buffer, 3 );
+      }
+  }
  
   /*
    * If it was a "fatal" signal, then exit here
diff --git a/c/src/exec/score/cpu/unix/cpu.h b/c/src/exec/score/cpu/unix/cpu.h
index e002a73f65..df582ab44b 100644
--- a/c/src/exec/score/cpu/unix/cpu.h
+++ b/c/src/exec/score/cpu/unix/cpu.h
@@ -278,7 +278,11 @@ extern "C" {
  *         in the executive to justify turning this on.
  */
 
+#ifdef __GNUC__
 #define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))
+#else
+#define CPU_STRUCTURE_ALIGNMENT
+#endif
 
 /*
  *  The following defines the number of bits actually used in the
diff --git a/c/src/exec/score/cpu/unix/unixtypes.h b/c/src/exec/score/cpu/unix/unixtypes.h
index f1dc442baa..45f5cf9366 100644
--- a/c/src/exec/score/cpu/unix/unixtypes.h
+++ b/c/src/exec/score/cpu/unix/unixtypes.h
@@ -24,20 +24,34 @@ extern "C" {
 #endif
 
 /*
+ * some C++ compilers (eg: HP's) don't do 'signed' or 'volatile'
+ */
+#if defined(__cplusplus) && !defined(__GNUC__)
+#define signed
+#define volatile
+#endif
+
+/*
  *  This section defines the basic types for this processor.
  */
 
 typedef unsigned char  unsigned8;      /* unsigned 8-bit  integer */
 typedef unsigned short unsigned16;     /* unsigned 16-bit integer */
 typedef unsigned int   unsigned32;     /* unsigned 32-bit integer */
-typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
 
 typedef unsigned16     Priority_Bit_map_control;
 
 typedef signed char      signed8;      /* 8-bit  signed integer */
 typedef signed short     signed16;     /* 16-bit signed integer */
 typedef signed int       signed32;     /* 32-bit signed integer */
+
+/*
+ * some C++ compilers (eg: HP's) don't do 'long long'
+ */
+#if defined(__GNUC__)
+typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
 typedef signed long long signed64;     /* 64 bit signed integer */
+#endif
 
 typedef unsigned32 boolean;     /* Boolean value   */
 
diff --git a/c/src/exec/score/headers/system.h b/c/src/exec/score/headers/system.h
index 22ae606342..9b50159c81 100644
--- a/c/src/exec/score/headers/system.h
+++ b/c/src/exec/score/headers/system.h
@@ -56,14 +56,15 @@ extern "C" {
  */
 
 #ifdef USE_INLINES
-#define STATIC static
-#define INLINE __inline__
+# define STATIC static
+# ifdef __GNUC__
+#  define INLINE __inline__
+# else
+#  define INLINE inline
+# endif
 #else
-/*
-#error Only the GNU C compiler is currently supported!!!
-*/
-#define STATIC
-#define INLINE
+# define STATIC
+# define INLINE
 #endif
 
 /*
diff --git a/c/src/exec/score/include/rtems/system.h b/c/src/exec/score/include/rtems/system.h
index 22ae606342..9b50159c81 100644
--- a/c/src/exec/score/include/rtems/system.h
+++ b/c/src/exec/score/include/rtems/system.h
@@ -56,14 +56,15 @@ extern "C" {
  */
 
 #ifdef USE_INLINES
-#define STATIC static
-#define INLINE __inline__
+# define STATIC static
+# ifdef __GNUC__
+#  define INLINE __inline__
+# else
+#  define INLINE inline
+# endif
 #else
-/*
-#error Only the GNU C compiler is currently supported!!!
-*/
-#define STATIC
-#define INLINE
+# define STATIC
+# define INLINE
 #endif
 
 /*
diff --git a/c/src/exec/score/inline/address.inl b/c/src/exec/score/inline/address.inl
index dd2a789b1e..c1bb098577 100644
--- a/c/src/exec/score/inline/address.inl
+++ b/c/src/exec/score/inline/address.inl
@@ -58,7 +58,7 @@ STATIC INLINE unsigned32 _Addresses_Subtract (
   void *right
 )
 {
-  return (left - right);
+  return ((char *) left - (char *) right);
 }
 
 /*PAGE
diff --git a/c/src/exec/score/inline/coremsg.inl b/c/src/exec/score/inline/coremsg.inl
index 6431979dd3..5a1b5d4a10 100644
--- a/c/src/exec/score/inline/coremsg.inl
+++ b/c/src/exec/score/inline/coremsg.inl
@@ -17,6 +17,8 @@
 #ifndef __CORE_MESSAGE_QUEUE_inl
 #define __CORE_MESSAGE_QUEUE_inl
 
+#include <string.h>   /* needed for memcpy */
+ 
 /*PAGE
  *
  *  _CORE_message_queue_Send
diff --git a/c/src/exec/score/inline/rtems/score/address.inl b/c/src/exec/score/inline/rtems/score/address.inl
index dd2a789b1e..c1bb098577 100644
--- a/c/src/exec/score/inline/rtems/score/address.inl
+++ b/c/src/exec/score/inline/rtems/score/address.inl
@@ -58,7 +58,7 @@ STATIC INLINE unsigned32 _Addresses_Subtract (
   void *right
 )
 {
-  return (left - right);
+  return ((char *) left - (char *) right);
 }
 
 /*PAGE
diff --git a/c/src/exec/score/inline/rtems/score/coremsg.inl b/c/src/exec/score/inline/rtems/score/coremsg.inl
index 6431979dd3..5a1b5d4a10 100644
--- a/c/src/exec/score/inline/rtems/score/coremsg.inl
+++ b/c/src/exec/score/inline/rtems/score/coremsg.inl
@@ -17,6 +17,8 @@
 #ifndef __CORE_MESSAGE_QUEUE_inl
 #define __CORE_MESSAGE_QUEUE_inl
 
+#include <string.h>   /* needed for memcpy */
+ 
 /*PAGE
  *
  *  _CORE_message_queue_Send
diff --git a/c/src/exec/score/inline/rtems/score/thread.inl b/c/src/exec/score/inline/rtems/score/thread.inl
index e326410112..3a96acf4ea 100644
--- a/c/src/exec/score/inline/rtems/score/thread.inl
+++ b/c/src/exec/score/inline/rtems/score/thread.inl
@@ -241,30 +241,36 @@ STATIC INLINE Thread_Control *_Thread_Get (
 {
   Objects_Classes      the_class;
   Objects_Information *information;
+  Thread_Control      *tp = (Thread_Control *) 0;
  
   if ( _Objects_Are_ids_equal( id, OBJECTS_ID_OF_SELF ) ) {
     _Thread_Disable_dispatch();
     *location = OBJECTS_LOCAL;
-    return( _Thread_Executing );
+    tp = _Thread_Executing;
+    goto done;
   }
  
   the_class = _Objects_Get_class( id );
  
   if ( the_class > OBJECTS_CLASSES_LAST ) {
     *location = OBJECTS_ERROR;
-    return (Thread_Control *) 0;
+    goto done;
   }
  
   information = _Objects_Information_table[ the_class ];
  
   if ( !information || !information->is_thread ) {
     *location = OBJECTS_ERROR;
-    return (Thread_Control *) 0;
+    goto done;
   }
  
-  return (Thread_Control *) _Objects_Get( information, id, location );
+  tp = (Thread_Control *) _Objects_Get( information, id, location );
+ 
+done:
+  return tp;
 }
 
+
 /*
  *  _Thread_Is_proxy_blocking
  *
diff --git a/c/src/exec/score/inline/thread.inl b/c/src/exec/score/inline/thread.inl
index e326410112..3a96acf4ea 100644
--- a/c/src/exec/score/inline/thread.inl
+++ b/c/src/exec/score/inline/thread.inl
@@ -241,30 +241,36 @@ STATIC INLINE Thread_Control *_Thread_Get (
 {
   Objects_Classes      the_class;
   Objects_Information *information;
+  Thread_Control      *tp = (Thread_Control *) 0;
  
   if ( _Objects_Are_ids_equal( id, OBJECTS_ID_OF_SELF ) ) {
     _Thread_Disable_dispatch();
     *location = OBJECTS_LOCAL;
-    return( _Thread_Executing );
+    tp = _Thread_Executing;
+    goto done;
   }
  
   the_class = _Objects_Get_class( id );
  
   if ( the_class > OBJECTS_CLASSES_LAST ) {
     *location = OBJECTS_ERROR;
-    return (Thread_Control *) 0;
+    goto done;
   }
  
   information = _Objects_Information_table[ the_class ];
  
   if ( !information || !information->is_thread ) {
     *location = OBJECTS_ERROR;
-    return (Thread_Control *) 0;
+    goto done;
   }
  
-  return (Thread_Control *) _Objects_Get( information, id, location );
+  tp = (Thread_Control *) _Objects_Get( information, id, location );
+ 
+done:
+  return tp;
 }
 
+
 /*
  *  _Thread_Is_proxy_blocking
  *