diff options
| author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2002-07-22 09:46:48 +0000 |
|---|---|---|
| committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2002-07-22 09:46:48 +0000 |
| commit | 2b3e9d9b244e279ef5693a7cf5dacc7903164af5 (patch) | |
| tree | 955e5242d4d08a8ec747c8350f55003bb9d4b519 /c/src/exec/score | |
| parent | Remove everything. (diff) | |
| download | rtems-2b3e9d9b244e279ef5693a7cf5dacc7903164af5.tar.bz2 | |
Remove, moved to cpukit.
Diffstat (limited to '')
433 files changed, 0 insertions, 70077 deletions
diff --git a/c/src/exec/score/.cvsignore b/c/src/exec/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/ChangeLog b/c/src/exec/score/ChangeLog deleted file mode 100644 index 7f7a5a1086..0000000000 --- a/c/src/exec/score/ChangeLog +++ /dev/null @@ -1,443 +0,0 @@ -2002-07-19 Joel Sherrill <joel@OARcorp.com> - - * include/rtems/score/apimutex.h (_API_Mutex_Lock): Added missing - _ISR_Disable. - -2002-07-16 Joel Sherrill <joel@OARcorp.com> - - * macros/rtems/score/object.inl: Corrected typos in - _Objects_Open, _Objects_Close, and _Objects_Namespace_remove. - -2002-07-05 Joel Sherrill <joel@OARcorp.com> - - * macros/rtems/score/object.inl: Corrected implementation of - _Objects_Open, _Objects_Close, and _Objects_Namespace_remove - to be consistent with the inline implementation. - -2002-07-01 Joel Sherrill <joel@OARcorp.com> - - * Mega patch merge to change the format of the object IDs to - loosen the dependency between the SCORE and the various APIs. - There was considerable work to simplify the object name management - and it appears that the name_table field is no longer needed. - This patch also includes the addition of the internal mutex - which is currently only used to protect some types of allocation - and deallocation. This significantly can reduce context - switch latency under certain circumstances. In particular, - some heap/region operations were O(n) and had dispatching - disabled. This should help enormously. With this merge, - the patch is not as clean as it should be. In particular, - the documentation has not been modified to reflect the new object - ID layout, the IDs in the test screens are not updated, and - _Objects_Get_information needs to be a real routine not inlined. - As part of this patch a lot of MP code for thread/proxy blocking - was made conditional and cleaned up. - * include/Makefile.am, include/rtems/score/coremsg.h, - include/rtems/score/coremutex.h, include/rtems/score/coresem.h, - include/rtems/score/object.h, include/rtems/score/threadq.h, - inline/rtems/score/object.inl, inline/rtems/score/thread.inl, - macros/rtems/score/object.inl, src/Makefile.am, src/coremsg.c, - src/coremutex.c, src/coresem.c, src/mpci.c, - src/objectcomparenameraw.c, src/objectextendinformation.c, - src/objectinitializeinformation.c, src/objectnametoid.c, - src/thread.c, src/threadclose.c, src/threadget.c, src/threadq.c, - src/threadqextractwithproxy.c: Modified as part of above. - * include/rtems/score/apimutex.h, src/objectgetnoprotection.c: New - files. - -2001-05-17 Joel Sherrill <joel@OARcorp.com> - - * macros/rtems/score/thread..inl: Implemented missing routines - for new libc reentrancy support. - -2002-05-15 Chris Johns <ccj@acm.org> - - * include/rtems/score/thread.h, inline/rtems/score/thread.inl, - src/threaddispatch.c, src/threadinitialize.c: - Move the C library re-enterrant support directly into - the thread dispatch code. RTEMS needs libc and so requiring - libc to use a user extension with its overhead is not the best - solution. This patch lowers the overhead to 2 pointer moves. - -2002-05-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * include/Makefile.am: Work-around to autoconf-2.53 adding PACKAGE_* - to autoheaders - sed out *PACKAGE* from cpuopts-tmp.h. - -2001-05-14 Till Straumann <strauman@slac.stanford.edu> - - * src/threaddispatch.c, src/threadhandler.c: Per PR211 fix - saving/restoring floating point context. The fpsave and fprestore - routines are only used in a executing context which _is_ fp and hence - has the FPU enabled. The current behavior required the FPU always to - be on which is very dangerous if lazy context switching is used. - [Joel Note: Some ports explicitly enabled the FPU in the FP save and - restore routines to avoid this.] - - The patch also makes sure (on powerpc only) that the FPU is disabled - for integer tasks. Note that this is crucial if deferred fp context - switching is used. Otherwise, fp context corruption may go undetected! - Also note that even tasks which merely push/pop FP registers to/from - the stack without modifying them still MUST be FP tasks - otherwise - (if lazy FP context switching is used), FP register corruption (of - other, FP, tasks may occur)! - - Furthermore, (on PPC) by default, lazy FP context save/restore - is _disabled_. - -2001-04-26 Joel Sherrill <joel@OARcorp.com> - - * src/objectcomparenamestring.c: Fix typos. - -2001-04-26 Joel Sherrill <joel@OARcorp.com> - - * include/rtems/score/object.h, inline/rtems/score/object.inl, - src/objectcomparenamestring.c: Address PR81 that - reworked POSIX message queues to add a descriptor separate from - the underlying message queue. This allows non-blocking to follow - the "open" not the underlying queue. As part of debugging this - it became clear that _Objects_Compare_name_string was broken - and a simple version using strncmp() was substituted. - -2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * include/rtems/system.h: Remove targopts.h. - -2002-04-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * include/rtems/system.h: Add the sparc to the target supporting - multlibs. - -2002-04-16 Chris Johns <ccj@acm.org> - - * src/threadinitialize.c: Per PR181, clear the array of user extension - pointers. This lets user extensions that have hooked the switch handler - know if a task has been processed by the user extension before. If a - user extension is created after a task is started it may not know it. - -2002-04-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * include/rtems/system.h: Add i386 to multilib-able targets. - -2001-04-11 Joel Sherrill <joel@OARcorp.com> - - - * macros/rtems/score/userext.inl: Now works after merging patch for - functionality requested in PR174. - * inline/rtems/score/userext.inl: Added a comment explaining the - order in which routines appear since it is not the obvious order. - -2002-04-08 Chris Johns <ccj@acm.org> - - * Per PR141 and PR174, make task switch extension its own list and - fix all odd problems introduced by providing macro version. - * inline/rtems/score/userext.inl: Fix. - -2001-04-08 Joel Sherrill <joel@OARcorp.com> - - * macros/rtems/score/object.inl: Corrected arguments. - -2001-04-08 Joel Sherrill <joel@OARcorp.com> - - * macros/rtems/score/userext.inl: Updated to reflect modifications - to inline version from PR142. - * inline/rtems/score/userext.inl: Cleanup as side-effect of above. - -2002-04-08 Chris Johns <ccj@acm.org> - - * Per PR142, make task switch extension its own list. - * include/rtems/score/userext.h: Reflect above by adding - User_extensions_Switch_control and adding it to User_extenions_Control. - * inline/rtems/score/userext.inl: Allocate all memory in one chunk - to minimize overhead. Address processing dedicated switch chain. - -2002-04-08 Chris Johns <ccj@acm.org> - - * Per PR142, make task switch extension its own list. - * include/rtems/score/userext.h: Reflect above by adding - User_extensions_Switch_control and adding it to User_extenions_Control. - * inline/rtems/score/userext.inl: Allocate all memory in one chunk - to minimize overhead. Address processing dedicated switch chain. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * cpu/Makefile.am: Remove AUTOMAKE_OPTIONS. - * src/Makefile.am: Remove AUTOMAKE_OPTIONS. - * Makefile.am: Remove AUTOMAKE_OPTIONS. - * include/Makefile.am: Remove AUTOMAKE_OPTIONS. - * inline/Makefile.am: Remove AUTOMAKE_OPTIONS. - * macros/Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Joel Sherrill <joel@OARcorp.com> - - * include/rtems/score/watchdog.h: Added WATCHDOG_MAXIMUM_INTERVAL. - -2002-01-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * include/rtems/system.h: Fix typo in yesterday's change: - RTEMS_MULTILIBS. - -2001-01-18 Joel Sherrill <joel@OARcorp.com> - - * include/rtems/system.h: Only include cpuopts.h when building a - multilib configuration. Some ports still need targopts.h but this - small modification lets those ports work non-multilib while - fixing being fixed for multilib. - -2002-01-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * include/rtems/seterr.h: Add do {..} while (0) in defines. - Rename set_errno_and_return_minus_one into - rtems_set_errno_and_return_minus_one. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * inline/rtems/score/object.inl, macros/rtems/score/object.inl: Add - add casts to Objects_Id in _Objects_Build_ids to avoid implicit - typecasts from enum to int16 on bit16 targets (here: h8300). - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * src/Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * include/rtems/score/isr.h, inline/rtems/score/isr.inl, - macros/rtems/score/isr.inl: Modified to allow any port to provide - its own implementation of the macro _ISR_Is_in_progress. If the - port overrides this macro, it must provide a non-inlined function - implementation. - -2001-11-20 Joel Sherrill <joel@OARcorp.com> - - * src/threadhandler.c: When __USE__MAIN__ is defined by the toolset, - invoke the global constructors via __main. Reported as tested by - Alexandra Kossovsky <sasha@oktet.ru> and Victor V. Vengerov - <vvv@oktet.ru> in conjunction with a new set of tool RPMs - (gcc2.95.3newlib1.9.0-3). This was tracked as GNATS PR tools/84. - -2001-11-07 Joel Sherrill <joel@OARcorp.com> - - Reported by Todor.Todorov@barco.com and tracked as PR36. - * include/rtems/score/object.h: Added prototype for - _Objects_Get_by_index(). - * src/objectget.c, src/objectgetisr.c: Corrected procedure for - getting index from Id so it is correct and optimal for both single - and multiprocessor configurations. - -2001-10-22 Joel Sherrill <joel@OARcorp.com> - - * src/threadhandler.c: Use __USE_INIT_FINI__ since USE_INIT_FINI - pollutes the application namespace. - -2001-10-16 Joel Sherrill <joel@OARcorp.com> - - * .cvsignore: Add stamp-h.in. - -2001-10-16 Joel Sherrill <joel@OARcorp.com> - - * include/Makefile.am: Fixed path to cpuopts-tmp.h. - -2001-10-16 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * include/rtems/Makefile.am: Remove. - * include/rtems/Makefile.am: Remove. - * include/Makefile.am: Handle subdirs, require automake-1.5. - * macros/rtems/Makefile.am: Remove. - * macros/rtems/score/Makefile.am: Remove. - * macros/Makefile.am: Handle subdirs, require automake-1.5. - * inline/rtems/Makefile.am: Remove. - * inline/rtems/score/Makefile.am: Remove. - * inline/Makefile.am: Handle subdirs, require automake-1.5. - * Makefile.am: require automake-1.5 - -2001-09-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * include/rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * include/rtems/Makefile.am: Use 'PREINSTALL_FILES ='. - * inline/rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * macros/rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-09-27 Eric Norum <eric.norum@usask.ca> - - * src/threadhandler.c: Now process C++ global constructors - (_init) as part of the first task execution not in BSP space. - This depends on the toolset defining USE_INIT_FINI so you - have to have the right toolset version. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * include/rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * include/rtems/Makefile.am: Use 'PREINSTALL_FILES ='. - * inline/rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * macros/rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-08-30 Joel Sherrill <joel@OARcorp.com> - - * src/coremutex.c, src/coremutexseize.c, src/coremutexsurrender.c, - inline/rtems/score/coremutex.inl: The per thread field resource_count - should only be manipulated when a mutex is priority ceiling or - priority inherit. This was reported by Chris Johns <ccj@acm.org> - who also noticed that the use of switches for all disciplines - generated less efficient code than using explicit tests for the one - or two cases we were really interested in. Further review of his - modifications made it apparent that the "isa" methods to test mutex - discipline were not being used so this modification was swept into - the code as well. - -2001-08-30 Joel Sherrill <joel@OARcorp.com> - - * src/coremutexseize.c: Add missing code for proper handling - of nesting acquisitions. This only impacts building with - inlines disabled on the source with the "fast mutex" optimizations. - This was post the 4.5 branch and did not impact released versions. - -2001-08-16 Joel Sherrill <joel@OARcorp.com> - - * src/coremutexsurrender.c: Use holder thread not executing - thread because even though they may and often are the same - it is not guaranteed unless the proper attribute is set. - -2001-08-16 Joel Sherrill <joel@OARcorp.com> - - * include/rtems/score/coremsg.h, src/coremsgsubmit.c: Add a new - return status to account for blocking sends. Otherwise, the - caller will think that the returned message status will have - the ultimate results of the operation. If the send times out, - the final status will be in the return_code of the thread. - -2001-08-09 Joel Sherrill <joel@OARcorp.com> - - * include/rtems/score/coremsg.h, inline/rtems/score/coremsg.inl, - src/coremsgsubmit.c: Unblocking message queue operations should - NOT use _Thread_Executing for return status since it is permissible - to invoke message send operations from an ISR. This was reported - by Suvrat Gupta <suvrat@utstar.com>. - -2000-05-25 Sergei Organov <osv@javad.ru> - - * macros/rtems/score/coresem.inl, inline/rtems/score/coresem.inl: - Cut and paste problem incorrectly enabled interrupts twice with - the first time being too early. - -2001-05-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * include/rtems/score/.cvsignore: Add stamp-h, cpuopts.h, - cpuopts.h.in, cpuopts-tmp.h. - -2001-02-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * include/rtems/Makefile.am, include/rtems/score/Makefile.am, - inline/rtems/score/Makefile.am, macros/rtems/score/Makefile.am - Apply include_*HEADERS instead of H_FILES. - -2001-01-29 Joel Sherrill <joel@OARcorp.com> - - * src/objectextendinformation.c: Added include of string.h to - eliminate warning. - -2001-01-08 Joel Sherrill <joel@OARcorp.com> - - * src/threadinitialize.c: Fix my bad hack of Ralf's fp_area - warning removal patch. :( - -2001-01-08 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * src/threadinitialize.c: Removed warning. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * src/isr.c: Modify to properly dereference _ISR_Vector_table - now that it is dynamically allocated. - -2000-12-19 Joel Sherrill <joel@OARcorp.com> - - * src/isr.c: Allocate the _ISR_Vector_table all the time not just when - we are allocating an interrupt stack. - -2000-12-13 Joel Sherrill <joel@OARcorp.com> - - * include/rtems/score/isr.h, src/isr.c: Allocate it from the - workspace rather than explicitly declaring it. This allows - the size to be a non-constant from the perspective of score/cpu. - -2000-12-01 Joel Sherrill <joel@OARcorp.com> - - * macros/rtems/score/coresem.inl: Removed comments since convention - calls for comments to be in inline versin. - * macros/rtems/score/object.inl (Objects_Get_local_object): Fixed - style to use _ prefix on variable names and use parentheses. - * macros/rtems/score/object.inl (_Objects_Namespace_remove): Added. - -2000-11-30 Joel Sherrill <joel@OARcorp.com> - - * General effort to make things compile with macros not inlines - * inline/rtems/score/coremutex.inl: Added comment indicating - for macros there is another copy of - _CORE_mutex_Seize_interrupt_trylock() in src/coremutexseize.c. - * src/coremutexseize.c: Added body of - _CORE_mutex_Seize_interrupt_trylock() for macro case. - * macros/rtems/score/coremutex.inl: Added prototype for - _CORE_mutex_Seize_interrupt_trylock() since there is a real - body when macros are enabled. - * macros/rtems/score/coresem.inl: Added macro implementation of - _CORE_semaphore_Seize_isr_disable. - * macros/score/Makefile.am: Fixed typos. - * rtems/score/address.inl: Correct macro implementation of - _Addresses_Is_aligned() so it would compile. - * macros/rtems/score/coremsg.inl: Added closing parentheses. - -2000-11-28 Chris Johns <ccj@acm.org> - - * src/heapallocate.c: Do not allow the size to overflow when - adjusting it. A test allocated a stack of -1 (~0). This - actually resulted in a stack being allocated but with a - size of 0xb. The allocator did not test the size to see if - it rolled through 0 and so allowed the allocation to happen, the - thread to get created. The task crashed as you would expect. - -2000-11-02 Joel Sherrill <joel@OARcorp.com> - - * include/rtems/system.h: Use proper conditional (RTEMS_POSIX_API) - so prototypes for POSIX_MP_NOT_IMPLEMENTED(), POSIX_NOT_IMPLEMENTED(), - POSIX_BOTTOM_REACHED() are actually included. - -2000-11-02 Joel Sherrill <joel@OARcorp.com> - - * include/rtems/system.h: Add prototypes for POSIX_MP_NOT_IMPLEMENTED(), - POSIX_NOT_IMPLEMENTED(), POSIX_BOTTOM_REACHED() removed from newlib. - -2000-10-18 Nick Simon <Nick.SIMON@syntegra.bt.co.uk> - - * src/heapgetinfo.c, include/rtems/score/heap.h, src/Makefile.am: - Added _Heap_Get_information() and information control block. - * src/heapgetinfo.c: New file. - -2000-09-25 Joel Sherrill <joel@OARcorp.com> - - * rtems/system.h: Switched a29k and hppa1.1 to using cpuopts.h not - targopts.h to reduce dependency on BSP. - -2000-09-20 Joel Sherrill <joel@OARcorp.com> - - * src/objectgetbyindex.c: Do not enable dispatching on an - error path it was not disabled on. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * src/Makefile.am: Include compile.am. - -2000-08-30 Joel Sherrill <joel@OARcorp.com> - - * Many files: Moved posix/include/rtems/posix/seterr.h to - score/include/rtems/seterr.h so it would be available within - all APIs. - -2000-08-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * include/rtems/system.h: Include cpuopts.h for __i386__. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/Makefile.am b/c/src/exec/score/Makefile.am deleted file mode 100644 index 96648a10e7..0000000000 --- a/c/src/exec/score/Makefile.am +++ /dev/null @@ -1,9 +0,0 @@ -## -## $Id$ -## - - -SUBDIRS = include inline macros cpu src - -include $(top_srcdir)/automake/subdirs.am -include $(top_srcdir)/automake/local.am diff --git a/c/src/exec/score/cpu/.cvsignore b/c/src/exec/score/cpu/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/Makefile.am b/c/src/exec/score/cpu/Makefile.am deleted file mode 100644 index 3e84557494..0000000000 --- a/c/src/exec/score/cpu/Makefile.am +++ /dev/null @@ -1,13 +0,0 @@ -## -## $Id$ -## - - -SUBDIRS = $(RTEMS_CPU) - -## FIXME: this does not work -## DIST_SUBDIRS = \ -## a29k hppa1.1 i386 i960 m68k mips64orion no_cpu powerpc sh sparc unix - -include $(top_srcdir)/automake/subdirs.am -include $(top_srcdir)/automake/local.am diff --git a/c/src/exec/score/cpu/a29k/.cvsignore b/c/src/exec/score/cpu/a29k/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/a29k/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/a29k/ChangeLog b/c/src/exec/score/cpu/a29k/ChangeLog deleted file mode 100644 index 0b516b2df7..0000000000 --- a/c/src/exec/score/cpu/a29k/ChangeLog +++ /dev/null @@ -1,124 +0,0 @@ -2002-07-05 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Filled in something that was marked XXX. - -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * asm.h: Use cpuopts.h instead of targopts.h. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/a29ktypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-25 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/a29k.h, rtems/score/cpu.h: Switched to using - cpuopts.h not targopts.h to reduce dependency on BSP. - -2000-09-22 Joel Sherrill <joel@OARcorp.com> - - * amd.ah, cpu.c, cpu_asm.S, register.ah, sig.S, rtems/score/cpu.h: - Updated and fixed minor things. Commented out offensive assembly - and made applications link. - -2000-09-22 Joel Sherrill <joel@OARcorp.com> - - * Makefile.am, cpu_asm.S, psmacro.ah, rtems/score/cpu.h: - First attempt to compile with GNU tools. Minor modifications - to compile enough to get to assembler errors. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am, remove duplicate includes. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/a29k/Makefile.am b/c/src/exec/score/cpu/a29k/Makefile.am deleted file mode 100644 index 113d0cd348..0000000000 --- a/c/src/exec/score/cpu/a29k/Makefile.am +++ /dev/null @@ -1,55 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = amd.ah asm.h pswmacro.ah register.ah -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/a29k.h \ - rtems/score/types.h \ - rtems/score/cpu.h \ - rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S sig.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S sig.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/a29k/amd.ah b/c/src/exec/score/cpu/a29k/amd.ah deleted file mode 100644 index 84a749edea..0000000000 --- a/c/src/exec/score/cpu/a29k/amd.ah +++ /dev/null @@ -1,534 +0,0 @@ -#if 0 - -; /* @(#)amd.ah 1.1 96/05/23 08:56:58, TEI */ -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Initialization values for registers after RESET -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; -: /* $Id$ */ -;* File information and includes. - -#endif - .file "amd.ah" - .ident "@(#)amd.ah 1.1 96/05/23 08:56:58, TEI" - - - -; -;* AMD PROCESSOR SPECIFIC VALUES... -; - -; -;* Processor revision levels... -; - -; PRL values: 31-28 27-24 -; Am29000 0 x -; Am29005 1 x -; Am29050 2 x -; Am29035 3 x -; Am29030 4 x -; Am29200 5 x -; Am29205 5 1x -; Am29240 6 0 -; Manx 7 0 -; Cougar 8 0 - - - .equ AM29000_PRL, 0x00 - - .equ AM29005_PRL, 0x10 - - .equ AM29050_PRL, 0x20 - - .equ AM29035_PRL, 0x30 - - .equ AM29030_PRL, 0x40 - - .equ AM29200_PRL, 0x50 - - .equ AM29205_PRL, 0x58 - - .equ AM29240_PRL, 0x60 - - .equ AM29040_PRL, 0x70 - - .equ MANX_PRL, 0x70 - - .equ COUGAR_PRL, 0x80 - -; -;* data structures sizes. -; - .equ CFGINFO_SIZE, 16*4 - - .equ PGMINFO_SIZE, 16*4 - - .equ VARARGS_SPACE, 16*4 - - .equ WINDOWSIZE, 0x80 -; -;* Am29027 Mode registers -; - - .equ Am29027Mode1, 0x0fc00820 - - .equ Am29027Mode2, 0x00001375 - - - -;* Processor Based Equates and Defines - - .equ SIG_SYNC, -1 - - .equ ENABLE, (SM) - - .equ DISABLE, (ENABLE | DI | DA) - - .equ DISABLE_FZ, (FZ | ENABLE | DI | DA) - - .equ CLR_TRAP, (FZ | DA) - - .equ InitOPS, (TD | SM | (3<<IMShift) | DI | DA) - - .equ InitCPS, (TD | SM | (0<<IMShift) | DI | DA) - - .equ InitCPS1, (TD | SM | (0<<IMShift) | DI ) - - .equ CPS_TMR, (SM | (0<<IMShift) | DI) - - .equ CPS_INT0, (TD | SM | (0<<IMShift)) - - .equ CPS_TMRINT0, (SM | (0<<IMShift)) - - .equ InitCFG, 0x0 - - .equ InitRBP, (B0|B1|B2|B3|B4|B5) - - .equ TMC_VALUE, 0xFFFFFF - - .equ TMR_VALUE, (IE | TMC_VALUE) - - - - - - -;* 29205 specific (internal) peripheral initialization constants. - -; Current Processor Status (CPS) Register. -; Old Processor Status Register (OPS). - - .equ DA, 0x00001 - .equ DI, 0x00002 - .equ IMShift,0x2 - .equ SM, 0x00010 - .equ PI, 0x00020 - .equ PD, 0x00040 - .equ WM, 0x00080 - .equ RE, 0x00100 - .equ LK, 0x00200 - .equ FZ, 0x00400 - .equ TU, 0x00800 - .equ TP, 0x01000 - .equ TE, 0x02000 - .equ IP, 0x04000 - .equ CA, 0x08000 - .equ MM, 0x10000 - .equ TD, 0x20000 - -; Configuration Register (CFG) - - .equ CD, 0x01 - .equ CP, 0x02 - .equ BO, 0x04 - .equ RV, 0x08 - .equ VF, 0x10 - .equ DW, 0x20 - .equ CO, 0x40 - .equ EE, 0x80 - .equ IDShift, 8 - .equ CFG_ID, 0x100 - .equ ILShift, 9 - .equ CFG_ILMask, 0x600 - .equ DDShift, 11 - .equ CFG_DD, 0x800 - .equ DLShift, 12 - .equ CFG_DLMask, 0x3000 - .equ PCEShift, 14 - .equ CFG_PCE, 0x4000 - .equ PMBShift, 16 - .equ D16, 0x8000 - .equ TBOShift, 23 - .equ PRLShift, 24 - -; Channel Control Register (CHC) - - .equ CV, 0x1 - .equ NN, 0x2 - .equ TRShift, 2 - .equ TF, 0x400 - .equ PER, 0x800 - .equ LA, 0x1000 - .equ ST, 0x2000 - .equ ML, 0x4000 - .equ LS, 0x8000 - .equ CRShift, 16 - .equ CNTLShift, 24 - .equ CEShift, 31 - .equ WBERShift, 31 - -; Register Bank Protect (RBP) - .equ B0, 0x1 - .equ B1, 0x2 - .equ B2, 0x4 - .equ B3, 0x8 - .equ B4, 0x10 - .equ B5, 0x20 - .equ B6, 0x40 - .equ B7, 0x80 - .equ B8, 0x100 - .equ B9, 0x200 - .equ B10, 0x400 - .equ B11, 0x800 - .equ B12, 0x1000 - .equ B13, 0x2000 - .equ B14, 0x4000 - .equ B15, 0x8000 - -; Timer Counter - - .equ TCVMask, 0xffffff - -; Timer Reload Register - - .equ IE, 0x1000000 - .equ IN, 0x2000000 - .equ OV, 0x4000000 - .equ TRVMAsk, 0xffffff - -; MMU Configuration - - .equ PSShift, 8 - .equ PS0Shift, 8 - .equ PS1Shift, 12 - -; LRU Recommendation (LRU) - .equ LRUMask, 0xff - -; Reason Vector (RSN) - .equ RSNMask, 0xff - -; Region Mapping Address (RMA0 | RMA1) - .equ PBAMask,0xffff - .equ VBAShift, 16 - -; Region Mapping Control (RMC0 | RMC1) - .equ TIDMask, 0xff - .equ RMC_UE, 0x100 - .equ RMC_UW, 0x200 - .equ RMC_UR, 0x400 - .equ RMC_SE, 0x800 - .equ RMC_SW, 0x1000 - .equ RMC_SR, 0x2000 - .equ RMC_VE, 0x4000 - .equ RMC_IO, 0x10000 - .equ RGSShift, 17 - .equ RMC_PGMShift, 22 - -; Instruction breakpoint Control (IBC0 | IBC1) - .equ BPIDMask, 0xff - .equ BTE, 0x100 - .equ BRM, 0x200 - .equ IBC_BSY, 0x400 - .equ BEN, 0x800 - .equ BHO, 0x1000 - -; Cache Data Register (CDR) - .equ CDR_US, 0x1 - .equ P, 0x2 - .equ CDR_V, 0x4 - .equ IATAGShift, 20 - -; Cache Interface Register (CIR) - .equ CPTRShift, 2 - .equ CIR_RW, 0x1000000 - .equ FSELShift, 28 - -; Indirect Pointer A, B, C (IPA, IPB, IPC) - .equ IPShift, 2 - -; ALU Status (ALU) - .equ FCMask, 0x1F - .equ BPShift, 5 - .equ C, 0x80 - .equ Z, 0x100 - .equ N, 0x200 - .equ ALU_V, 0x400 - .equ DF, 0x800 - -; Byte Pointer - .equ BPMask, 0x3 - -; Load/Store Count Remaining (CR) - .equ CRMask, 0xff - -; Floating Point Environment (FPE) - .equ NM, 0x1 - .equ RM, 0x2 - .equ VM, 0x4 - .equ UM, 0x8 - .equ XM, 0x10 - .equ DM, 0x20 - .equ FRMShift, 6 - .equ FF, 0x100 - .equ ACFShift, 9 - -; Integer Environment (INTE) - .equ MO, 0x1 - .equ DO, 0x2 - -; Floating Point Status (FPS) - .equ NS, 0x1 - .equ RS, 0x2 - .equ VS, 0x4 - .equ FPS_US, 0x8 - .equ XS, 0x10 - .equ DS, 0x20 - .equ NT, 0x100 - .equ RT, 0x200 - .equ VT, 0x400 - .equ UT, 0x800 - .equ XT, 0x1000 - .equ DT, 0x2000 - -; Exception Opcode (EXOP) - .equ IOPMask, 0xff - -; TLB Entry Word 0 -; .equ TIDMask, 0xff already defined above - .equ TLB_UE, 0x100 - .equ TLB_UW, 0x200 - .equ TLB_UR, 0x400 - .equ TLB_SE, 0x800 - .equ TLB_SW, 0x1000 - .equ TLB_SR, 0x2000 - .equ TLB_VE, 0x4000 - .equ VTAGShift, 15 - -; TLB Entry Word 1 - .equ TLB_IO, 0x1 - .equ U, 0x2 - .equ TLB_PGMShift, 6 - .equ RPNShift, 10 - -; Am29200 ROM Control bits. - .equ RMCT_DW0Shift, 29 - .equ RMCT_DW1Shift, 21 - .equ RMCT_DW2Shift, 13 - .equ RMCT_DW3Shift, 5 - -; Am29200 DRAM Control bits. - .equ DW3, (1<<18) - .equ DW2, (1<<22) - .equ DW1, (1<<26) - .equ DW0, (1<<30) - - ; Internal peripheral address assignments. - .equ RMCT, 0x80000000 - .equ RMCF, 0x80000004 - .equ DRCT, 0x80000008 - .equ DRCF, 0x8000000C - .equ DRM0, 0x80000010 - .equ DRM1, 0x80000014 - .equ DRM2, 0x80000018 - .equ DRM3, 0x8000001C - .equ PIACT0, 0x80000020 - .equ PIACT1, 0x80000020 - .equ ICT, 0x80000028 - .equ DMCT0, 0x80000030 - .equ DMAD0, 0x80000034 - .ifdef revA - .equ TAD0, 0x80000036 - .equ TCN0, 0x8000003A - .else - .equ TAD0, 0x80000070 ; default - .equ TCN0, 0x8000003C ; default - .endif - .equ DMCN0, 0x80000038 - .equ DMCT1, 0x80000040 - .equ DMAD1, 0x80000044 - .equ DMCN1, 0x80000048 - .equ SPCT, 0x80000080 - .equ SPST, 0x80000084 - .equ SPTH, 0x80000088 - .equ SPRB, 0x8000008C - .equ BAUD, 0x80000090 - .equ PPCT, 0x800000C0 - .equ PPST, 0x800000C1 - .equ PPDT, 0x800000C4 - .equ POCT, 0x800000D0 - .equ PIN, 0x800000D4 - .equ POUT, 0x800000D8 - .equ POEN, 0x800000DC - .equ VCT, 0x800000E0 - .equ TOP, 0x800000E4 - .equ SIDE, 0x800000E8 - .equ VDT, 0x800000EC - - ; Interrupt Controller Register bits. - .equ TXDI, (1<<5) - .equ RXDI, (1<<6) - .equ RXSI, (1<<7) - .equ PPI, (1<<11) - .equ DMA1I, (1<<13) - .equ DMA0I, (1<<14) - .equ IOPIMask, (0xFF<<16) - .equ VDI, (1<<27) - .equ ICT200_I, (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI) - .equ ICT205_I, (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI) - - ; Serial port Initialization bits - .equ NO_PARITY, 0 - - - ; SPST bits - .equ THREShift, 22 - -;* REGISTER Addresses - - .equ ROMCntlRegAddr, 0x80000000 - - .equ ROMCfgRegAddr, 0x80000004 - - .equ DRAMCntlRegAddr, 0x80000008 - - .equ DRAMCfgRegAddr, 0x8000000C - - .equ DRAMMap0RegAddr, 0x80000010 - - .equ DRAMMap1RegAddr, 0x80000014 - - .equ DRAMMap2RegAddr, 0x80000018 - - .equ DRAMMap3RegAddr, 0x8000001C - - .equ PIACntl0RegAddr, 0x80000020 - - .equ PIACntl1RegAddr, 0x80000024 - - .equ INTRCntlRegAddr, 0x80000028 - - .equ DMACntl0RegAddr, 0x80000030 - - .equ DMACntl1RegAddr, 0x80000040 - - .equ SERPortCntlRegAddr, 0x80000080 - - .equ SERPortStatRegAddr, 0x80000084 - - .equ SERPortTHLDRegAddr, 0x80000088 - - .equ SERPortRbufRegAddr, 0x8000008C - - .equ SERPortBaudRegAddr, 0x80000090 - - .equ PARPortCntlRegAddr, 0x800000C0 - - .equ PIOCntlRegAddr, 0x800000D0 - - .equ PIOInpRegAddr, 0x800000D4 - - .equ PIOOutRegAddr, 0x800000D8 - - .equ PIOOutEnaRegAddr, 0x800000DC - - .equ VCTCntlRegAddr, 0x800000E0 - -; -;* Control constants -; - -;* AM29030 Timer related constants. - - .equ TMR_IE, 0x01000000 - - .equ TMR_IN, 0x02000000 - - .equ TMR_OV, 0x04000000 - - .equ TMC_INITCNT, 1613 - -; -;* System initialization values. -; - - .equ __os_version, 0x0001 ; - - .equ STACKSize, 0x8000 ; - - .equ PGMExecMode, 0x0000 ; - - .equ TSTCK_OFST, 28 * 4 - - .equ CSTCK_OFST, 29 * 4 - - .equ TMSTCK_OFST, 30 * 4 - - .equ CMSTCK_OFST, 31 * 4 - - .equ CTXSW_OK, 0xA55A ; ctx switch ok - - .set NV_STARTOFST, 0x20 ; 32 bytes - - .set NV_BAUDOFST, 0x00 ; 00 bytes - - .set reg_cir, 29 - - .set reg_cdr, 30 - - .equ MSG_BUFSIZE, 0x1000 ; serial buffer size - - .equ ILLOPTRAP, 0 - - .equ UATRAP, 1 - - .equ PVTRAP, 5 - - .equ UITLBMISSTRAP, 8 - - .equ UDTLBMISSTRAP, 9 - - .equ TIMERTRAP, 14 - - .equ TRACETRAP, 15 - - .equ XLINXTRAP, 16 - - .equ SERIALTRAP, 17 - - .equ SLOWTMRTRAP, 18 - - .equ PORTTRAP, 19 - - .equ SVSCTRAP, 80 - - .equ SVSCTRAP1, 81 - - .equ V_CACHETRAP, 66 ; - - .equ V_SETSERVICE, 67 ; - - .equ INIT_TIMER, 100 - - .equ DISABLE_TIMER, 101 - - .equ GET_TIMER, 102 - - .equ CLEAR_TIMER, 103 - - .equ V_SPILL, 64 - - .equ V_FILL, 65 - - .equ SIGDFL, 105 diff --git a/c/src/exec/score/cpu/a29k/asm.h b/c/src/exec/score/cpu/a29k/asm.h deleted file mode 100644 index 51e77ec194..0000000000 --- a/c/src/exec/score/cpu/a29k/asm.h +++ /dev/null @@ -1,101 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * !!! THIS FILE DOES NOT APPEAR TO HAVE BEEN USED IN THE 29K PORT !!! - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1989-1997 - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __A29K_ASM_h -#define __A29K_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/asm.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/a29k/configure.ac b/c/src/exec/score/cpu/a29k/configure.ac deleted file mode 100644 index 8139f18a04..0000000000 --- a/c/src/exec/score/cpu/a29k/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-a29k],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/a29k/cpu.c b/c/src/exec/score/cpu/a29k/cpu.c deleted file mode 100644 index 158f680d4e..0000000000 --- a/c/src/exec/score/cpu/a29k/cpu.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * AMD 29K CPU Dependent Source - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/score/cpu/no_cpu/cpu.c: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ -#ifndef lint -static char _sccsid[] = "@(#)cpu.c 10/21/96 1.8\n"; -#endif - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/thread.h> -#include <stdio.h> -#include <stdlib.h> - -void a29k_ISR_Handler(unsigned32 vector); - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch)() /* ignored on this CPU */ -) -{ - unsigned int i; - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; - - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ - - _CPU_Table = *cpu_table; - - for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ ) - { - _ISR_Vector_table[i] = (proc_ptr)NULL; - } -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 cps; - - /* - * This routine returns the current interrupt level. - */ - cps = a29k_getops(); - if (cps & (TD|DI)) - return 1; - else - return 0; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -extern void intr14( void ); -extern void intr18( void ); -extern void intr19( void ); - -/* just to link with GNU tools JRS 09/22/2000 */ -asm (".global V_SPILL, V_FILL" ); -asm (".global V_EPI_OS, V_BSD_OS" ); - -asm (".equ V_SPILL, 64" ); -asm (".equ V_FILL, 65" ); - -asm (".equ V_BSD_OS, 66" ); -asm (".equ V_EPI_OS, 69" ); - -/* end of just to link with GNU tools */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ - switch( vector ) - { -/* where is this code? JRS */ -#if 0 - case 14: - _settrap( vector, intr14 ); - break; - case 18: - _settrap( vector, intr18 ); - break; - case 19: - _settrap( vector, intr19 ); - break; -#endif - - default: - break; - } -} - - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -void _CPU_Thread_Idle_body( void ) -{ - - for( ; ; ) - { - } - /* insert your "halt" instruction here */ ; -} - -void a29k_fatal_error( unsigned32 error ) -{ - printf("\n\nfatal error %d, rebooting!!!\n",error ); - exit(error); -} - - /* - * This discussion ignores a lot of the ugly details in a real - * implementation such as saving enough registers/state to be - * able to do something real. Keep in mind that the goal is - * to invoke a user's ISR handler which is written in C and - * uses a certain set of registers. - * - * Also note that the exact order is to a large extent flexible. - * Hardware will dictate a sequence for a certain subset of - * _ISR_Handler while requirements for setting - */ - - /* - * At entry to "common" _ISR_Handler, the vector number must be - * available. On some CPUs the hardware puts either the vector - * number or the offset into the vector table for this ISR in a - * known place. If the hardware does not give us this information, - * then the assembly portion of RTEMS for this port will contain - * a set of distinct interrupt entry points which somehow place - * the vector number in a known place (which is safe if another - * interrupt nests this one) and branches to _ISR_Handler. - * - */ - -void a29k_ISR_Handler(unsigned32 vector) -{ - _ISR_Nest_level++; - _Thread_Dispatch_disable_level++; - if ( _ISR_Vector_table[ vector ] ) - (*_ISR_Vector_table[ vector ])( vector ); - --_Thread_Dispatch_disable_level; - --_ISR_Nest_level; - if ( !_Thread_Dispatch_disable_level && !_ISR_Nest_level && - (_Context_Switch_necessary || _ISR_Signals_to_thread_executing )) - _Thread_Dispatch(); - return; -} diff --git a/c/src/exec/score/cpu/a29k/cpu_asm.S b/c/src/exec/score/cpu/a29k/cpu_asm.S deleted file mode 100644 index cc35e79ee3..0000000000 --- a/c/src/exec/score/cpu/a29k/cpu_asm.S +++ /dev/null @@ -1,522 +0,0 @@ -;/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s -; * -; * Author: Craig Lebakken <craigl@transition.com> -; * -; * COPYRIGHT (c) 1996 by Transition Networks Inc. -; * -; * To anyone who acknowledges that this file is provided "AS IS" -; * without any express or implied warranty: -; * permission to use, copy, modify, and distribute this file -; * for any purpose is hereby granted without fee, provided that -; * the above copyright notice and this notice appears in all -; * copies, and that the name of Transition Networks not be used in -; * advertising or publicity pertaining to distribution of the -; * software without specific, written prior permission. -; * Transition Networks makes no representations about the suitability -; * of this software for any purpose. -; * -; * -; * This file contains the basic algorithms for all assembly code used -; * in an specific CPU port of RTEMS. These algorithms must be implemented -; * in assembly language -; * -; * NOTE: This is supposed to be a .S or .s file NOT a C file. -; * -; * COPYRIGHT (c) 1989-1999. -; * On-Line Applications Research Corporation (OAR). -; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.OARcorp.com/rtems/license.html. -; * -; * $Id$ -; */ - -;/* -; * This is supposed to be an assembly file. This means that system.h -; * and cpu.h should not be included in a "real" cpu_asm file. An -; * implementation in assembly should include "cpu_asm.h> -; */ - -;#include <cpu_asm.h> -#include <register.ah> -#include <amd.ah> -#include <pswmacro.ah> -; .extern _bsp_exit -; -; push a register onto the struct - .macro spush, sp, reg - store 0, 0, reg, sp ; push register - add sp, sp, 4 ; adjust stack pointer - .endm -; push a register onto the struct - .macro spushsr, sp, reg, sr - mfsr reg, sr - store 0, 0, reg, sp ; push register - add sp, sp, 4 ; adjust stack pointer - .endm -; pop a register from the struct - .macro spop, reg, sp - load 0, 0, reg, sp - add sp,sp,4 - .endm -; pop a special register from the struct - .macro spopsr, sreg, reg, sp - load 0, 0, reg, sp - mtsr sreg, reg - add sp,sp,4 - .endm -; -;/* -; * _CPU_Context_save_fp_context -; * -; * This routine is responsible for saving the FP context -; * at *fp_context_ptr. If the point to load the FP context -; * from is changed then the pointer is modified by this routine. -; * -; * Sometimes a macro implementation of this is in cpu.h which dereferences -; * the ** and a similarly named routine in this file is passed something -; * like a (Context_Control_fp *). The general rule on making this decision -; * is to avoid writing assembly language. -; */ - -;#if 0 -;void _CPU_Context_save_fp( -; void **fp_context_ptr -;) -;{ -;} -;#endif - .global _CPU_Context_save_fp -_CPU_Context_save_fp: - jmpi lr0 - nop - -;/* -; * _CPU_Context_restore_fp_context -; * -; * This routine is responsible for restoring the FP context -; * at *fp_context_ptr. If the point to load the FP context -; * from is changed then the pointer is modified by this routine. -; * -; * Sometimes a macro implementation of this is in cpu.h which dereferences -; * the ** and a similarly named routine in this file is passed something -; * like a (Context_Control_fp *). The general rule on making this decision -; * is to avoid writing assembly language. -; */ - -;#if 0 -;void _CPU_Context_restore_fp( -; void **fp_context_ptr -;) -;{ -;} -;#endif - .global __CPU_Context_restore_fp -__CPU_Context_restore_fp: - jmpi lr0 - nop - -;/* _CPU_Context_switch -; * -; * This routine performs a normal non-FP context switch. -; */ -;#if 0 -;void _CPU_Context_switch( -; Context_Control *run, -; Context_Control *heir -;) -;{ -;} -;#endif - .global __CPU_Context_switch -__CPU_Context_switch: - asneq 106, gr1, gr1 ; syscall - jmpi lr0 ; - nop ; - - - - .global _a29k_context_switch_sup -_a29k_context_switch_sup: -#if 0 - add pcb,lr2,0 - add kt1,lr3,0 ;move heir pointer to safe location - constn it0,SIG_SYNC - spush pcb,it0 - spush pcb,gr1 - spush pcb,rab ;push rab - spushsr pcb,it0,pc0 ;push specials - spushsr pcb,it0,pc1 - add pcb,pcb,1*4 ;space pc2 - spushsr pcb,it0,CHA ;push CHA - spushsr pcb,it0,CHD ;push CHD - spushsr pcb,it0,CHC ;push CHC - add pcb,pcb,1*4 ;space for alu - spushsr pcb,it0,ops ;push OPS - mfsr kt0,cps ;current status - const it1,FZ ;FZ constant - andn it1,kt0,it1 ;clear FZ bit - mtsr cps,it1 ;cps without FZ - add pcb,pcb,1*4 ;space for tav - mtsrim chc,0 ;possible DERR -; - spush pcb,lr1 ;push R-stack - spush pcb,rfb ; support - spush pcb,msp ;push M-stack pnt. -; - add pcb,pcb,3*4 ;space for floating point -; spush pcb,FPStat0 ;floating point -; spush pcb,FPStat1 -; spush pcb,FPStat2 -; - add pcb,pcb,4*4 ;space for IPA..Q -; - mtsrim cr,29-1 - storem 0,0,gr96,pcb ;push gr96-124, optional - add pcb,pcb,29*4 ;space for gr96-124 -; - sub it0,rfb,gr1 ;get bytes in cache - srl it0,it0,2 ;adjust to words - sub it0,it0,1 - spush pcb,it0 - mtsr cr,it0 - storem 0,0,lr0,pcb ;save lr0-rfb -; -context_restore: - add pcb,kt1,0 ;pcb=heir - add pcb,pcb,4 ;space for signal num - spop gr1,pcb ;restore freeze registers - add gr1,gr1,0 ;alu op - add pcb,pcb,9*4 ;move past freeze registers - add pcb,pcb,1*4 ;space for tav - spop lr1,pcb - spop rfb,pcb - spop msp,pcb -; spop FPStat0,pcb -; spop FPStat1,pcb -; spop FPStat2,pcb - add pcb,pcb,3*4 ;space for floating point - add pcb,pcb,4*4 ;space for IPA..Q - mtsrim cr,29-1 - loadm 0,0,gr96,pcb ;pop gr96-gr124 - add pcb,pcb,29*4 ;space for gr96-124 - - spop it1,pcb ;pop locals count - mtsr cr,it1 - loadm 0,0,lr0,pcb ;load locals - - add pcb,kt1,0 ;pcb=heir - mtsr cps,kt0 ;cps with FZ - nop - add pcb,pcb,4 ;space for signal num - spop gr1,pcb ;restore freeze registers - add gr1,gr1,0 ;alu op - spop rab,pcb - spopsr pc0,it1,pcb - spopsr pc1,it1,pcb - add pcb,pcb,4 ;space for pc2 - spopsr CHA,it1,pcb - spopsr CHD,it1,pcb - spopsr CHC,it1,pcb - add pcb,pcb,4 ;space for alu - spopsr ops,it1,pcb - nop - iret -#endif - - -;/* -; * _CPU_Context_restore -; * -; * This routine is generally used only to restart self in an -; * efficient manner. It may simply be a label in _CPU_Context_switch. -; * -; * NOTE: May be unnecessary to reload some registers. -; */ -;#if 0 -;void _CPU_Context_restore( -; Context_Control *new_context -;) -;{ -;} -;#endif - - .global __CPU_Context_restore -__CPU_Context_restore: -#if 0 - asneq 107, gr1, gr1 ; syscall - jmpi lr0 ; - nop ; - - .global _a29k_context_restore_sup -_a29k_context_restore_sup: - add kt1,lr2,0 ;kt1 = restore context - mfsr kt0,cps ;current status - const it1,FZ ;FZ constant - andn it1,kt0,it1 ;clear FZ bit - mtsr cps,it1 ;cps without FZ - jmp context_restore - nop - - .global _a29k_context_save_sup -_a29k_context_save_sup: - add pcb,lr2,0 - constn it0,SIG_SYNC - spush pcb,it0 - spush pcb,gr1 - spush pcb,rab ;push rab - spushsr pcb,it0,pc0 ;push specials - spushsr pcb,it0,pc1 - add pcb,pcb,1*4 ;space pc2 - spushsr pcb,it0,CHA ;push CHA - spushsr pcb,it0,CHD ;push CHD - spushsr pcb,it0,CHC ;push CHC - add pcb,pcb,1*4 ;space for alu - spushsr pcb,it0,ops ;push OPS - mfsr it0,cps ;current status -SaveFZState it1,it2 - add pcb,pcb,1*4 ;space for tav - mtsrim chc,0 ;possible DERR -; - spush pcb,lr1 ;push R-stack - spush pcb,rfb ; support - spush pcb,msp ;push M-stack pnt. -; - spush pcb,FPStat0 ;floating point - spush pcb,FPStat1 - spush pcb,FPStat2 -; - add pcb,pcb,4*4 ;space for IPA..Q -; - mtsrim cr,29-1 - storem 0,0,gr96,pcb ;push gr96-124, optional - add pcb,pcb,29*4 ;space for gr96-124 -; - sub kt0,rfb,gr1 ;get bytes in cache - srl kt0,kt0,2 ;adjust to words - sub kt0,kt0,1 - spush pcb,kt0 ;push number of words - mtsr cr,kt0 - storem 0,0,lr0,pcb ;save lr0-rfb -; - mtsr cps,it0 ;cps with FZ -RestoreFZState it1,it2 - - nop - nop - nop -; - iret -; -#endif - - .global __CPU_Context_save -__CPU_Context_save: -#if 0 - asneq 108, gr1, gr1 ; syscall - jmpi lr0 ; - nop ; -#endif - - -;/* void __ISR_Handler() -; * -; * This routine provides the RTEMS interrupt management. -; * -; */ - -;#if 0 -;void _ISR_Handler() -;{ -; /* -; * This discussion ignores a lot of the ugly details in a real -; * implementation such as saving enough registers/state to be -; * able to do something real. Keep in mind that the goal is -; * to invoke a user's ISR handler which is written in C and -; * uses a certain set of registers. -; * -; * Also note that the exact order is to a large extent flexible. -; * Hardware will dictate a sequence for a certain subset of -; * _ISR_Handler while requirements for setting -; */ - -; /* -; * At entry to "common" _ISR_Handler, the vector number must be -; * available. On some CPUs the hardware puts either the vector -; * number or the offset into the vector table for this ISR in a -; * known place. If the hardware does not give us this information, -; * then the assembly portion of RTEMS for this port will contain -; * a set of distinct interrupt entry points which somehow place -; * the vector number in a known place (which is safe if another -; * interrupt nests this one) and branches to _ISR_Handler. -; * -; * save some or all context on stack -; * may need to save some special interrupt information for exit -; * -; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) -; * if ( _ISR_Nest_level == 0 ) -; * switch to software interrupt stack -; * #endif -; * -; * _ISR_Nest_level++; -; * -; * _Thread_Dispatch_disable_level++; -; * -; * (*_ISR_Vector_table[ vector ])( vector ); -; * -; * --_ISR_Nest_level; -; * -; * if ( _ISR_Nest_level ) -; * goto the label "exit interrupt (simple case)" -; * -; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) -; * restore stack -; * #endif -; * -; * if ( !_Context_Switch_necessary ) -; * goto the label "exit interrupt (simple case)" -; * -; * if ( !_ISR_Signals_to_thread_executing ) -; * goto the label "exit interrupt (simple case)" -; * -; * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch -; * -; * prepare to get out of interrupt -; * return from interrupt (maybe to _ISR_Dispatch) -; * -; * LABEL "exit interrupt (simple case): -; * prepare to get out of interrupt -; * return from interrupt -; */ -;} -;#endif -; .global __ISR_Handler -;__ISR_Handler: -; jmpi lr0 -; nop - - .global _a29k_getops -_a29k_getops: -#if 0 - asneq 113, gr96, gr96 - jmpi lr0 - nop -#endif - - .global _a29k_getops_sup -_a29k_getops_sup: -#if 0 - mfsr gr96, ops ; caller wants ops - iret - nop -#endif - - .global _a29k_disable -_a29k_disable: -#if 0 - asneq 110, gr96, gr96 - jmpi lr0 - nop -#endif - - .global _a29k_disable_sup -_a29k_disable_sup: -#if 0 - mfsr kt0, ops - add gr96, kt0, 0 ; return ops to caller - const kt1, (DI | TD) - consth kt1, (DI | TD) - or kt1, kt0, kt1 - mtsr ops, kt1 - iret - nop -#endif - - .global _a29k_disable_all -_a29k_disable_all: -#if 0 - asneq 112, gr96, gr96 - jmpi lr0 - nop -#endif - - .global _a29k_disable_all_sup -_a29k_disable_all_sup: -#if 0 - mfsr kt0, ops - const kt1, (DI | TD) - consth kt1, (DI | TD) - or kt1, kt0, kt1 - mtsr ops, kt1 - iret - nop -#endif - - .global _a29k_enable_all -_a29k_enable_all: -#if 0 - asneq 111, gr96, gr96 - jmpi lr0 - nop -#endif - - .global _a29k_enable_all_sup -_a29k_enable_all_sup: -#if 0 - mfsr kt0, ops - const kt1, (DI | TD) - consth kt1, (DI | TD) - andn kt1, kt0, kt1 - mtsr ops, kt1 - iret - nop -#endif - - .global _a29k_enable -_a29k_enable: -#if 0 - asneq 109, gr96, gr96 - jmpi lr0 - nop -#endif - - .global _a29k_enable_sup -_a29k_enable_sup: -#if 0 - mfsr kt0, ops - const kt1, (DI | TD) - consth kt1, (DI | TD) - and kt3, lr2, kt1 - andn kt0, kt0, kt1 - or kt1, kt0, kt3 - mtsr ops, kt1 - iret - nop -#endif - - .global _a29k_halt -_a29k_halt: -#if 0 - halt - jmp _a29k_halt - nop -#endif - - .global _a29k_super_mode -_a29k_super_mode: -#if 0 - mfsr gr96, ops - or gr96, gr96, 0x10 - mtsr ops, gr96 - iret - nop -#endif - - .global _a29k_as70 -_a29k_as70: -#if 0 - asneq 70,gr96,gr96 - jmpi lr0 - nop -#endif diff --git a/c/src/exec/score/cpu/a29k/pswmacro.ah b/c/src/exec/score/cpu/a29k/pswmacro.ah deleted file mode 100644 index 12f6dc6abd..0000000000 --- a/c/src/exec/score/cpu/a29k/pswmacro.ah +++ /dev/null @@ -1,442 +0,0 @@ -; /* @(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI */ -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; macros: Do_install and init_TLB -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; /* $Id$ */ - -;* File information and includes. - - .file "macro.ah" - .ident "@(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI" - - - .macro CONST32, RegName, RegValue - const RegName, RegValue - consth RegName, RegValue - .endm - - .macro CONSTX, RegName, RegValue - .if (RegValue) <= 0x0000ffff - const RegName, RegValue - .else - const RegName, RegValue - consth RegName, RegValue - .endif - .endm - - .macro PRODEV, RegName - srl RegName, RegName, 24 - .endm - -; -;* MACRO TO INSTALL VECTOR TABLE ENTRIES -; - -;* Assumes vector table address in v0 - - .macro _setvec, trapnum, trapaddr - mfsr v0, vab ; - const v2, trapnum ; - sll v1, v2, 2 ; - add v1, v1, v0 ; v0 has location of vector tab - - const v2, trapaddr ; - consth v2, trapaddr ; - store 0, 0, v2, v1 ; - nop ; - .endm - - .macro syscall, name - const tav, HIF_@name ; - asneq V_SYSCALL, gr1, gr1 ; - nop ; - nop ; - .endm - - - -;* MACRO TO INSTALL VECTOR TABLE ENTRIES - - .macro Do_Install, V_Number, V_Address - const lr4, V_Address - consth lr4, V_Address - const lr3, V_Number * 4 - consth lr3, V_Number * 4 - call lr0, V_Install - nop - .endm - - .macro Do_InstallX, V_Number, V_Address - const lr4, V_Address - consth lr4, V_Address - const lr3, V_Number * 4 - consth lr3, V_Number * 4 - call lr0, V_InstallX - nop - .endm - - - -; push a register onto the stack - .macro pushreg, reg, sp - sub sp, sp, 4 ; adjust stack pointer - store 0, 0, reg, sp ; push register - .endm - - .macro push, sp, reg - sub sp, sp, 4 - store 0, 0, reg, sp - .endm - -; pop the register from stack - .macro popreg, reg, sp - load 0, 0, reg, sp ; pop register - add sp, sp, 4 ; adjust stack pointer - .endm - .macro pop, reg, sp - load 0, 0, reg, sp - add sp, sp, 4 - .endm - -; push a special register onto stack - .macro pushspcl, spcl, tmpreg, sp - sub sp, sp, 4 ; adjust stack pointer - mfsr tmpreg, spcl ; get spcl reg - store 0, 0, tmpreg, sp ; push onto stack - .endm - - .macro pushsr, sp, reg, sreg - mfsr reg, sreg - sub sp, sp, 4 - store 0, 0, reg, sp - .endm - -; pop a special register from stack - .macro popspcl, spcl, tmpreg, sp - load 0, 0, tmpreg, sp ; pop from stack - add sp, sp, 4 ; adjust stack pointer - mtsr spcl, tmpreg ; set spcl reg - .endm - - .macro popsr, sreg, reg, sp - load 0, 0, reg, sp - add sp, sp, 4 - mtsr sreg, reg - .endm - -; -; save freeze mode registers on memory stack. -; - - .macro SaveFZState, tmp1, tmp2 - - ; save freeze mode registers. - - pushspcl pc0, tmp1, msp - pushspcl pc1, tmp1, msp - pushspcl alu, tmp1, msp - - pushspcl cha, tmp1, msp - pushspcl chd, tmp1, msp - pushspcl chc, tmp1, msp - - pushspcl ops, tmp1, msp - - ; turn freeze off - - const tmp2, FZ - mfsr tmp1, cps - andn tmp1, tmp1, tmp2 - mtsr cps, tmp1 - .endm - -; restore freeze mode registers from memory stack. - - .macro RestoreFZState, tmp1, tmp2 - - ; turn freeze on - - const tmp2, (FZ|DI|DA) - mfsr tmp1, cps - or tmp1, tmp1, tmp2 - mtsr cps, tmp1 - - ; restore freeze mode registers. - - popspcl ops, tmp1, msp - popspcl chc, tmp1, msp - popspcl chd, tmp1, msp - popspcl cha, tmp1, msp - popspcl alu, tmp1, msp - popspcl pc1, tmp1, msp - popspcl pc0, tmp1, msp - .endm - -; -;* -; - .equ WS, 512 ; window size - .equ RALLOC, 4 * 4 ; stack alloc for C - .equ SIGCTX_UM_SIZE, 40 * 4 ; - .equ SIGCTX_RFB, (38) * 4 ; user mode saved - .equ SIGCTX_SM_SIZE, 12 * 4 ; - .equ SIGCTX_SIG, (11)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_GR1, (10)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_RAB, (9)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_PC0, (8)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_PC1, (7)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_PC2, (6)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_CHC, (3)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_OPS, (1)*4 + SIGCTX_UM_SIZE ; - .equ SIGCTX_TAV, (0)*4 + SIGCTX_UM_SIZE ; - - .macro sup_sv - add it2, trapreg, 0 ; transfer signal # - sub msp, msp, 4 ; - store 0, 0, it2, msp ; save signal number - sub msp, msp, 4 ; push gr1 - - store 0, 0, gr1, msp ; - sub msp, msp, 4 ; push rab - store 0, 0, rab, msp ; - const it0, WS ; Window size - - sub rab, rfb, it0 ; set rab = rfb-512 - pushsr msp, it0, PC0 ; save program counter0 - pushsr msp, it0, PC1 ; save program counter1 - pushsr msp, it0, PC2 ; save program counter2 - - pushsr msp, it0, CHA ; save channel address - pushsr msp, it0, CHD ; save channel data - pushsr msp, it0, CHC ; save channel control - pushsr msp, it0, ALU ; save alu - - pushsr msp, it0, OPS ; save ops - sub msp, msp, 4 ; - store 0, 0, tav, msp ; push tav - mtsrim chc, 0 ; no loadm/storem - - mfsr it0, ops ; get ops value - const it1, (TD | DI) ; disable interrupts - consth it1, (TD | DI) ; disable interrupts - or it0, it0, it1 ; set bits - - mtsr ops, it0 ; set new ops - const it0, _sigcode ; signal handler - consth it0, _sigcode ; signal handler - mtsr pc1, it0 ; store pc1 - - add it1, it0, 4 ; next addr - mtsr pc0, it1 ; store pc1 location - iret ; return - nop ; ALIGN - .endm - - .macro sig_return - mfsr it0, cps ; get processor status - const it1, FZ|DA ; Freeze + traps disable - or it0, it0, it1 ; to set FZ+DA - mtsr cps, it0 ; in freeze mode - - load 0, 0, tav, msp ; restore tav - add msp, msp, 4 ; - - popsr OPS,it0, msp ; - popsr ALU,it0, msp ; - popsr CHC,it0, msp ; - popsr CHD,it0, msp ; - - popsr CHA,it0, msp ; - popsr PC2,it0, msp ; - popsr PC1,it0, msp ; - popsr PC0,it0, msp ; - - load 0, 0, rab, msp ; - add msp, msp, 4 ; - load 0, 0, it0, msp ; - add gr1, it0, 0 ; pop rsp - - add msp, msp, 8 ; discount signal # - iret - .endm - - .macro repair_R_stack - add v0, msp, SIGCTX_GR1 ; interrupted gr1 - load 0, 0, v2, v0 ; - add v0, msp, SIGCTX_RFB ; - load 0, 0, v3, v0 ; interupted rfb - - const v1, WS ; - sub v1, v3, v1 ; rfb-512 - cpltu v0, v2, v1 ; test gr1 < rfb-512 - jmpf v0, $1 ; - - add gr1, rab, 0 ; - add v2, v1, 0 ; set LB = rfb-512 -$1: -;* if gr1 < rfb-512 yes LB = rfb-512 signalled during spill -;* if no, LB=gr1 interrupted cache < 126 registers - cpleu v0, v2, rfb ; test LB<=rfb - jmpf v0, $2 ; - nop ; - add v2, rfb, 0 ; -$2: - cpeq v0, v3, rfb ; fill rfb->rfb - jmpt v0, $3 ; if rfb==rfb - const tav, (0x80<<2) ; prepare for fill - or tav, tav, v2 ; - - mtsr IPA, tav ; IPA=LA<<2 - sub tav, v3, gr98 ; cache fill LA->rfb - srl tav, tav, 2 ; convert to words - sub tav, tav, 1 ; - - mtsr cr, tav ; - loadm 0, 0, gr0, v2 ; fill from LA->rfb -$3: - add rfb, v3, 0 ; move rfb upto rfb - sub rab, v1, 0 ; assign rab to rfb-512 - - add v0, msp, SIGCTX_GR1 ; - load 0, 0, v2, v0 ; v0 = interrupted gr1 - add gr1, v2, 0 ; move gr1 upto gr1 - nop ; - .endm - - .macro repair_regs - mtsrim cr, 29 - 1 ; to restore locals - loadm 0, 0, v0, msp ; - add msp, msp, 29*4 ; - popsr Q, tav, msp ; - - popsr IPC, tav, msp ; - popsr IPB, tav, msp ; - popsr IPA, tav, msp ; - pop FPStat3, msp ; floating point regs - - pop FPStat2, msp ; floating point regs - pop FPStat1, msp ; floating point regs - pop FPStat0, msp ; floating point regs - - add msp, msp, 3*4 ; R-stack repaired - .endm - -; -;*HIF related... -; - - - - -; send the message in bufaddr to Montip. - .macro SendMessageToMontip, bufaddr - const lr2, bufaddr -$1: - call lr0, _msg_send - consth lr2, bufaddr - cpeq gr96, gr96, 0 - jmpf gr96, $1 - const lr2, bufaddr - .endm - -; build a HIF_CALL message in bufaddr to send to montip. - .macro BuildHIFCALLMsg, bufaddr, tmp1, tmp2 - const tmp1, bufaddr - consth tmp1, bufaddr - const tmp2, HIF_CALL_MSGCODE - store 0, 0, tmp2, tmp1 ; msg code - add tmp1, tmp1, 4 - const tmp2, HIF_CALL_MSGLEN - store 0, 0, tmp2, tmp1 ; msg len - add tmp1, tmp1, 4 - store 0, 0, gr121, tmp1 ; service number - add tmp1, tmp1, 4 - store 0, 0, lr2, tmp1 ; lr2 - add tmp1, tmp1, 4 - store 0, 0, lr3, tmp1 ; lr3 - add tmp1, tmp1, 4 - store 0, 0, lr4, tmp1 ; lr4 - .endm - -; -;* -;* All the funky AMD style macros go in here...simply for -;* compatility -; -; - .macro IMPORT, symbol - .extern symbol - .endm - - .macro GLOBAL, symbol - .global symbol - .endm - - .macro USESECT, name, type - .sect name, type - .use name - .endm - - .macro SECTION, name, type - .sect name, type - .endm - - .macro FUNC, fname, lineno - .global fname -fname: - .endm - - .macro ENDFUNC, fname, lineno - .endm - -;*************************************LONG - .macro LONG, varname -varname: - .block 4 - .endm - -;*************************************UNSIGNED LONG - .macro ULONG, varname -varname: - .block 4 - .endm - -;*************************************SHORT - .macro SHORT, varname -varname: - .block 2 - .endm - -;*************************************CHAR - .macro CHAR, varname -varname: - .block 1 - .endm - -;*************************************LONGARRAY - .macro LONGARRAY, name, count -name: - .block count*4 - .endm - -;*************************************SHORTARRAY - - .macro SHORTARRAY, name, count -name: - .block count*2 - .endm - -;*************************************CHARARRAY - - .macro CHARARRAY, name, count -name: - .block count - .endm - - -;*************************************VOID_FPTR - - .macro VOID_FPTR, name -name: - .block 4 - .endm diff --git a/c/src/exec/score/cpu/a29k/register.ah b/c/src/exec/score/cpu/a29k/register.ah deleted file mode 100644 index 853e6ef049..0000000000 --- a/c/src/exec/score/cpu/a29k/register.ah +++ /dev/null @@ -1,217 +0,0 @@ -; /* @(#)register.ah 1.1 96/05/23 08:56:57, TEI */ -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; naming of various registers -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; /* $Id$ */ - -;* File information and includes. - - .file "register.ah" - .ident "@(#)register.ah 1.1 96/05/23 08:56:57, TEI\n" - -;* Register Stack pointer and frame pointer registers. - -/* The assembly language is supposed to be Sierra High-C */ -#if 0 - .extern Rrsp, Rfp - - .reg regsp, %%Rrsp - .reg fp, %%Rfp - - - .extern RTrapReg - .extern Rtrapreg - - .reg TrapReg, %%RTrapReg - .reg trapreg, %%Rtrapreg - - -;* Operating system Interrupt handler registers (gr64-gr67) - - .extern ROSint0, ROSint1, ROSint2, ROSint3 - - .reg OSint0, %%ROSint0 - .reg OSint1, %%ROSint1 - .reg OSint2, %%ROSint2 - .reg OSint3, %%ROSint3 - - .reg it0, %%ROSint0 - .reg it1, %%ROSint1 - .reg it2, %%ROSint2 - .reg it3, %%ROSint3 - - - -;* Operating system temporary (or scratch) registers (gr68-gr79) - - .extern ROStmp0, ROStmp1, ROStmp2, ROStmp3 - .extern ROStmp4, ROStmp5, ROStmp6, ROStmp7 - .extern ROStmp8, ROStmp9, ROStmp10, ROStmp11 - - .reg OStmp0, %%ROStmp0 - .reg OStmp1, %%ROStmp1 - .reg OStmp2, %%ROStmp2 - .reg OStmp3, %%ROStmp3 - - .reg OStmp4, %%ROStmp4 - .reg OStmp5, %%ROStmp5 - .reg OStmp6, %%ROStmp6 - .reg OStmp7, %%ROStmp7 - - .reg OStmp8, %%ROStmp8 - .reg OStmp9, %%ROStmp9 - .reg OStmp10, %%ROStmp10 - .reg OStmp11, %%ROStmp11 - - - .reg kt0, %%ROStmp0 - .reg kt1, %%ROStmp1 - .reg kt2, %%ROStmp2 - .reg kt3, %%ROStmp3 - - .reg kt4, %%ROStmp4 - .reg kt5, %%ROStmp5 - .reg kt6, %%ROStmp6 - .reg kt7, %%ROStmp7 - - .reg kt8, %%ROStmp8 - .reg kt9, %%ROStmp9 - .reg kt10, %%ROStmp10 - .reg kt11, %%ROStmp11 - - - .reg TempReg0, %%ROSint0 - .reg TempReg1, %%ROSint1 - .reg TempReg2, %%ROSint2 - .reg TempReg3, %%ROSint3 - - .reg TempReg4, %%ROStmp0 - .reg TempReg5, %%ROStmp1 - .reg TempReg6, %%ROStmp2 - .reg TempReg7, %%ROStmp3 - - .reg TempReg8, %%ROStmp4 - .reg TempReg9, %%ROStmp5 - .reg TempReg10, %%ROStmp6 - .reg TempReg11, %%ROStmp7 - - .reg TempReg12, %%ROStmp8 - .reg TempReg13, %%ROStmp9 - .reg TempReg14, %%ROStmp10 - .reg TempReg15, %%ROStmp11 - - -;* Assigned static registers - - .extern RSpillAddrReg, RFillAddrReg, RSignalAddrReg - .extern Rpcb, Retc - .extern RTimerExt, RTimerUtil, RLEDReg, RERRReg - .extern Ret0, Ret1, Ret2, Ret3, Ret4, Ret5, Ret6, Ret7, Reta, Retb - .extern Retx, Rety, Retz - - - .reg SpillAddrReg, %%RSpillAddrReg - .reg FillAddrReg, %%RFillAddrReg - .reg SignalAddrReg, %%RSignalAddrReg - .reg pcb, %%Rpcb - - .reg etx, %%Retx - .reg ety, %%Rety - .reg etz, %%Retz - .reg eta, %%Reta - - .reg etb, %%Retb - .reg etc, %%Retc - .reg TimerExt, %%RTimerExt - .reg TimerUtil, %%RTimerUtil - - .reg LEDReg, %%RLEDReg - .reg ERRReg, %%RERRReg - - - .reg et0, %%Ret0 - .reg et1, %%Ret1 - .reg et2, %%Ret2 - .reg et3, %%Ret3 - - .reg et4, %%Ret4 - .reg et5, %%Ret5 - .reg et6, %%Ret6 - .reg et7, %%Ret7 - -; - .equ SCB1REG_NUM, 88 - .reg SCB1REG_PTR, %%Ret0 - -; The floating point trap handlers need a few static registers - - .extern RFPStat0, RFPStat1, RFPStat2, RFPStat3 - .extern Rheapptr, RHeapPtr, RArgvPtr - - .reg FPStat0, %%RFPStat0 - .reg FPStat1, %%RFPStat1 - .reg FPStat2, %%RFPStat2 - .reg FPStat3, %%RFPStat3 - - .reg heapptr, %%Rheapptr - .reg HeapPtr, %%RHeapPtr - .reg ArgvPtr, %%RArgvPtr - - .extern RXLINXReg, RVMBCReg, RUARTReg, RETHERReg - - .reg XLINXReg, %%RXLINXReg - .reg VMBCReg, %%RVMBCReg - .reg UARTReg, %%RUARTReg - .reg ETHERReg, %%RXLINXReg - -;* Compiler and programmer registers. (gr96-gr127) - - .extern Rv0, Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, Rv7, Rv8, Rv9 - .extern Rv10, Rv11, Rv12, Rv13, Rv14, Rv15 - - .reg v0, %%Rv0 - .reg v1, %%Rv1 - .reg v2, %%Rv2 - .reg v3, %%Rv3 - - .reg v4, %%Rv4 - .reg v5, %%Rv5 - .reg v6, %%Rv6 - .reg v7, %%Rv7 - - .reg v8, %%Rv8 - .reg v9, %%Rv9 - .reg v10, %%Rv10 - .reg v11, %%Rv11 - - .reg v12, %%Rv12 - .reg v13, %%Rv13 - .reg v14, %%Rv14 - .reg v15, %%Rv15 - - .extern Rtv0, Rtv1, Rtv2, Rtv3, Rtv4 - - .reg tv0, %%Rtv0 - .reg tv1, %%Rtv1 - .reg tv2, %%Rtv2 - .reg tv3, %%Rtv3 - .reg tv4, %%Rtv4 - -; **************************************************************************** -; For uatrap -; register definitions -- since this trap handler must allow for -; nested traps and interrupts such as TLB miss, protection violation, -; or Data Access Exception, and these trap handlers use the shared -; Temp registers, we must maintain our own that are safe over user- -; mode loads and stores. The following must be assigned global -; registers which are not used in INTR[0-3], TRAP[0-1], TLB miss, -; TLB protection violation, or data exception trap handlers. - -; .reg cha_cpy, OStmp4 ; copy of CHA -; .reg chd_cpy, OStmp5 ; copy of CHD -; .reg chc_cpy, OStmp6 ; copy of CHC -; .reg LTemp0, OStmp7 ; local temp 0 -; .reg LTemp1, OStmp8 ; local temp 1 - -; **************************************************************************** -#endif diff --git a/c/src/exec/score/cpu/a29k/rtems/.cvsignore b/c/src/exec/score/cpu/a29k/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/a29k/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/a29k/rtems/score/.cvsignore b/c/src/exec/score/cpu/a29k/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/a29k/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/a29k/rtems/score/a29k.h b/c/src/exec/score/cpu/a29k/rtems/score/a29k.h deleted file mode 100644 index 99a2626202..0000000000 --- a/c/src/exec/score/cpu/a29k/rtems/score/a29k.h +++ /dev/null @@ -1,78 +0,0 @@ -/* a29k.h - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ -/* @(#)a29k.h 10/21/96 1.3 */ - -#ifndef _INCLUDE_A29K_h -#define _INCLUDE_A29K_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "no cpu" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -#define A29K_HAS_FPU 0 -#define CPU_MODEL_NAME "a29xxx" - -/* - * Moving toward multilib with no attempt to distinguish - * multilib features in gcc. - */ - -#if 0 -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define A29K_HAS_FPU 0 - -#elif defined(a29205) - -#define CPU_MODEL_NAME "a29205" -#define A29K_HAS_FPU 0 - -#else - -#error "Unsupported CPU Model" - -#endif -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "AMD 29K" - -/* - * Some bits in the CPS: - */ -#define TD 0x20000 -#define DI 0x00002 - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_A29K_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/a29k/rtems/score/cpu.h b/c/src/exec/score/cpu/a29k/rtems/score/cpu.h deleted file mode 100644 index 10c7be3b3f..0000000000 --- a/c/src/exec/score/cpu/a29k/rtems/score/cpu.h +++ /dev/null @@ -1,1008 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the AMD 29K - * processor. - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.c: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ -/* @(#)cpu.h 10/21/96 1.11 */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/a29k.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -extern unsigned int a29k_disable( void ); -extern void a29k_enable( unsigned int cookie ); -extern unsigned int a29k_getops( void ); -extern void a29k_getops_sup( void ); -extern void a29k_disable_sup( void ); -extern void a29k_enable_sup( void ); -extern void a29k_disable_all( void ); -extern void a29k_disable_all_sup( void ); -extern void a29k_enable_all( void ); -extern void a29k_enable_all_sup( void ); -extern void a29k_halt( void ); -extern void a29k_fatal_error( unsigned32 error ); -extern void a29k_as70( void ); -extern void a29k_super_mode( void ); -extern void a29k_context_switch_sup(void); -extern void a29k_context_restore_sup(void); -extern void a29k_context_save_sup(void); -extern void a29k_sigdfl_sup(void); - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( A29K_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - */ - -/* #warning "Check these definitions!!!" */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - unsigned32 signal; - unsigned32 gr1; - unsigned32 rab; - unsigned32 PC0; - unsigned32 PC1; - unsigned32 PC2; - unsigned32 CHA; - unsigned32 CHD; - unsigned32 CHC; - unsigned32 ALU; - unsigned32 OPS; - unsigned32 tav; - unsigned32 lr1; - unsigned32 rfb; - unsigned32 msp; - - unsigned32 FPStat0; - unsigned32 FPStat1; - unsigned32 FPStat2; - unsigned32 IPA; - unsigned32 IPB; - unsigned32 IPC; - unsigned32 Q; - - unsigned32 gr96; - unsigned32 gr97; - unsigned32 gr98; - unsigned32 gr99; - unsigned32 gr100; - unsigned32 gr101; - unsigned32 gr102; - unsigned32 gr103; - unsigned32 gr104; - unsigned32 gr105; - unsigned32 gr106; - unsigned32 gr107; - unsigned32 gr108; - unsigned32 gr109; - unsigned32 gr110; - unsigned32 gr111; - - unsigned32 gr112; - unsigned32 gr113; - unsigned32 gr114; - unsigned32 gr115; - - unsigned32 gr116; - unsigned32 gr117; - unsigned32 gr118; - unsigned32 gr119; - unsigned32 gr120; - unsigned32 gr121; - unsigned32 gr122; - unsigned32 gr123; - unsigned32 gr124; - - unsigned32 local_count; - - unsigned32 locals[128]; -} Context_Control; - -typedef struct { - double some_float_register; -} Context_Control_fp; - -typedef struct { - unsigned32 special_interrupt_register; -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the a29K processor specific parameters. - * - * NOTE: The interrupt_stack_size field is required if - * CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE. - * - * The pretasking_hook, predriver_hook, and postdriver_hook, - * and the do_zero_of_workspace fields are required on ALL CPUs. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access AMD A29K specific additions to the CPU Table - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (8192) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT 4 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* ISR handler macros */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do{ _isr_cookie = a29k_disable(); }while(0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - do{ a29k_enable(_isr_cookie) ; }while(0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - do{ \ - _CPU_ISR_Enable( _isr_cookie ); \ - _CPU_ISR_Disable( _isr_cookie ); \ - }while(0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ - -#define _CPU_ISR_Set_level( new_level ) \ - do{ \ - if ( new_level ) a29k_disable_all(); \ - else a29k_enable_all(); \ - }while(0); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -extern void _CPU_Context_save( - Context_Control *new_context -); - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - */ - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - do{ /* allocate 1/4 of stack for memory stack, 3/4 of stack for register stack */ \ - unsigned32 _mem_stack_tmp = (unsigned32)(_stack_base) + (_size); \ - unsigned32 _reg_stack_tmp = (unsigned32)(_stack_base) + (((_size)*3)/4); \ - _mem_stack_tmp &= ~(CPU_ALIGNMENT-1); \ - _reg_stack_tmp &= ~(CPU_ALIGNMENT-1); \ - _CPU_Context_save(_the_context); \ - (_the_context)->msp = _mem_stack_tmp; /* gr125 */ \ - (_the_context)->lr1 = \ - (_the_context)->locals[1] = \ - (_the_context)->rfb = _reg_stack_tmp; /* gr127 */ \ - (_the_context)->gr1 = _reg_stack_tmp - 4 * 4; \ - (_the_context)->rab = _reg_stack_tmp - 128 * 4; /* gr126 */ \ - (_the_context)->local_count = 1-1; \ - (_the_context)->PC1 = _entry_point; \ - (_the_context)->PC0 = (unsigned32)((char *)_entry_point + 4); \ - if (_isr) { (_the_context)->OPS |= (TD | DI); } \ - else \ - { (_the_context)->OPS &= ~(TD | DI); } \ - }while(0) - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ) - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (char *) (_base) + (_offset) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } while(0) - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - a29k_fatal_error(_error) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch)() -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -#define CPU_swap_u32( value ) \ - ((value&0xff) << 24) | (((value >> 8)&0xff) << 16) | \ - (((value >> 16)&0xff) << 8) | ((value>>24)&0xff) - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/a29k/rtems/score/cpu_asm.h b/c/src/exec/score/cpu/a29k/rtems/score/cpu_asm.h deleted file mode 100644 index d2c09fa103..0000000000 --- a/c/src/exec/score/cpu/a29k/rtems/score/cpu_asm.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * cpu_asm.h - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ -/* @(#)cpu_asm.h 06/08/96 1.2 */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - -/* pull in the generated offsets */ - -/* #include <rtems/score/offsets.h> */ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/c/src/exec/score/cpu/a29k/rtems/score/types.h b/c/src/exec/score/cpu/a29k/rtems/score/types.h deleted file mode 100644 index 130fd30dd4..0000000000 --- a/c/src/exec/score/cpu/a29k/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/* no_cputypes.h - * - * This include file contains type definitions pertaining to the Intel - * no_cpu processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __NO_CPU_TYPES_h -#define __NO_CPU_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void no_cpu_isr; -typedef void ( *no_cpu_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/a29k/sig.S b/c/src/exec/score/cpu/a29k/sig.S deleted file mode 100644 index 9caddf1382..0000000000 --- a/c/src/exec/score/cpu/a29k/sig.S +++ /dev/null @@ -1,213 +0,0 @@ -;/* -; * $Id$ -; */ - -; .include "register.ah" -#include <amd.ah> -#include <pswmacro.ah> - .comm WindowSize,4 - .text - .reg it0,gr64 - .reg it1,gr65 - .reg it2,gr66 - .reg it3,gr67 - .reg v0,gr96 - .reg v1,gr97 - .reg v2,gr98 - .reg v3,gr99 - .reg trapreg,it0 - .reg FPStat0,gr79 - .reg FPStat1,gr79 - .reg FPStat2,gr79 - .reg FPStat3,gr79 - - .global _intr14 -_intr14: -#if 0 - const it3,14 - sup_sv - jmp interrupt - nop -#endif - - .global _intr18 -_intr18: -#if 0 - const it3,18 - sup_sv - jmp interrupt - nop -#endif - - .global _intr19 -_intr19: -#if 0 - const it3,19 - sup_sv - jmp interrupt - nop -#endif - -interrupt: -#if 0 - push msp,it3 - push msp,gr1 - push msp,rab - const it0,512 - sub rab,rfb,it0 ;set rab = rfb-512 - pushsr msp,it0,pc0 - pushsr msp,it0,pc1 - pushsr msp,it0,pc2 - pushsr msp,it0,cha - pushsr msp,it0,chd - pushsr msp,it0,chc - pushsr msp,it0,alu - pushsr msp,it0,ops - push msp,tav -; -;now come off freeze, and go to user-mode code. -;ensure load/store does not restart -; - mtsrim chc,0 - - mfsr it0, cps - const it1, FZ - consth it1, FZ - andn it0, it0, it1 - const it1,(DI|TD) - consth it1,(DI|TD) - or it0,it1,it0 - mtsr cps, it0 -; fall through to _sigcode -#endif - - .extern _a29k_ISR_Handler - .global _sigcode -_sigcode: -#if 0 - - push msp, lr1 ; R stack support - push msp, rfb ; support - push msp, msp ; M stack support - -; push msp, FPStat0 ; Floating point 0 -; push msp, FPStat1 ; Floating point 1 -; push msp, FPStat2 ; Floating point 2 -; push msp, FPStat3 ; Floating point 3 - sub msp,msp,4*4 - - pushsr msp, tav, IPA ; save user mode special - pushsr msp, tav, IPB ; save user mode special - pushsr msp, tav, IPC ; save user mode special - pushsr msp, tav, Q ; save user mode special - - sub msp, msp, 29*4 ; gr96-gr124 - mtsrim cr, 29-1 ; - storem 0, 0, gr96, msp ; - - - const v0, WindowSize ; Window Size value - consth v0, WindowSize ; Window Size value - load 0, 0, v0, v0 ; load Window size - add v2, msp, SIGCTX_RAB ; intr RAB value - - load 0, 0, v2, v2 ; rab value - - sub v1, rfb, v2 ; - cpgeu v1, v1, v0 ; - jmpt v1, nfill ; jmp if spill - add v1, gr1, 8 ; - - cpgtu v1, v1, rfb ; longjump test - jmpt v1, nfill ; - nop ; - -ifill: - add v0, msp, SIGCTX_RAB+4 ; - push v0, rab ; - const v2, fill+4 ; - consth v2, fill+4 ; - - push v0, v2 ; resave PC0 - sub v2, v2, 4 ; - push v0, v2 ; resave PC1 - const v2, 0 ; - - sub v0, v0, 3*4 ; - push v0, v2 ; - -nfill: - cpgtu v0, gr1, rfb ; if gr1>rfb -> gr1=rfb - jmpt v0, lower ; - cpltu v0, gr1, rab ; - jmpt v0, raise ; gr1<rab then gr1=rab - nop ; - -sendsig: - sub gr1, gr1, RALLOC ; - asgeu V_SPILL, gr1, rab ; - add lr1, rfb, 0 ; - add v1, msp, SIGCTX_SIG ; - -cont: - add lr2,it3,0 ; signal # - call lr0, _a29k_ISR_Handler ; call the handler - nop - - nop ; WASTE - jmp _a29k_sigdfl ; return code - nop ; WASTE - nop ; ALIGN - -lower: - jmp sendsig ; - add gr1, rfb, 0 ; -raise: - jmp sendsig ; - add gr1, rab, 0 ; -#endif - - - .global _a29k_sigdfl_sup -_a29k_sigdfl_sup: -#if 0 - repair_R_stack ; - repair_regs ; - sig_return ; return - halt ; never executes -#endif - - - .global _sigret -_sigret: -#if 0 -;assume msp points to tav - mfsr it0,cps - const it1,FZ - or it1,it0,it1 - mtsr cps,it1 - nop - nop -_sigret1: - pop tav,msp - popsr ops,it0,msp - popsr alu,it0,msp - popsr chc,it0,msp - popsr chd,it0,msp - popsr cha,it0,msp - popsr pc2,it0,msp - popsr pc1,it0,msp - popsr pc0,it0,msp - pop rab,msp - pop it0,msp - add gr1,it0,0 - add msp,msp,4 ;discount signal - iret -#endif - -_a29k_sigdfl: -#if 0 - asneq SIGDFL,gr1,gr1 - jmpi lr0 - nop -#endif diff --git a/c/src/exec/score/cpu/arm/.cvsignore b/c/src/exec/score/cpu/arm/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/arm/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/arm/ChangeLog b/c/src/exec/score/cpu/arm/ChangeLog deleted file mode 100644 index 8b946f1ad2..0000000000 --- a/c/src/exec/score/cpu/arm/ChangeLog +++ /dev/null @@ -1,153 +0,0 @@ -2002-07-17 Jay Monkman <jtm@smoothsmoothie.com> - - * rtems/score/cpu_asm.h: Enhanced to include register offsets. - * Makefile.am: Install rtems/score/cpu_asm.h. - * cpu.c: Significantly enhanced including the implementation of - _CPU_ISR_Get_level. - * cpu_asm.S: Improved behavior of context switch and interrupt - dispatching. - * rtems/score/arm.h: Improved the CPU model name determination. - * rtems/score/cpu.h: Improved interrupt disable/enable functions. - -2002-07-05 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Filled in something that was marked XXX. - -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-04-18 Jay Monkman <jtm@smoothsmoothie.com> - - * rtems/score/cpu.h (CPU_ISR_Disable and CPU_ISR_Enable): Correct them - where they correctly inform the compiler about the register they - are modifying. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/a29ktypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2001-02-04 Joel Sherrill <joel@OARcorp.com> - - * configure.ac: Removed references to rtems/Makefile and - rtems/score/Makefile. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2002-02-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP. - -2002-01-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * cpu.c: Include rtems/bspIo.h instead of bspIo.h. - -2001-12-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use RTEMS_ENV_RTEMSCPU. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-12-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * asm.h: include cpuopts.h instead of targopts.h - * rtems/score/arm.h: Use __arm__. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am, formatting. - * rtems/Makefile.am: Formatting. - * rtems/score/Makefile.am: Formatting. - -2000-08-29 Joel Sherrill <joel.sherrill@OARcorp.com> - - * cpu.c: Spacing issues. - * rtems/score/cpu.h: Removed warning by setting _level. - -2000-08-29 Joel Sherrill <joel.sherrill@OARcorp.com> - - * Makefile.am: Added S_O_FILES to list of objects. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/arm/Makefile.am b/c/src/exec/score/cpu/arm/Makefile.am deleted file mode 100644 index 03e6e36ebf..0000000000 --- a/c/src/exec/score/cpu/arm/Makefile.am +++ /dev/null @@ -1,55 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/cpu_asm.h \ - rtems/score/arm.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/arm/asm.h b/c/src/exec/score/cpu/arm/asm.h deleted file mode 100644 index b974287b45..0000000000 --- a/c/src/exec/score/cpu/arm/asm.h +++ /dev/null @@ -1,125 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#ifndef __ARM_ASM_h -#define __ARM_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/arm.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) -#define r8 REG(r8) -#define r9 REG(r9) -#define r10 REG(r10) -#define r11 REG(r11) -#define r12 REG(r12) -#define r13 REG(r13) -#define r14 REG(r14) -#define r15 REG(r15) - -#define CPSR REG(CPSR) - -#define SPSR REG(SPSR) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/arm/configure.ac b/c/src/exec/score/cpu/arm/configure.ac deleted file mode 100644 index d7094bae11..0000000000 --- a/c/src/exec/score/cpu/arm/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-arm],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/arm/cpu.c b/c/src/exec/score/cpu/arm/cpu.c deleted file mode 100644 index 3ae3f5828a..0000000000 --- a/c/src/exec/score/cpu/arm/cpu.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * ARM CPU Dependent Source - * - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * Copyright (c) 2002 Advent Networks, Inc - * Jay Monkman <jmonkman@adventnetworks.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#include <rtems/system.h> -#include <rtems.h> -#include <rtems/bspIo.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/thread.h> -#include <rtems/score/cpu.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of ISR disptaching routine (unused) - * - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - _CPU_Table = *cpu_table; -} - -/* - * - * _CPU_ISR_Get_level - returns the current interrupt level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 reg; - - asm volatile ("mrs %0, cpsr \n" \ - "and %0, %0, #0xc0 \n" \ - : "=r" (reg)); - - return reg; -} - -/* - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * new_handler - replacement ISR for this vector number - * old_handler - pointer to store former ISR for this vector number - * - * FIXME: This vector scheme should be changed to allow FIQ to be - * handled better. I'd like to be able to put VectorTable - * elsewhere - JTM - * - * - * Output parameters: NONE - * - */ -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* pointer on the redirection table in RAM */ - long *VectorTable = (long *)(MAX_EXCEPTIONS * 4); - - if (old_handler != NULL) { - old_handler = *(proc_ptr *)(VectorTable + vector); - } - - *(VectorTable + vector) = (long)new_handler ; - -} - -void _CPU_Context_Initialize( - Context_Control *the_context, - unsigned32 *stack_base, - unsigned32 size, - unsigned32 new_level, - void *entry_point, - boolean is_fp -) -{ - the_context->register_sp = ((unsigned32)(stack_base)) + (size) ; - the_context->register_pc = (entry_point); - the_context->register_cpsr = (new_level | 0x13); -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -/* FIXME: do something here */ -#if 0 - extern unsigned long _fiq_stack; - extern unsigned long _fiq_stack_size; - extern unsigned long _irq_stack; - extern unsigned long _irq_stack_size; - extern unsigned long _abt_stack; - extern unsigned long _abt_stack_size; - unsigned long *ptr; - int i; - - ptr = &_fiq_stack; - for (i = 0; i < ((int)&_fiq_stack_size/4); i++) { - ptr[i] = 0x13131313; - } - - ptr = &_irq_stack; - for (i = 0; i < ((int)&_irq_stack_size/4); i++) { - ptr[i] = 0xf0f0f0f0; - } - - ptr = &_abt_stack; - for (i = 0; i < ((int)&_abt_stack_size/4); i++) { - ptr[i] = 0x55555555; - } -#endif -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -void _CPU_Thread_Idle_body( void ) -{ - - while(1); /* FIXME: finish this */ - /* insert your "halt" instruction here */ ; -} - -void _defaultExcHandler (CPU_Exception_frame *ctx) -{ - printk("\n\r"); - printk("----------------------------------------------------------\n\r"); - printk("Exception 0x%x caught at PC 0x%x by thread %d\n", - ctx->register_pc, ctx->register_lr - 4, - _Thread_Executing->Object.id); - printk("----------------------------------------------------------\n\r"); - printk("Processor execution context at time of the fault was :\n\r"); - printk("----------------------------------------------------------\n\r"); - printk(" r0 = %8x r1 = %8x r2 = %8x r3 = %8x\n\r", - ctx->register_r0, ctx->register_r1, - ctx->register_r2, ctx->register_r3); - printk(" r4 = %8x r5 = %8x r6 = %8x r7 = %8x\n\r", - ctx->register_r4, ctx->register_r5, - ctx->register_r6, ctx->register_r7); - printk(" r8 = %8x r9 = %8x r10 = %8x\n\r", - ctx->register_r8, ctx->register_r9, ctx->register_r10); - printk(" fp = %8x ip = %8x sp = %8x pc = %8x\n\r", - ctx->register_fp, ctx->register_ip, - ctx->register_sp, ctx->register_lr - 4); - printk("----------------------------------------------------------\n\r"); - - if (_ISR_Nest_level > 0) { - /* - * In this case we shall not delete the task interrupted as - * it has nothing to do with the fault. We cannot return either - * because the eip points to the faulty instruction so... - */ - printk("Exception while executing ISR!!!. System locked\n\r"); - while(1); - } - else { - printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r"); - rtems_task_delete(_Thread_Executing->Object.id); - } -} - -cpuExcHandlerType _currentExcHandler = _defaultExcHandler; - -extern void _Exception_Handler_Undef_Swi(); -extern void _Exception_Handler_Abort(); -/* FIXME: put comments here */ -void rtems_exception_init_mngt() -{ - ISR_Level level; - - _CPU_ISR_Disable(level); - _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF, - _Exception_Handler_Undef_Swi, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_SWI, - _Exception_Handler_Undef_Swi, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_Enable(level); -} - - diff --git a/c/src/exec/score/cpu/arm/cpu_asm.S b/c/src/exec/score/cpu/arm/cpu_asm.S deleted file mode 100644 index 60c638d80a..0000000000 --- a/c/src/exec/score/cpu/arm/cpu_asm.S +++ /dev/null @@ -1,216 +0,0 @@ -/* - * $Id$ - * - * This file contains all assembly code for the ARM implementation - * of RTEMS. - * - * Copyright (c) 2002 by Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#include <asm.h> -#include <rtems/score/cpu_asm.h> - - -/* - * void _CPU_Context_switch( run_context, heir_context ) - * void _CPU_Context_restore( run_context, heir_context ) - * - * This routine performs a normal non-FP context. - * - * R0 = run_context R1 = heir_context - * - * This function copies the current registers to where r0 points, then - * restores the ones from where r1 points. - * - * - * NOTE: The function should be able to only save/restore the registers - * that would be saved by a C function since the others have already - * been saved. - * - * It should also be able to use the stm/ldm instructions. - * - */ - - .globl _CPU_Context_switch -_CPU_Context_switch: -/* FIXME: This should use load and store multiple instructions */ -/* Start saving context */ - str r2, [r0, #REG_R2] - str r3, [r0, #REG_R3] - str r4, [r0, #REG_R4] - str r5, [r0, #REG_R5] - str r6, [r0, #REG_R6] - str r7, [r0, #REG_R7] - str r8, [r0, #REG_R8] - str r9, [r0, #REG_R9] - str r10, [r0, #REG_R10] - - str r11, [r0, #REG_R11] - str r12, [r0, #REG_R12] - - str sp, [r0, #REG_SP] - str lr, [r0, #REG_PC] /* save LR at PC's location */ - - mrs r2, cpsr - str r2, [r0, #REG_CPSR] - -/* Start restoring context */ - - ldr r2, [r1, #REG_CPSR] - msr cpsr, r2 - - ldr r2, [r1, #REG_R2] - ldr r3, [r1, #REG_R3] - ldr r4, [r1, #REG_R4] - ldr r5, [r1, #REG_R5] - ldr r6, [r1, #REG_R6] - ldr r7, [r1, #REG_R7] - ldr r8, [r1, #REG_R8] - ldr r9, [r1, #REG_R9] - ldr r10, [r1, #REG_R10] - ldr r11, [r1, #REG_R11] - ldr r12, [r1, #REG_R12] - - ldr sp, [r1, #REG_SP] - ldr lr, [r1, #REG_PC] - mov pc, lr - -/* - * void _CPU_Context_restore( new_context ) - * - * This function copies the restores the registers from where r0 points. - * It must match _CPU_Context_switch() - * - * NOTE: The function should be able to only save/restore the registers - * that would be saved by a C function since the others have already - * been saved. - * - * It should also be able to use the stm/ldm instructions. - * - */ - .globl _CPU_Context_restore -_CPU_Context_restore: -/* FIXME: This should use load and store multiple instructions */ - ldr r2, [r0, #REG_CPSR] - msr cpsr, r2 - - ldr r2, [r0, #REG_R2] - ldr r3, [r0, #REG_R3] - ldr r4, [r0, #REG_R4] - ldr r5, [r0, #REG_R5] - ldr r6, [r0, #REG_R6] - ldr r7, [r0, #REG_R7] - ldr r8, [r0, #REG_R8] - ldr r9, [r0, #REG_R9] - ldr r10, [r0, #REG_R10] - ldr r11, [r1, #REG_R11] - ldr r12, [r1, #REG_R12] - - ldr sp, [r0, #REG_SP] - ldr lr, [r0, #REG_PC] - mov pc, lr - - -/* FIXME: _Exception_Handler_Undef_Swi is untested */ - .globl _Exception_Handler_Undef_Swi -_Exception_Handler_Undef_Swi: -/* FIXME: This should use load and store multiple instructions */ - sub r13,r13,#SIZE_REGS - str r0, [r13, #REG_R0] - str r1, [r13, #REG_R1] - str r2, [r13, #REG_R2] - str r3, [r13, #REG_R3] - str r4, [r13, #REG_R4] - str r5, [r13, #REG_R5] - str r6, [r13, #REG_R6] - str r7, [r13, #REG_R7] - str r8, [r13, #REG_R8] - str r9, [r13, #REG_R9] - str r10, [r13, #REG_R10] - str r11, [r13, #REG_R11] - str r12, [r13, #REG_R12] - str sp, [r13, #REG_SP] - str lr, [r13, #REG_LR] - mrs r0, cpsr /* read the status */ - and r0, r0,#0x1f /* we keep the mode as exception number */ - str r0, [r13, #REG_PC] /* we store it in a free place */ - mov r0, r13 /* put frame address in r0 (C arg 1) */ - - ldr r1, =SWI_Handler - ldr lr, =_go_back_1 - ldr pc,[r1] /* call handler */ -_go_back_1: - ldr r0, [r13, #REG_R0] - ldr r1, [r13, #REG_R1] - ldr r2, [r13, #REG_R2] - ldr r3, [r13, #REG_R3] - ldr r4, [r13, #REG_R4] - ldr r5, [r13, #REG_R5] - ldr r6, [r13, #REG_R6] - ldr r7, [r13, #REG_R7] - ldr r8, [r13, #REG_R8] - ldr r9, [r13, #REG_R9] - ldr r10, [r13, #REG_R10] - ldr r11, [r13, #REG_R11] - ldr r12, [r13, #REG_R12] - ldr sp, [r13, #REG_SP] - ldr lr, [r13, #REG_LR] - add r13,r13,#SIZE_REGS - movs pc,r14 /* return */ - -/* FIXME: _Exception_Handler_Abort is untested */ - .globl _Exception_Handler_Abort -_Exception_Handler_Abort: -/* FIXME: This should use load and store multiple instructions */ - sub r13,r13,#SIZE_REGS - str r0, [r13, #REG_R0] - str r1, [r13, #REG_R1] - str r2, [r13, #REG_R2] - str r3, [r13, #REG_R3] - str r4, [r13, #REG_R4] - str r5, [r13, #REG_R5] - str r6, [r13, #REG_R6] - str r7, [r13, #REG_R7] - str r8, [r13, #REG_R8] - str r9, [r13, #REG_R9] - str r10, [r13, #REG_R10] - str sp, [r13, #REG_R11] - str lr, [r13, #REG_R12] - str lr, [r13, #REG_SP] - str lr, [r13, #REG_LR] - mrs r0, cpsr /* read the status */ - and r0, r0,#0x1f /* we keep the mode as exception number */ - str r0, [r13, #REG_PC] /* we store it in a free place */ - mov r0, r13 /* put frame address in ro (C arg 1) */ - - ldr r1, =_currentExcHandler - ldr lr, =_go_back_2 - ldr pc,[r1] /* call handler */ -_go_back_2: - ldr r0, [r13, #REG_R0] - ldr r1, [r13, #REG_R1] - ldr r2, [r13, #REG_R2] - ldr r3, [r13, #REG_R3] - ldr r4, [r13, #REG_R4] - ldr r5, [r13, #REG_R5] - ldr r6, [r13, #REG_R6] - ldr r7, [r13, #REG_R7] - ldr r8, [r13, #REG_R8] - ldr r9, [r13, #REG_R9] - ldr r10, [r13, #REG_R10] - ldr sp, [r13, #REG_R11] - ldr lr, [r13, #REG_R12] - ldr lr, [r13, #REG_SP] - ldr lr, [r13, #REG_LR] - add r13,r13,#SIZE_REGS - subs pc,r14,#4 /* return */ - diff --git a/c/src/exec/score/cpu/arm/rtems/.cvsignore b/c/src/exec/score/cpu/arm/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/arm/rtems/score/.cvsignore b/c/src/exec/score/cpu/arm/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/arm/rtems/score/arm.h b/c/src/exec/score/cpu/arm/rtems/score/arm.h deleted file mode 100644 index 05aed89892..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/arm.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * $Id$ - * - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * Copyright (c) 2002 Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#ifndef _INCLUDE_ARM_h -#define _INCLUDE_ARM_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "arm" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ -#if defined(__arm9__) -# define CPU_MODEL_NAME "arm9" -# define ARM_HAS_FPU 0 -#elif defined(__arm9tdmi__) -# define CPU_MODEL_NAME "arm9tdmi" -# define ARM_HAS_FPU 0 -#elif defined(__arm7__) -# define CPU_MODEL_NAME "arm7" -# define ARM_HAS_FPU 0 -#elif defined(__arm7tdmi__) -# define CPU_MODEL_NAME "arm7tdmi" -# define ARM_HAS_FPU 0 -#elif defined(__arm__) -# define CPU_MODEL_NAME "unknown ARM" -# define ARM_HAS_FPU 0 -#else -# error "Unsupported CPU Model" -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "ARM" - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_ARM_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/arm/rtems/score/cpu.h b/c/src/exec/score/cpu/arm/rtems/score/cpu.h deleted file mode 100644 index 7074d0022e..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/cpu.h +++ /dev/null @@ -1,962 +0,0 @@ -/* - * This include file contains information pertaining to the ARM - * processor. - * - * COPYRIGHT (c) 2002 Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -/* FIXME: finish commenting/cleaning up this file */ -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/arm.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRU - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( ARM_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif - -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x000000c0 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - unsigned32 register_r0; - unsigned32 register_r1; - unsigned32 register_r2; - unsigned32 register_r3; - unsigned32 register_r4; - unsigned32 register_r5; - unsigned32 register_r6; - unsigned32 register_r7; - unsigned32 register_r8; - unsigned32 register_r9; - unsigned32 register_r10; - unsigned32 register_fp; - unsigned32 register_ip; - unsigned32 register_sp; - unsigned32 register_lr; - unsigned32 register_pc; - unsigned32 register_cpsr; -} Context_Control; - -typedef struct { - double some_float_register; -} Context_Control_fp; - -typedef Context_Control CPU_Exception_frame; - -typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); -extern cpuExcHandlerType _currentExcHandler; -extern void rtems_exception_init_mngt(); - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of each interrupt - * that will lead to re-enter the kernel to signal the thread. - */ - -typedef CPU_Exception_frame CPU_Interrupt_frame; - -/* - * The following table contains the information required to configure - * the ARM processor specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access NO_CPU specific additions to the CPU Table - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 8 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*16) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT 4 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT 4 - -/* ISR handler macros */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level ) \ - do { \ - int reg; \ - asm volatile ("MRS %0, cpsr \n" \ - "ORR %1, %0, #0xc0 \n" \ - "MSR cpsr, %1 \n" \ - "AND %0, %0, #0xc0 \n" \ - : "=r" (_level), "=r" (reg) \ - : "0" (_level), "1" (reg)); \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - do { \ - int reg; \ - asm volatile ("MRS %0, cpsr \n" \ - "BIC %0, %0, #0xc0 \n" \ - "ORR %0, %0, %2 \n" \ - "MSR cpsr, %0 \n" \ - : "=r" (reg) \ - : "0" (reg), "r" (_level)); \ - } while (0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level ) \ - { \ - int reg1; \ - int reg2; \ - asm volatile ("MRS %0, cpsr \n" \ - "BIC %1, %0, #0xc0 \n" \ - "ORR %1, %1, %4 \n" \ - "MSR cpsr, %1 \n" \ - "MSR cpsr, %0 \n" \ - : "=r" (reg1), "=r" (reg2) \ - : "0" (reg1), "1" (reg2), "r" (_level)); \ - } - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - */ - -#define _CPU_ISR_Set_level( new_level ) \ - { \ - int reg; \ - asm volatile ("MRS %0, cpsr \n" \ - "BIC %0, %0, #0xc0 \n" \ - "ORR %0, %0, %2 \n" \ - "MSR cpsr_c, %0 \n" \ - : "=r" (reg) \ - : "0" (reg), "r" (new_level)); \ - } - - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - unsigned32 *stack_base, - unsigned32 size, - unsigned32 new_level, - void *entry_point, - boolean is_fp -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -typedef enum { - ARM_EXCEPTION_RESET = 0, - ARM_EXCEPTION_UNDEF = 1, - ARM_EXCEPTION_SWI = 2, - ARM_EXCEPTION_PREF_ABORT = 3, - ARM_EXCEPTION_DATA_ABORT = 4, - ARM_EXCEPTION_RESERVED = 5, - ARM_EXCEPTION_IRQ = 6, - ARM_EXCEPTION_FIQ = 7, - MAX_EXCEPTIONS = 8 -} Arm_symbolic_exception_name; - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/arm/rtems/score/cpu_asm.h b/c/src/exec/score/cpu/arm/rtems/score/cpu_asm.h deleted file mode 100644 index 2c13347578..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/cpu_asm.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * $Id$ - * - * Copyright (c) 2002 by Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * This file is the include file for cpu_asm.S - * - * - */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - - -/* Registers saved in context switch: */ -.set REG_R0, 0 -.set REG_R1, 4 -.set REG_R2, 8 -.set REG_R3, 12 -.set REG_R4, 16 -.set REG_R5, 20 -.set REG_R6, 24 -.set REG_R7, 28 -.set REG_R8, 32 -.set REG_R9, 36 -.set REG_R10, 40 -.set REG_R11, 44 -.set REG_R12, 48 -.set REG_SP, 52 -.set REG_LR, 56 -.set REG_PC, 60 -.set REG_CPSR, 64 -.set SIZE_REGS, REG_CPSR + 4 - - -#endif diff --git a/c/src/exec/score/cpu/arm/rtems/score/types.h b/c/src/exec/score/cpu/arm/rtems/score/types.h deleted file mode 100644 index 4408046d4e..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/types.h +++ /dev/null @@ -1,55 +0,0 @@ -/* armtypes.h - * - * This include file contains type definitions pertaining to the - * arm processor family. - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#ifndef __ARM_TYPES_h -#define __ARM_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void no_cpu_isr; -typedef void ( *no_cpu_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/c4x/.cvsignore b/c/src/exec/score/cpu/c4x/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/c4x/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/c4x/ChangeLog b/c/src/exec/score/cpu/c4x/ChangeLog deleted file mode 100644 index 9682f57b5b..0000000000 --- a/c/src/exec/score/cpu/c4x/ChangeLog +++ /dev/null @@ -1,126 +0,0 @@ -2002-07-05 Joel Sherrill <joel@OARcorp.com> - - * cpu.c, irq.c, rtems/score/cpu.h: Filled in something that was - marked XXX. - -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/c4xtypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2002-02-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * asm.h: Remove #include <rtems/score/targopts.h>. - Add #include <rtems/score/cpuopts.h>. - - - -2002-02-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP. - -2001-12-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use RTEMS_ENV_RTEMSCPU. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-10-18 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/c4x.h: Modified to properly multilib. This required - using only macros predefined by gcc. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am, formatting. - * rtems/Makefile.am: formatting. - * rtems/score/Makefile.am: formatting. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/c4x/Makefile.am b/c/src/exec/score/cpu/c4x/Makefile.am deleted file mode 100644 index 2c35fe7137..0000000000 --- a/c/src/exec/score/cpu/c4x/Makefile.am +++ /dev/null @@ -1,55 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h c4xio.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/c4x.h \ - rtems/score/types.h \ - rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c irq.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c irq.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/c4x/asm.h b/c/src/exec/score/cpu/c4x/asm.h deleted file mode 100644 index 24f9c5e391..0000000000 --- a/c/src/exec/score/cpu/c4x/asm.h +++ /dev/null @@ -1,101 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __C4X_ASM_h -#define __C4X_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/c4x.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/c4x/c4xio.h b/c/src/exec/score/cpu/c4x/c4xio.h deleted file mode 100644 index f85f461ebc..0000000000 --- a/c/src/exec/score/cpu/c4x/c4xio.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * C4X IO Information - * - * $Id$ - */ - -#ifndef __C4XIO_h -#define __C4XIO_h - -/* - * Address defines - */ - -#ifdef _TMS320C40 -#define C4X_TIMER_0 ((struct c4x_timer*)0x100020) -#else -#define C4X_TIMER_0 ((struct c4x_timer*)0x808020) -#define C4X_TIMER_1 ((struct c4x_timer*)0x808030) -#endif - -/* XXX how portable */ - -/* C32 Internal Control Registers */ -#define C4X_STRB0_REG 0x808064 -#define C4X_STRB1_REG 0x808068 -#define C4X_IOSTRB_REG 0x808060 - -/* C32 Internal RAM Locations */ -/* XXX how long */ -#define C4X_RAM_BLK_0 0x87fe00 -#define C4X_RAM_BLK_1 0x87ff00 - -/* - * Data Structures to Overlay the Peripherals on the CPU - */ - -struct c4x_timer { - volatile int tcontrol; - volatile int r1[3]; - volatile int tcounter; - volatile int r2[3]; - volatile int tperiod; -}; - - - - -/* - * Timer Support Routines - * - * The following section of C4x timer code is based on C40 specific - * timer code from Ran Cabell <rcabell@norfolk.infi.net>. The - * only C3x/C4x difference spotted was the address of the timer. - * The names have been changed to be more RTEMS like. - */ - -#define c4x_timer_get_control( _timer ) (volatile int)(_timer->tcontrol) - -#define c4x_timer_set_control( _timer, _value ) \ - do { \ - (volatile int)(_timer->tcontrol) = _value; \ - } while (0); - -#define c4x_timer_start( _timer ) \ - c4x_timer_set_control(_timer, 0x02c1 ) - -#define c4x_timer_stop( _timer ) _timer->tcontrol = 0 - -#define c4x_timer_get_counter( _timer ) (volatile int)(_timer->tcounter) - -#define c4x_timer_set_counter( _timer, _value ) \ - do { \ - (volatile int)(_timer->tcounter) = _value; \ - } while (0); - -#define c4x_timer_get_period( _timer ) (volatile int)(_timer->tperiod) - -#define c4x_timer_set_period( _timer, _value ) \ - do { \ - (volatile int)(_timer->tperiod) = _value; \ - } while (0); - -/* - * IO Flags - * - * NOTE: iof on c3x, iiof on c4x - */ - -#ifdef _TMS320C40 - -#else - -static inline unsigned32 c3x_get_iof( void ) -{ - register unsigned32 iof_value; - - __asm__ volatile ("ldi iof, %0" : "=r" (iof_value)); - return iof_value; -} - -static inline void c3x_set_iof( unsigned32 value ) -{ - __asm__ volatile ("ldi %0,iof" : : "g" (value) : "iof", "cc"); -} - -#endif - - -#endif -/* end if include file */ diff --git a/c/src/exec/score/cpu/c4x/configure.ac b/c/src/exec/score/cpu/c4x/configure.ac deleted file mode 100644 index c181e52669..0000000000 --- a/c/src/exec/score/cpu/c4x/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-c4x],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/c4x/cpu.c b/c/src/exec/score/cpu/c4x/cpu.c deleted file mode 100644 index 44d43f837a..0000000000 --- a/c/src/exec/score/cpu/c4x/cpu.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * C4x CPU Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> - - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - * - * C4x Specific Information: - * - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ -#if 0 - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; -#endif - -#if (CPU_HARDWARE_FP == TRUE) - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ -#endif - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * C4x Specific Information: - * - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - void **ittp; - - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ - - ittp = c4x_get_ittp(); - *old_handler = ittp[ vector ]; - ittp[ vector ] = new_handler; -} - -/*XXX */ - -#define C4X_CACHE 1 -#define C4X_BASE_ST (C4X_CACHE==1) ? 0x4800 : 0x4000 - -void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - unsigned32 _size, - unsigned32 _isr, - void (*_entry_point)(void), - int _is_fp -) -{ - unsigned int *_stack; - _stack = (unsigned int *)_stack_base; - - *_stack = (unsigned int) _entry_point; - _the_context->sp = (unsigned int) _stack; - _the_context->st = C4X_BASE_ST; - if ( _isr == 0 ) - _the_context->st |= C4X_ST_GIE; -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - * - * C4x Specific Information: - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - proc_ptr ignored; - extern void rtems_irq_prologue_0(void); - extern void rtems_irq_prologue_1(void); - void *entry; - - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - entry = (void *)rtems_irq_prologue_0 + - ((rtems_irq_prologue_1 - rtems_irq_prologue_0) * vector); - _CPU_ISR_install_raw_handler( vector, entry, &ignored ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - * - * C4x Specific Information: - * - * - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == 1) -void _CPU_Thread_Idle_body( void ) -{ - - for( ; ; ) { - __asm__( "idle" ); - __asm__( "nop" ); - __asm__( "nop" ); - __asm__( "nop" ); - /* insert your "halt" instruction here */ ; - } -} -#endif diff --git a/c/src/exec/score/cpu/c4x/cpu_asm.S b/c/src/exec/score/cpu/c4x/cpu_asm.S deleted file mode 100644 index 9dbc227563..0000000000 --- a/c/src/exec/score/cpu/c4x/cpu_asm.S +++ /dev/null @@ -1,770 +0,0 @@ -/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s - * - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * NOTE: This is supposed to be a .S or .s file NOT a C file. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <asm.h> - -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - * - * void _CPU_Context_save_fp( - * void **fp_context_ptr - * - * C4x Specific Information: - * - * There is no distiniction between FP and integer context in this port. - */ - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - * - * void _CPU_Context_restore_fp( - * void **fp_context_ptr - * ) - * - * C4x Specific Information: - * - * There is no distiniction between FP and integer context in this port. - */ - - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - * - * void _CPU_Context_switch( - * Context_Control *run, - * Context_Control *heir - * ) - * - * TMS320C3x General-Purpose Applications User's Guide, section 2.4 - * (p 2-11 and following), Context Switching in Interrupts and - * Subroutines states that "If the program is in a subroutine, it - * must preserve the dedicated C registers as follows:" - * - * Save as Integers Save as Floating-Point - * ================ ====================== - * R4 R8 R6 R7 - * AR4 AR5 - * AR6 AR7 - * FP DP (small model only) - * SP - */ - - .global SYM(_CPU_Context_switch) -SYM(_CPU_Context_switch): - .if .REGPARM == 0 - ldi sp, ar0 - ldi *ar0, ar2 ; get the location of running context - .endif - sti st,*ar2++ ; store status word - sti ar3,*ar2++ ; store ar3 - sti ar4,*ar2++ ; store ar4 - sti ar5,*ar2++ ; store ar5 - sti ar6,*ar2++ ; store ar6 - sti ar7,*ar2++ ; store ar7 - sti r4,*ar2++ ; store integer portion of r4 - sti r5,*ar2++ ; store integer portion of r5 - stf r6,*ar2++ ; store float portion of r6 - stf r7,*ar2++ ; store float portion of r7 - .if .TMS320C40 - sti r8,*ar2++ ; store integer portion of r8 - .endif - sti sp,*ar2++ ; store sp - - ; end of save - - .if .REGPARM == 0 - ldi *-ar0(2), ar2 ; get the location of heir context - .else - ldi r2,ar2 - .endif -_local_restore: - ldi *ar2++,ar0 ; load status word into register - ldi *ar2++,ar3 ; load ar3 - ldi *ar2++,ar4 ; load ar4 - ldi *ar2++,ar5 ; load ar5 - ldi *ar2++,ar6 ; load ar6 - ldi *ar2++,ar7 ; load ar7 - ldi *ar2++,r4 ; load integer portion of r4 - ldi *ar2++,r5 ; load integer portion of r5 - ldf *ar2++,r6 ; load float portion of r6 - ldf *ar2++,r7 ; load float portion of r7 - .if .TMS320C40 - ldi *ar2++,r8 ; load integer portion of r8 - .endif - ldi *ar2++,sp ; load sp - ldi ar0,st ; restore status word and interrupts - rets - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * void _CPU_Context_restore( - * Context_Control *new_context - * ) - */ - - .global SYM(_CPU_Context_restore) -SYM(_CPU_Context_restore): - .if .REGPARM == 0 - ldi sp, ar0 - ldi *ar0, ar2 ; get the location of context to restore - .endif - br _local_restore - -/* void _ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * void _ISR_Handler() - */ - - /* - * At entry to "common" _ISR_Handler, the vector number must be - * available. On some CPUs the hardware puts either the vector - * number or the offset into the vector table for this ISR in a - * known place. If the hardware does not give us this information, - * then the assembly portion of RTEMS for this port will contain - * a set of distinct interrupt entry points which somehow place - * the vector number in a known place (which is safe if another - * interrupt nests this one) and branches to _ISR_Handler. - */ - - /* - * save some or all context on stack - * may need to save some special interrupt information for exit - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * if ( _ISR_Nest_level == 0 ) - * switch to software interrupt stack - * #endif - * - * _ISR_Nest_level++; - * - * _Thread_Dispatch_disable_level++; - * - * (*_ISR_Vector_table[ vector ])( vector ); - * - * --_ISR_Nest_level; - * - * if ( _ISR_Nest_level ) - * goto the label "exit interrupt (simple case)" - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * restore stack - * #endif - * - * if ( !_Context_Switch_necessary ) - * goto the label "exit interrupt (simple case)" - * - * if ( !_ISR_Signals_to_thread_executing ) - * _ISR_Signals_to_thread_executing = FALSE; - * goto the label "exit interrupt (simple case)" - * - * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch - * - * prepare to get out of interrupt - * return from interrupt (maybe to _ISR_Dispatch) - * - * LABEL "exit interrupt (simple case): - * prepare to get out of interrupt - * return from interrupt - */ - - .global SYM(_ISR_Handler_save_registers) -SYM(_ISR_Handler_save_registers): - ; no push st because it is already pushed - ; no push ar2 because it is already pushed and vector number loaded - push ar0 - push ar1 - push dp - push ir0 - push ir1 - push rs - push re - push rc - push bk - - push r0 - pushf r0 - push r1 - pushf r1 - push r2 - pushf r2 - push r3 - pushf r3 - ; no push r4 because other part of register is in basic context - push r4 - pushf r4 - ; no push r5 because other part of register is in basic context - push r5 - pushf r5 - push r6 - pushf r6 - ; no pushf r6 because other part of register is in basic context - push r7 - pushf r7 - ; no pushf r7 because other part of register is in basic context - .if .TMS320C40 - push r8 - ; no pushf r8 because other part of register is in basic context - push r9 - pushf r9 - push r10 - pushf r10 - push r11 - pushf r11 - .endif - - ldi sp,r2 - call SYM(__ISR_Handler) - - .if .TMS320C40 - popf r11 - pop r11 - popf r10 - pop r10 - popf r9 - pop r9 - ; no popf r8 because other part of register is in basic context - pop r8 - .endif - ; no popf r7 because other part of register is in basic context - popf r7 - pop r7 - ; no popf r6 because other part of register is in basic context - popf r6 - pop r6 - ; no popf r5 because other part of register is in basic context - popf r5 - pop r5 - ; no pop r4 because other part of register is in basic context - popf r4 - pop r4 - popf r3 - pop r3 - popf r2 - pop r2 - popf r1 - pop r1 - popf r0 - pop r0 - - pop bk - pop rc - pop re - pop rs - pop ir1 - pop ir0 - pop dp - pop ar1 - pop ar0 - pop ar2 ; because the vector numbers goes here - pop st - reti - -/* - * Prologues so we can know the vector number. Generated by this script: - * - * i=0 - * while test $i -lt 64 - * do - * - * printf "\t.global\tSYM(rtems_irq_prologue_%X)\n" $i - * printf "SYM(rtems_irq_prologue_%X):\n" $i - * printf "\tpush\tst\n" - * printf "\tpush\tar2\n" - * printf "\tldi\t0x%x,ar2\n" $i - * printf "\tbr\tSYM(_ISR_Handler_save_registers)\n" - * printf "\n" - * i=`expr $i + 1` - * - * done - */ - - .global SYM(rtems_irq_prologue_0) -SYM(rtems_irq_prologue_0): - push st - push ar2 - ldi 0x0,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1) -SYM(rtems_irq_prologue_1): - push st - push ar2 - ldi 0x1,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2) -SYM(rtems_irq_prologue_2): - push st - push ar2 - ldi 0x2,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3) -SYM(rtems_irq_prologue_3): - push st - push ar2 - ldi 0x3,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_4) -SYM(rtems_irq_prologue_4): - push st - push ar2 - ldi 0x4,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_5) -SYM(rtems_irq_prologue_5): - push st - push ar2 - ldi 0x5,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_6) -SYM(rtems_irq_prologue_6): - push st - push ar2 - ldi 0x6,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_7) -SYM(rtems_irq_prologue_7): - push st - push ar2 - ldi 0x7,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_8) -SYM(rtems_irq_prologue_8): - push st - push ar2 - ldi 0x8,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_9) -SYM(rtems_irq_prologue_9): - push st - push ar2 - ldi 0x9,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_A) -SYM(rtems_irq_prologue_A): - push st - push ar2 - ldi 0xa,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_B) -SYM(rtems_irq_prologue_B): - push st - push ar2 - ldi 0xb,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_C) -SYM(rtems_irq_prologue_C): - push st - push ar2 - ldi 0xc,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_D) -SYM(rtems_irq_prologue_D): - push st - push ar2 - ldi 0xd,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_E) -SYM(rtems_irq_prologue_E): - push st - push ar2 - ldi 0xe,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_F) -SYM(rtems_irq_prologue_F): - push st - push ar2 - ldi 0xf,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_10) -SYM(rtems_irq_prologue_10): - push st - push ar2 - ldi 0x10,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_11) -SYM(rtems_irq_prologue_11): - push st - push ar2 - ldi 0x11,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_12) -SYM(rtems_irq_prologue_12): - push st - push ar2 - ldi 0x12,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_13) -SYM(rtems_irq_prologue_13): - push st - push ar2 - ldi 0x13,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_14) -SYM(rtems_irq_prologue_14): - push st - push ar2 - ldi 0x14,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_15) -SYM(rtems_irq_prologue_15): - push st - push ar2 - ldi 0x15,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_16) -SYM(rtems_irq_prologue_16): - push st - push ar2 - ldi 0x16,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_17) -SYM(rtems_irq_prologue_17): - push st - push ar2 - ldi 0x17,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_18) -SYM(rtems_irq_prologue_18): - push st - push ar2 - ldi 0x18,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_19) -SYM(rtems_irq_prologue_19): - push st - push ar2 - ldi 0x19,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1A) -SYM(rtems_irq_prologue_1A): - push st - push ar2 - ldi 0x1a,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1B) -SYM(rtems_irq_prologue_1B): - push st - push ar2 - ldi 0x1b,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1C) -SYM(rtems_irq_prologue_1C): - push st - push ar2 - ldi 0x1c,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1D) -SYM(rtems_irq_prologue_1D): - push st - push ar2 - ldi 0x1d,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1E) -SYM(rtems_irq_prologue_1E): - push st - push ar2 - ldi 0x1e,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_1F) -SYM(rtems_irq_prologue_1F): - push st - push ar2 - ldi 0x1f,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_20) -SYM(rtems_irq_prologue_20): - push st - push ar2 - ldi 0x20,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_21) -SYM(rtems_irq_prologue_21): - push st - push ar2 - ldi 0x21,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_22) -SYM(rtems_irq_prologue_22): - push st - push ar2 - ldi 0x22,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_23) -SYM(rtems_irq_prologue_23): - push st - push ar2 - ldi 0x23,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_24) -SYM(rtems_irq_prologue_24): - push st - push ar2 - ldi 0x24,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_25) -SYM(rtems_irq_prologue_25): - push st - push ar2 - ldi 0x25,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_26) -SYM(rtems_irq_prologue_26): - push st - push ar2 - ldi 0x26,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_27) -SYM(rtems_irq_prologue_27): - push st - push ar2 - ldi 0x27,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_28) -SYM(rtems_irq_prologue_28): - push st - push ar2 - ldi 0x28,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_29) -SYM(rtems_irq_prologue_29): - push st - push ar2 - ldi 0x29,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2A) -SYM(rtems_irq_prologue_2A): - push st - push ar2 - ldi 0x2a,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2B) -SYM(rtems_irq_prologue_2B): - push st - push ar2 - ldi 0x2b,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2C) -SYM(rtems_irq_prologue_2C): - push st - push ar2 - ldi 0x2c,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2D) -SYM(rtems_irq_prologue_2D): - push st - push ar2 - ldi 0x2d,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2E) -SYM(rtems_irq_prologue_2E): - push st - push ar2 - ldi 0x2e,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_2F) -SYM(rtems_irq_prologue_2F): - push st - push ar2 - ldi 0x2f,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_30) -SYM(rtems_irq_prologue_30): - push st - push ar2 - ldi 0x30,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_31) -SYM(rtems_irq_prologue_31): - push st - push ar2 - ldi 0x31,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_32) -SYM(rtems_irq_prologue_32): - push st - push ar2 - ldi 0x32,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_33) -SYM(rtems_irq_prologue_33): - push st - push ar2 - ldi 0x33,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_34) -SYM(rtems_irq_prologue_34): - push st - push ar2 - ldi 0x34,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_35) -SYM(rtems_irq_prologue_35): - push st - push ar2 - ldi 0x35,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_36) -SYM(rtems_irq_prologue_36): - push st - push ar2 - ldi 0x36,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_37) -SYM(rtems_irq_prologue_37): - push st - push ar2 - ldi 0x37,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_38) -SYM(rtems_irq_prologue_38): - push st - push ar2 - ldi 0x38,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_39) -SYM(rtems_irq_prologue_39): - push st - push ar2 - ldi 0x39,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3A) -SYM(rtems_irq_prologue_3A): - push st - push ar2 - ldi 0x3a,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3B) -SYM(rtems_irq_prologue_3B): - push st - push ar2 - ldi 0x3b,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3C) -SYM(rtems_irq_prologue_3C): - push st - push ar2 - ldi 0x3c,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3D) -SYM(rtems_irq_prologue_3D): - push st - push ar2 - ldi 0x3d,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3E) -SYM(rtems_irq_prologue_3E): - push st - push ar2 - ldi 0x3e,ar2 - br SYM(_ISR_Handler_save_registers) - - .global SYM(rtems_irq_prologue_3F) -SYM(rtems_irq_prologue_3F): - push st - push ar2 - ldi 0x3f,ar2 - br SYM(_ISR_Handler_save_registers) - diff --git a/c/src/exec/score/cpu/c4x/irq.c b/c/src/exec/score/cpu/c4x/irq.c deleted file mode 100644 index 055bae40c4..0000000000 --- a/c/src/exec/score/cpu/c4x/irq.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * C4x CPU Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/cpu.h> -#include <rtems/score/isr.h> -#include <rtems/score/thread.h> - -/* - * This routine provides the RTEMS interrupt management. - */ - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - unsigned long *_old_stack_ptr; -#endif - -register unsigned long *stack_ptr asm("sp"); - -void __ISR_Handler(unsigned32 vector, void *isr_sp) -{ - register unsigned32 level; - - /* already disabled when we get here */ - /* _CPU_ISR_Disable( level ); */ - - _Thread_Dispatch_disable_level++; - -#if 0 - if ( stack_ptr > (_Thread_Executing->Start.stack + - _Thread_Executing->Start.Initial_stack.size) ) { - printk( "Blown interrupt stack at 0x%x\n", stack_ptr ); - } -#endif - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - if ( _ISR_Nest_level == 0 ) { - /* Install irq stack */ - _old_stack_ptr = stack_ptr; - stack_ptr = _CPU_Interrupt_stack_low; - } -#endif - - _ISR_Nest_level++; - - /* leave it to the ISR to decide if they get reenabled */ - /* _CPU_ISR_Enable( level ); */ - - /* call isp */ - if ( _ISR_Vector_table[ vector] ) - (*_ISR_Vector_table[ vector ])( - vector, isr_sp - sizeof(CPU_Interrupt_frame) + 1 ); - - _CPU_ISR_Disable( level ); - - _ISR_Nest_level--; - -#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) - if ( _ISR_Nest_level == 0 ) /* restore old stack pointer */ - stack_ptr = _old_stack_ptr; -#endif - - _Thread_Dispatch_disable_level--; - - _CPU_ISR_Enable( level ); - if ( _Thread_Dispatch_disable_level == 0 ) { - if ( _Context_Switch_necessary || !_ISR_Signals_to_thread_executing ) { - _ISR_Signals_to_thread_executing = FALSE; - _Thread_Dispatch(); - } - } -} diff --git a/c/src/exec/score/cpu/c4x/rtems/.cvsignore b/c/src/exec/score/cpu/c4x/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/c4x/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/c4x/rtems/score/.cvsignore b/c/src/exec/score/cpu/c4x/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/c4x/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/c4x/rtems/score/c4x.h b/c/src/exec/score/cpu/c4x/rtems/score/c4x.h deleted file mode 100644 index 757b8ea012..0000000000 --- a/c/src/exec/score/cpu/c4x/rtems/score/c4x.h +++ /dev/null @@ -1,365 +0,0 @@ -/* c4x.h - * - * This file is an example (i.e. "no CPU") of the file which is - * created for each CPU family port of RTEMS. - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ - -#ifndef _INCLUDE_C4X_h -#define _INCLUDE_C4X_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "no cpu" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -#if defined(_C30) -#define CPU_MODEL_NAME "C30" - -#elif defined(_C31) -#define CPU_MODEL_NAME "C31" - -#elif defined(_C32) -#define CPU_MODEL_NAME "C32" - -#elif defined(_C33) -#define CPU_MODEL_NAME "C33" - -#elif defined(_C40) -#define CPU_MODEL_NAME "C40" - -#elif defined(_C44) -#define CPU_MODEL_NAME "C44" - -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "Texas Instruments C3x/C4x" - -/* - * This port is a little unusual in that even though there are "floating - * point registers", the notion of floating point is very inherent to - * applications. In addition, the calling conventions require that - * only a few extended registers be preserved across subroutine calls. - * The overhead of including these few registers in the basic - * context is small compared to the overhead of managing the notion - * of separate floating point contexts. So we decided to pretend that - * there is no FPU on the C3x or C4x. - */ - -#define C4X_HAS_FPU 0 - -/* - * Routines to manipulate the bits in the Status Word (ST). - */ - -#define C4X_ST_C 0x0001 -#define C4X_ST_V 0x0002 -#define C4X_ST_Z 0x0004 -#define C4X_ST_N 0x0008 -#define C4X_ST_UF 0x0010 -#define C4X_ST_LV 0x0020 -#define C4X_ST_LUF 0x0040 -#define C4X_ST_OVM 0x0080 -#define C4X_ST_RM 0x0100 -#define C4X_ST_CF 0x0400 -#define C4X_ST_CE 0x0800 -#define C4X_ST_CC 0x1000 -#define C4X_ST_GIE 0x2000 - -#ifndef _TMS320C40 -#define C3X_IE_INTERRUPT_MASK_BITS 0xffff -#define C3x_IE_INTERRUPTS_ALL_ENABLED 0x0000 -#define C3x_IE_INTERRUPTS_ALL_DISABLED 0xffff -#endif - -#ifndef ASM - -/* - * A nop macro. - */ - -#define c4x_nop() \ - __asm__("nop"); - -/* - * Routines to set and clear individual bits in the ST (status word). - * - * cpu_st_bit_clear - clear bit in ST - * cpu_st_bit_set - set bit in ST - * cpu_st_get - obtain entire ST - */ - -#ifdef _TMS320C40 -#define c4x_gie_nop() -#else -#define c4x_gie_nop() { c4x_nop(); c4x_nop(); } -#endif - -#define cpu_st_bit_clear(_st_bit) \ - do { \ - __asm__("andn %0,st" : : "g" (_st_bit) : "cc"); \ - c4x_gie_nop(); \ - } while (0) - -#define cpu_st_bit_set(_st_bit) \ - do { \ - __asm__("or %0,st" : : "g" (_st_bit) : "cc"); \ - c4x_gie_nop(); \ - } while (0) - -static inline unsigned int cpu_st_get(void) -{ - register unsigned int st_value; - __asm__("ldi st, %0" : "=r" (st_value)); - return st_value; -} - -/* - * Routines to manipulate the Global Interrupt Enable (GIE) bit in - * the Status Word (ST). - * - * c4x_global_interrupts_get - returns current GIE setting - * c4x_global_interrupts_disable - disables global interrupts - * c4x_global_interrupts_enable - enables global interrupts - * c4x_global_interrupts_restore - restores GIE to pre-disable state - * c4x_global_interrupts_flash - temporarily enable global interrupts - */ - -#define c4x_global_interrupts_get() \ - (cpu_st_get() & C4X_ST_GIE) - -#define c4x_global_interrupts_disable() \ - cpu_st_bit_clear(C4X_ST_GIE) - -#define c4x_global_interrupts_enable() \ - cpu_st_bit_set(C4X_ST_GIE) - -#define c4x_global_interrupts_restore(_old_level) \ - cpu_st_bit_set(_old_level) - -#define c4x_global_interrupts_flash(_old_level) \ - do { \ - cpu_st_bit_set(_old_level); \ - cpu_st_bit_clear(C4X_ST_GIE); \ - } while (0) - -#ifndef _TMS320C40 - -/* - * Routines to set and get the IF register - * - * c3x_get_if - obtains IF register - * c3x_set_if - sets IF register - */ - -static inline unsigned int c3x_get_if(void) -{ - register unsigned int _if_value; - - __asm__( "ldi if, %0" : "=r" (_if_value) ); - return _if_value; -} - -static inline void c3x_set_if(unsigned int _if_value) -{ - __asm__( "ldi %0, if" : : "g" (_if_value) : "if", "cc"); -} - -/* - * Routines to set and get the IE register - * - * c3x_get_ie - obtains IE register - * c3x_set_ie - sets IE register - */ - -static inline unsigned int c3x_get_ie(void) -{ - register unsigned int _ie_value; - - __asm__ volatile ( "ldi ie, %0" : "=r" (_ie_value) ); - return _ie_value; -} - -static inline void c3x_set_ie(unsigned int _ie_value) -{ - __asm__ volatile ( "ldi %0, ie" : : "g" (_ie_value) : "ie", "cc"); -} - -/* - * Routines to manipulates the mask portion of the IE register. - * - * c3x_ie_mask_all - returns previous IE mask - * c3x_ie_mask_restore - restores previous IE mask - * c3x_ie_mask_flash - temporarily restores previous IE mask - * c3x_ie_mask_set - sets a specific set of the IE mask - */ - -#define c3x_ie_mask_all( _isr_cookie ) \ - do { \ - __asm__("ldi ie,%0\n" \ - "\tandn 0ffffh, ie" \ - : "=r" (_isr_cookie): : "ie", "cc" ); \ - } while (0) - -#define c3x_ie_mask_restore( _isr_cookie ) \ - do { \ - __asm__("or %0, ie" \ - : : "g" (_isr_cookie) : "ie", "cc" ); \ - } while (0) - -#define c3x_ie_mask_flash( _isr_cookie ) \ - do { \ - __asm__("or %0, ie\n" \ - "\tandn 0ffffh, ie" \ - : : "g" (_isr_cookie) : "ie", "cc" ); \ - } while (0) - -#define c3x_ie_mask_set( _new_mask ) \ - do { unsigned int _ie_mask; \ - unsigned int _ie_value; \ - \ - if ( _new_mask == 0 ) _ie_mask = 0; \ - else _ie_mask = 0xffff; \ - _ie_value = c3x_get_ie(); \ - _ie_value &= C4X_IE_INTERRUPT_MASK_BITS; \ - _ie_value |= _ie_mask; \ - c3x_set_ie(_ie_value); \ - } while (0) -#endif -/* end of C3x specific interrupt flag routines */ - -/* - * This is a section of C4x specific interrupt flag management routines. - */ - -#ifdef _TMS320C40 - -/* - * Routines to set and get the IIF register - * - * c4x_get_iif - obtains IIF register - * c4x_set_iif - sets IIF register - */ - -static inline unsigned int c4x_get_iif(void) -{ - register unsigned int _iif_value; - - __asm__( "ldi iif, %0" : "=r" (_iif_value) ); - return _iif_value; -} - -static inline void c4x_set_iif(unsigned int _iif_value) -{ - __asm__( "ldi %0, iif" : : "g" (_iif_value) : "iif", "cc"); -} - -/* - * Routines to set and get the IIE register - * - * c4x_get_iie - obtains IIE register - * c4x_set_iie - sets IIE register - */ - -static inline unsigned int c4x_get_iie(void) -{ - register unsigned int _iie_value; - - __asm__( "ldi iie, %0" : "=r" (_iie_value) ); - return _iie_value; -} - -static inline void c4x_set_iie(unsigned int _iie_value) -{ - __asm__( "ldi %0, iie" : : "g" (_iie_value) : "iie", "cc"); -} - -/* - * Routines to manipulates the mask portion of the IIE register. - * - * c4x_ie_mask_all - returns previous IIE mask - * c4x_ie_mask_restore - restores previous IIE mask - * c4x_ie_mask_flash - temporarily restores previous IIE mask - * c4x_ie_mask_set - sets a specific set of the IIE mask - */ - -#if 0 -#warning "C4x IIE masking routines not implemented." -#define c4x_iie_mask_all( _isr_cookie ) -#define c4x_iie_mask_restore( _isr_cookie ) -#define c4x_iie_mask_flash( _isr_cookie ) -#define c4x_iie_mask_set( _new_mask ) -#endif - -#endif -/* end of C4x specific interrupt flag routines */ - -/* - * Routines to access the Interrupt Trap Table Pointer - * - * c4x_get_ittp - get ITTP - * c4x_set_ittp - set ITTP - */ - -static inline void * c4x_get_ittp(void) -{ - register unsigned int _if_value; - - __asm__( "ldi if, %0" : "=r" (_if_value) ); - return (void *)((_if_value & 0xffff0000) >> 8); -} - -static inline void c4x_set_ittp(void *_ittp_value) -{ - unsigned int _if_value; - unsigned int _ittp_field; - -#ifdef _TMS320C40 - _if_value = c4x_get_iif(); -#else - _if_value = c3x_get_if(); -#endif - _if_value &= 0xffff; - _ittp_field = (((unsigned int) _ittp_value) >> 8); - _if_value |= _ittp_field << 16 ; -#ifdef _TMS320C40 - c4x_set_iif( _if_value ); -#else - c3x_set_if( _if_value ); -#endif -} - -#endif /* ifndef ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_C4X_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/c4x/rtems/score/cpu.h b/c/src/exec/score/cpu/c4x/rtems/score/cpu.h deleted file mode 100644 index f42895c4f1..0000000000 --- a/c/src/exec/score/cpu/c4x/rtems/score/cpu.h +++ /dev/null @@ -1,1268 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the C4x - * processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/c4x.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * C4x Specific Information: - * - * We might as well try to inline this code until there is a - * code space problem. - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - * - * C4x Specific Information: - * - * We might as well unroll this loop until there is a reason not to do so. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * C4x Specific Information: - * - * Initial investigation indicates a software managed stack will be needed. - * But the implementation does not currently include support for one. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * C4x Specific Information: - * - * XXXanswer - * - * Initial investigation indicates a software managed stack will be needed. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - * C4x Specific Information: - * - * XXXanswer - * - * Until we know what to do with the memory, we should not allocated it. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * C4x Specific Information: - * - * XXXanswer - * - * The interrupt code will have to be written before this is answered - * but the answer should be yes. - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "C4X_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * C4x Specific Information: - * - * See c4x.h for more details but the bottom line is that the - * few extended registers required to be preserved across subroutines - * calls are considered part of the integer context. This eliminates - * overhead. - * - * The C4X_HAS_FPU refers to the extended precision registers R0-R7 - * (plus R8-R11 on some models). - * - * XXX check that we even need to have the context area pointer in - * the TCB in this case. - */ - -#if ( C4X_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * C4x Specific Information: - * - * There is no known reason to make all tasks include the extended - * precision registers (i.e. floating point context). - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * C4x Specific Information: - * - * There is no known reason to make the IDLE task floating point and - * no point in wasting the memory or increasing the context switch - * time for the IDLE task. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * C4x Specific Information: - * - * There is no reason to avoid the deferred FP switch logic on this - * CPU family. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * C4x Specific Information: - * - * There is currently no reason to avoid using the generic implementation. - * In the future, a C4x specific IDLE thread body may be added to take - * advantage of low power modes. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * C4x Specific Information: - * - * The system stack grows from low to high memory. - * - * C4x Specific Information: - * - * This setting was derived from the discussion of stack management - * in section 6.1 (p. 6-29) System and User Stack Management of the - * TMS32C3x User's Guide (rev L, July 1997) which states: "A push - * performs a preincrement, and a pop performs a postdecrement of the - * system-stack pointer." There are instructions for making "a stack" - * run from high to low memory but this appears to be the exception. - */ - -#define CPU_STACK_GROWS_UP TRUE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * C4x Specific Information: - * - * The C4x is word oriented and there should be no alignment issues. - */ - -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * C4x Specific Information: - * - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * C4x Specific Information: - * - * Currently we are only supporting interrupt levels 0 (all on) and - * 1 (all off). Levels 2-255 COULD be looked up in a user provided - * table that gives GIE and IE Mask settings. But this is not the - * case today. - */ - -#define CPU_MODES_INTERRUPT_MASK 0x000000FF - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - * - * C4x Specific Information: - * - * XXXanswer - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * C4x Specific Information: - * - * From email with Michael Hayes: - * > > But what are the rules for what is passed in what registers? - * - * Args are passed in the following registers (in order): - * - * AR2, R2, R3, RC, RS, RE - * - * However, the first and second floating point values are always in R2 - * and R3 (and all other floats are on the stack). Structs are always - * passed on the stack. If the last argument is an ellipsis, the - * previous argument is passed on the stack so that its address can be - * taken for the stdargs macros. - * - * > > What is assumed to be preserved across calls? - * - * AR3, AR4, AR5, AR6, AR7 - * R4, R5, R8 (using STI/LDI) - * R6, R7 (using STF/LDF) - * - * > > What is assumed to be scratch registers? - * - * R0, R1, R2, R3, AR0, AR1, AR2, IR0, IR1, BK, RS, RE, RC, R9, R10, R11 - * - * Based on this information, the task specific context is quite small - * but the interrupt context is much larger. In fact, it could - * easily be argued that there is no point in distinguishing between - * integer and floating point contexts on the Cxx since there is - * so little context involved. So that is the decision made. - * - * Not Mentioned in list: DP - * - * Assumed to be global resources: - * - * C3X: IE, IF, and IOF - * C4X: DIE, IIF, and IIF - */ - - -typedef struct { - unsigned int st; - unsigned int ar3; - unsigned int ar4; - unsigned int ar5; - unsigned int ar6; - unsigned int ar7; - unsigned int r4_sti; /* other part of register is in interrupt context */ - unsigned int r5_sti; /* other part of register is in interrupt context */ - unsigned int r6_stf; /* other part of register is in interrupt context */ - unsigned int r7_stf; /* other part of register is in interrupt context */ -#ifdef _TMS320C40 - unsigned int r8_sti; /* other part of register is in interrupt context */ -#endif - unsigned int sp; -} Context_Control; - -typedef struct { -} Context_Control_fp; - -/* - * This is the order the interrupt entry code pushes the registers. - */ - -typedef struct { - void *interrupted; - unsigned int st; - unsigned int ar2; /* because the vector numbers goes here */ - unsigned int ar0; - unsigned int ar1; - unsigned int dp; - unsigned int ir0; - unsigned int ir1; - unsigned int rs; - unsigned int re; - unsigned int rc; - unsigned int bk; - unsigned int r0_sti; - unsigned int r0_stf; - unsigned int r1_sti; - unsigned int r1_stf; - unsigned int r2_sti; - unsigned int r2_stf; - unsigned int r3_sti; - unsigned int r3_stf; - unsigned int r4_stf; /* other part of register is in basic context */ - unsigned int r5_stf; /* other part of register is in basic context */ - unsigned int r6_sti; /* other part of register is in basic context */ - unsigned int r7_sti; /* other part of register is in basic context */ - -#ifdef _TMS320C40 - unsigned int r8_sti; /* other part of register is in basic context */ - unsigned int r9_sti; - unsigned int r9_stf; - unsigned int r10_sti; - unsigned int r10_stf; - unsigned int r11_sti; - unsigned int r11_stf; -#endif - -} CPU_Interrupt_frame; - -/* - * The following table contains the information required to configure - * the C4x processor specific parameters. - * - * C4x Specific Information: - * - * XXXanswer - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access C4X specific additions to the CPU Table - * - * C4x Specific Information: - * - * XXXanswer - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -#if 0 -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * C4x Specific Information: - * - * Unused - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -#endif - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * C4x Specific Information: - * - * XXXanswer - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - * - * C4x Specific Information: - * - * This port should not require this. - */ - -#if 0 -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); -#endif - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * C4x Specific Information: - * - * XXXanswer - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * C4x Specific Information: - * - * If we decide to have a separate floating point context, then - * the answer is the size of the data structure. Otherwise, we - * need to define it as 0 to let upper level configuration work. - */ - -#if ( C4X_HAS_FPU == 1 ) -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) -#else -#define CPU_CONTEXT_FP_SIZE 0 -#endif - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * C4x Specific Information: - * - * Based on the information provided in section 7.6.1 (p. 7-26) - * titled "TMS320C30 and TMS320C31 Interrupt Vector Table" and section - * 7.6.2 "TMS320C32 Interrupt Vector Table" of the TMS32C3x User's - * Guide (rev L, July 1997), vectors are numbered 0x00 - 0x3F. Thus - * there are 0x40 or 64 vectors. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 0x40 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define CPU_STACK_MINIMUM_SIZE (1024) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * C4x Specific Information: - * - * XXXanswer - * As best I can tell, there are no restrictions since this is a word - * -- not byte -- oriented archtiecture. - */ - -#define CPU_ALIGNMENT 0 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * C4x Specific Information: - * - * XXXanswer - * - * A CPU_HEAP_ALIGNMENT of 2 comes close to disabling all the rounding - * while still ensuring that the least significant bit of the front - * and back flags can be used as the used bit -- not part of the size. - */ - -#define CPU_HEAP_ALIGNMENT 2 - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * C4x Specific Information: - * - * XXXanswer - * I think a CPU_PARTITION_ALIGNMENT of 1 will effectively disable all - * the rounding. - */ - -#define CPU_PARTITION_ALIGNMENT 1 - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - * - * C4x Specific Information: - * - * These macros disable interrupts using the GIE (global interrupts enable) - * bit in the status word. - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _isr_cookie. - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - (_isr_cookie) = c4x_global_interrupts_get(); \ - c4x_global_interrupts_disable(); \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _isr_cookie is not modified. - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - c4x_global_interrupts_restore( _isr_cookie ) - -/* - * This temporarily restores the interrupt to _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _isr_cookie is not - * modified. - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - c4x_global_interrupts_flash( _isr_cookie ) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - * C4x Specific Information: - * - * The C4x port probably needs to allow the BSP to define - * a mask table for all values 0-255. For now, 0 is global - * interrupts enabled and and non-zero is global interrupts - * disabled. In the future, values 1-254 could be defined as - * specific combinations of the global interrupt enabled and the IE mask. - * - * The logic for setting the mask field is something like this: - * _ie_value = c4x_get_ie(); - * _ie_value &= C4X_IE_INTERRUPT_MASK_BITS; - * _ie_value |= _ie_mask; - * c4x_set_ie(_ie_value); - * - * NOTE: If this is implemented, then the context of each task - * must be extended to include the IE register. - */ - -#define _CPU_ISR_Set_level( _new_level ) \ - do { \ - if ( _new_level == 0 ) c4x_global_interrupts_enable(); \ - else c4x_global_interrupts_disable(); \ - } while (0) - -/* if GIE = 1, then logical level is 0. */ -#define _CPU_ISR_Get_level() \ - (c4x_global_interrupts_get() ? 0 : 1) - - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - unsigned32 _size, - unsigned32 _isr, - void (*_entry_point)(void), - int _is_fp -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#if ( C4X_HAS_FPU == 1 ) -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * C4x Specific Information: - * - * No Floating Point from RTEMS perspective. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) -#endif - -#if ( C4X_HAS_FPU == 1 ) -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * C4x Specific Information: - * - * No Floating Point from RTEMS perspective. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } while (0) -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#define _CPU_Fatal_halt( _error ) \ - do { \ - } while (0) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * C4x Specific Information: - * - * There does not appear to be a simple way to do this on this - * processor family that is better than the generic algorithm. - * Almost certainly, a hand-optimized assembly version of the - * generic algorithm could be written although it is not - * worth the development effort at this time. - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - do { \ - (_output) = 0; /* do something to prevent warnings */ \ - } while (0) - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * C4x Specific Information: - * - * XXXanswer - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * - * C4x Specific Information: - * - * XXXanswer - * is TRUE. - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == 1) -void _CPU_Thread_Idle_body( void ); -#endif - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * C4x Specific Information: - * - * XXXanswer - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * C4x Specific Information: - * - * No Floating Point from RTEMS perspective. - */ - -#if ( C4X_HAS_FPU == 1 ) -void _CPU_Context_save_fp( - void **fp_context_ptr -); -#endif - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * C4x Specific Information: - * - * No Floating Point from RTEMS perspective. - */ - -#if ( C4X_HAS_FPU == 1 ) -void _CPU_Context_restore_fp( - void **fp_context_ptr -); -#endif - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * C4x Specific Information: - * - * XXXanswer - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/c4x/rtems/score/cpu_asm.h b/c/src/exec/score/cpu/c4x/rtems/score/cpu_asm.h deleted file mode 100644 index b5f3673d61..0000000000 --- a/c/src/exec/score/cpu/c4x/rtems/score/cpu_asm.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * cpu_asm.h - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/c/src/exec/score/cpu/c4x/rtems/score/types.h b/c/src/exec/score/cpu/c4x/rtems/score/types.h deleted file mode 100644 index 89d7bc3c35..0000000000 --- a/c/src/exec/score/cpu/c4x/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/* c4xtypes.h - * - * This include file contains type definitions pertaining to the Intel - * C4x processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __C4X_TYPES_h -#define __C4X_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void c4x_isr; -typedef void ( *c4x_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/h8300/.cvsignore b/c/src/exec/score/cpu/h8300/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/h8300/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/h8300/ChangeLog b/c/src/exec/score/cpu/h8300/ChangeLog deleted file mode 100644 index 6d9bc588a0..0000000000 --- a/c/src/exec/score/cpu/h8300/ChangeLog +++ /dev/null @@ -1,126 +0,0 @@ -2002-07-05 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Filled in something that was marked XXX. - -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-04 Joel Sherrill <joel@OARcorp.com> - - * Makefile.am: Remove reference to deprecated rtems.c. - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Fixed comments and renamed - CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK to - CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK to be consistent with other code. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/h8300types.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2002-01-07 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/cpu.h: #include <rtems/bspIo.h>. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - * cpu_asm.S: Modify to properly dereference _ISR_Vector_table - now that it is dynamically allocated. - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-10-18 Joel Sherrill <joel@OARcorp.com> - - * cpu_asm.S, rtems/score/cpu.h: Modified to better support - multilibing. These changes result in the code being able to - compile with the default gcc settings. It is not functional - in this configuration but does compile. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/h8300/Makefile.am b/c/src/exec/score/cpu/h8300/Makefile.am deleted file mode 100644 index e910a63f3c..0000000000 --- a/c/src/exec/score/cpu/h8300/Makefile.am +++ /dev/null @@ -1,54 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/h8300.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/h8300/README b/c/src/exec/score/cpu/h8300/README deleted file mode 100644 index a55c61c662..0000000000 --- a/c/src/exec/score/cpu/h8300/README +++ /dev/null @@ -1,31 +0,0 @@ -# -# $Id$ -# - - -This port was done by Philip Quaife <philip@qs.co.nz> of Q Solutions -using RTEMS 3.5.1 under DOS and Hiview. Philip used an H8300H -to develop and test this port. - -It was updated to 4.5 and merged into the main development trunk -by Joel Sherrill <joel@OARcorp.com>. As part of the merger, the -port was made to conditionally compile for the H8, H8300H, and H8300S -series. - -The status of each CPU subfamily is as follows. - -H8 - Although RTEMS compiles with for these CPUs, it does not - truly support them. All code that will not work on these - CPUs is conditionally disabled. These CPUs have a 16-bit - address space. Thus although a port is technically - feasible, some work will to be performed on RTEMS to - further minimize its footprint and address pointer - manipulation issues. - -H8H - Port was developed on this class of H8 so there should be - no problems. - -H8S - Port should work on this class of H8 but it is untested. - ---joel -28 June 2000 diff --git a/c/src/exec/score/cpu/h8300/asm.h b/c/src/exec/score/cpu/h8300/asm.h deleted file mode 100644 index ecd858f968..0000000000 --- a/c/src/exec/score/cpu/h8300/asm.h +++ /dev/null @@ -1,123 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __H8300_CPU_ASM_h -#define __H8300_CPU_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#define ASM -#include <rtems/score/h8300.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) - -#define er0 REG(er0) -#define er1 REG(er1) -#define er2 REG(er2) -#define er3 REG(er3) -#define er4 REG(er4) -#define er5 REG(er5) -#define er6 REG(er6) -#define er7 REG(er7) - -#define sp REG(sp) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE asm ( ".text -#define END_CODE "); -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - asm( \".h8300h\" ); - diff --git a/c/src/exec/score/cpu/h8300/configure.ac b/c/src/exec/score/cpu/h8300/configure.ac deleted file mode 100644 index 6cfb01fd98..0000000000 --- a/c/src/exec/score/cpu/h8300/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-h8300],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/h8300/cpu.c b/c/src/exec/score/cpu/h8300/cpu.c deleted file mode 100644 index f01c39d969..0000000000 --- a/c/src/exec/score/cpu/h8300/cpu.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Hitachi H8300 CPU Dependent Source - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; - - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * This routine returns the current interrupt level. - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned int _ccr; - -#if defined(__H8300__) -#warning "How do we get ccr on base CPU models" -#else - asm volatile ( "stc ccr, %0" : "=m" (_ccr) : ); -#endif - - if ( _ccr & 0x80 ) - return 1; - return 0; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - * Use Debug level IRQ Handlers - */ - H8BD_Install_IRQ(vector,new_handler,old_handler); -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -#if 0 -void _CPU_Thread_Idle_body( void ) -{ - - for( ; ; ) - IDLE_Monitor(); - /*asm(" sleep \n"); */ - /* insert your "halt" instruction here */ ; -} -#endif diff --git a/c/src/exec/score/cpu/h8300/cpu_asm.S b/c/src/exec/score/cpu/h8300/cpu_asm.S deleted file mode 100644 index 1cef5abf67..0000000000 --- a/c/src/exec/score/cpu/h8300/cpu_asm.S +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Hitachi H8 Score CPU functions - * Copyright Comnet Technologies Ltd 1999 - * - * Based on example code and other ports with this copyright: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -;.equ RUNCONTEXT_ARG, er0 -;.equ HEIRCONTEXT_ARG, er1 - -/* - * Make sure we tell the assembler what type of CPU model we are - * being compiled for. - */ - -#if defined(__H8300H__) - .h8300h -#endif -#if defined(__H8300S__) - .h8300s -#endif - .text - - .text -/* - GCC Compiled with optimisations and Wimplicit decs to ensure - that stack from doesn't change - - Supposedly R2 and R3 do not need to be saved but who knows - - Arg1 = er0 (not on stack) - Arg2 = er1 (not on stack) -*/ - - .align 2 - - .global __CPU_Context_switch - -__CPU_Context_switch: - /* Save Context */ -#if defined(__H8300H__) || defined(__H8300S__) - stc.w ccr,@(0:16,er0) - mov.l er7,@(2:16,er0) - mov.l er6,@(6:16,er0) - mov.l er5,@(10:16,er0) - mov.l er4,@(14:16,er0) - mov.l er3,@(18:16,er0) - mov.l er2,@(22:16,er0) - - /* Install New context */ - -restore: - mov.l @(22:16,er1),er2 - mov.l @(18:16,er1),er3 - mov.l @(14:16,er1),er4 - mov.l @(10:16,er1),er5 - mov.l @(6:16,er1),er6 - mov.l @(2:16,er1),er7 - ldc.w @(0:16,er1),ccr -#endif - - rts - - .align 2 - - .global __CPU_Context_restore - -__CPU_Context_restore: - -#if defined(__H8300H__) || defined(__H8300S__) - mov.l er0,er1 - jmp @restore:24 -#endif - - - -/* - VHandler for Vectored Interrupts - - All IRQ's are vectored to routine _ISR_#vector_number - This routine stacks er0 and loads er0 with vector number - before transferring to here - -*/ - .align 2 - .global __ISR_Handler - .extern __ISR_Nest_level - .extern __Vector_table - .extern __Context_switch_necessary - - -__ISR_Handler: -#if defined(__H8300H__) || defined(__H8300S__) - mov.l er1,@-er7 - mov.l er2,@-er7 - mov.l er3,@-er7 - mov.l er4,@-er7 - mov.l er5,@-er7 - mov.l er6,@-er7 - -/* Set IRQ Stack */ - orc #0xc0,ccr - mov.l er7,er6 ; save stack pointer - mov.l @__ISR_Nest_level,er1 - bne nested - mov.l @__CPU_Interrupt_stack_high,er7 - -nested: - mov.l er6,@-er7 ; save sp so pop regardless of nest level - -;; Inc system counters - mov.l @__ISR_Nest_level,er1 - inc.l #1,er1 - mov.l er1,@__ISR_Nest_level - mov.l @__Thread_Dispatch_disable_level,er1 - inc.l #1,er1 - mov.l er1,@__Thread_Dispatch_disable_level - -/* Vector to ISR */ - - mov.l @__ISR_Vector_table,er1 - mov er0,er2 ; copy vector - shll.l er2 - shll.l er2 ; vector = vector * 4 (sizeof(int)) - add.l er2,er1 - mov.l @er1,er1 - jsr @er1 ; er0 = arg1 =vector - - orc #0xc0,ccr - mov.l @__ISR_Nest_level,er1 - dec.l #1,er1 - mov.l er1,@__ISR_Nest_level - mov.l @__Thread_Dispatch_disable_level,er1 - dec.l #1,er1 - mov.l er1,@__Thread_Dispatch_disable_level - bne exit - - mov.l @__Context_Switch_necessary,er1 - bne bframe ; If yes then dispatch next task - - mov.l @__ISR_Signals_to_thread_executing,er1 - beq exit ; If no signals waiting - - /* Context switch here through ISR_Dispatch */ - -bframe: - orc #0xc0,ccr -/* Pop Stack */ - mov @er7+,er6 - mov er6,er7 - mov.l #0,er2 - mov.l er2,@__ISR_Signals_to_thread_executing - - /* Set up IRQ stack frame and dispatch to _ISR_Dispatch */ - - mov.l #0xc0000000,er2 /* Disable IRQ */ - or.l #_ISR_Dispatch,er2 - mov.l er2,@-er7 - rte - -/* Inner IRQ Return, pop flags and return */ -exit: -/* Pop Stack */ - orc #0x80,ccr - mov @er7+,er6 - mov er6,er7 - mov @er7+,er6 - mov @er7+,er5 - mov @er7+,er4 - mov @er7+,er3 - mov @er7+,er2 - mov @er7+,er1 - mov @er7+,er0 -#endif - rte - -/* - Called from ISR_Handler as a way of ending IRQ - but allowing dispatch to another task. - Must use RTE as CCR is still on stack but IRQ has been serviced. - CCR and PC occupy same word so rte can be used. - now using task stack -*/ - - .align 2 - .global _ISR_Dispatch - -_ISR_Dispatch: - -#if defined(__H8300H__) || defined(__H8300S__) - jsr @__Thread_Dispatch - mov @er7+,er6 - mov @er7+,er5 - mov @er7+,er4 - mov @er7+,er3 - mov @er7+,er2 - mov @er7+,er1 - mov @er7+,er0 -#endif - rte - - - .align 2 - .global __CPU_Context_save_fp - -__CPU_Context_save_fp: - rts - - - .align 2 - .global __CPU_Context_restore_fp - -__CPU_Context_restore_fp: - rts - diff --git a/c/src/exec/score/cpu/h8300/rtems/.cvsignore b/c/src/exec/score/cpu/h8300/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/h8300/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/h8300/rtems/score/.cvsignore b/c/src/exec/score/cpu/h8300/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/h8300/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/h8300/rtems/score/cpu.h b/c/src/exec/score/cpu/h8300/rtems/score/cpu.h deleted file mode 100644 index fc3a4011f3..0000000000 --- a/c/src/exec/score/cpu/h8300/rtems/score/cpu.h +++ /dev/null @@ -1,1187 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the H8300 - * processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/h8300.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -#include <rtems/bspIo.h> /* printk */ - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HARDWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * H8300 Specific Information: - * - * XXX - * The port initially called a BSP dependent routine called - * IDLE_Monitor. The idle task body can be overridden by - * the BSP in newer versions of RTEMS. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - * - * H8300 Specific Information: - * - * XXX - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * H8300 Specific Information: - * - * XXX - */ - - - -#define nogap __attribute__ ((packed)) - -typedef struct { - unsigned16 ccr nogap; - void *er7 nogap; - void *er6 nogap; - unsigned32 er5 nogap; - unsigned32 er4 nogap; - unsigned32 er3 nogap; - unsigned32 er2 nogap; - unsigned32 er1 nogap; - unsigned32 er0 nogap; - unsigned32 xxx nogap; -} Context_Control; - -typedef struct { - double some_float_register[2]; -} Context_Control_fp; - -typedef struct { - unsigned32 special_interrupt_register; -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the XXX processor specific parameters. - * - * NOTE: The interrupt_stack_size field is required if - * CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE. - * - * The pretasking_hook, predriver_hook, and postdriver_hook, - * and the do_zero_of_workspace fields are required on ALL CPUs. - * - * H8300 Specific Information: - * - * XXX - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); -} rtems_cpu_table; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * H8300 Specific Information: - * - * XXX - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - * - * H8300 Specific Information: - * - * XXX - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * H8300 Specific Information: - * - * XXX - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - * - * H8300 Specific Information: - * - * It is highly unlikely the H8300 will get used in a multiprocessor system. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STACK_MINIMUM_SIZE (1536) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STACK_ALIGNMENT 2 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools. - Note requires ISR_Level be unsigned16 or assembler croaks. -*/ - -#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 ) - - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - asm volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" : : "r" (_isr_cookie) ); \ - } while (0) - - -/* - * Enable interrupts to the previois level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - - -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" : : "r" (_isr_cookie) ); \ - } while (0) - - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - - -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" : : "r" (_isr_cookie) ); \ - } while (0) - -/* end of ISR handler macros */ - -#else /* modern gcc version */ - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - * H8300 Specific Information: - * - * XXX - */ - -#if defined(__H8300H__) || defined(__H8300S__) -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - unsigned char __ccr; \ - asm volatile( "stc ccr, %0 ; orc #0x80,ccr " \ - : "=m" (__ccr) : "0" (__ccr) ); \ - (_isr_cookie) = __ccr; \ - } while (0) -#else -#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0 -#endif - - -/* - * Enable interrupts to the previois level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - * H8300 Specific Information: - * - * XXX - */ - -#if defined(__H8300H__) || defined(__H8300S__) -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - unsigned char __ccr = (unsigned char) (_isr_cookie); \ - asm volatile( "ldc %0, ccr" : : "m" (__ccr) ); \ - } while (0) -#else -#define _CPU_ISR_Enable( _isr_cookie ) -#endif - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - * H8300 Specific Information: - * - * XXX - */ - -#if defined(__H8300H__) || defined(__H8300S__) -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - unsigned char __ccr = (unsigned char) (_isr_cookie); \ - asm volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \ - } while (0) -#else -#define _CPU_ISR_Flash( _isr_cookie ) -#endif - -#endif /* end of old gcc */ - - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - if ( _new_level ) asm volatile ( "orc #0x80,ccr\n" ); \ - else asm volatile ( "andc #0x7f,ccr\n" ); \ - } - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * H8300 Specific Information: - * - * XXX - */ - - -#define CPU_CCR_INTERRUPTS_ON 0x80 -#define CPU_CCR_INTERRUPTS_OFF 0x00 - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - /* Locate Me */ \ - do { \ - unsigned32 _stack; \ - \ - if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \ - else (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \ - \ - _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \ - *((proc_ptr *)(_stack)) = (_entry_point); \ - (_the_context)->er7 = (void *) _stack; \ - (_the_context)->er6 = (void *) _stack; \ - (_the_context)->er5 = 0; \ - (_the_context)->er4 = 1; \ - (_the_context)->er3 = 2; \ - } while (0) - - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) (_base) + (_offset) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Fatal_halt( _error ) \ - printk("Fatal Error %d Halted\n",_error); \ - for(;;) - - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * H8300 Specific Information: - * - * XXX - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * H8300 Specific Information: - * - * XXX - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * H8300 Specific Information: - * - * XXX - */ - -static inline unsigned32 CPU_swap_u32( - unsigned32 value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/h8300/rtems/score/h8300.h b/c/src/exec/score/cpu/h8300/rtems/score/h8300.h deleted file mode 100644 index becaed362f..0000000000 --- a/c/src/exec/score/cpu/h8300/rtems/score/h8300.h +++ /dev/null @@ -1,57 +0,0 @@ -/* h8300.h - * - * This file contains information pertaining to the Hitachi H8/300 - * processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef _INCLUDE_H8300_h -#define _INCLUDE_H8300_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "h8300" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -/* - * RTEMS compiles for the base H8 with numerous warnings but has never - * been tested on a CPU with 16 bit address space. - * - * FIXME: - * This macro is defined to handle a couple of places where - * addresses are cast to pointers. There really should be - * a "int-pointer" type that pointers are cast to before being - * mathematcically manipulated. When that is added, search - * for all references to this macro and remove them. - */ - -#if defined(__H8300__) -#define RTEMS_CPU_HAS_16_BIT_ADDRESSES 1 -#endif - -#define CPU_NAME "Hitachi H8300" -#define CPU_MODEL_NAME "h8300" -#define H8300_HAS_FPU 0 - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/h8300/rtems/score/types.h b/c/src/exec/score/cpu/h8300/rtems/score/types.h deleted file mode 100644 index d1fec2699e..0000000000 --- a/c/src/exec/score/cpu/h8300/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/* h8300types.h - * - * This include file contains type definitions pertaining to the Hitachi - * h8300 processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __H8300_TYPES_h -#define __H8300_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned long unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed long signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void h8300_isr; -typedef void ( *h8300_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/hppa1.1/.cvsignore b/c/src/exec/score/cpu/hppa1.1/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/hppa1.1/ChangeLog b/c/src/exec/score/cpu/hppa1.1/ChangeLog deleted file mode 100644 index c634275fa4..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/ChangeLog +++ /dev/null @@ -1,121 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.S: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Joel Sherrill <joel@OARcorp.com> - - * Makefile.am, cpu.c, cpu_asm.S, rtems.S: Modified to make - this all compile again. It has been a while since we have - had a semi-working hppa1.1-rtems cross compiler. :) - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/hppa.h: Remove rtems/score/targopts.h. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/hppa1.1types.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'CLEANFILES ='. - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Remove references to PROJECT_INCLUDE. - * rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - * cpu_asm.S: Modify to properly dereference _ISR_Vector_table - now that it is dynamically allocated. - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-25 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/hppa.h: Switched to using cpuopts.h not - targopts.h to reduce dependency on BSP. - -2000-09-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use PROJECT_TOPdir in path to genoffsets. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/hppa1.1/Makefile.am b/c/src/exec/score/cpu/hppa1.1/Makefile.am deleted file mode 100644 index 6563d63282..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/Makefile.am +++ /dev/null @@ -1,66 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS= -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/cpu_asm.h \ - rtems/score/hppa.h \ - rtems/score/types.h \ - rtems/score/offsets.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) rtems/score/offsets.h $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -# FIXME: We should get rid of genoffsets -GENOFFSETS = $(PROJECT_TOPdir)/tools/cpu/hppa1.1/genoffsets - -GENERIC_H_FILES = rtems/score/offsets.h -rtems/score/offsets.h: $(GENOFFSETS) rtems/score/cpu.h - $(mkinstalldirs) rtems/score - $(RM) $@ - $(GENOFFSETS) > $@ -CLEANFILES = rtems/score/offsets.h - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/hppa1.1/configure.ac b/c/src/exec/score/cpu/hppa1.1/configure.ac deleted file mode 100644 index 0d8764cdc0..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-hppa1.1],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/hppa1.1/cpu.c b/c/src/exec/score/cpu/hppa1.1/cpu.c deleted file mode 100644 index 19a5476a79..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/cpu.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * HP PA-RISC Dependent Source - * - * COPYRIGHT (c) 1994 by Division Incorporated - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -void hppa_cpu_halt(unsigned32 the_error); - - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is unsupported. For HPPA this function is handled by BSP - */ - - _CPU_Fatal_halt( 0xdeaddead ); -} - - - -/* - * This is the default handler which is called if - * _CPU_ISR_install_vector() has not been called for the - * specified vector. It simply forwards onto the spurious - * handler defined in the cpu-table. - */ - -static ISR_Handler -hppa_interrupt_report_spurious(ISR_Vector_number vector, - void* rtems_isr_frame) /* HPPA extension */ -{ - - /* - * If the CPU table defines a spurious_handler, then - * call it. If the handler returns halt. - */ - if ( _CPU_Table.spurious_handler ) - _CPU_Table.spurious_handler(vector, rtems_isr_frame); - - hppa_cpu_halt(vector); -} - - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level(void) -{ - int level; - HPPA_ASM_SSM(0, level); /* change no bits; just get copy */ - if (level & HPPA_PSW_I) - return 0; - return 1; -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. The handler is a C callable routine. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[vector]; - - _ISR_Vector_table[vector] = new_handler; -} - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - * - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - register unsigned8 *fp_context; - unsigned32 i; - proc_ptr old_handler; - - /* - * This is the default fp context for all tasks - * Set it up so that denormalized results go to zero. - */ - - fp_context = (unsigned8*) &_CPU_Null_fp_context; - for (i=0 ; i<sizeof(Context_Control_fp); i++) - *fp_context++ = 0; - *((unsigned32 *) &_CPU_Null_fp_context) = HPPA_FPSTATUS_D; - - /* - * Save r27 into _CPU_Default_gr27 so it will hopefully be the correct - * global data pointer for the entire system. - */ - - asm volatile( "stw %%r27,%0" : "=m" (_CPU_Default_gr27): ); - - /* - * Init the 2nd level interrupt handlers - */ - - for (i=0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++) - _CPU_ISR_install_vector(i, - hppa_interrupt_report_spurious, - &old_handler); - - _CPU_Table = *cpu_table; - -} - - -/* - * Halt the system. - * Called by the _CPU_Fatal_halt macro - * - * XXX - * Later on, this will allow us to return to the prom. - * For now, we just ignore 'type_of_halt' - * - * XXX - * NOTE: for gcc, this function must be at the bottom - * of the file, that is because if it is at the top - * of the file, gcc will inline it's calls. Since - * the function uses the HPPA_ASM_LABEL() macro, when - * gcc inlines it, you get two definitions of the same - * label name, which is an assembly error. - */ - - -void -hppa_cpu_halt(unsigned32 the_error) -{ - unsigned32 isrlevel; - - _CPU_ISR_Disable(isrlevel); - - /* - * XXXXX NOTE: This label is only needed that that when - * the simulator stops, it shows the label name specified - */ - /* HPPA_ASM_LABEL("_asm_hppa_cpu_halt");*/ - HPPA_ASM_BREAK(0, 0); -} - diff --git a/c/src/exec/score/cpu/hppa1.1/cpu_asm.S b/c/src/exec/score/cpu/hppa1.1/cpu_asm.S deleted file mode 100644 index 7ad9b39810..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/cpu_asm.S +++ /dev/null @@ -1,805 +0,0 @@ -/* - * TODO: - * Context_switch needs to only save callee save registers - * I think this means can skip: r1, r2, r19-29, r31 - * Ref: p 3-2 of Procedure Calling Conventions Manual - * This should be #ifndef DEBUG so that debugger has - * accurate visibility into all registers - * - * This file contains the assembly code for the HPPA implementation - * of RTEMS. - * - * COPYRIGHT (c) 1994,95 by Division Incorporated - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/score/hppa.h> -#include <rtems/score/cpu_asm.h> -#include <rtems/score/cpu.h> -#include <rtems/score/offsets.h> - -#if 0 -#define TEXT_SEGMENT \ - .SPACE $TEXT$ !\ - .SUBSPA $CODE$ -#define RO_SEGMENT \ - .SPACE $TEXT$ !\ - .SUBSPA $lit$ -#define DATA_SEGMENT \ - .SPACE $PRIVATE$ !\ - .SUBSPA $data$ -#define BSS_SEGMENT \ - .SPACE $PRIVATE$ !\ - .SUBSPA $bss$ -#else -#define TEXT_SEGMENT .text -#define RO_SEGMENT .rodata -#define DATA_SEGMENT .data -#define BSS_SEGMENT .bss -#endif - - - -#if 0 - .SPACE $PRIVATE$ - .SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31 - .SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82 - .SPACE $TEXT$ - .SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44 - .SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY - .SPACE $TEXT$ - .SUBSPA $CODE$ - -#endif - TEXT_SEGMENT - -/* - * Special register usage for context switch and interrupts - * Stay away from %cr28 which is used for TLB misses on 72000 - */ - -isr_arg0 .reg %cr24 -isr_r9 .reg %cr25 -isr_r8 .reg %cr26 - -/* - * Interrupt stack frame looks like this - * - * offset item - * ----------------------------------------------------------------- - * INTEGER_CONTEXT_OFFSET Context_Control - * FP_CONTEXT_OFFSET Context_Control_fp - * - * It is padded out to a multiple of 64 - */ - - -/*PAGE^L - * void _Generic_ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * We jump here from the interrupt vector. - * The HPPA hardware has done some stuff for us: - * PSW saved in IPSW - * PSW set to 0 - * PSW[E] set to default (0) - * PSW[M] set to 1 iff this is HPMC - * - * IIA queue is frozen (since PSW[Q] is now 0) - * privilege level promoted to 0 - * IIR, ISR, IOR potentially updated if PSW[Q] was 1 at trap - * registers GR 1,8,9,16,17,24,25 copied to shadow regs - * SHR 0 1 2 3 4 5 6 - * - * Our vector stub (in the BSP) MUST have done the following: - * - * a) Saved the original %r9 into %isr_r9 (%cr25) - * b) Placed the vector number in %r9 - * c) Was allowed to also destroy $isr_r8 (%cr26), - * but the stub was NOT allowed to destroy any other registers. - * - * The typical stub sequence (in the BSP) should look like this: - * - * a) mtctl %r9,isr_r9 ; (save r9 in cr25) - * b) ldi vector,%r9 ; (load constant vector number in r9) - * c) mtctl %r8,isr_r8 ; (save r8 in cr26) - * d) ldil L%MY_BSP_first_level_interrupt_handler,%r8 - * e) ldo R%MY_BSP_first_level_interrupt_handler(%r8),%r8 - * ; (point to BSP raw handler table) - * f) ldwx,s %r9(%r8),%r8 ; (load value from raw handler table) - * g) bv 0(%r8) ; (call raw handler: _Generic_ISR_Handler) - * h) mfctl isr_r8,%r8 ; (restore r8 from cr26 in delay slot) - * - * Optionally, steps (c) thru (h) _could_ be replaced with a single - * bl,n _Generic_ISR_Handler,%r0 - * - * - */ - .EXPORT _Generic_ISR_Handler,ENTRY,PRIV_LEV=0 -_Generic_ISR_Handler: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - - mtctl arg0, isr_arg0 - -/* - * save interrupt state - */ - mfctl ipsw, arg0 - stw arg0, IPSW_OFFSET(sp) - - mfctl iir, arg0 - stw arg0, IIR_OFFSET(sp) - - mfctl ior, arg0 - stw arg0, IOR_OFFSET(sp) - - mfctl pcoq, arg0 - stw arg0, PCOQFRONT_OFFSET(sp) - - mtctl %r0, pcoq - mfctl pcoq, arg0 - stw arg0, PCOQBACK_OFFSET(sp) - - mfctl %sar, arg0 - stw arg0, SAR_OFFSET(sp) - -/* - * Build an interrupt frame to hold the contexts we will need. - * We have already saved the interrupt items on the stack - * - * At this point the following registers are damaged wrt the interrupt - * reg current value saved value - * ------------------------------------------------ - * arg0 scratch isr_arg0 (cr24) - * r9 vector number isr_r9 (cr25) - * - * Point to beginning of integer context and - * save the integer context - */ - stw %r1,R1_OFFSET(sp) - stw %r2,R2_OFFSET(sp) - stw %r3,R3_OFFSET(sp) - stw %r4,R4_OFFSET(sp) - stw %r5,R5_OFFSET(sp) - stw %r6,R6_OFFSET(sp) - stw %r7,R7_OFFSET(sp) - stw %r8,R8_OFFSET(sp) -/* - * skip r9 - */ - stw %r10,R10_OFFSET(sp) - stw %r11,R11_OFFSET(sp) - stw %r12,R12_OFFSET(sp) - stw %r13,R13_OFFSET(sp) - stw %r14,R14_OFFSET(sp) - stw %r15,R15_OFFSET(sp) - stw %r16,R16_OFFSET(sp) - stw %r17,R17_OFFSET(sp) - stw %r18,R18_OFFSET(sp) - stw %r19,R19_OFFSET(sp) - stw %r20,R20_OFFSET(sp) - stw %r21,R21_OFFSET(sp) - stw %r22,R22_OFFSET(sp) - stw %r23,R23_OFFSET(sp) - stw %r24,R24_OFFSET(sp) - stw %r25,R25_OFFSET(sp) -/* - * skip arg0 - */ - stw %r27,R27_OFFSET(sp) - stw %r28,R28_OFFSET(sp) - stw %r29,R29_OFFSET(sp) - stw %r30,R30_OFFSET(sp) - stw %r31,R31_OFFSET(sp) - -/* Now most registers are available since they have been saved - * - * The following items are currently wrong in the integer context - * reg current value saved value - * ------------------------------------------------ - * arg0 scratch isr_arg0 (cr24) - * r9 vector number isr_r9 (cr25) - * - * Fix them - */ - - mfctl isr_arg0,%r3 - stw %r3,ARG0_OFFSET(sp) - - mfctl isr_r9,%r3 - stw %r3,R9_OFFSET(sp) - -/* - * At this point we are done with isr_arg0, and isr_r9 control registers - * - * Prepare to re-enter virtual mode - * We need Q in case the interrupt handler enables interrupts - */ - - ldil L%CPU_PSW_DEFAULT, arg0 - ldo R%CPU_PSW_DEFAULT(arg0), arg0 - mtctl arg0, ipsw - -/* - * Now jump to "rest_of_isr_handler" with the rfi - * We are assuming the space queues are all correct already - */ - - ldil L%rest_of_isr_handler, arg0 - ldo R%rest_of_isr_handler(arg0), arg0 - mtctl arg0, pcoq - ldo 4(arg0), arg0 - mtctl arg0, pcoq - - rfi - nop - -/* - * At this point we are back in virtual mode and all our - * normal addressing is once again ok. - * - * It is now ok to take an exception or trap - */ - -rest_of_isr_handler: - -/* - * Point to beginning of float context and - * save the floating point context -- doing whatever patches are necessary - */ - - .call ARGW0=GR - bl _CPU_Save_float_context,%r2 - ldo FP_CONTEXT_OFFSET(sp),arg0 - -/* - * save the ptr to interrupt frame as an argument for the interrupt handler - */ - - copy sp, arg1 - -/* - * Advance the frame to point beyond all interrupt contexts (integer & float) - * this also includes the pad to align to 64byte stack boundary - */ - ldo CPU_INTERRUPT_FRAME_SIZE(sp), sp - -/* - * r3 -- &_ISR_Nest_level - * r5 -- value _ISR_Nest_level - * r4 -- &_Thread_Dispatch_disable_level - * r6 -- value _Thread_Dispatch_disable_level - * r9 -- vector number - */ - - .import _ISR_Nest_level,data - ldil L%_ISR_Nest_level,%r3 - ldo R%_ISR_Nest_level(%r3),%r3 - ldw 0(%r3),%r5 - - .import _Thread_Dispatch_disable_level,data - ldil L%_Thread_Dispatch_disable_level,%r4 - ldo R%_Thread_Dispatch_disable_level(%r4),%r4 - ldw 0(%r4),%r6 - -/* - * increment interrupt nest level counter. If outermost interrupt - * switch the stack and squirrel away the previous sp. - */ - addi 1,%r5,%r5 - stw %r5, 0(%r3) - -/* - * compute and save new stack (with frame) - * just in case we are nested -- simpler this way - */ - comibf,= 1,%r5,stack_done - ldo 128(sp),%r7 - -/* - * Switch to interrupt stack allocated by the interrupt manager (intr.c) - */ - .import _CPU_Interrupt_stack_low,data - ldil L%_CPU_Interrupt_stack_low,%r7 - ldw R%_CPU_Interrupt_stack_low(%r7),%r7 - ldo 128(%r7),%r7 - -stack_done: -/* - * save our current stack pointer where the "old sp" is supposed to be - */ - stw sp, -4(%r7) -/* - * and switch stacks (or advance old stack in nested case) - */ - copy %r7, sp - -/* - * increment the dispatch disable level counter. - */ - addi 1,%r6,%r6 - stw %r6, 0(%r4) - -/* - * load address of user handler - * Note: No error checking is done, it is assumed that the - * vector table contains a valid address or a stub - * spurious handler. - */ - .import _ISR_Vector_table,data - ldil L%_ISR_Vector_table,%r8 - ldo R%_ISR_Vector_table(%r8),%r8 - ldw 0(%r8),%r8 - ldwx,s %r9(%r8),%r8 - -/* - * invoke user interrupt handler - * Interrupts are currently disabled, as per RTEMS convention - * The handler has the option of re-enabling interrupts - * NOTE: can not use 'bl' since it uses "pc-relative" addressing - * and we are using a hard coded address from a table - * So... we fudge r2 ourselves (ala dynacall) - * arg0 = vector number, arg1 = ptr to rtems_interrupt_frame - */ - copy %r9, %r26 - .call ARGW0=GR, ARGW1=GR - blr %r0, rp - bv,n 0(%r8) - -post_user_interrupt_handler: - -/* - * Back from user handler(s) - * Disable external interrupts (since the interrupt handler could - * have turned them on) and return to the interrupted task stack (assuming - * (_ISR_Nest_level == 0) - */ - - rsm HPPA_PSW_I + HPPA_PSW_R, %r0 - ldw -4(sp), sp - -/* - * r3 -- (most of) &_ISR_Nest_level - * r5 -- value _ISR_Nest_level - * r4 -- (most of) &_Thread_Dispatch_disable_level - * r6 -- value _Thread_Dispatch_disable_level - * r7 -- (most of) &_ISR_Signals_to_thread_executing - * r8 -- value _ISR_Signals_to_thread_executing - */ - - .import _ISR_Nest_level,data - ldil L%_ISR_Nest_level,%r3 - ldw R%_ISR_Nest_level(%r3),%r5 - - .import _Thread_Dispatch_disable_level,data - ldil L%_Thread_Dispatch_disable_level,%r4 - ldw R%_Thread_Dispatch_disable_level(%r4),%r6 - - .import _ISR_Signals_to_thread_executing,data - ldil L%_ISR_Signals_to_thread_executing,%r7 - -/* - * decrement isr nest level - */ - addi -1, %r5, %r5 - stw %r5, R%_ISR_Nest_level(%r3) - -/* - * decrement dispatch disable level counter and, if not 0, go on - */ - addi -1,%r6,%r6 - comibf,= 0,%r6,isr_restore - stw %r6, R%_Thread_Dispatch_disable_level(%r4) - -/* - * check whether or not a context switch is necessary - */ - .import _Context_Switch_necessary,data - ldil L%_Context_Switch_necessary,%r8 - ldw R%_Context_Switch_necessary(%r8),%r8 - comibf,=,n 0,%r8,ISR_dispatch - -/* - * check whether or not a context switch is necessary because an ISR - * sent signals to the interrupted task - */ - ldw R%_ISR_Signals_to_thread_executing(%r7),%r8 - comibt,=,n 0,%r8,isr_restore - - -/* - * OK, something happened while in ISR and we need to switch to a task - * other than the one which was interrupted or the - * ISR_Signals_to_thread_executing case - * We also turn on interrupts, since the interrupted task had them - * on (obviously :-) and Thread_Dispatch is happy to leave ints on. - */ - -ISR_dispatch: - stw %r0, R%_ISR_Signals_to_thread_executing(%r7) - - ssm HPPA_PSW_I, %r0 - - .import _Thread_Dispatch,code - .call - bl _Thread_Dispatch,%r2 - ldo 128(sp),sp - - ldo -128(sp),sp - -isr_restore: - -/* - * enable interrupts during most of restore - */ - ssm HPPA_PSW_I, %r0 - -/* - * Get a pointer to beginning of our stack frame - */ - ldo -CPU_INTERRUPT_FRAME_SIZE(sp), %arg1 - -/* - * restore float - */ - .call ARGW0=GR - bl _CPU_Restore_float_context,%r2 - ldo FP_CONTEXT_OFFSET(%arg1), arg0 - - copy %arg1, %arg0 - -/* - * ********** FALL THRU ********** - */ - -/* - * Jump here from bottom of Context_Switch - * Also called directly by _CPU_Context_Restart_self via _Thread_Restart_self - * restore interrupt state - */ - - .EXPORT _CPU_Context_restore -_CPU_Context_restore: - -/* - * restore integer state - */ - ldw R1_OFFSET(arg0),%r1 - ldw R2_OFFSET(arg0),%r2 - ldw R3_OFFSET(arg0),%r3 - ldw R4_OFFSET(arg0),%r4 - ldw R5_OFFSET(arg0),%r5 - ldw R6_OFFSET(arg0),%r6 - ldw R7_OFFSET(arg0),%r7 - ldw R8_OFFSET(arg0),%r8 - ldw R9_OFFSET(arg0),%r9 - ldw R10_OFFSET(arg0),%r10 - ldw R11_OFFSET(arg0),%r11 - ldw R12_OFFSET(arg0),%r12 - ldw R13_OFFSET(arg0),%r13 - ldw R14_OFFSET(arg0),%r14 - ldw R15_OFFSET(arg0),%r15 - ldw R16_OFFSET(arg0),%r16 - ldw R17_OFFSET(arg0),%r17 - ldw R18_OFFSET(arg0),%r18 - ldw R19_OFFSET(arg0),%r19 - ldw R20_OFFSET(arg0),%r20 - ldw R21_OFFSET(arg0),%r21 - ldw R22_OFFSET(arg0),%r22 - ldw R23_OFFSET(arg0),%r23 - ldw R24_OFFSET(arg0),%r24 -/* - * skipping r25; used as scratch register below - * skipping r26 (arg0) until we are done with it - */ - ldw R27_OFFSET(arg0),%r27 - ldw R28_OFFSET(arg0),%r28 - ldw R29_OFFSET(arg0),%r29 -/* - * skipping r30 (sp) until we turn off interrupts - */ - ldw R31_OFFSET(arg0),%r31 - -/* - * Turn off Q & R & I so we can write r30 and interrupt control registers - */ - rsm HPPA_PSW_Q + HPPA_PSW_R + HPPA_PSW_I, %r0 - -/* - * now safe to restore r30 - */ - ldw R30_OFFSET(arg0),%r30 - - ldw IPSW_OFFSET(arg0), %r25 - mtctl %r25, ipsw - - ldw SAR_OFFSET(arg0), %r25 - mtctl %r25, sar - - ldw PCOQFRONT_OFFSET(arg0), %r25 - mtctl %r25, pcoq - - ldw PCOQBACK_OFFSET(arg0), %r25 - mtctl %r25, pcoq - -/* - * Load r25 with interrupts off - */ - ldw R25_OFFSET(arg0),%r25 -/* - * Must load r26 (arg0) last - */ - ldw R26_OFFSET(arg0),%r26 - -isr_exit: - rfi - .EXIT - .PROCEND - -/* - * This section is used to context switch floating point registers. - * Ref: 6-35 of Architecture 1.1 - * - * NOTE: since integer multiply uses the floating point unit, - * we have to save/restore fp on every trap. We cannot - * just try to keep track of fp usage. - */ - - .align 32 - .EXPORT _CPU_Save_float_context,ENTRY,PRIV_LEV=0 -_CPU_Save_float_context: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - fstds,ma %fr0,8(%arg0) - fstds,ma %fr1,8(%arg0) - fstds,ma %fr2,8(%arg0) - fstds,ma %fr3,8(%arg0) - fstds,ma %fr4,8(%arg0) - fstds,ma %fr5,8(%arg0) - fstds,ma %fr6,8(%arg0) - fstds,ma %fr7,8(%arg0) - fstds,ma %fr8,8(%arg0) - fstds,ma %fr9,8(%arg0) - fstds,ma %fr10,8(%arg0) - fstds,ma %fr11,8(%arg0) - fstds,ma %fr12,8(%arg0) - fstds,ma %fr13,8(%arg0) - fstds,ma %fr14,8(%arg0) - fstds,ma %fr15,8(%arg0) - fstds,ma %fr16,8(%arg0) - fstds,ma %fr17,8(%arg0) - fstds,ma %fr18,8(%arg0) - fstds,ma %fr19,8(%arg0) - fstds,ma %fr20,8(%arg0) - fstds,ma %fr21,8(%arg0) - fstds,ma %fr22,8(%arg0) - fstds,ma %fr23,8(%arg0) - fstds,ma %fr24,8(%arg0) - fstds,ma %fr25,8(%arg0) - fstds,ma %fr26,8(%arg0) - fstds,ma %fr27,8(%arg0) - fstds,ma %fr28,8(%arg0) - fstds,ma %fr29,8(%arg0) - fstds,ma %fr30,8(%arg0) - fstds %fr31,0(%arg0) - bv 0(%r2) - addi -(31*8), %arg0, %arg0 ; restore arg0 just for fun - .EXIT - .PROCEND - - .align 32 - .EXPORT _CPU_Restore_float_context,ENTRY,PRIV_LEV=0 -_CPU_Restore_float_context: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - addi (31*8), %arg0, %arg0 ; point at last double - fldds 0(%arg0),%fr31 - fldds,mb -8(%arg0),%fr30 - fldds,mb -8(%arg0),%fr29 - fldds,mb -8(%arg0),%fr28 - fldds,mb -8(%arg0),%fr27 - fldds,mb -8(%arg0),%fr26 - fldds,mb -8(%arg0),%fr25 - fldds,mb -8(%arg0),%fr24 - fldds,mb -8(%arg0),%fr23 - fldds,mb -8(%arg0),%fr22 - fldds,mb -8(%arg0),%fr21 - fldds,mb -8(%arg0),%fr20 - fldds,mb -8(%arg0),%fr19 - fldds,mb -8(%arg0),%fr18 - fldds,mb -8(%arg0),%fr17 - fldds,mb -8(%arg0),%fr16 - fldds,mb -8(%arg0),%fr15 - fldds,mb -8(%arg0),%fr14 - fldds,mb -8(%arg0),%fr13 - fldds,mb -8(%arg0),%fr12 - fldds,mb -8(%arg0),%fr11 - fldds,mb -8(%arg0),%fr10 - fldds,mb -8(%arg0),%fr9 - fldds,mb -8(%arg0),%fr8 - fldds,mb -8(%arg0),%fr7 - fldds,mb -8(%arg0),%fr6 - fldds,mb -8(%arg0),%fr5 - fldds,mb -8(%arg0),%fr4 - fldds,mb -8(%arg0),%fr3 - fldds,mb -8(%arg0),%fr2 - fldds,mb -8(%arg0),%fr1 - bv 0(%r2) - fldds,mb -8(%arg0),%fr0 - .EXIT - .PROCEND - -/* - * These 2 small routines are unused right now. - * Normally we just go thru _CPU_Save_float_context (and Restore) - * - * Here we just deref the ptr and jump up, letting _CPU_Save_float_context - * do the return for us. - */ - - .EXPORT _CPU_Context_save_fp,ENTRY,PRIV_LEV=0 -_CPU_Context_save_fp: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - bl _CPU_Save_float_context, %r0 - ldw 0(%arg0), %arg0 - .EXIT - .PROCEND - - .EXPORT _CPU_Context_restore_fp,ENTRY,PRIV_LEV=0 -_CPU_Context_restore_fp: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - bl _CPU_Restore_float_context, %r0 - ldw 0(%arg0), %arg0 - .EXIT - .PROCEND - - -/* - * void _CPU_Context_switch( run_context, heir_context ) - * - * This routine performs a normal non-FP context switch. - */ - - .align 32 - .EXPORT _CPU_Context_switch,ENTRY,PRIV_LEV=0,ARGW0=GR,ARGW1=GR -_CPU_Context_switch: - .PROC - .CALLINFO FRAME=64 - .ENTRY - -/* - * Save the integer context - */ - stw %r1,R1_OFFSET(arg0) - stw %r2,R2_OFFSET(arg0) - stw %r3,R3_OFFSET(arg0) - stw %r4,R4_OFFSET(arg0) - stw %r5,R5_OFFSET(arg0) - stw %r6,R6_OFFSET(arg0) - stw %r7,R7_OFFSET(arg0) - stw %r8,R8_OFFSET(arg0) - stw %r9,R9_OFFSET(arg0) - stw %r10,R10_OFFSET(arg0) - stw %r11,R11_OFFSET(arg0) - stw %r12,R12_OFFSET(arg0) - stw %r13,R13_OFFSET(arg0) - stw %r14,R14_OFFSET(arg0) - stw %r15,R15_OFFSET(arg0) - stw %r16,R16_OFFSET(arg0) - stw %r17,R17_OFFSET(arg0) - stw %r18,R18_OFFSET(arg0) - stw %r19,R19_OFFSET(arg0) - stw %r20,R20_OFFSET(arg0) - stw %r21,R21_OFFSET(arg0) - stw %r22,R22_OFFSET(arg0) - stw %r23,R23_OFFSET(arg0) - stw %r24,R24_OFFSET(arg0) - stw %r25,R25_OFFSET(arg0) - stw %r26,R26_OFFSET(arg0) - stw %r27,R27_OFFSET(arg0) - stw %r28,R28_OFFSET(arg0) - stw %r29,R29_OFFSET(arg0) - stw %r30,R30_OFFSET(arg0) - stw %r31,R31_OFFSET(arg0) - -/* - * fill in interrupt context section - */ - stw %r2, PCOQFRONT_OFFSET(%arg0) - ldo 4(%r2), %r2 - stw %r2, PCOQBACK_OFFSET(%arg0) - -/* - * Generate a suitable IPSW by using the system default psw - * with the current low bits added in. - */ - - ldil L%CPU_PSW_DEFAULT, %r2 - ldo R%CPU_PSW_DEFAULT(%r2), %r2 - ssm 0, %arg2 - dep %arg2, 31, 8, %r2 - stw %r2, IPSW_OFFSET(%arg0) - -/* - * at this point, the running task context is completely saved - * Now jump to the bottom of the interrupt handler to load the - * heirs context - */ - - b _CPU_Context_restore - copy %arg1, %arg0 - - .EXIT - .PROCEND - - -/* - * Find first bit - * NOTE: - * This is used (and written) only for the ready chain code and - * priority bit maps. - * Any other use constitutes fraud. - * Returns first bit from the least significant side. - * Eg: if input is 0x8001 - * output will indicate the '1' bit and return 0. - * This is counter to HPPA bit numbering which calls this - * bit 31. This way simplifies the macros _CPU_Priority_Mask - * and _CPU_Priority_Bits_index. - * - * NOTE: - * We just use 16 bit version - * does not handle zero case - * - * Based on the UTAH Mach libc version of ffs. - */ - - .align 32 - .EXPORT hppa_rtems_ffs,ENTRY,PRIV_LEV=0,ARGW0=GR -hppa_rtems_ffs: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - -#ifdef RETURN_ERROR_ON_ZERO - comb,= %arg0,%r0,ffsdone ; If arg0 is 0 - ldi -1,%ret0 ; return -1 -#endif - -#if BITFIELD_SIZE == 32 - ldi 31,%ret0 ; Set return to high bit - extru,= %arg0,31,16,%r0 ; If low 16 bits are non-zero - addi,tr -16,%ret0,%ret0 ; subtract 16 from bitpos - shd %r0,%arg0,16,%arg0 ; else shift right 16 bits -#else - ldi 15,%ret0 ; Set return to high bit -#endif - extru,= %arg0,31,8,%r0 ; If low 8 bits are non-zero - addi,tr -8,%ret0,%ret0 ; subtract 8 from bitpos - shd %r0,%arg0,8,%arg0 ; else shift right 8 bits - extru,= %arg0,31,4,%r0 ; If low 4 bits are non-zero - addi,tr -4,%ret0,%ret0 ; subtract 4 from bitpos - shd %r0,%arg0,4,%arg0 ; else shift right 4 bits - extru,= %arg0,31,2,%r0 ; If low 2 bits are non-zero - addi,tr -2,%ret0,%ret0 ; subtract 2 from bitpos - shd %r0,%arg0,2,%arg0 ; else shift right 2 bits - extru,= %arg0,31,1,%r0 ; If low bit is non-zero - addi -1,%ret0,%ret0 ; subtract 1 from bitpos -ffsdone: - bv,n 0(%r2) - nop - .EXIT - .PROCEND diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/.cvsignore b/c/src/exec/score/cpu/hppa1.1/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/score/.cvsignore b/c/src/exec/score/cpu/hppa1.1/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu.h b/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu.h deleted file mode 100644 index fe4182c342..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu.h +++ /dev/null @@ -1,653 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the HP - * PA-RISC processor (Level 1.1). - * - * COPYRIGHT (c) 1994 by Division Incorporated - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Note: - * This file is included by both C and assembler code ( -DASM ) - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/hppa.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * RTEMS manages an interrupt stack in software for the HPPA. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * HPPA has hardware FP, it is assumed to exist by GCC so all tasks - * may implicitly use it (especially for integer multiplies). Because - * the FP context is technically part of the basic integer context - * on this CPU, we cannot use the deferred FP context switch algorithm. - */ - -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE -#define CPU_ALL_TASKS_ARE_FP TRUE -#define CPU_IDLE_TASK_IS_FP FALSE -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE -#define CPU_STACK_GROWS_UP TRUE -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((__aligned__ (32))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* constants */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * PSW contstants - */ - -#define CPU_PSW_BASE (HPPA_PSW_C | HPPA_PSW_Q | HPPA_PSW_P | HPPA_PSW_D) -#define CPU_PSW_INTERRUPTS_ON (CPU_PSW_BASE | HPPA_PSW_I) -#define CPU_PSW_INTERRUPTS_OFF (CPU_PSW_BASE) - -#define CPU_PSW_DEFAULT CPU_PSW_BASE - - -#ifndef ASM - -/* - * Contexts - * - * This means we have the following context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * - * The PA-RISC is very fast so the expense of saving an extra register - * or two is not of great concern at the present. So we are not making - * a distinction between what is saved during a task switch and what is - * saved at each interrupt. Plus saving the entire context should make - * it easier to make gdb aware of RTEMS tasks. - */ - -typedef struct { - unsigned32 flags; /* whatever */ - unsigned32 gr1; /* scratch -- caller saves */ - unsigned32 gr2; /* RP -- return pointer */ - unsigned32 gr3; /* scratch -- callee saves */ - unsigned32 gr4; /* scratch -- callee saves */ - unsigned32 gr5; /* scratch -- callee saves */ - unsigned32 gr6; /* scratch -- callee saves */ - unsigned32 gr7; /* scratch -- callee saves */ - unsigned32 gr8; /* scratch -- callee saves */ - unsigned32 gr9; /* scratch -- callee saves */ - unsigned32 gr10; /* scratch -- callee saves */ - unsigned32 gr11; /* scratch -- callee saves */ - unsigned32 gr12; /* scratch -- callee saves */ - unsigned32 gr13; /* scratch -- callee saves */ - unsigned32 gr14; /* scratch -- callee saves */ - unsigned32 gr15; /* scratch -- callee saves */ - unsigned32 gr16; /* scratch -- callee saves */ - unsigned32 gr17; /* scratch -- callee saves */ - unsigned32 gr18; /* scratch -- callee saves */ - unsigned32 gr19; /* scratch -- caller saves */ - unsigned32 gr20; /* scratch -- caller saves */ - unsigned32 gr21; /* scratch -- caller saves */ - unsigned32 gr22; /* scratch -- caller saves */ - unsigned32 gr23; /* argument 3 */ - unsigned32 gr24; /* argument 2 */ - unsigned32 gr25; /* argument 1 */ - unsigned32 gr26; /* argument 0 */ - unsigned32 gr27; /* DP -- global data pointer */ - unsigned32 gr28; /* return values -- caller saves */ - unsigned32 gr29; /* return values -- caller saves */ - unsigned32 sp; /* gr30 */ - unsigned32 gr31; - - /* Various control registers */ - - unsigned32 sar; /* cr11 */ - unsigned32 ipsw; /* cr22; full 32 bits of psw */ - unsigned32 iir; /* cr19; interrupt instruction register */ - unsigned32 ior; /* cr21; interrupt offset register */ - unsigned32 isr; /* cr20; interrupt space register (not used) */ - unsigned32 pcoqfront; /* cr18; front que offset */ - unsigned32 pcoqback; /* cr18; back que offset */ - unsigned32 pcsqfront; /* cr17; front que space (not used) */ - unsigned32 pcsqback; /* cr17; back que space (not used) */ - unsigned32 itimer; /* cr16; itimer value */ - -} Context_Control; - - -/* Must be double word aligned. - * This will be ok since our allocator returns 8 byte aligned chunks - */ - -typedef struct { - double fr0; /* status */ - double fr1; /* exception information */ - double fr2; /* exception information */ - double fr3; /* exception information */ - double fr4; /* argument */ - double fr5; /* argument */ - double fr6; /* argument */ - double fr7; /* argument */ - double fr8; /* scratch -- caller saves */ - double fr9; /* scratch -- caller saves */ - double fr10; /* scratch -- caller saves */ - double fr11; /* scratch -- caller saves */ - double fr12; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr13; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr14; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr15; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr16; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr17; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr18; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr19; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr20; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr21; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr22; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr23; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr24; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr25; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr26; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr27; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr28; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr29; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr30; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr31; /* caller saves -- (PA-RISC 1.1 CPUs) */ -} Context_Control_fp; - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of each interrupt. - */ - -typedef struct { - Context_Control Integer; - Context_Control_fp Floating_Point; -} CPU_Interrupt_frame; - -/* - * Our interrupt handlers take a 2nd argument: - * a pointer to a CPU_Interrupt_frame - * So we use our own prototype instead of rtems_isr_entry - */ - -typedef void ( *hppa_rtems_isr_entry )( - unsigned32, - CPU_Interrupt_frame * - ); - -/* - * The following table contains the information required to configure - * the HPPA specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void * ); - /* end of fields required on all CPUs */ - - hppa_rtems_isr_entry spurious_handler; - - unsigned32 itimer_clicks_per_microsecond; /* for use by Clock driver */ -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access HPPA specific additions to the CPU Table - */ - -#define rtems_cpu_configuration_get_spurious_handler() \ - (_CPU_Table.spurious_handler) - -#define rtems_cpu_configuration_get_itimer_clicks_per_microsecond() \ - (_CPU_Table.itimer_clicks_per_microsecond) - -/* variables */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -SCORE_EXTERN unsigned32 _CPU_Default_gr27; -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -#endif /* ! ASM */ - -/* - * context sizes - */ - -#ifndef ASM -#define CPU_CONTEXT_SIZE sizeof( Context_Control ) -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) -#endif - -/* - * size of a frame on the stack - */ - -#define CPU_FRAME_SIZE (16 * 4) - -/* - * (Optional) # of bytes for libmisc/stackchk to check - * If not specifed, then it defaults to something reasonable - * for most architectures. - */ - -#define CPU_STACK_CHECK_SIZE (CPU_FRAME_SIZE * 2) - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * HPPA has 32 traps, then 32 external interrupts - * Rtems (_ISR_Vector_Table) is aware ONLY of the first 32 - * The BSP is aware of the external interrupts and possibly more. - * - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS (HPPA_INTERNAL_TRAPS) -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Don't be chintzy here; we don't want to debug these problems - * Some of the tests eat almost 4k. - * Plus, the HPPA always allocates chunks of 64 bytes for stack - * growth. - */ - -#define CPU_STACK_MINIMUM_SIZE (8 * 1024) - -/* - * HPPA double's must be on 8 byte boundary - */ - -#define CPU_ALIGNMENT 8 - -/* - * just follow the basic HPPA alignment for the heap and partition - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * HPPA stack is best when 64 byte aligned. - */ - -#define CPU_STACK_ALIGNMENT 64 - -#ifndef ASM - -/* macros */ - -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* Disable interrupts; returning previous psw bits in _isr_level */ - -#define _CPU_ISR_Disable( _isr_level ) \ - do { \ - HPPA_ASM_RSM(HPPA_PSW_I, _isr_level); \ - if (_isr_level & HPPA_PSW_I) _isr_level = 0; \ - else _isr_level = 1; \ - } while(0) - -/* Enable interrupts to previous level from _CPU_ISR_Disable - * does not change 'level' - */ - -#define _CPU_ISR_Enable( _isr_level ) \ - { \ - register int _ignore; \ - if (_isr_level == 0) HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \ - else HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \ - } - -/* restore, then disable interrupts; does not change level */ -#define _CPU_ISR_Flash( _isr_level ) \ - { \ - if (_isr_level == 0) \ - { \ - register int _ignore; \ - HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \ - HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \ - } \ - } - -/* - * Interrupt task levels - * - * Future scheme proposal - * level will be an index into a array. - * Each entry of array will be the interrupt bits - * enabled for that level. There will be 32 bits of external - * interrupts (to be placed in EIEM) and some (optional) bsp - * specific bits - * - * For pixel flow this *may* mean something like: - * level 0: all interrupts enabled (external + rhino) - * level 1: rhino disabled - * level 2: all io interrupts disabled (timer still enabled) - * level 7: *ALL* disabled (timer disabled) - */ - -/* set interrupts on or off; does not return new level */ -#define _CPU_ISR_Set_level( new_level ) \ - { \ - volatile int ignore; \ - if ( new_level ) HPPA_ASM_RSM(HPPA_PSW_I, ignore); \ - else HPPA_ASM_SSM(HPPA_PSW_I, ignore); \ - } - -/* return current level */ -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - * - * HPPA port adds two macros which hide the "indirectness" of the - * pointer passed the save/restore FP context assembly routines. - */ - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _new_level, _entry_point, _is_fp ) \ - do { \ - unsigned32 _stack; \ - \ - (_the_context)->flags = 0xfeedf00d; \ - (_the_context)->pcoqfront = (unsigned32)(_entry_point); \ - (_the_context)->pcoqback = (unsigned32)(_entry_point) + 4; \ - (_the_context)->pcsqfront = 0; \ - (_the_context)->pcsqback = 0; \ - if ( (_new_level) ) \ - (_the_context)->ipsw = CPU_PSW_INTERRUPTS_OFF; \ - else \ - (_the_context)->ipsw = CPU_PSW_INTERRUPTS_ON; \ - \ - _stack = ((unsigned32)(_stack_base) + (CPU_STACK_ALIGNMENT - 1)); \ - _stack &= ~(CPU_STACK_ALIGNMENT - 1); \ - if ((_stack - (unsigned32) (_stack_base)) < CPU_FRAME_SIZE) \ - _stack += CPU_FRAME_SIZE; \ - \ - (_the_context)->sp = (_stack); \ - (_the_context)->gr27 = _CPU_Default_gr27; \ - } while (0) - -#define _CPU_Context_Restart_self( _the_context ) \ - do { \ - _CPU_Context_restore( (_the_context) ); \ - } while (0) - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\ - } while(0) - -#define _CPU_Context_save_fp( _fp_context ) \ - _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context) ) - -#define _CPU_Context_restore_fp( _fp_context ) \ - _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context) ) - -/* end of Context handler macros */ - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -void hppa_cpu_halt(unsigned32 the_error); -#define _CPU_Fatal_halt( _error ) \ - hppa_cpu_halt(_error) - -/* end of Fatal Error manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - * - * NOTE: - * - * The HPPA does not have a scan instruction. This functionality - * is implemented in software. - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE -#define CPU_USE_GENERIC_BITFIELD_DATA FALSE - -int hppa_rtems_ffs(unsigned int value); -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - _output = hppa_rtems_ffs(_value) - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - * - * Note: 255 is the lowest priority - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner and avoid stack conflicts. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Save_float_context - * - * This routine saves the floating point context passed to it. - * - * NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA - * which dereferences the pointer before calling this. - */ - -void _CPU_Save_float_context( - Context_Control_fp *fp_context -); - -/* - * _CPU_Restore_float_context - * - * This routine restores the floating point context passed to it. - * - * NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA - * which dereferences the pointer before calling this. - */ - -void _CPU_Restore_float_context( - Context_Control_fp *fp_context -); - - -/* - * The raw interrupt handler for external interrupts - */ - -extern void _Generic_ISR_Handler( - void -); - - -/* The following routine swaps the endian format of an unsigned int. - * It must be static so it can be referenced indirectly. - */ - -static inline unsigned int -CPU_swap_u32(unsigned32 value) -{ - unsigned32 swapped; - - HPPA_ASM_SWAPBYTES(value, swapped); - - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#endif /* ! ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* ! __CPU_h */ diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu_asm.h b/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu_asm.h deleted file mode 100644 index 951f80dcf0..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu_asm.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 1990,1991 The University of Utah and - * the Center for Software Science (CSS). All rights reserved. - * - * Permission to use, copy, modify and distribute this software is hereby - * granted provided that (1) source code retains these copyright, permission, - * and disclaimer notices, and (2) redistributions including binaries - * reproduce the notices in supporting documentation, and (3) all advertising - * materials mentioning features or use of this software display the following - * acknowledgement: ``This product includes software developed by the Center - * for Software Science at the University of Utah.'' - * - * THE UNIVERSITY OF UTAH AND CSS ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS - * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSS DISCLAIM ANY LIABILITY OF - * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * - * CSS requests users of this software to return to css-dist@cs.utah.edu any - * improvements that they make and grant CSS redistribution rights. - * - * Utah $Hdr: asm.h 1.6 91/12/03$ - * - * $Id$ - */ - -/* - * Hardware Space Registers - */ -sr0 .reg %sr0 -sr1 .reg %sr1 -sr2 .reg %sr2 -sr3 .reg %sr3 -sr4 .reg %sr4 -sr5 .reg %sr5 -sr6 .reg %sr6 -sr7 .reg %sr7 - -/* - * Control register aliases - */ - -rctr .reg %cr0 -pidr1 .reg %cr8 -pidr2 .reg %cr9 -ccr .reg %cr10 -sar .reg %cr11 -pidr3 .reg %cr12 -pidr4 .reg %cr13 -iva .reg %cr14 -eiem .reg %cr15 -itmr .reg %cr16 -pcsq .reg %cr17 -pcoq .reg %cr18 -iir .reg %cr19 -isr .reg %cr20 -ior .reg %cr21 -ipsw .reg %cr22 -eirr .reg %cr23 - -/* - * Calling Convention - */ -rp .reg %r2 -arg3 .reg %r23 -arg2 .reg %r24 -arg1 .reg %r25 -arg0 .reg %r26 -dp .reg %r27 -ret0 .reg %r28 -ret1 .reg %r29 -sl .reg %r29 -sp .reg %r30 - - diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/score/hppa.h b/c/src/exec/score/cpu/hppa1.1/rtems/score/hppa.h deleted file mode 100644 index ceaf2fcce2..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems/score/hppa.h +++ /dev/null @@ -1,727 +0,0 @@ -/* - * Description: - * - * Definitions for HP PA Risc - * ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual - * - * COPYRIGHT (c) 1994 by Division Incorporated - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Note: - * This file is included by both C and assembler code ( -DASM ) - * - * $Id$ - */ - -#ifndef _INCLUDE_HPPA_H -#define _INCLUDE_HPPA_H - -#if defined(__cplusplus) -extern "C" { -#endif - -/* - * This section contains the information required to build - * RTEMS for a particular member of the Hewlett Packard - * PA-RISC family. It does this by setting variables to - * indicate which implementation dependent features are - * present in a particular member of the family. - */ - -/* - * Hack to allow multlib effort to continue -- known to build. - */ - -#define CPU_MODEL_NAME "hppa 7xxx" -#if 0 -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" - -#elif defined(hppa7100) - -#define CPU_MODEL_NAME "hppa 7100" - -#elif defined(hppa7200) - -#define CPU_MODEL_NAME "hppa 7200" - -#else - -#error "Unsupported CPU Model" - -#endif -#endif - -/* - * Define the name of the CPU family. - */ - -#if !defined(CPU_NAME) -#define CPU_NAME "HP PA-RISC 1.1" -#endif - -/* - * Processor Status Word (PSW) Masks - */ - - -#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */ -#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */ -#define HPPA_PSW_r2 0x20000000 /* reserved */ -#define HPPA_PSW_r3 0x10000000 /* reserved */ -#define HPPA_PSW_r4 0x08000000 /* reserved */ -#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */ -#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */ -#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */ -#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/ -#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */ -#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */ -#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */ -#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */ -#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */ -#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */ -#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */ -#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */ -#define HPPA_PSW_r24 0x00000080 /* reserved */ -#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */ -#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */ -#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */ -#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */ -#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */ -#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */ -#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */ - /* Low-Priority Machine Check */ - /* Interruption Enable */ - -/* - * HPPA traps and interrupts - * basic layout. Note numbers do not denote priority - * - * 0-31 basic traps and interrupts defined by HPPA architecture - * 0-31 32 external interrupts - * 32-... bsp defined - */ - -#define HPPA_TRAP_NON_EXISTENT 0 -/* group 1 */ -#define HPPA_TRAP_HIGH_PRIORITY_MACHINE_CHECK 1 -/* group 2 */ -#define HPPA_TRAP_POWER_FAIL 2 -#define HPPA_TRAP_RECOVERY_COUNTER 3 -#define HPPA_TRAP_EXTERNAL_INTERRUPT 4 -#define HPPA_TRAP_LOW_PRIORITY_MACHINE_CHECK 5 -#define HPPA_TRAP_PERFORMANCE_MONITOR 29 -/* group 3 */ -#define HPPA_TRAP_INSTRUCTION_TLB_MISS 6 -#define HPPA_TRAP_INSTRUCTION_MEMORY_PROTECTION 7 -#define HPPA_TRAP_INSTRUCTION_DEBUG 30 -#define HPPA_TRAP_ILLEGAL_INSTRUCTION 8 -#define HPPA_TRAP_BREAK_INSTRUCTION 9 -#define HPPA_TRAP_PRIVILEGED_OPERATION 10 -#define HPPA_TRAP_PRIVILEGED_REGISTER 11 -#define HPPA_TRAP_OVERFLOW 12 -#define HPPA_TRAP_CONDITIONAL 13 -#define HPPA_TRAP_ASSIST_EXCEPTION 14 -#define HPPA_TRAP_DATA_TLB_MISS 15 -#define HPPA_TRAP_NON_ACCESS_INSTRUCTION_TLB_MISS 16 -#define HPPA_TRAP_NON_ACCESS_DATA_TLB_MISS 17 -#define HPPA_TRAP_DATA_MEMORY_ACCESS_RIGHTS 26 -#define HPPA_TRAP_DATA_MEMORY_PROTECTION_ID 27 -#define HPPA_TRAP_UNALIGNED_DATA_REFERENCE 28 -#define HPPA_TRAP_DATA_MEMORY_PROTECTION 18 -#define HPPA_TRAP_DATA_MEMORY_BREAK 19 -#define HPPA_TRAP_TLB_DIRTY_BIT 20 -#define HPPA_TRAP_PAGE_REFERENCE 21 -#define HPPA_TRAP_DATA_DEBUG 31 -#define HPPA_TRAP_ASSIST_EMULATION 22 -/* group 4 */ -#define HPPA_TRAP_HIGHER_PRIVILEGE_TRANSFER 23 -#define HPPA_TRAP_LOWER_PRIVILEGE_TRANSFER 24 -#define HPPA_TRAP_TAKEN_BRANCH 25 - -#define HPPA_INTERNAL_TRAPS 32 - -/* External Interrupts via interrupt 4 */ - -#define HPPA_INTERRUPT_EXTERNAL_0 0 -#define HPPA_INTERRUPT_EXTERNAL_1 1 -#define HPPA_INTERRUPT_EXTERNAL_2 2 -#define HPPA_INTERRUPT_EXTERNAL_3 3 -#define HPPA_INTERRUPT_EXTERNAL_4 4 -#define HPPA_INTERRUPT_EXTERNAL_5 5 -#define HPPA_INTERRUPT_EXTERNAL_6 6 -#define HPPA_INTERRUPT_EXTERNAL_7 7 -#define HPPA_INTERRUPT_EXTERNAL_8 8 -#define HPPA_INTERRUPT_EXTERNAL_9 9 -#define HPPA_INTERRUPT_EXTERNAL_10 10 -#define HPPA_INTERRUPT_EXTERNAL_11 11 -#define HPPA_INTERRUPT_EXTERNAL_12 12 -#define HPPA_INTERRUPT_EXTERNAL_13 13 -#define HPPA_INTERRUPT_EXTERNAL_14 14 -#define HPPA_INTERRUPT_EXTERNAL_15 15 -#define HPPA_INTERRUPT_EXTERNAL_16 16 -#define HPPA_INTERRUPT_EXTERNAL_17 17 -#define HPPA_INTERRUPT_EXTERNAL_18 18 -#define HPPA_INTERRUPT_EXTERNAL_19 19 -#define HPPA_INTERRUPT_EXTERNAL_20 20 -#define HPPA_INTERRUPT_EXTERNAL_21 21 -#define HPPA_INTERRUPT_EXTERNAL_22 22 -#define HPPA_INTERRUPT_EXTERNAL_23 23 -#define HPPA_INTERRUPT_EXTERNAL_24 24 -#define HPPA_INTERRUPT_EXTERNAL_25 25 -#define HPPA_INTERRUPT_EXTERNAL_26 26 -#define HPPA_INTERRUPT_EXTERNAL_27 27 -#define HPPA_INTERRUPT_EXTERNAL_28 28 -#define HPPA_INTERRUPT_EXTERNAL_29 29 -#define HPPA_INTERRUPT_EXTERNAL_30 30 -#define HPPA_INTERRUPT_EXTERNAL_31 31 - -#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0 -#define HPPA_EXTERNAL_INTERRUPTS 32 - -/* BSP defined interrupts begin here */ - -#define HPPA_INTERRUPT_MAX 32 - -/* - * Cache characteristics - */ - -#define HPPA_CACHELINE_SIZE 32 -#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1) - -/* - * page size characteristics - */ - -#define HPPA_PAGE_SIZE 4096 -#define HPPA_PAGE_MASK (0xfffff000) - - -/* - * TLB characteristics - * - * Flags and Access Control layout for using TLB protection insertion - * - * 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 - * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |?|?|T|D|B|type |PL1|Pl2|U| access id |?| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * - */ - -/* - * Access rights (type + PL1 + PL2) - */ -#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */ -#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */ -#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */ -#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */ -#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */ -#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */ -#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */ -#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */ - -/* - * Floating point status register definitions - */ - -#define HPPA_FPSTATUS_ENABLE_I 0x00000001 /* inexact operation */ -#define HPPA_FPSTATUS_ENABLE_U 0x00000002 /* underflow */ -#define HPPA_FPSTATUS_ENABLE_O 0x00000004 /* overflow */ -#define HPPA_FPSTATUS_ENABLE_Z 0x00000008 /* division by zero */ -#define HPPA_FPSTATUS_ENABLE_V 0x00000010 /* invalid operation */ -#define HPPA_FPSTATUS_D 0x00000020 /* denormalize as zero */ -#define HPPA_FPSTATUS_T 0x00000040 /* delayed trap */ -#define HPPA_FPSTATUS_RM_MASK 0x00000600 /* rounding mode */ -#define HPPA_FPSTATUS_RM_SHIFT 9 -#define HPPA_FPSTATUS_CQ_MASK 0x001FFC00 /* compare queue */ -#define HPPA_FPSTATUS_CQ_SHIFT 13 -#define HPPA_FPSTATUS_C 0x04000000 /* most recent ompare bit */ -#define HPPA_FPSTATUS_FLAG_I 0x08000000 /* inexact */ -#define HPPA_FPSTATUS_FLAG_U 0x10000000 /* underflow */ -#define HPPA_FPSTATUS_FLAG_O 0x20000000 /* overflow */ -#define HPPA_FPSTATUS_FLAG_Z 0x40000000 /* division by zero */ -#define HPPA_FPSTATUS_FLAG_V 0x80000000 /* invalid operation */ - - -/* - * Inline macros for misc. interesting opcodes - */ - -/* generate a global label */ -#define HPPA_ASM_LABEL(label) \ - asm(".export " label ", ! .label " label); - -/* Return From Interrupt RFI */ -#define HPPA_ASM_RFI() asm volatile ("rfi") - -/* Set System Mask SSM i,t */ -#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \ - : "=r" (gr) \ - : "i" (i)) -/* Reset System Mask RSM i,t */ -#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \ - : "=r" (gr) \ - : "i" (i)) -/* Move To System Mask MTSM r */ -#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \ - : : "r" (gr)) - -/* Load Space Identifier LDSID (s,b),t */ -#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (grb)) - -/* - * Gcc extended asm doesn't really allow for treatment of space registers - * as "registers", so we have to use "i" format. - * Unfortunately this means that the "=" constraint is not available. - */ - -/* Move To Space Register MTSP r,sr */ -#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \ - : : "i" (sr), \ - "r" (gr)) - -/* Move From Space Register MFSP sr,t */ -#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \ - : "=r" (gr) \ - : "i" (sr)) - -/* Move To Control register MTCTL r,t */ -#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \ - : : "i" (cr), \ - "r" (gr)) - -/* Move From Control register MFCTL r,t */ -#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \ - : "=r" (gr) \ - : "i" (cr)) - -/* Synchronize caches SYNC */ -#define HPPA_ASM_SYNC() asm volatile ("sync") - -/* Probe Read Access PROBER (s,b),r,t */ -#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \ - asm volatile ("prober (%1,%2),%3,%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (groff), \ - "r" (gracc)) - -/* Probe Read Access Immediate PROBERI (s,b),i,t*/ -#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \ - asm volatile ("proberi (%1,%2),%3,%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (groff), \ - "i" (iacc)) - -/* Probe Write Access PROBEW (s,b),r,t */ -#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \ - asm volatile ("probew (%1,%2),%3,%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (groff), \ - "r" (gracc)) - -/* Probe Write Access Immediate PROBEWI (s,b),i,t */ -#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \ - asm volatile ("probewi (%1,%2),%3,%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (groff), \ - "i" (iacc)) - -/* Load Physical Address LPA x(s,b),t */ -#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (grb)) - -/* Load Coherence Index LCI x(s,b),t */ -/* AKA: Load Hash Address LHA x(s,b),t */ -#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \ - : "=r" (grt) \ - : "r" (grx),\ - "i" (sr), \ - "r" (grb)) -#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt) - -/* Purge Data Tlb PDTLB x(s,b) */ -#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Purge Instruction Tlb PITLB x(s,b) */ -#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Purge Data Tlb Entry PDTLBE x(s,b) */ -#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Purge Instruction Tlb Entry PITLBE x(s,b) */ -#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - - -/* Insert Data TLB Address IDTLBA r,(s,b) */ -#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \ - : : "r" (gr), \ - "i" (sr), \ - "r" (grb)) - -/* Insert Instruction TLB Address IITLBA r,(s,b) */ -#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \ - : : "r" (gr), \ - "i" (sr), \ - "r" (grb)) - -/* Insert Data TLB Protection IDTLBP r,(s,b) */ -#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \ - : : "r" (gr), \ - "i" (sr), \ - "r" (grb)) - -/* Insert Instruction TLB Protection IITLBP r,(s,b) */ -#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \ - : : "r" (gr), \ - "i" (sr), \ - "r" (grb)) - -/* Purge Data Cache PDC x(s,b) */ -#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Flush Data Cache FDC x(s,b) */ -#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Flush Instruction Cache FDC x(s,b) */ -#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Flush Data Cache Entry FDCE x(s,b) */ -#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Flush Instruction Cache Entry FICE x(s,b) */ -#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Break BREAK i5,i13 */ -#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \ - : : "i" (i5), \ - "i" (i13)) - -/* Load and Clear Word Short LDCWS d(s,b),t */ -#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \ - : "=r" (grt) \ - : "i" (i), \ - "i" (sr), \ - "r" (grb)) - -/* Load and Clear Word Indexed LDCWX x(s,b),t */ -#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \ - : "=r" (grt) \ - : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Load Word Absolute Short LDWAS d(b),t */ -/* NOTE: "short" here means "short displacement" */ -#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \ - : "=r" (gr) \ - : "i" (disp), \ - "r" (grbase)) - -/* Store Word Absolute Short STWAS r,d(b) */ -/* NOTE: "short" here means "short displacement" */ -#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \ - : : "r" (gr), \ - "i" (disp), \ - "r" (grbase)) - -/* - * Swap bytes - * REFERENCE: PA72000 TRM -- Appendix C - */ -#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \ - " shd %1,%1,16,%0 \n\ - dep %0,15,8,%0 \n\ - shd %1,%0,8,%0" \ - : "=r" (swapped) \ - : "r" (value) \ - ) - - -/* 72000 Diagnose instructions follow - * These macros assume gas knows about these instructions. - * gas2.2.u1 did not. - * I added them to my copy and installed it locally. - * - * There are *very* special requirements for these guys - * ref: TRM 6.1.3 Programming Constraints - * - * The macros below handle the following rules - * - * Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled. - * Must never be nullified (hence the leading nop) - * NOP must preced every RDD,RDT,WDD,WDT,RDTLB - * Instruction preceeding GR_SHDW must not set any of the GR's saved - * - * The macros do *NOT* deal with the following problems - * doubled DIAGNOSE instructions must not straddle a page boundary - * if code translation enabled. (since 2nd could trap on ITLB) - * If you care about DHIT and DPE bits of DR0, then - * No store instruction in the 2 insn window before RDD - */ - - -/* Move To CPU/DIAG register MTCPU r,t */ -#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \ - " mtcpu %1,%0 \n" \ - " mtcpu %1,%0" \ - : : "i" (dr), \ - "r" (gr)) - -/* Move From CPU/DIAG register MFCPU r,t */ -#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \ - " mfcpu %1,%0\n" \ - " mfcpu %1,%0" \ - : "=r" (gr) \ - : "i" (dr)) - -/* Transfer of Control Enable TOC_EN */ -#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \ - " tocen") - -/* Transfer of Control Disable TOC_DIS */ -#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \ - " tocdis") - -/* Shadow Registers to General Register SHDW_GR */ -#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \ - " shdwgr" \ - ::: "r1" "r8" "r9" "r16" \ - "r17" "r24" "r25") - -/* General Registers to Shadow Register GR_SHDW */ -#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \ - " grshdw \n" \ - " grshdw") - -/* - * Definitions of special registers for use by the above macros. - */ - -/* Hardware Space Registers */ -#define HPPA_SR0 0 -#define HPPA_SR1 1 -#define HPPA_SR2 2 -#define HPPA_SR3 3 -#define HPPA_SR4 4 -#define HPPA_SR5 5 -#define HPPA_SR6 6 -#define HPPA_SR7 7 - -/* Hardware Control Registers */ -#define HPPA_CR0 0 -#define HPPA_RCTR 0 /* Recovery Counter Register */ - -#define HPPA_CR8 8 /* Protection ID 1 */ -#define HPPA_PIDR1 8 - -#define HPPA_CR9 9 /* Protection ID 2 */ -#define HPPA_PIDR2 9 - -#define HPPA_CR10 10 -#define HPPA_CCR 10 /* Coprocessor Confiquration Register */ - -#define HPPA_CR11 11 -#define HPPA_SAR 11 /* Shift Amount Register */ - -#define HPPA_CR12 12 -#define HPPA_PIDR3 12 /* Protection ID 3 */ - -#define HPPA_CR13 13 -#define HPPA_PIDR4 13 /* Protection ID 4 */ - -#define HPPA_CR14 14 -#define HPPA_IVA 14 /* Interrupt Vector Address */ - -#define HPPA_CR15 15 -#define HPPA_EIEM 15 /* External Interrupt Enable Mask */ - -#define HPPA_CR16 16 -#define HPPA_ITMR 16 /* Interval Timer */ - -#define HPPA_CR17 17 -#define HPPA_PCSQ 17 /* Program Counter Space queue */ - -#define HPPA_CR18 18 -#define HPPA_PCOQ 18 /* Program Counter Offset queue */ - -#define HPPA_CR19 19 -#define HPPA_IIR 19 /* Interruption Instruction Register */ - -#define HPPA_CR20 20 -#define HPPA_ISR 20 /* Interruption Space Register */ - -#define HPPA_CR21 21 -#define HPPA_IOR 21 /* Interruption Offset Register */ - -#define HPPA_CR22 22 -#define HPPA_IPSW 22 /* Interrpution Processor Status Word */ - -#define HPPA_CR23 23 -#define HPPA_EIRR 23 /* External Interrupt Request */ - -#define HPPA_CR24 24 -#define HPPA_PPDA 24 /* Physcial Page Directory Address */ -#define HPPA_TR0 24 /* Temporary register 0 */ - -#define HPPA_CR25 25 -#define HPPA_HTA 25 /* Hash Table Address */ -#define HPPA_TR1 25 /* Temporary register 1 */ - -#define HPPA_CR26 26 -#define HPPA_TR2 26 /* Temporary register 2 */ - -#define HPPA_CR27 27 -#define HPPA_TR3 27 /* Temporary register 3 */ - -#define HPPA_CR28 28 -#define HPPA_TR4 28 /* Temporary register 4 */ - -#define HPPA_CR29 29 -#define HPPA_TR5 29 /* Temporary register 5 */ - -#define HPPA_CR30 30 -#define HPPA_TR6 30 /* Temporary register 6 */ - -#define HPPA_CR31 31 -#define HPPA_CPUID 31 /* MP identifier */ - -/* - * Diagnose registers - */ - -#define HPPA_DR0 0 -#define HPPA_DR1 1 -#define HPPA_DR8 8 -#define HPPA_DR24 24 -#define HPPA_DR25 25 - -/* - * Tear apart a break instruction to find its type. - */ -#define HPPA_BREAK5(x) ((x) & 0x1F) -#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF) - -/* assemble a break instruction */ -#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) | (((i13) & 0x1FFF) << 13)) - - -/* - * this won't work in ASM or non-GNU compilers - */ - -#if !defined(ASM) && defined(__GNUC__) - -/* - * static inline utility functions to get at control registers - */ - -#define EMIT_GET_CONTROL(name, reg) \ -static __inline__ unsigned int \ -get_ ## name (void) \ -{ \ - unsigned int value; \ - HPPA_ASM_MFCTL(reg, value); \ - return value; \ -} - -#define EMIT_SET_CONTROL(name, reg) \ -static __inline__ void \ -set_ ## name (unsigned int new_value) \ -{ \ - HPPA_ASM_MTCTL(new_value, reg); \ -} - -#define EMIT_CONTROLS(name, reg) \ - EMIT_GET_CONTROL(name, reg) \ - EMIT_SET_CONTROL(name, reg) - -EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */ -EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */ -EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */ -EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */ -EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */ -EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */ -EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */ -EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */ -EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */ -EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */ -EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */ -EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */ -EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */ -EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */ -EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */ -EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */ -EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */ -EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */ -EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */ -EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */ -EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */ -EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */ -EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */ -EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */ -EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */ -EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */ - -#endif /* ASM and GNU */ - -/* - * If and How to invoke the debugger (a ROM debugger generally) - */ -#define CPU_INVOKE_DEBUGGER \ - do { \ - HPPA_ASM_BREAK(1,1); \ - } while (0) - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_HPPA_H */ - diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/score/types.h b/c/src/exec/score/cpu/hppa1.1/rtems/score/types.h deleted file mode 100644 index 512323819b..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems/score/types.h +++ /dev/null @@ -1,46 +0,0 @@ -/* hppatypes.h - * - * This include file contains type definitions pertaining to the Hewlett - * Packard PA-RISC processor family. - * - * $Id$ - */ - -#ifndef _INCLUDE_HPPATYPES_H -#define _INCLUDE_HPPATYPES_H - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* 8-bit unsigned integer */ -typedef unsigned short unsigned16; /* 16-bit unsigned integer */ -typedef unsigned int unsigned32; /* 32-bit unsigned integer */ -typedef unsigned long long unsigned64; /* 64-bit unsigned integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif /* _INCLUDE_HPPATYPES_H */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/i386/.cvsignore b/c/src/exec/score/cpu/i386/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/i386/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/i386/ChangeLog b/c/src/exec/score/cpu/i386/ChangeLog deleted file mode 100644 index 5ba423533b..0000000000 --- a/c/src/exec/score/cpu/i386/ChangeLog +++ /dev/null @@ -1,135 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.S: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-03-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/idtr.h: New file, extracted from libcpu/cpu.h. - * rtems/score/interrupts.h: New file, extracted from libcpu/cpu.h. - * rtems/score/registers.h: New file, moved from libcpu. - * Makefile.am: Reflect changes above. - * cpu.c: Don't include cpuModel.h, - #include <rtems.h>, - #include <rtems/score/i386types.h>, - #include <rtems/score/idtr.h>. - * rtems/score/cpu.h: Don't include libcpu/cpu.h. - #include <rtems/score/interrupts.h>, - #include <rtems/score/registers.h>. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/i386types.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2001-02-05 Joel Sherrill <joel@OARcorp.com> - - * rtems/Makefile.am, rtems/score/Makefile.am: Removed again. - -2002-01-31 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-01-30 Joel Sherrill <joel@OARcorp.com> - - * Makefile.am: Corrected so .h files from rtems/score/ are installed. - -2002-01-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * cpu.c: Include rtems/bspIo.h instead of bspIo.h. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-12 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/i386.h: Corrected "#elsif" to be "#elif". - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/i386.h: cpu-variant define handling - Rewrite due to introduction of multilib defines. - * asm.h: include cpuopts.h instead of targopts.h - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/i386/Makefile.am b/c/src/exec/score/cpu/i386/Makefile.am deleted file mode 100644 index efcc908a16..0000000000 --- a/c/src/exec/score/cpu/i386/Makefile.am +++ /dev/null @@ -1,58 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS= asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/i386.h \ - rtems/score/types.h \ - rtems/score/interrupts.h \ - rtems/score/registers.h \ - rtems/score/idtr.h - -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -REL = $(ARCH)/rtems-cpu.rel - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/i386/asm.h b/c/src/exec/score/cpu/i386/asm.h deleted file mode 100644 index f1981791a3..0000000000 --- a/c/src/exec/score/cpu/i386/asm.h +++ /dev/null @@ -1,138 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __i386_ASM_h -#define __i386_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/i386.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -/* - * Looks like there is a bug in gcc 2.6.2 where this is not - * defined correctly when configured as i386-coff and - * i386-aout. - */ - -#undef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ % - -/* -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif -*/ - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -#define eax REG (eax) -#define ebx REG (ebx) -#define ecx REG (ecx) -#define edx REG (edx) -#define esi REG (esi) -#define edi REG (edi) -#define esp REG (esp) -#define ebp REG (ebp) -#define cr0 REG (cr0) - -#define ax REG (ax) -#define bx REG (bx) -#define cx REG (cx) -#define dx REG (dx) -#define si REG (si) -#define di REG (di) -#define sp REG (sp) -#define bp REG (bp) - -#define ah REG (ah) -#define bh REG (bh) -#define ch REG (ch) -#define dh REG (dh) - -#define al REG (al) -#define bl REG (bl) -#define cl REG (cl) -#define dl REG (dl) - -#define cs REG (cs) -#define ds REG (ds) -#define es REG (es) -#define fs REG (fs) -#define gs REG (gs) -#define ss REG (ss) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/i386/configure.ac b/c/src/exec/score/cpu/i386/configure.ac deleted file mode 100644 index ce9ddef33e..0000000000 --- a/c/src/exec/score/cpu/i386/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-i386],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/i386/cpu.c b/c/src/exec/score/cpu/i386/cpu.c deleted file mode 100644 index b55be879ab..0000000000 --- a/c/src/exec/score/cpu/i386/cpu.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Intel i386 Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems.h> -#include <rtems/system.h> -#include <rtems/score/types.h> -#include <rtems/score/isr.h> -#include <rtems/score/idtr.h> - -#include <rtems/bspIo.h> -#include <rtems/score/thread.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ -#if CPU_HARDWARE_FP - register unsigned16 fp_status asm ("ax"); - register void *fp_context; -#endif - - _CPU_Table = *cpu_table; - - /* - * The following code saves a NULL i387 context which is given - * to each task at start and restart time. The following code - * is based upon that provided in the i386 Programmer's - * Manual and should work on any coprocessor greater than - * the i80287. - * - * NOTE: The NO WAIT form of the coprocessor instructions - * MUST be used in case there is not a coprocessor - * to wait for. - */ - -#if CPU_HARDWARE_FP - fp_status = 0xa5a5; - asm volatile( "fninit" ); - asm volatile( "fnstsw %0" : "=a" (fp_status) : "0" (fp_status) ); - - if ( fp_status == 0 ) { - - fp_context = &_CPU_Null_fp_context; - - asm volatile( "fsave (%0)" : "=r" (fp_context) - : "0" (fp_context) - ); - } -#endif - -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 level; - - i386_get_interrupt_level( level ); - - return level; -} - -void _CPU_Thread_Idle_body () -{ - while(1){ - asm volatile ("hlt"); - } -} - -void _defaultExcHandler (CPU_Exception_frame *ctx) -{ - unsigned int faultAddr = 0; - printk("----------------------------------------------------------\n"); - printk("Exception %d caught at PC %x by thread %d\n", - ctx->idtIndex, - ctx->eip, - _Thread_Executing->Object.id); - printk("----------------------------------------------------------\n"); - printk("Processor execution context at time of the fault was :\n"); - printk("----------------------------------------------------------\n"); - printk(" EAX = %x EBX = %x ECX = %x EDX = %x\n", - ctx->eax, ctx->ebx, ctx->ecx, ctx->edx); - printk(" ESI = %x EDI = %x EBP = %x ESP = %x\n", - ctx->esi, ctx->edi, ctx->ebp, ctx->esp0); - printk("----------------------------------------------------------\n"); - printk("Error code pushed by processor itself (if not 0) = %x\n", - ctx->faultCode); - printk("----------------------------------------------------------\n"); - if (ctx->idtIndex == I386_EXCEPTION_PAGE_FAULT){ - faultAddr = i386_get_cr2(); - printk("Page fault linear address (CR2) = %x\n", faultAddr); - printk("----------------------------------------------------------\n\n"); - } - if (_ISR_Nest_level > 0) { - /* - * In this case we shall not delete the task interrupted as - * it has nothing to do with the fault. We cannot return either - * because the eip points to the faulty instruction so... - */ - printk("Exception while executing ISR!!!. System locked\n"); - _CPU_Fatal_halt(faultAddr); - } - else { - /* - * OK I could probably use a simplified version but at least this - * should work. - */ - printk(" ************ FAULTY THREAD WILL BE DELETED **************\n"); - rtems_task_delete(_Thread_Executing->Object.id); - } -} - -cpuExcHandlerType _currentExcHandler = _defaultExcHandler; - -extern void rtems_exception_prologue_0(); -extern void rtems_exception_prologue_1(); -extern void rtems_exception_prologue_2(); -extern void rtems_exception_prologue_3(); -extern void rtems_exception_prologue_4(); -extern void rtems_exception_prologue_5(); -extern void rtems_exception_prologue_6(); -extern void rtems_exception_prologue_7(); -extern void rtems_exception_prologue_8(); -extern void rtems_exception_prologue_9(); -extern void rtems_exception_prologue_10(); -extern void rtems_exception_prologue_11(); -extern void rtems_exception_prologue_12(); -extern void rtems_exception_prologue_13(); -extern void rtems_exception_prologue_14(); -extern void rtems_exception_prologue_16(); -extern void rtems_exception_prologue_17(); -extern void rtems_exception_prologue_18(); - -static rtems_raw_irq_hdl tbl[] = { - rtems_exception_prologue_0, - rtems_exception_prologue_1, - rtems_exception_prologue_2, - rtems_exception_prologue_3, - rtems_exception_prologue_4, - rtems_exception_prologue_5, - rtems_exception_prologue_6, - rtems_exception_prologue_7, - rtems_exception_prologue_8, - rtems_exception_prologue_9, - rtems_exception_prologue_10, - rtems_exception_prologue_11, - rtems_exception_prologue_12, - rtems_exception_prologue_13, - rtems_exception_prologue_14, - rtems_exception_prologue_16, - rtems_exception_prologue_17, - rtems_exception_prologue_18, -}; - -void rtems_exception_init_mngt() -{ - unsigned int i,j; - interrupt_gate_descriptor *currentIdtEntry; - unsigned limit; - unsigned level; - - i = sizeof(tbl) / sizeof (rtems_raw_irq_hdl); - - i386_get_info_from_IDTR (¤tIdtEntry, &limit); - - _CPU_ISR_Disable(level); - for (j = 0; j < i; j++) { - create_interrupt_gate_descriptor (¤tIdtEntry[j], tbl[j]); - } - _CPU_ISR_Enable(level); -} - diff --git a/c/src/exec/score/cpu/i386/cpu_asm.S b/c/src/exec/score/cpu/i386/cpu_asm.S deleted file mode 100644 index 85316e357a..0000000000 --- a/c/src/exec/score/cpu/i386/cpu_asm.S +++ /dev/null @@ -1,274 +0,0 @@ -/* cpu_asm.s - * - * This file contains all assembly code for the Intel i386 implementation - * of RTEMS. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <asm.h> - -/* - * Format of i386 Register structure - */ - -.set REG_EFLAGS, 0 -.set REG_ESP, REG_EFLAGS + 4 -.set REG_EBP, REG_ESP + 4 -.set REG_EBX, REG_EBP + 4 -.set REG_ESI, REG_EBX + 4 -.set REG_EDI, REG_ESI + 4 -.set SIZE_REGS, REG_EDI + 4 - - BEGIN_CODE - -/* - * void _CPU_Context_switch( run_context, heir_context ) - * - * This routine performs a normal non-FP context. - */ - - .p2align 1 - PUBLIC (_CPU_Context_switch) - -.set RUNCONTEXT_ARG, 4 # save context argument -.set HEIRCONTEXT_ARG, 8 # restore context argument - -SYM (_CPU_Context_switch): - movl RUNCONTEXT_ARG(esp),eax # eax = running threads context - pushf # push eflags - popl REG_EFLAGS(eax) # save eflags - movl esp,REG_ESP(eax) # save stack pointer - movl ebp,REG_EBP(eax) # save base pointer - movl ebx,REG_EBX(eax) # save ebx - movl esi,REG_ESI(eax) # save source register - movl edi,REG_EDI(eax) # save destination register - - movl HEIRCONTEXT_ARG(esp),eax # eax = heir threads context - -restore: - pushl REG_EFLAGS(eax) # push eflags - popf # restore eflags - movl REG_ESP(eax),esp # restore stack pointer - movl REG_EBP(eax),ebp # restore base pointer - movl REG_EBX(eax),ebx # restore ebx - movl REG_ESI(eax),esi # restore source register - movl REG_EDI(eax),edi # restore destination register - ret - -/* - * NOTE: May be unnecessary to reload some registers. - */ - -/* - * void _CPU_Context_restore( new_context ) - * - * This routine performs a normal non-FP context. - */ - - PUBLIC (_CPU_Context_restore) - -.set NEWCONTEXT_ARG, 4 # context to restore argument - -SYM (_CPU_Context_restore): - - movl NEWCONTEXT_ARG(esp),eax # eax = running threads context - jmp restore - -/*PAGE - * void _CPU_Context_save_fp_context( &fp_context_ptr ) - * void _CPU_Context_restore_fp_context( &fp_context_ptr ) - * - * This section is used to context switch an i80287, i80387, - * the built-in coprocessor or the i80486 or compatible. - */ - -.set FPCONTEXT_ARG, 4 # FP context argument - - .p2align 1 - PUBLIC (_CPU_Context_save_fp) -SYM (_CPU_Context_save_fp): - movl FPCONTEXT_ARG(esp),eax # eax = &ptr to FP context area - movl (eax),eax # eax = FP context area - fsave (eax) # save FP context - ret - - .p2align 1 - PUBLIC (_CPU_Context_restore_fp) -SYM (_CPU_Context_restore_fp): - movl FPCONTEXT_ARG(esp),eax # eax = &ptr to FP context area - movl (eax),eax # eax = FP context area - frstor (eax) # restore FP context - ret - - PUBLIC (_Exception_Handler) -SYM (_Exception_Handler): - pusha # Push general purpose registers - pushl esp # Push exception frame address - movl _currentExcHandler, eax # Call function storead in _currentExcHandler - call * eax - addl $4, esp - popa # restore general purpose registers - addl $8, esp # skill vector number and faultCode - iret - -#define DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY(_vector) \ - .p2align 4 ; \ - PUBLIC (rtems_exception_prologue_ ## _vector ) ; \ -SYM (rtems_exception_prologue_ ## _vector ): \ - pushl $ _vector ; \ - jmp SYM (_Exception_Handler) ; - -#define DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY(_vector) \ - .p2align 4 ; \ - PUBLIC (rtems_exception_prologue_ ## _vector ) ; \ -SYM (rtems_exception_prologue_ ## _vector ): \ - pushl $ 0 ; \ - pushl $ _vector ; \ - jmp SYM (_Exception_Handler) ; - -/* - * Divide Error - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (0) -/* - * Debug Exception - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (1) -/* - * NMI - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (2) -/* - * Breakpoint - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (3) -/* - * Overflow - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (4) -/* - * Bound Range Exceeded - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (5) -/* - * Invalid Opcode - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (6) -/* - * No Math Coproc - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (7) -/* - * Double Fault - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (8) -/* - * Coprocessor segment overrun - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (9) -/* - * Invalid TSS - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (10) -/* - * Segment Not Present - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (11) -/* - * Stack segment Fault - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (12) -/* - * General Protection Fault - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (13) -/* - * Page Fault - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (14) -/* - * Floating point error (NB 15 is reserved it is therefor skipped) - */ -DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (16) -/* - * Aligment Check - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (17) -/* - * Machine Check - */ -DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (18) - - -/* - * void *i386_Logical_to_physical( - * rtems_unsigned16 segment, - * void *address - * ); - * - * Returns thirty-two bit physical address for segment:address. - */ - -.set SEGMENT_ARG, 4 -.set ADDRESS_ARG, 8 - - PUBLIC (i386_Logical_to_physical) - -SYM (i386_Logical_to_physical): - - xorl eax,eax # clear eax - movzwl SEGMENT_ARG(esp),ecx # ecx = segment value - movl $ SYM (_Global_descriptor_table),edx - # edx = address of our GDT - addl ecx,edx # edx = address of desired entry - movb 7(edx),ah # ah = base 31:24 - movb 4(edx),al # al = base 23:16 - shll $16,eax # move ax into correct bits - movw 2(edx),ax # ax = base 0:15 - movl ADDRESS_ARG(esp),ecx # ecx = address to convert - addl eax,ecx # ecx = physical address equivalent - movl ecx,eax # eax = ecx - ret - -/* - * void *i386_Physical_to_logical( - * rtems_unsigned16 segment, - * void *address - * ); - * - * Returns thirty-two bit physical address for segment:address. - */ - -/* - *.set SEGMENT_ARG, 4 - *.set ADDRESS_ARG, 8 -- use sets from above - */ - - PUBLIC (i386_Physical_to_logical) - -SYM (i386_Physical_to_logical): - xorl eax,eax # clear eax - movzwl SEGMENT_ARG(esp),ecx # ecx = segment value - movl $ SYM (_Global_descriptor_table),edx - # edx = address of our GDT - addl ecx,edx # edx = address of desired entry - movb 7(edx),ah # ah = base 31:24 - movb 4(edx),al # al = base 23:16 - shll $16,eax # move ax into correct bits - movw 2(edx),ax # ax = base 0:15 - movl ADDRESS_ARG(esp),ecx # ecx = address to convert - subl eax,ecx # ecx = logical address equivalent - movl ecx,eax # eax = ecx - ret - -END_CODE - -END diff --git a/c/src/exec/score/cpu/i386/rtems/.cvsignore b/c/src/exec/score/cpu/i386/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/i386/rtems/score/.cvsignore b/c/src/exec/score/cpu/i386/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/i386/rtems/score/cpu.h b/c/src/exec/score/cpu/i386/rtems/score/cpu.h deleted file mode 100644 index a6ea2c7628..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/cpu.h +++ /dev/null @@ -1,513 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the Intel - * i386 processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/i386.h> /* pick up machine definitions */ - -#ifndef ASM -#include <rtems/score/types.h> -#include <rtems/score/interrupts.h> /* formerly in libcpu/cpu.h> */ -#include <rtems/score/registers.h> /* formerly part of libcpu */ -#endif - -/* conditional compilation parameters */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE -#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE - -/* - * i386 has an RTEMS allocated and managed interrupt stack. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Some family members have no FP, some have an FPU such as the i387 - * for the i386, others have it built in (i486DX, Pentium). - */ - -#if ( I386_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE /* i387 for i386 */ -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP FALSE -#define CPU_IDLE_TASK_IS_FP FALSE -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_STACK_GROWS_UP FALSE -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE - -/* structures */ - -/* - * Basic integer context for the i386 family. - */ - -typedef struct { - unsigned32 eflags; /* extended flags register */ - void *esp; /* extended stack pointer register */ - void *ebp; /* extended base pointer register */ - unsigned32 ebx; /* extended bx register */ - unsigned32 esi; /* extended source index register */ - unsigned32 edi; /* extended destination index flags register */ -} Context_Control; - -/* - * FP context save area for the i387 numeric coprocessors. - */ - -typedef struct { - unsigned8 fp_save_area[108]; /* context size area for I80387 */ - /* 28 bytes for environment */ -} Context_Control_fp; - - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of execptions. - * - * idtIndex is either the interrupt number or the trap/exception number. - * faultCode is the code pushed by the processor on some exceptions. - */ - -typedef struct { - unsigned32 edi; - unsigned32 esi; - unsigned32 ebp; - unsigned32 esp0; - unsigned32 ebx; - unsigned32 edx; - unsigned32 ecx; - unsigned32 eax; - unsigned32 idtIndex; - unsigned32 faultCode; - unsigned32 eip; - unsigned32 cs; - unsigned32 eflags; -} CPU_Exception_frame; - -typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); -extern cpuExcHandlerType _currentExcHandler; -extern void rtems_exception_init_mngt(); - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of each interrupt - * that will lead to re-enter the kernel to signal the thread. - */ - -typedef CPU_Exception_frame CPU_Interrupt_frame; - -typedef enum { - I386_EXCEPTION_DIVIDE_BY_ZERO = 0, - I386_EXCEPTION_DEBUG = 1, - I386_EXCEPTION_NMI = 2, - I386_EXCEPTION_BREAKPOINT = 3, - I386_EXCEPTION_OVERFLOW = 4, - I386_EXCEPTION_BOUND = 5, - I386_EXCEPTION_ILLEGAL_INSTR = 6, - I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7, - I386_EXCEPTION_DOUBLE_FAULT = 8, - I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, - I386_EXCEPTION_INVALID_TSS = 10, - I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11, - I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, - I386_EXCEPTION_GENERAL_PROT_ERR = 13, - I386_EXCEPTION_PAGE_FAULT = 14, - I386_EXCEPTION_INTEL_RES15 = 15, - I386_EXCEPTION_FLOAT_ERROR = 16, - I386_EXCEPTION_ALIGN_CHECK = 17, - I386_EXCEPTION_MACHINE_CHECK = 18, - I386_EXCEPTION_ENTER_RDBG = 50 /* to enter manually RDBG */ - -} Intel_symbolic_exception_name; - - -/* - * The following table contains the information required to configure - * the i386 specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - - unsigned32 interrupt_table_segment; - void *interrupt_table_offset; -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access i386 specific additions to the CPU Table - */ - -#define rtems_cpu_configuration_get_interrupt_table_segment() \ - (_CPU_Table.interrupt_table_segment) - -#define rtems_cpu_configuration_get_interrupt_table_offset() \ - (_CPU_Table.interrupt_table_offset) - -/* - * context size area for floating point - * - * NOTE: This is out of place on the i386 to avoid a forward reference. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* variables */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* constants */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * i386 family supports 256 distinct vectors. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Minimum size of a thread's stack. - */ - -#define CPU_STACK_MINIMUM_SIZE 1024 - -/* - * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. - */ - -#define CPU_ALIGNMENT 4 -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * On i386 thread stacks require no further alignment after allocation - * from the Workspace. - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* macros */ - -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -#define _CPU_Initialize_vectors() - -#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) - -#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) - -#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) - -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - if ( _new_level ) asm volatile ( "cli" ); \ - else asm volatile ( "sti" ); \ - } - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - */ - -#define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 -#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - do { \ - unsigned32 _stack; \ - \ - if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \ - else (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \ - \ - _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \ - \ - *((proc_ptr *)(_stack)) = (_entry_point); \ - (_the_context)->ebp = (void *) _stack; \ - (_the_context)->esp = (void *) _stack; \ - } while (0) - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -#define _CPU_Context_Initialize_fp( _fp_area ) \ - { \ - unsigned32 *_source = (unsigned32 *) &_CPU_Null_fp_context; \ - unsigned32 *_destination = *(_fp_area); \ - unsigned32 _index; \ - \ - for ( _index=0 ; _index < CPU_CONTEXT_FP_SIZE/4 ; _index++ ) \ - *_destination++ = *_source++; \ - } - -/* end of Context handler macros */ - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -#define _CPU_Fatal_halt( _error ) \ - { \ - asm volatile ( "cli ; \ - movl %0,%%eax ; \ - hlt" \ - : "=r" ((_error)) : "0" ((_error)) \ - ); \ - } - -/* end of Fatal Error manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE -#define CPU_USE_GENERIC_BITFIELD_DATA FALSE - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register unsigned16 __value_in_register = (_value); \ - \ - _output = 0; \ - \ - asm volatile ( "bsfw %0,%1 " \ - : "=r" (__value_in_register), "=r" (_output) \ - : "0" (__value_in_register), "1" (_output) \ - ); \ - } - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Thread_Idle_body - * - * Use the halt instruction of low power mode of a particular i386 model. - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) - -void _CPU_Thread_Idle_body( void ); - -#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner and avoid stack conflicts. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/i386/rtems/score/i386.h b/c/src/exec/score/cpu/i386/rtems/score/i386.h deleted file mode 100644 index 9d317f7843..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/i386.h +++ /dev/null @@ -1,244 +0,0 @@ -/* i386.h - * - * This include file contains information pertaining to the Intel - * i386 processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __i386_h -#define __i386_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section contains the information required to build - * RTEMS for a particular member of the Intel i386 - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - * - * Currently recognized: - * i386_fp (i386 DX or SX w/i387) - * i386_nofp (i386 DX or SX w/o i387) - * i486dx - * i486sx - * pentium - * pentiumpro - * - * CPU Model Feature Flags: - * - * I386_HAS_BSWAP: Defined to "1" if the instruction for endian swapping - * (bswap) should be used. This instruction appears to - * be present in all i486's and above. - * - * I386_HAS_FPU: Defined to "1" if the CPU has an FPU. - * - */ - -#if defined(_SOFT_FLOAT) -#define I386_HAS_FPU 0 -#else -#define I386_HAS_FPU 1 -#endif - -#if defined(__pentiumpro__) - -#define CPU_MODEL_NAME "Pentium Pro" - -#elif defined(__i586__) - -# if defined(__pentium__) -# define CPU_MODEL_NAME "Pentium" -# elif defined(__k6__) -# define CPU_MODEL_NAME "K6" -# else -# define CPU_MODEL_NAME "i586" -# endif - -#elif defined(__i486__) - -# if !defined(_SOFT_FLOAT) -# define CPU_MODEL_NAME "i486dx" -# else -# define CPU_MODEL_NAME "i486sx" -# endif - -#elif defined(__i386__) - -#define I386_HAS_BSWAP 0 - -# if !defined(_SOFT_FLOAT) -# define CPU_MODEL_NAME "i386 with i387" -# else -# define CPU_MODEL_NAME "i386 w/o i387" -# endif - -#else -#error "Unknown CPU Model" -#endif - -/* - * Set default values for CPU model feature flags - * - * NOTE: These settings are chosen to reflect most of the family members. - */ - -#ifndef I386_HAS_FPU -#define I386_HAS_FPU 1 -#endif - -#ifndef I386_HAS_BSWAP -#define I386_HAS_BSWAP 1 -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "Intel i386" - -#ifndef ASM - -/* - * The following routine swaps the endian format of an unsigned int. - * It must be static so it can be referenced indirectly. - */ - -static inline unsigned int i386_swap_U32( - unsigned int value -) -{ - unsigned long lout; - -#if (I386_HAS_BSWAP == 0) - asm volatile( "rorw $8,%%ax;" - "rorl $16,%0;" - "rorw $8,%%ax" : "=a" (lout) : "0" (value) ); -#else - __asm__ volatile( "bswap %0" : "=r" (lout) : "0" (value)); -#endif - return( lout ); -} - -static inline unsigned int i386_swap_U16( - unsigned int value -) -{ - unsigned short sout; - - __asm__ volatile( "rorw $8,%0" : "=r" (sout) : "0" (value)); - return (sout); -} - - -/* - * Added for pagination management - */ - -static inline unsigned int i386_get_cr0() -{ - register unsigned int segment = 0; - - asm volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static inline void i386_set_cr0(unsigned int segment) -{ - asm volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) ); -} - -static inline unsigned int i386_get_cr2() -{ - register unsigned int segment = 0; - - asm volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static inline unsigned int i386_get_cr3() -{ - register unsigned int segment = 0; - - asm volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) ); - - return segment; -} - -static inline void i386_set_cr3(unsigned int segment) -{ - asm volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) ); -} - -/* routines */ - -/* - * i386_Logical_to_physical - * - * Converts logical address to physical address. - */ - -void *i386_Logical_to_physical( - unsigned short segment, - void *address -); - -/* - * i386_Physical_to_logical - * - * Converts physical address to logical address. - */ - -void *i386_Physical_to_logical( - unsigned short segment, - void *address -); - - -/* - * "Simpler" names for a lot of the things defined in this file - */ - -/* segment access routines */ - -#define get_cs() i386_get_cs() -#define get_ds() i386_get_ds() -#define get_es() i386_get_es() -#define get_ss() i386_get_ss() -#define get_fs() i386_get_fs() -#define get_gs() i386_get_gs() - -#define CPU_swap_u32( _value ) i386_swap_U32( _value ) -#define CPU_swap_u16( _value ) i386_swap_U16( _value ) - -/* i80x86 I/O instructions */ - -#define outport_byte( _port, _value ) i386_outport_byte( _port, _value ) -#define outport_word( _port, _value ) i386_outport_word( _port, _value ) -#define outport_long( _port, _value ) i386_outport_long( _port, _value ) -#define inport_byte( _port, _value ) i386_inport_byte( _port, _value ) -#define inport_word( _port, _value ) i386_inport_word( _port, _value ) -#define inport_long( _port, _value ) i386_inport_long( _port, _value ) - - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/i386/rtems/score/idtr.h b/c/src/exec/score/cpu/i386/rtems/score/idtr.h deleted file mode 100644 index 7c4f95214f..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/idtr.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file contains definitions for data structure related - * to Intel system programming. More information can be found - * on Intel site and more precisely in the following book : - * - * Pentium Processor familly - * Developper's Manual - * - * Volume 3 : Architecture and Programming Manual - * - * Formerly contained in and extracted from libcpu/i386/cpu.h. - * - * Copyright (C) 1998 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - * Applications must not include this file directly. - */ - -#ifndef _rtems_score_idtr_h -#define _rtems_score_idtr_h - -/* - * See page 14.9 Figure 14-2. - * - */ -typedef struct -{ - unsigned int low_offsets_bits:16; - unsigned int segment_selector:16; - unsigned int fixed_value_bits:8; - unsigned int gate_type:5; - unsigned int privilege:2; - unsigned int present:1; - unsigned int high_offsets_bits:16; -} interrupt_gate_descriptor; - -/* - * C callable function enabling to create a interrupt_gate_descriptor - */ -extern void create_interrupt_gate_descriptor (interrupt_gate_descriptor*, rtems_raw_irq_hdl); - -/* - * C callable function enabling to get easily usable info from - * the actual value of IDT register. - */ -extern void i386_get_info_from_IDTR (interrupt_gate_descriptor** table, - unsigned* limit); - -/* - * C callable function enabling to change the value of IDT register. Must be called - * with interrupts masked at processor level!!!. - */ -extern void i386_set_IDTR (interrupt_gate_descriptor* table, - unsigned limit); - -#endif diff --git a/c/src/exec/score/cpu/i386/rtems/score/interrupts.h b/c/src/exec/score/cpu/i386/rtems/score/interrupts.h deleted file mode 100644 index bcc1dfb85a..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/interrupts.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * i386 interrupt macros. - * - * Formerly contained in and extracted from libcpu/i386/cpu.h - * - * COPYRIGHT (c) 1998 valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - * Applications must not include this file directly. - */ - -#ifndef _rtems_score_interrupts_h -#define _rtems_score_interrupts_h - -#ifndef ASM - -struct __rtems_raw_irq_connect_data__; - -typedef void (*rtems_raw_irq_hdl) (void); -typedef void (*rtems_raw_irq_enable) (const struct __rtems_raw_irq_connect_data__*); -typedef void (*rtems_raw_irq_disable) (const struct __rtems_raw_irq_connect_data__*); -typedef int (*rtems_raw_irq_is_enabled) (const struct __rtems_raw_irq_connect_data__*); - -/* - * Interrupt Level Macros - */ - -#define i386_disable_interrupts( _level ) \ - { \ - asm volatile ( "pushf ; \ - cli ; \ - pop %0" \ - : "=rm" ((_level)) \ - ); \ - } - -#define i386_enable_interrupts( _level ) \ - { \ - asm volatile ( "push %0 ; \ - popf" \ - : : "rm" ((_level)) : "cc" \ - ); \ - } - -#define i386_flash_interrupts( _level ) \ - { \ - asm volatile ( "push %0 ; \ - popf ; \ - cli" \ - : : "rm" ((_level)) : "cc" \ - ); \ - } - -#define i386_get_interrupt_level( _level ) \ - do { \ - register unsigned32 _eflags; \ - \ - asm volatile ( "pushf ; \ - pop %0" \ - : "=rm" ((_eflags)) \ - ); \ - \ - _level = (_eflags & EFLAGS_INTR_ENABLE) ? 0 : 1; \ - } while (0) - -#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) -#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) - -#endif -#endif diff --git a/c/src/exec/score/cpu/i386/rtems/score/registers.h b/c/src/exec/score/cpu/i386/rtems/score/registers.h deleted file mode 100644 index 993b7fb834..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/registers.h +++ /dev/null @@ -1,184 +0,0 @@ -/* registers.h - * - * This file contains definition and constants related to Intel Cpu - * - * COPYRIGHT (c) 1998 valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef _rtems_score_registers_h -#define _rtems_score_registers_h - -/* - * definition related to EFLAGS - */ -#define EFLAGS_CARRY 0x1 -#define EFLAGS_PARITY 0x4 - -#define EFLAGS_AUX_CARRY 0x10 -#define EFLAGS_ZERO 0x40 -#define EFLAGS_SIGN 0x80 - -#define EFLAGS_TRAP 0x100 -#define EFLAGS_INTR_ENABLE 0x200 -#define EFLAGS_DIRECTION 0x400 -#define EFLAGS_OVERFLOW 0x800 - -#define EFLAGS_IOPL_MASK 0x3000 -#define EFLAGS_NESTED_TASK 0x8000 - -#define EFLAGS_RESUME 0x10000 -#define EFLAGS_VIRTUAL_MODE 0x20000 -#define EFLAGS_ALIGN_CHECK 0x40000 -#define EFLAGS_VIRTUAL_INTR 0x80000 - -#define EFLAGS_VIRTUAL_INTR_PEND 0x100000 -#define EFLAGS_ID 0x200000 - -/* - * definitions related to CR0 - */ -#define CR0_PROTECTION_ENABLE 0x1 -#define CR0_MONITOR_COPROC 0x2 -#define CR0_COPROC_SOFT_EMUL 0x4 -#define CR0_FLOATING_INSTR_EXCEPTION 0x8 - -#define CR0_EXTENSION_TYPE 0x10 -#define CR0_NUMERIC_ERROR 0x20 - -#define CR0_WRITE_PROTECT 0x10000 -#define CR0_ALIGMENT_MASK 0x40000 - -#define CR0_NO_WRITE_THROUGH 0x20000000 -#define CR0_PAGE_LEVEL_CACHE_DISABLE 0x40000000 -#define CR0_PAGING 0x80000000 - -/* - * definitions related to CR3 - */ - -#define CR3_PAGE_CACHE_DISABLE 0x10 -#define CR3_PAGE_WRITE_THROUGH 0x8 - - -#ifndef ASM - -/* - * definition of eflags registers has a bit field structure - */ -typedef struct { - /* - * fist byte : bits 0->7 - */ - unsigned int carry : 1; - unsigned int : 1; - unsigned int parity : 1; - unsigned int : 1; - - unsigned int auxiliary_carry : 1; - unsigned int : 1; - unsigned int zero : 1; /* result is zero */ - unsigned int sign : 1; /* result is less than zero */ - /* - * Second byte : bits 7->15 - */ - unsigned int trap : 1; - unsigned int intr_enable : 1; /* set => intr on */ - unsigned int direction : 1; /* set => autodecrement */ - unsigned int overflow : 1; - - unsigned int IO_privilege : 2; - unsigned int nested_task : 1; - unsigned int : 1; - /* - * Third byte : bits 15->23 - */ - unsigned int resume : 1; - unsigned int virtual_mode : 1; - unsigned int aligment_check : 1; - unsigned int virtual_intr : 1; - - unsigned int virtual_intr_pending : 1; - unsigned int id : 1; - unsigned int : 2; - - /* - * fourth byte : bits 24->31 : UNUSED - */ - unsigned int : 8; -}eflags_bits; - -typedef union { - eflags_bits eflags; - unsigned int i; -}eflags; -/* - * definition of eflags registers has a bit field structure - */ -typedef struct { - /* - * fist byte : bits 0->7 - */ - unsigned int protection_enable : 1; - unsigned int monitor_coproc : 1; - unsigned int coproc_soft_emul : 1; - unsigned int floating_instr_except : 1; - - unsigned int extension_type : 1; - unsigned int numeric_error : 1; - unsigned int : 2; - /* - * second byte 8->15 : UNUSED - */ - unsigned int : 8; - /* - * third byte 16->23 - */ - unsigned int write_protect : 1; - unsigned int : 1; - unsigned int aligment_mask : 1; - unsigned int : 1; - - unsigned int : 4; - /* - * fourth byte 24->31 - */ - unsigned int : 4; - - unsigned int : 1; - unsigned int no_write_through : 1; - unsigned int page_level_cache_disable : 1; - unsigned int paging : 1; -}cr0_bits; - -typedef union { - cr0_bits cr0; - unsigned int i; -}cr0; - -/* - * definition of cr3 registers has a bit field structure - */ -typedef struct { - - unsigned int : 3; - unsigned int page_write_transparent : 1; - unsigned int page_cache_disable : 1; - unsigned int : 7; - unsigned int page_directory_base :20; -}cr3_bits; - -typedef union { - cr3_bits cr3; - unsigned int i; -}cr3; - -#endif - -#endif - diff --git a/c/src/exec/score/cpu/i386/rtems/score/types.h b/c/src/exec/score/cpu/i386/rtems/score/types.h deleted file mode 100644 index 1b9091f501..0000000000 --- a/c/src/exec/score/cpu/i386/rtems/score/types.h +++ /dev/null @@ -1,57 +0,0 @@ -/* i386types.h - * - * This include file contains type definitions pertaining to the Intel - * i386 processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __i386_TYPES_h -#define __i386_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void i386_isr; - -typedef i386_isr ( *i386_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/i960/.cvsignore b/c/src/exec/score/cpu/i960/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/i960/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/i960/ChangeLog b/c/src/exec/score/cpu/i960/ChangeLog deleted file mode 100644 index 61e394c060..0000000000 --- a/c/src/exec/score/cpu/i960/ChangeLog +++ /dev/null @@ -1,113 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.S: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/m68ktypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/i960types.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - * cpu_asm.S: Modify to properly dereference _ISR_Vector_table - now that it is dynamically allocated. - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/i960/Makefile.am b/c/src/exec/score/cpu/i960/Makefile.am deleted file mode 100644 index 4a60795a5e..0000000000 --- a/c/src/exec/score/cpu/i960/Makefile.am +++ /dev/null @@ -1,54 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/i960.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S i960RP.h - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/i960/asm.h b/c/src/exec/score/cpu/i960/asm.h deleted file mode 100644 index e98f900f59..0000000000 --- a/c/src/exec/score/cpu/i960/asm.h +++ /dev/null @@ -1,110 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __i960_ASM_h -#define __i960_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/i960.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -#define g0 REG (g0) -#define g1 REG (g1) -#define g2 REG (g2) -#define g3 REG (g3) -#define g4 REG (g4) -#define g5 REG (g5) -#define g6 REG (g6) -#define g7 REG (g7) -#define g8 REG (g8) -#define g9 REG (g9) -#define g10 REG (g10) -#define g11 REG (g11) -#define g12 REG (g12) -#define g13 REG (g13) -#define g14 REG (g14) -#define g15 REG (g15) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/i960/configure.ac b/c/src/exec/score/cpu/i960/configure.ac deleted file mode 100644 index 90beb7ec0d..0000000000 --- a/c/src/exec/score/cpu/i960/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-i960],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/i960/cpu.c b/c/src/exec/score/cpu/i960/cpu.c deleted file mode 100644 index 78eeb3c5f2..0000000000 --- a/c/src/exec/score/cpu/i960/cpu.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Intel i960CA Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - * - * OUTPUT PARAMETERS: NONE - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - - _CPU_Table = *cpu_table; - -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 level; - - i960_get_interrupt_level( level ); - - return level; -} - -/*PAGE - * - * _CPU__ISR_install_vector - * - * Install the RTEMS vector wrapper in the CPU's interrupt table. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - proc_ptr ignored; - - *old_handler = _ISR_Vector_table[ vector ]; - - _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); - - _ISR_Vector_table[ vector ] = new_handler; -} diff --git a/c/src/exec/score/cpu/i960/cpu_asm.S b/c/src/exec/score/cpu/i960/cpu_asm.S deleted file mode 100644 index 82906ad4ff..0000000000 --- a/c/src/exec/score/cpu/i960/cpu_asm.S +++ /dev/null @@ -1,214 +0,0 @@ -/* - * This file contains all assembly code for the i960 port of RTEMS. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - .data -_ISR_reg_save: - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - - .text -/* - * Format of i960ca Register structure - */ - -.set REG_R0_PFP , 0 # (r0) Previous Frame Pointer -.set REG_R1_SP , REG_R0_PFP+4 # (r1) Stack Pointer -.set REG_PC , REG_R1_SP+4 # (pc) Processor Controls -.set REG_G8 , REG_PC+4 # (g8) Global Register 8 -.set REG_G9 , REG_G8+4 # (g9) Global Register 9 -.set REG_G10 , REG_G9+4 # (g10) Global Register 10 -.set REG_G11 , REG_G10+4 # (g11) Global Register 11 -.set REG_G12 , REG_G11+4 # (g12) Global Register 12 -.set REG_G13 , REG_G12+4 # (g13) Global Register 13 -.set REG_G14 , REG_G13+4 # (g14) Global Register 14 -.set REG_G15_FP , REG_G14+4 # (g15) Global Register 15 -.set SIZE_REGS , REG_G15_FP+4 # size of cpu_context_registers - # structure - -/* - * void _CPU_Context_switch( run_context, heir_context ) - * - * This routine performs a normal non-FP context. - */ - .align 4 - .globl __CPU_Context_switch - -__CPU_Context_switch: - modpc 0,0,g2 # get old intr level (PC) - st g2,REG_PC(g0) # save pc - stq g8,REG_G8(g0) # save g8-g11 - stq g12,REG_G12(g0) # save g12-g15 - stl pfp,REG_R0_PFP(g0) # save pfp, sp - -restore: flushreg # flush register cache - ldconst 0x001f0000,g2 # g2 = PC mask - ld REG_PC(g1),g3 # thread->Regs.pc = pc; - ldq REG_G12(g1),g12 # restore g12-g15 - ldl REG_R0_PFP(g1),pfp # restore pfp, sp - ldq REG_G8(g1),g8 # restore g8-g11 - modpc 0,g2,g3 # restore PC register - ret - -/* - * void _CPU_Context_restore( new_context ) - * - * This routine performs a normal non-FP context. - */ - - .globl __CPU_Context_restore -__CPU_Context_restore: - mov g0,g1 # g0 = _Thread_executing - b restore - -/*PAGE - * void _CPU_Context_save_fp_context( &fp_context_ptr ) - * void _CPU_Context_restore_fp_context( &fp_context_ptr ) - * - * There is currently no hardware floating point for the i960. - */ - - .globl __CPU_Context_save_fp - .globl __CPU_Context_restore_fp -__CPU_Context_save_fp: -__CPU_Context_restore_fp: -#if ( I960_HAS_FPU == 1 ) -#error "Floating point support for i960 family has been implemented!!!" -#endif - ret - -/*PAGE - * void __ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * NOTE: - * Upon entry, the supervisor stack will contain a stack frame - * back to the interrupted thread and the interrupt stack will contain - * an interrupt stack frame. If dispatching is enabled, this - * is the outer most interrupt, and (a context switch is necessary or - * the current thread has signals), then set up the supervisor stack to - * transfer control to the interrupt dispatcher. - */ - - .globl __ISR_Handler -__ISR_Handler: - #ldconst 1,r8 - #modpc 0,r8,r8 # enable tracing - - # r4 = &_Thread_Dispatch_disable_level - ld __Thread_Dispatch_disable_level,r4 - movl g0,r8 # save g0-g1 - - ld -16+8(fp),g0 # g0 = vector number - movl g2,r10 # save g2-g3 - - ld __ISR_Nest_level,r5 # r5 = &_Isr_nest_level - mov g14,r7 # save g14 - - lda 0,g14 # NOT Branch and Link - movl g4,r12 # save g4-g5 - - lda 1(r4),r4 # increment dispatch disable level - movl g6,r14 # save g6-g7 - - ld __ISR_Vector_table,g1 # g1 = base of vector table - - stq g8, _ISR_reg_save # save g8-g11 - stl g12, _ISR_reg_save+16 # save g12-g13 - - ld (g1)[g0*4],g1 # g1 = Users handler - addo 1,r5,r5 # increment ISR level - - st r4,__Thread_Dispatch_disable_level - # one ISR nest level deeper - subo 1,r4,r4 # decrement dispatch disable level - - st r5,__ISR_Nest_level # disable multitasking - subo 1,r5,r5 # decrement ISR nest level - - callx (g1) # invoke user ISR - - # unnest multitasking - st r5,__ISR_Nest_level # one less ISR nest level - cmpobne.f 0,r4,exit # If dispatch disabled, exit - ldl -16(fp),g0 # g0 = threads PC reg - # g1 = threads AC reg - ld __Context_Switch_necessary,r6 - # r6 = Is thread switch necessary? - bbs.f 13,g0,exit # not outer level, then exit - cmpobne.f 0,r6,bframe # Switch necessary? - - ld __ISR_Signals_to_thread_executing,g2 - # signals sent to Run_thread - # while in interrupt handler? - cmpobe.f 0,g2,exit # No, then exit - -bframe: mov 0,g2 - st g2,__ISR_Signals_to_thread_executing - - ldconst 0x1f0000,g2 # g2 = intr disable mask - mov g2,g3 # g3 = new intr level - modpc 0,g2,g3 # set new level - - andnot 7,pfp,r4 # r4 = pfp without ret type - flushreg # flush registers - # push _Isr_dispatch ret frame - # build ISF in r4-r6 - ldconst 64,g2 # g2 = size of stack frame - ld 4(r4),g3 # g3 = previous sp - addo g2,g3,r5 # r5 = _Isr_dispatch SP - lda __ISR_Dispatch,r6 # r6 = _Isr_dispatch entry - stt r4,(g3) # set _Isr_dispatch ret info - st g1,16(g3) # set r4 = AC for ISR disp - or 7,g3,pfp # pfp to _Isr_dispatch - flushreg - b exit1 -exit: st r4,__Thread_Dispatch_disable_level -exit1: mov r7,g14 # restore g14 - movq r8,g0 # restore g0-g3 - movq r12,g4 # restore g4-g7 - ldq _ISR_reg_save, g8 # restore g8-g11 - ldl _ISR_reg_save+16, g12 # restore g12-g13 - ret - - -/*PAGE - * - * void __ISR_Dispatch() - * - * Entry point from the outermost interrupt service routine exit. - * The current stack is the supervisor mode stack. - */ - - .globl __ISR_Dispatch -__ISR_Dispatch: - mov g14,r7 - mov 0,g14 - movq g0,r8 - movq g4,r12 - call __Thread_Dispatch - - ldconst -1,r5 # r5 = reload mask - modac r5,r4,r4 # restore threads AC register - mov r7,g14 - movq r8,g0 - movq r12,g4 - ret - diff --git a/c/src/exec/score/cpu/i960/rtems/.cvsignore b/c/src/exec/score/cpu/i960/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/i960/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/i960/rtems/score/.cvsignore b/c/src/exec/score/cpu/i960/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/i960/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/i960/rtems/score/cpu.h b/c/src/exec/score/cpu/i960/rtems/score/cpu.h deleted file mode 100644 index a3251dae3c..0000000000 --- a/c/src/exec/score/cpu/i960/rtems/score/cpu.h +++ /dev/null @@ -1,485 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the Intel - * i960 processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/i960.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -#define CPU_INLINE_ENABLE_DISPATCH FALSE -#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE - -/* - * Use the i960's hardware interrupt stack support and have the - * interrupt manager allocate the memory for it. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Some family members have no FP (SA/KA/CA/CF), others have it built in - * (KB/MC/MX). There does not appear to be an external coprocessor - * for this family. - */ - -#if ( I960_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#error "Floating point support for i960 family has been implemented!!!" -#else -#define CPU_HARDWARE_FP FALSE -#endif - -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP FALSE -#define CPU_IDLE_TASK_IS_FP FALSE -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE -#define CPU_STACK_GROWS_UP TRUE -#define CPU_STRUCTURE_ALIGNMENT /* __attribute__ ((aligned (16))) */ - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - - -/* structures */ - -/* - * Basic integer context for the i960 family. - */ - -typedef struct { - void *r0_pfp; /* (r0) Previous Frame Pointer */ - void *r1_sp; /* (r1) Stack Pointer */ - unsigned32 pc; /* (pc) Processor Control */ - void *g8; /* (g8) Global Register 8 */ - void *g9; /* (g9) Global Register 9 */ - void *g10; /* (g10) Global Register 10 */ - void *g11; /* (g11) Global Register 11 */ - void *g12; /* (g12) Global Register 12 */ - void *g13; /* (g13) Global Register 13 */ - unsigned32 g14; /* (g14) Global Register 14 */ - void *g15_fp; /* (g15) Frame Pointer */ -} Context_Control; - -/* - * FP context save area for the i960 Numeric Extension - */ - -typedef struct { - unsigned32 fp0_1; /* (fp0) first word */ - unsigned32 fp0_2; /* (fp0) second word */ - unsigned32 fp0_3; /* (fp0) third word */ - unsigned32 fp1_1; /* (fp1) first word */ - unsigned32 fp1_2; /* (fp1) second word */ - unsigned32 fp1_3; /* (fp1) third word */ - unsigned32 fp2_1; /* (fp2) first word */ - unsigned32 fp2_2; /* (fp2) second word */ - unsigned32 fp2_3; /* (fp2) third word */ - unsigned32 fp3_1; /* (fp3) first word */ - unsigned32 fp3_2; /* (fp3) second word */ - unsigned32 fp3_3; /* (fp3) third word */ -} Context_Control_fp; - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of each interrupt. - */ - -typedef struct { - unsigned32 TBD; /* XXX Fix for this CPU */ -} CPU_Interrupt_frame; - -/* - * Call frame for the i960 family. - */ - -typedef struct { - void *r0_pfp; /* (r0) Previous Frame Pointer */ - void *r1_sp; /* (r1) Stack Pointer */ - void *r2_rip; /* (r2) Return Instruction Pointer */ - void *r3; /* (r3) Local Register 3 */ - void *r4; /* (r4) Local Register 4 */ - void *r5; /* (r5) Local Register 5 */ - void *r6; /* (r6) Local Register 6 */ - void *r7; /* (r7) Local Register 7 */ - void *r8; /* (r8) Local Register 8 */ - void *r9; /* (r9) Local Register 9 */ - void *r10; /* (r10) Local Register 10 */ - void *r11; /* (r11) Local Register 11 */ - void *r12; /* (r12) Local Register 12 */ - void *r13; /* (r13) Local Register 13 */ - void *r14; /* (r14) Local Register 14 */ - void *r15; /* (r15) Local Register 15 */ - /* XXX Looks like sometimes there is FP stuff here (MC manual)? */ -} CPU_Call_frame; - -/* - * The following table contains the information required to configure - * the i960 specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access i960 specific additions to the CPU Table - * - * NONE - */ - -/* variables */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* constants */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x0000001f /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x0000001f /* interrupt level in mode */ - -/* - * context size area for floating point - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE) - -/* - * i960 family supports 256 distinct vectors. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Minimum size of a thread's stack. - * - * NOTE: See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK - */ - -#define CPU_STACK_MINIMUM_SIZE 2048 - -/* - * i960 is pretty tolerant of alignment but some CPU models do - * better with different default aligments so we use what the - * CPU model selected in rtems/score/i960.h. - */ - -#define CPU_ALIGNMENT I960_CPU_ALIGNMENT -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * i960ca stack requires 16 byte alignment - * - * NOTE: This factor may need to be family member dependent. - */ - -#define CPU_STACK_ALIGNMENT 16 - -/* macros */ - -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -#define _CPU_Initialize_vectors() -#define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level ) -#define _CPU_ISR_Enable( _level ) i960_enable_interrupts( _level ) -#define _CPU_ISR_Flash( _level ) i960_flash_interrupts( _level ) - -#define _CPU_ISR_Set_level( newlevel ) \ - { \ - unsigned32 _mask = 0; \ - unsigned32 _level = (newlevel); \ - \ - __asm__ volatile ( "ldconst 0x1f0000,%0; \ - modpc 0,%0,%1" : "=d" (_mask), "=d" (_level) \ - : "0" (_mask), "1" (_level) \ - ); \ - } - -unsigned32 _CPU_ISR_Get_level( void ); - -/* ISR handler section macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - */ - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry, _is_fp ) \ - { CPU_Call_frame *_texit_frame; \ - unsigned32 _mask; \ - unsigned32 _base_pc; \ - unsigned32 _stack_tmp; \ - void *_stack; \ - \ - _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \ - _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \ - _stack = (void *) _stack_tmp; \ - \ - __asm__ volatile ( "flushreg" : : ); /* flush register cache */ \ - \ - (_the_context)->r0_pfp = _stack; \ - (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \ - (_the_context)->r1_sp = _stack + (2 * sizeof(CPU_Call_frame)); \ - __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \ - "modpc 0,0,%1 ; " \ - "andnot %0,%1,%1 ; " \ - : "=d" (_mask), "=d" (_base_pc) : ); \ - (_the_context)->pc = _base_pc | ((_isr) << 16); \ - (_the_context)->g14 = 0; \ - \ - _texit_frame = (CPU_Call_frame *)_stack; \ - _texit_frame->r0_pfp = NULL; \ - _texit_frame->r1_sp = (_the_context)->g15_fp; \ - _texit_frame->r2_rip = (_entry); \ - } - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#define _CPU_Context_Fp_start( _base, _offset ) NULL - -#define _CPU_Context_Initialize_fp( _fp_area ) - -/* end of Context handler macros */ - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -#define _CPU_Fatal_halt( _errorcode ) \ - { unsigned32 _mask, _level; \ - unsigned32 _error = (_errorcode); \ - \ - __asm__ volatile ( "ldconst 0x1f0000,%0 ; \ - mov %0,%1 ; \ - modpc 0,%0,%1 ; \ - mov %2,g0 ; \ - self: b self " \ - : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \ - } - -/* end of Fatal Error Manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE -#define CPU_USE_GENERIC_BITFIELD_DATA FALSE - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { unsigned32 _search = (_value); \ - \ - (_output) = 0; /* to prevent warnings */ \ - __asm__ volatile ( "scanbit %0,%1 " \ - : "=d" (_search), "=d" (_output) \ - : "0" (_search), "1" (_output) ); \ - } - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x8000 >> (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - ( 15 - (_priority) ) - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner and avoid stack conflicts. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/i960/rtems/score/i960.h b/c/src/exec/score/cpu/i960/rtems/score/i960.h deleted file mode 100644 index 6cc60af8c9..0000000000 --- a/c/src/exec/score/cpu/i960/rtems/score/i960.h +++ /dev/null @@ -1,194 +0,0 @@ -/* i960.h - * - * This include file contains information pertaining to the Intel - * i960 processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __i960_h -#define __i960_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the Intel i960 - * family. It does this by setting variables to indicate - * which implementation dependent features are present - * in a particular member of the family. - * - * NOTE: For now i960 support is for models without an FPU. - * The stubs for FP routines are in place so only need to be filled in. - * - * NOTE: RTEMS defines a canonical name for each cpu model. - */ - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "Intel i960" - -/* - * This should work since most i960 models do not have FPUs. The logic is: - * - * + If the user specifically asks for soft-float, give it to them - * regardless of hardware availability. - * + If the CPU has hardware FPU, then use it. - * + Otherwise, we have to use soft float. - */ - -#if defined(_SOFT_FLOAT) -#define I960_HAS_FPU 0 -#elif defined(_i960_KB__) || defined(_i960_SB__) || defined(_i960_SB__) || \ - defined(_i960_JF__) || defined(_i960_MC__) || defined(_i960_CC__) -#define I960_HAS_FPU 1 -#else -#define I960_HAS_FPU 0 -#endif - -/* - * Some of the CPU models may have better performance with - * alignment of 8 or 16 but we don't know what model we are - * being compiled for based solely on the information provided - * when multilibbing. - */ - -#define I960_CPU_ALIGNMENT 4 - -/* - * This is not the perfect CPU model name but it is adequate and - * reflects what we know from multilib. - */ - -#if I960_HAS_FPU -#define CPU_MODEL_NAME "w/FPU" -#else -#define CPU_MODEL_NAME "w/soft-float" -#endif -#ifndef ASM - - -/* - * Miscellaneous Support Routines - */ - -#define i960_reload_ctl_group( group ) \ - { register int _cmd = ((group)|0x400) ; \ - asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \ - } - -#define i960_atomic_modify( mask, addr, prev ) \ - { register unsigned int _mask = (mask); \ - register unsigned int *_addr = (unsigned int *)(addr); \ - asm volatile( "atmod %0,%1,%1" \ - : "=d" (_addr), "=d" (_mask) \ - : "0" (_addr), "1" (_mask) ); \ - (prev) = _mask; \ - } - -#define atomic_modify( _mask, _address, _previous ) \ - i960_atomic_modify( _mask, _address, _previous ) - -#define i960_enable_tracing() \ - { register unsigned int _pc = 0x1; \ - asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \ - } - -/* - * Interrupt Level Routines - */ - -#define i960_disable_interrupts( oldlevel ) \ - { (oldlevel) = 0x1f0000; \ - asm volatile ( "modpc 0,%1,%1" \ - : "=d" ((oldlevel)) \ - : "0" ((oldlevel)) ); \ - } - -#define i960_enable_interrupts( oldlevel ) \ - { unsigned int _mask = 0x1f0000; \ - asm volatile ( "modpc 0,%0,%1" \ - : "=d" (_mask), "=d" ((oldlevel)) \ - : "0" (_mask), "1" ((oldlevel)) ); \ - } - -#define i960_flash_interrupts( oldlevel ) \ - { unsigned int _mask = 0x1f0000; \ - asm volatile ( "modpc 0,%0,%1 ; \ - mov %0,%1 ; \ - modpc 0,%0,%1" \ - : "=d" (_mask), "=d" ((oldlevel)) \ - : "0" (_mask), "1" ((oldlevel)) ); \ - } - -#define i960_get_interrupt_level( _level ) \ - { \ - i960_disable_interrupts( _level ); \ - i960_enable_interrupts( _level ); \ - (_level) = ((_level) & 0x1f0000) >> 16; \ - } while ( 0 ) - -#define i960_cause_intr( intr ) \ - { register int _intr = (intr); \ - asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \ - } - -/* - * Interrupt Masking Routines - */ - -static inline unsigned int i960_get_fp() -{ register unsigned int _fp=0; - asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) ); - return ( _fp ); -} - -/* - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version is based on code presented in Vol. 4, No. 4 of - * Insight 960. It is certainly something you wouldn't think - * of on your own. - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - register unsigned int to_swap = value; - register unsigned int temp = 0xFF00FF00; - register unsigned int swapped = 0; - - /* to_swap swapped */ - asm volatile ( "rotate 16,%0,%2 ;" /* 0x12345678 0x56781234 */ - "modify %1,%0,%2 ;" /* 0x12345678 0x12785634 */ - "rotate 8,%2,%2" /* 0x12345678 0x78563412 */ - : "=r" (to_swap), "=r" (temp), "=r" (swapped) - : "0" (to_swap), "1" (temp), "2" (swapped) - ); - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/i960/rtems/score/types.h b/c/src/exec/score/cpu/i960/rtems/score/types.h deleted file mode 100644 index 81deddaa1f..0000000000 --- a/c/src/exec/score/cpu/i960/rtems/score/types.h +++ /dev/null @@ -1,57 +0,0 @@ -/* i960types.h - * - * This include file contains type definitions pertaining to the Intel - * i960 processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __i960_TYPES_h -#define __i960_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned32 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void i960_isr; - -typedef void ( *i960_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/m68k/.cvsignore b/c/src/exec/score/cpu/m68k/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/m68k/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/m68k/ChangeLog b/c/src/exec/score/cpu/m68k/ChangeLog deleted file mode 100644 index 6cf037728b..0000000000 --- a/c/src/exec/score/cpu/m68k/ChangeLog +++ /dev/null @@ -1,145 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.S: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-05-28 Chris Johns <ccj@acm.org> - - * rtems/score/m68k.h: Per PR227, mc68060 does not require FPSP - since it is now multilib'ed. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * include/rtems/score/ispsh7750.h, score/ispsh7750.c: Account for - name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-03-15 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/m68k.h: m68k_swap_u32 fix typo. - -2002-03-06 Victor V. Vengerov <vvv@oktet.ru> - - * rtems/score/m68k.h [M68K_COLDFIRE_ARCH] (CPU_swap_u16, CPU_swap_u32): - Generic implementation of endian swap primitives added for Coldfire - family. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-08-09 Chris Johns <ccj@acm.org> - - * cpu_asm.S: This patch was co-developed with Eric Norum - <eric.norum@usask.ca>. It closes a one instruction window - on some m68k CPU cores. It fixes symptoms seen as: - 1) No more `interrupt handler invoked twice for - a single interrupt'. - 2) No more `lockup when mc68360 CPM and PIT interrupts - are at different levels'. - It does insert a little more overhead on machines without hardware - interrupt stacks but correctness has a price. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - * cpu_asm.S: Modify to properly dereference _ISR_Vector_table - now that it is dynamically allocated. - -2000-12-19 Joel Sherrill <joel@OARcorp.com> - - * cpu.c: Do not read or write raw interrupt vector table if - we are on a CPU that does not have a %vbr register and the - BSP is configured as having the table in ROM. - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-10-19 Antti P Miettinen <anmietti@trshp.ntc.nokia.com> - - * rtems/score/cpu.h: define CPU_Exception_frame for rdbg. - * m68302.h: Make buffer pointer in m302_SCC_bd volatile. - -2000-10-12 John S Gwynne <jgwynne@mrcday.com> - - * sim.h: These changes enable RTEMS to automatically generate - the ram_init file used by gdb with the BDM patches. The 332 has - on-board chip select lines (for RAM and FLASH) that must be - configured before use of these peripherals. These patches parse - data from start.c where the chip select lines are configured in - the runtime executable and automatically generates the gdb - initialization file using the same settings. A great time saver. - A similar file, ram_init_FW (flash writable), is also generated - that the flash programming tool uses. - * BSP/start/start.c: Must be modified to support above. - * BSP/start/ram_init.ld, BSP/start/ram_init.sed: New files. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/m68k/Makefile.am b/c/src/exec/score/cpu/m68k/Makefile.am deleted file mode 100644 index 147cbfae7d..0000000000 --- a/c/src/exec/score/cpu/m68k/Makefile.am +++ /dev/null @@ -1,54 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h m68302.h m68360.h qsm.h sim.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/m68k.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c memcpy.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S memcpy.c - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/m68k/asm.h b/c/src/exec/score/cpu/m68k/asm.h deleted file mode 100644 index 6c388fb396..0000000000 --- a/c/src/exec/score/cpu/m68k/asm.h +++ /dev/null @@ -1,144 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __M68k_ASM_h -#define __M68k_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/cpu.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -#define d0 REG (d0) -#define d1 REG (d1) -#define d2 REG (d2) -#define d3 REG (d3) -#define d4 REG (d4) -#define d5 REG (d5) -#define d6 REG (d6) -#define d7 REG (d7) -#define a0 REG (a0) -#define a1 REG (a1) -#define a2 REG (a2) -#define a3 REG (a3) -#define a4 REG (a4) -#define a5 REG (a5) -#define a6 REG (a6) -#define a7 REG (a7) -#define sp REG (sp) - -#define msp REG (msp) -#define usp REG (usp) -#define isp REG (isp) -#define sr REG (sr) -#define vbr REG (vbr) -#define dfc REG (dfc) -#define sfc REG (sfc) - -/* mcf52xx special regs */ -#define cacr REG (cacr) -#define acr0 REG (acr0) -#define acr1 REG (acr1) -#define rambar0 REG (rambar0) -#define mbar REG (mbar) - - -#define fp0 REG (fp0) -#define fp1 REG (fp1) -#define fp2 REG (fp2) -#define fp3 REG (fp3) -#define fp4 REG (fp4) -#define fp5 REG (fp5) -#define fp6 REG (fp6) -#define fp7 REG (fp7) - -#define fpc REG (fpc) -#define fpi REG (fpi) -#define fps REG (fps) -#define fpsr REG (fpsr) - - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/m68k/configure.ac b/c/src/exec/score/cpu/m68k/configure.ac deleted file mode 100644 index b812d9897a..0000000000 --- a/c/src/exec/score/cpu/m68k/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-m68k],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/m68k/cpu.c b/c/src/exec/score/cpu/m68k/cpu.c deleted file mode 100644 index c7337c378e..0000000000 --- a/c/src/exec/score/cpu/m68k/cpu.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Motorola MC68xxx Dependent Source - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - entry pointer to thread dispatcher - * - * OUTPUT PARAMETERS: NONE - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ -#if ( M68K_HAS_VBR == 0 ) - /* fill the isr redirect table with the code to place the format/id - onto the stack */ - - unsigned32 slot; - - for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++) - { - _CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7; - _CPU_ISR_jump_table[slot].format_id = slot << 2; - _CPU_ISR_jump_table[slot].jmp = M68K_JMP; - _CPU_ISR_jump_table[slot].isr_handler = (unsigned32) 0xDEADDEAD; - } -#endif /* M68K_HAS_VBR */ - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 level; - - m68k_get_interrupt_level( level ); - - return level; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - proc_ptr *interrupt_table = NULL; - -#if (M68K_HAS_FPSP_PACKAGE == 1) - /* - * If this vector being installed is one related to FP, then the - * FPSP will install the handler itself and handle it completely - * with no intervention from RTEMS. - */ - - if (*_FPSP_install_raw_handler && - (*_FPSP_install_raw_handler)(vector, new_handler, *old_handler)) - return; -#endif - - - /* - * On CPU models without a VBR, it is necessary for there to be some - * header code for each ISR which saves a register, loads the vector - * number, and jumps to _ISR_Handler. - */ - - m68k_get_vbr( interrupt_table ); -#if ( M68K_HAS_VBR == 1 ) - *old_handler = interrupt_table[ vector ]; - interrupt_table[ vector ] = new_handler; -#else - - /* - * Install handler into RTEMS jump table and if VBR table is in - * RAM, install the pointer to the appropriate jump table slot. - * If the VBR table is in ROM, it is the BSP's responsibility to - * load it appropriately to vector to the RTEMS jump table. - */ - - *old_handler = _CPU_ISR_jump_table[vector].isr_handler; - _CPU_ISR_jump_table[vector].isr_handler = (unsigned32) new_handler; - if ( (unsigned32) interrupt_table != 0xFFFFFFFF ) - interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector]; -#endif /* M68K_HAS_VBR */ -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * new_handler - replacement ISR for this vector number - * old_handler - former ISR for this vector number - * - * Output parameters: NONE - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - proc_ptr ignored; - - *old_handler = _ISR_Vector_table[ vector ]; - - _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); - - _ISR_Vector_table[ vector ] = new_handler; -} - - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - void *isp = _CPU_Interrupt_stack_high; - - asm volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) ); -#endif -} - -#if ( M68K_HAS_BFFFO != 1 ) -/* - * Returns table for duplication of the BFFFO instruction (16 bits only) - */ -const unsigned char __BFFFOtable[256] = { - 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; -#endif - -/*PAGE - * - * The following code context switches the software FPU emulation - * code provided with GCC. - */ - -#if (CPU_SOFTWARE_FP == TRUE) -extern Context_Control_fp _fpCCR; - -void CPU_Context_save_fp (void **fp_context_ptr) -{ - Context_Control_fp *fp; - - fp = (Context_Control_fp *) *fp_context_ptr; - - *fp = _fpCCR; -} - -void CPU_Context_restore_fp (void **fp_context_ptr) -{ - Context_Control_fp *fp; - - fp = (Context_Control_fp *) *fp_context_ptr; - - _fpCCR = *fp; -} -#endif - diff --git a/c/src/exec/score/cpu/m68k/cpu_asm.S b/c/src/exec/score/cpu/m68k/cpu_asm.S deleted file mode 100644 index 0d14c16401..0000000000 --- a/c/src/exec/score/cpu/m68k/cpu_asm.S +++ /dev/null @@ -1,263 +0,0 @@ -/* cpu_asm.s - * - * This file contains all assembly code for the MC68020 implementation - * of RTEMS. - * - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -#include <asm.h> - - .text - -/* void _CPU_Context_switch( run_context, heir_context ) - * - * This routine performs a normal non-FP context. - */ - - .align 4 - .global SYM (_CPU_Context_switch) - -.set RUNCONTEXT_ARG, 4 | save context argument -.set HEIRCONTEXT_ARG, 8 | restore context argument - -SYM (_CPU_Context_switch): - moval a7@(RUNCONTEXT_ARG),a0| a0 = running thread context - movw sr,d1 | d1 = status register - movml d1-d7/a2-a7,a0@ | save context - - moval a7@(HEIRCONTEXT_ARG),a0| a0 = heir thread context -restore: movml a0@,d1-d7/a2-a7 | restore context - movw d1,sr | restore status register - rts - -/*PAGE - * void __CPU_Context_save_fp_context( &fp_context_ptr ) - * void __CPU_Context_restore_fp_context( &fp_context_ptr ) - * - * These routines are used to context switch a MC68881 or MC68882. - * - * NOTE: Context save and restore code is based upon the code shown - * on page 6-38 of the MC68881/68882 Users Manual (rev 1). - * - * CPU_FP_CONTEXT_SIZE is higher than expected to account for the - * -1 pushed at end of this sequence. - * - * Neither of these entries is required if we have software FPU - * emulation. But if we don't have an FPU or emulation, then - * we need the stub versions of these routines. - */ - -#if (CPU_SOFTWARE_FP == FALSE) - -.set FPCONTEXT_ARG, 4 | save FP context argument - - .align 4 - .global SYM (_CPU_Context_save_fp) -SYM (_CPU_Context_save_fp): -#if ( M68K_HAS_FPU == 1 ) - moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area - moval a1@,a0 | a0 = Save context area - fsave a0@- | save 68881/68882 state frame - tstb a0@ | check for a null frame - beq.b nosv | Yes, skip save of user model - fmovem fp0-fp7,a0@- | save data registers (fp0-fp7) - fmovem fpc/fps/fpi,a0@- | and save control registers - movl #-1,a0@- | place not-null flag on stack -nosv: movl a0,a1@ | save pointer to saved context -#endif - rts - - .align 4 - .global SYM (_CPU_Context_restore_fp) -SYM (_CPU_Context_restore_fp): -#if ( M68K_HAS_FPU == 1 ) - moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area - moval a1@,a0 | a0 = address of saved context - tstb a0@ | Null context frame? - beq.b norst | Yes, skip fp restore - addql #4,a0 | throwaway non-null flag - fmovem a0@+,fpc/fps/fpi | restore control registers - fmovem a0@+,fp0-fp7 | restore data regs (fp0-fp7) -norst: frestore a0@+ | restore the fp state frame - movl a0,a1@ | save pointer to saved context -#endif - rts -#endif - -/*PAGE - * void _ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * NOTE: - * Upon entry, the master stack will contain an interrupt stack frame - * back to the interrupted thread and the interrupt stack will contain - * a throwaway interrupt stack frame. If dispatching is enabled, and this - * is the outer most interrupt, and a context switch is necessary or - * the current thread has pending signals, then set up the master stack to - * transfer control to the interrupt dispatcher. - */ - -#if ( M68K_COLDFIRE_ARCH == 1 ) -.set SR_OFFSET, 2 | Status register offset -.set PC_OFFSET, 4 | Program Counter offset -.set FVO_OFFSET, 0 | Format/vector offset -#elif ( M68K_HAS_VBR == 1) -.set SR_OFFSET, 0 | Status register offset -.set PC_OFFSET, 2 | Program Counter offset -.set FVO_OFFSET, 6 | Format/vector offset -#else -.set SR_OFFSET, 2 | Status register offset -.set PC_OFFSET, 4 | Program Counter offset -.set FVO_OFFSET, 0 | Format/vector offset placed in the stack -#endif /* M68K_HAS_VBR */ - -.set SAVED, 16 | space for saved registers - - .align 4 - .global SYM (_ISR_Handler) - -SYM (_ISR_Handler): - addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking -#if ( M68K_COLDFIRE_ARCH == 0 ) - moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 -#else - lea a7@(-SAVED),a7 - movm.l d0-d1/a0-a1,a7@ | save d0-d1,a0-a1 -#endif - movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO - andl #0x0ffc,d0 | d0 = vector offset in vbr - - -#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) - movel _CPU_Interrupt_stack_high,a0 | a0 now point just above interrupt stack - cmpl _CPU_Interrupt_stack_low,a7 | stack below interrupt stack? - bcs.b 1f | yes, switch to interrupt stack - cmpl a0,a7 | stack above interrupt stack? - bcs.b 2f | no, do not switch stacks -1: - movel a7,a1 | copy task stack pointer - movel a0,a7 | switch to interrupt stack - movel a1,a7@- | store task stack pointer on interrupt stack -2: -#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ - - movel SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table -#if ( M68K_HAS_PREINDEXING == 1 ) - movel (a0,d0:w:1),a0 | a0 = address of user routine -#else - addal d0,a0 | a0 = address of vector - movel (a0),a0 | a0 = address of user routine -#endif - - lsrl #2,d0 | d0 = vector number - movel d0,a7@- | push vector number - jbsr a0@ | invoke the user ISR - addql #4,a7 | remove vector number - -#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) - movel _CPU_Interrupt_stack_high,a0 - subql #4,a0 - cmpl a0,a7 | At top of interrupt stack? - bne.b 1f | No, do not restore task stack pointer - movel (a7),a7 | Restore task stack pointer -1: -#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ - - subql #1,SYM (_Thread_Dispatch_disable_level) - | unnest multitasking - bne.b exit | If dispatch disabled, exit - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - movew #0xf000,d0 | isolate format nibble - andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO - cmpiw #0x1000,d0 | is it a throwaway isf? - bne.b exit | NOT outer level, so branch -#else -/* - * If we have a CPU which allows a higher-priority interrupt to preempt a - * lower priority handler before the lower-priority handler can increment - * _Thread_Dispatch_disable_level then we must check the PC on the stack to - * see if it is _ISR_Handler. If it is we have the case of nesting interrupts - * without the dispatch level being incremented. - */ - #if ( M68K_COLDFIRE_ARCH == 0 && M68K_MC68060_ARCH == 0 ) - cmpl #_ISR_Handler,a7@(SAVED+PC_OFFSET) - beq.b exit - #endif -#endif - tstl SYM (_Context_Switch_necessary) - | Is thread switch necessary? - bne.b bframe | Yes, invoke dispatcher - - tstl SYM (_ISR_Signals_to_thread_executing) - | signals sent to Run_thread - | while in interrupt handler? - beq.b exit | No, then exit - -bframe: clrl SYM (_ISR_Signals_to_thread_executing) - | If sent, will be processed -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - movec msp,a0 | a0 = master stack pointer - movew #0,a0@- | push format word - movel #SYM(_ISR_Dispatch),a0@- | push return addr - movew a0@(6),a0@- | push saved sr - movec a0,msp | set master stack pointer -#else - jsr SYM (_Thread_Dispatch) | Perform context switch -#endif - -#if ( M68K_COLDFIRE_ARCH == 0 ) -exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1 -#else -exit: moveml a7@,d0-d1/a0-a1 | restore d0-d1,a0-a1 - lea a7@(SAVED),a7 -#endif - -#if ( M68K_HAS_VBR == 0 ) - addql #2,a7 | pop format/id -#endif /* M68K_HAS_VBR */ - rte | return to thread - | OR _Isr_dispatch - -/*PAGE - * void _ISR_Dispatch() - * - * Entry point from the outermost interrupt service routine exit. - * The current stack is the supervisor mode stack if this processor - * has separate stacks. - * - * 1. save all registers not preserved across C calls. - * 2. invoke the _Thread_Dispatch routine to switch tasks - * or a signal to the currently executing task. - * 3. restore all registers not preserved across C calls. - * 4. return from interrupt - */ - - .global SYM (_ISR_Dispatch) -SYM (_ISR_Dispatch): -#if ( M68K_COLDFIRE_ARCH == 0 ) - movml d0-d1/a0-a1,a7@- - jsr SYM (_Thread_Dispatch) - movml a7@+,d0-d1/a0-a1 -#else - lea a7@(-SAVED),a7 - movml d0-d1/a0-a1,a7@ - jsr SYM (_Thread_Dispatch) - movml a7@,d0-d1/a0-a1 - lea a7@(SAVED),a7 -#endif - -#if ( M68K_HAS_VBR == 0 ) - addql #2,a7 | pop format/id -#endif /* M68K_HAS_VBR */ - rte diff --git a/c/src/exec/score/cpu/m68k/m68302.h b/c/src/exec/score/cpu/m68k/m68302.h deleted file mode 100644 index c4bd0a5586..0000000000 --- a/c/src/exec/score/cpu/m68k/m68302.h +++ /dev/null @@ -1,661 +0,0 @@ -/* - *------------------------------------------------------------------ - * - * m68302.h - Definitions for Motorola MC68302 processor. - * - * Section references in this file refer to revision 2 of Motorola's - * "MC68302 Integrated Multiprotocol Processor User's Manual". - * (Motorola document MC68302UM/AD REV 2.) - * - * Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k - * on 17 February, 1993. - * - * Copyright 1995 David W. Glessner. - * - * Redistribution and use in source and binary forms are permitted - * provided that the following conditions are met: - * 1. Redistribution of source code and documentation must retain - * the above copyright notice, this list of conditions and the - * following disclaimer. - * 2. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * This software is provided "AS IS" without warranty of any kind, - * either expressed or implied, including, but not limited to, the - * implied warranties of merchantability, title and fitness for a - * particular purpose. - * - * - * $Id$ - * - *------------------------------------------------------------------ - */ - -#ifndef __MOTOROLA_MC68302_DEFINITIONS_h -#define __MOTOROLA_MC68302_DEFINITIONS_h - -/* - * BAR - Base Address Register - * Section 2.7 - */ -#define M302_BAR (*((volatile rtems_unsigned16 *) 0xf2)) - -/* - * SCR - System Control Register - * Section 3.8.1 - */ -#define M302_SCR (*((volatile rtems_unsigned32 *) 0xf4)) -/* - * SCR bits - */ -#define RBIT_SCR_IPA 0x08000000 -#define RBIT_SCR_HWT 0x04000000 -#define RBIT_SCR_WPV 0x02000000 -#define RBIT_SCR_ADC 0x01000000 - -#define RBIT_SCR_ERRE 0x00400000 -#define RBIT_SCR_VGE 0x00200000 -#define RBIT_SCR_WPVE 0x00100000 -#define RBIT_SCR_RMCST 0x00080000 -#define RBIT_SCR_EMWS 0x00040000 -#define RBIT_SCR_ADCE 0x00020000 -#define RBIT_SCR_BCLM 0x00010000 - -#define RBIT_SCR_FRZW 0x00008000 -#define RBIT_SCR_FRZ2 0x00004000 -#define RBIT_SCR_FRZ1 0x00002000 -#define RBIT_SCR_SAM 0x00001000 -#define RBIT_SCR_HWDEN 0x00000800 -#define RBIT_SCR_HWDCN2 0x00000400 -#define RBIT_SCR_HWDCN1 0x00000200 /* 512 clocks */ -#define RBIT_SCR_HWDCN0 0x00000100 /* 128 clocks */ - -#define RBIT_SCR_LPREC 0x00000080 -#define RBIT_SCR_LPP16 0x00000040 -#define RBIT_SCR_LPEN 0x00000020 -#define RBIT_SCR_LPCLKDIV 0x0000001f - - -/* - * 68000 interrupt and trap vector numbers - */ -#define M68K_IVEC_BUS_ERROR 2 -#define M68K_IVEC_ADDRESS_ERROR 3 -#define M68K_IVEC_ILLEGAL_OPCODE 4 -#define M68K_IVEC_ZERO_DIVIDE 5 -#define M68K_IVEC_CHK 6 -#define M68K_IVEC_TRAPV 7 -#define M68K_IVEC_PRIVILEGE 8 -#define M68K_IVEC_TRACE 9 -#define M68K_IVEC_LINE_A 10 -#define M68K_IVEC_LINE_F 11 -/* Unassigned, Reserved 12-14 */ -#define M68K_IVEC_UNINITIALIZED_INT 15 -/* Unassigned, Reserved 16-23 */ -#define M68K_IVEC_SPURIOUS_INT 24 - -#define M68K_IVEC_LEVEL1_AUTOVECTOR 25 -#define M68K_IVEC_LEVEL2_AUTOVECTOR 26 -#define M68K_IVEC_LEVEL3_AUTOVECTOR 27 -#define M68K_IVEC_LEVEL4_AUTOVECTOR 28 -#define M68K_IVEC_LEVEL5_AUTOVECTOR 29 -#define M68K_IVEC_LEVEL6_AUTOVECTOR 30 -#define M68K_IVEC_LEVEL7_AUTOVECTOR 31 - -#define M68K_IVEC_TRAP0 32 -#define M68K_IVEC_TRAP1 33 -#define M68K_IVEC_TRAP2 34 -#define M68K_IVEC_TRAP3 35 -#define M68K_IVEC_TRAP4 36 -#define M68K_IVEC_TRAP5 37 -#define M68K_IVEC_TRAP6 38 -#define M68K_IVEC_TRAP7 39 -#define M68K_IVEC_TRAP8 40 -#define M68K_IVEC_TRAP9 41 -#define M68K_IVEC_TRAP10 42 -#define M68K_IVEC_TRAP11 43 -#define M68K_IVEC_TRAP12 44 -#define M68K_IVEC_TRAP13 45 -#define M68K_IVEC_TRAP14 46 -#define M68K_IVEC_TRAP15 47 -/* - * Unassigned, Reserved 48-59 - * - * Note: Vectors 60-63 are used by the MC68302 (e.g. BAR, SCR). - */ - -/* - * MC68302 Interrupt Vectors - * Section 3.2 - */ -enum m68302_ivec_e { - M302_IVEC_ERR =0, - M302_IVEC_PB8 =1, /* General-Purpose Interrupt 0 */ - M302_IVEC_SMC2 =2, - M302_IVEC_SMC1 =3, - M302_IVEC_TIMER3 =4, - M302_IVEC_SCP =5, - M302_IVEC_TIMER2 =6, - M302_IVEC_PB9 =7, /* General-Purpose Interrupt 1 */ - M302_IVEC_SCC3 =8, - M302_IVEC_TIMER1 =9, - M302_IVEC_SCC2 =10, - M302_IVEC_IDMA =11, - M302_IVEC_SDMA =12, /* SDMA Channels Bus Error */ - M302_IVEC_SCC1 =13, - M302_IVEC_PB10 =14, /* General-Purpose Interrupt 2 */ - M302_IVEC_PB11 =15, /* General-Purpose Interrupt 3 */ - M302_IVEC_IRQ1 =17, /* External Device */ - M302_IVEC_IRQ6 =22, /* External Device */ - M302_IVEC_IRQ7 =23 /* External Device */ -}; - - -/* - * GIMR - Global Interrupt Mode Register - * Section 3.2.5.1 - */ -#define RBIT_GIMR_MOD (1<<15) -#define RBIT_GIMR_IV7 (1<<14) -#define RBIT_GIMR_IV6 (1<<13) -#define RBIT_GIMR_IV1 (1<<12) -#define RBIT_GIMR_ET7 (1<<10) -#define RBIT_GIMR_ET6 (1<<9) -#define RBIT_GIMR_ET1 (1<<8) -#define RBIT_GIMR_VECTOR (7<<5) - -/* - * IPR - Interrupt Pending Register (Section 3.2.5.2) - * IMR - Interrupt Mask Register (Section 3.2.5.3) - * ISR - Interrupt In-Service Register (Section 3.2.5.4) - */ -#define RBIT_IPR_PB11 (1<<15) -#define RBIT_IPR_PB10 (1<<14) -#define RBIT_IPR_SCC1 (1<<13) -#define RBIT_IPR_SDMA (1<<12) -#define RBIT_IPR_IDMA (1<<11) -#define RBIT_IPR_SCC2 (1<<10) -#define RBIT_IPR_TIMER1 (1<<9) -#define RBIT_IPR_SCC3 (1<<8) -#define RBIT_IPR_PB9 (1<<7) -#define RBIT_IPR_TIMER2 (1<<6) -#define RBIT_IPR_SCP (1<<5) -#define RBIT_IPR_TIMER3 (1<<4) -#define RBIT_IPR_SMC1 (1<<3) -#define RBIT_IPR_SMC2 (1<<2) -#define RBIT_IPR_PB8 (1<<1) -#define RBIT_IPR_ERR (1<<0) - -#define RBIT_ISR_PB11 (1<<15) -#define RBIT_ISR_PB10 (1<<14) -#define RBIT_ISR_SCC1 (1<<13) -#define RBIT_ISR_SDMA (1<<12) -#define RBIT_ISR_IDMA (1<<11) -#define RBIT_ISR_SCC2 (1<<10) -#define RBIT_ISR_TIMER1 (1<<9) -#define RBIT_ISR_SCC3 (1<<8) -#define RBIT_ISR_PB9 (1<<7) -#define RBIT_ISR_TIMER2 (1<<6) -#define RBIT_ISR_SCP (1<<5) -#define RBIT_ISR_TIMER3 (1<<4) -#define RBIT_ISR_SMC1 (1<<3) -#define RBIT_ISR_SMC2 (1<<2) -#define RBIT_ISR_PB8 (1<<1) - -#define RBIT_IMR_PB11 (1<<15) /* PB11 Interrupt Mask */ -#define RBIT_IMR_PB10 (1<<14) /* PB10 Interrupt Mask */ -#define RBIT_IMR_SCC1 (1<<13) /* SCC1 Interrupt Mask */ -#define RBIT_IMR_SDMA (1<<12) /* SDMA Interrupt Mask */ -#define RBIT_IMR_IDMA (1<<11) /* IDMA Interrupt Mask */ -#define RBIT_IMR_SCC2 (1<<10) /* SCC2 Interrupt Mask */ -#define RBIT_IMR_TIMER1 (1<<9) /* TIMER1 Interrupt Mask */ -#define RBIT_IMR_SCC3 (1<<8) /* SCC3 Interrupt Mask */ -#define RBIT_IMR_PB9 (1<<7) /* PB9 Interrupt Mask */ -#define RBIT_IMR_TIMER2 (1<<6) /* TIMER2 Interrupt Mask */ -#define RBIT_IMR_SCP (1<<5) /* SCP Interrupt Mask */ -#define RBIT_IMR_TIMER3 (1<<4) /* TIMER3 Interrupt Mask */ -#define RBIT_IMR_SMC1 (1<<3) /* SMC1 Interrupt Mask */ -#define RBIT_IMR_SMC2 (1<<2) /* SMC2 Interrupt Mask */ -#define RBIT_IMR_PB8 (1<<1) /* PB8 Interrupt Mask */ - - -/* - * DRAM Refresh - * Section 3.9 - * - * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7 - * structures in the parameter RAM. - * - * Access to the DRAM registers can be accomplished by - * the following approach: - * - * volatile m302_DRAM_refresh_t *dram; - * dram = (volatile m302_DRAM_refresh_t *) &m302.scc2.bd.tx[6]; - * - * Then simply use pointer references (e.g. dram->count = 3). - */ -typedef struct { - rtems_unsigned16 dram_high; /* DRAM high address and FC */ - rtems_unsigned16 dram_low; /* DRAM low address */ - rtems_unsigned16 increment; /* increment step (bytes/row) */ - rtems_unsigned16 count; /* RAM refresh cycle count (#rows) */ - rtems_unsigned16 t_ptr_h; /* temporary refresh high addr & FC */ - rtems_unsigned16 t_ptr_l; /* temporary refresh low address */ - rtems_unsigned16 t_count; /* temporary refresh cycles count */ - rtems_unsigned16 res; /* reserved */ -} m302_DRAM_refresh_t; - - -/* - * TMR - Timer Mode Register (for timers 1 and 2) - * Section 3.5.2.1 - */ -#define RBIT_TMR_ICLK_STOP (0<<1) -#define RBIT_TMR_ICLK_MASTER (1<<1) -#define RBIT_TMR_ICLK_MASTER16 (2<<1) -#define RBIT_TMR_ICLK_TIN (3<<1) - -#define RBIT_TMR_OM (1<<5) -#define RBIT_TMR_ORI (1<<4) -#define RBIT_TMR_FRR (1<<3) -#define RBIT_TMR_RST (1<<0) - - -/* - * TER - Timer Event Register (for timers 1 and 2) - * Section 3.5.2.5 - */ -#define RBIT_TER_REF (1<<1) /* Output Reference Event */ -#define RBIT_TER_CAP (1<<0) /* Capture Event */ - - -/* - * SCC Buffer Descriptors and Buffer Descriptors Table - * Section 4.5.5 - */ -typedef struct m302_SCC_bd { - rtems_unsigned16 status; /* status and control */ - rtems_unsigned16 length; /* data length */ - volatile rtems_unsigned8 *buffer; /* data buffer pointer */ -} m302_SCC_bd_t; - -typedef struct { - m302_SCC_bd_t rx[8]; /* receive buffer descriptors */ - m302_SCC_bd_t tx[8]; /* transmit buffer descriptors */ -} m302_SCC_bd_table_t; - - -/* - * SCC Parameter RAM (offset 0x080 from an SCC Base) - * Section 4.5.6 - * - * Each SCC parameter RAM area begins at offset 0x80 from each SCC base - * area (0x400, 0x500, or 0x600 from the dual-port RAM base). - * - * Offsets 0x9c-0xbf from each SCC base area compose the protocol-specific - * portion of the SCC parameter RAM. - */ -typedef struct { - rtems_unsigned8 rfcr; /* Rx Function Code */ - rtems_unsigned8 tfcr; /* Tx Function Code */ - rtems_unsigned16 mrblr; /* Maximum Rx Buffer Length */ - rtems_unsigned16 _rstate; /* Rx Internal State */ - rtems_unsigned8 res2; - rtems_unsigned8 rbd; /* Rx Internal Buffer Number */ - rtems_unsigned32 _rdptr; /* Rx Internal Data Pointer */ - rtems_unsigned16 _rcount; /* Rx Internal Byte Count */ - rtems_unsigned16 _rtmp; /* Rx Temp */ - rtems_unsigned16 _tstate; /* Tx Internal State */ - rtems_unsigned8 res7; - rtems_unsigned8 tbd; /* Tx Internal Buffer Number */ - rtems_unsigned32 _tdptr; /* Tx Internal Data Pointer */ - rtems_unsigned16 _tcount; /* Tx Internal Byte Count */ - rtems_unsigned16 _ttmp; /* Tx Temp */ -} m302_SCC_parameters_t; - -/* - * UART-Specific SCC Parameter RAM - * Section 4.5.11.3 - */ -typedef struct { - rtems_unsigned16 max_idl; /* Maximum IDLE Characters (rx) */ - rtems_unsigned16 idlc; /* Temporary rx IDLE counter */ - rtems_unsigned16 brkcr; /* Break Count Register (tx) */ - rtems_unsigned16 parec; /* Receive Parity Error Counter */ - rtems_unsigned16 frmec; /* Receive Framing Error Counter */ - rtems_unsigned16 nosec; /* Receive Noise Counter */ - rtems_unsigned16 brkec; /* Receive Break Condition Counter */ - rtems_unsigned16 uaddr1; /* UART ADDRESS Character 1 */ - rtems_unsigned16 uaddr2; /* UART ADDRESS Character 2 */ - rtems_unsigned16 rccr; /* Receive Control Character Register */ - rtems_unsigned16 character[8]; /* Control Characters 1 through 8*/ -} m302_SCC_UartSpecific_t; -/* - * This definition allows for the checking of receive buffers - * for errors. - */ - -#define RCV_ERR 0x003F - -/* - * UART receive buffer descriptor bit definitions. - * Section 4.5.11.14 - */ -#define RBIT_UART_CTRL (1<<11) /* buffer contains a control char */ -#define RBIT_UART_ADDR (1<<10) /* first byte contains an address */ -#define RBIT_UART_MATCH (1<<9) /* indicates which addr char matched */ -#define RBIT_UART_IDLE (1<<8) /* buffer closed due to IDLE sequence */ -#define RBIT_UART_BR (1<<5) /* break sequence was received */ -#define RBIT_UART_FR (1<<4) /* framing error was received */ -#define RBIT_UART_PR (1<<3) /* parity error was received */ -#define RBIT_UART_OV (1<<1) /* receiver overrun occurred */ -#define RBIT_UART_CD (1<<0) /* carrier detect lost */ -#define RBIT_UART_STATUS 0x003B /* all status bits */ - -/* - * UART transmit buffer descriptor bit definitions. - * Section 4.5.11.15 - */ -#define RBIT_UART_CR (1<<11) /* clear-to-send report - * this results in two idle bits - * between back-to-back frames - */ -#define RBIT_UART_A (1<<10) /* buffer contains address characters - * only valid in multidrop mode (UM0=1) - */ -#define RBIT_UART_PREAMBLE (1<<9) /* send preamble before data */ -#define RBIT_UART_CTS_LOST (1<<0) /* CTS lost */ - -/* - * UART event register - * Section 4.5.11.16 - */ -#define M302_UART_EV_CTS (1<<7) /* CTS status changed */ -#define M302_UART_EV_CD (1<<6) /* carrier detect status changed */ -#define M302_UART_EV_IDL (1<<5) /* IDLE sequence status changed */ -#define M302_UART_EV_BRK (1<<4) /* break character was received */ -#define M302_UART_EV_CCR (1<<3) /* control character received */ -#define M302_UART_EV_TX (1<<1) /* buffer has been transmitted */ -#define M302_UART_EV_RX (1<<0) /* buffer has been received */ - - -/* - * HDLC-Specific SCC Parameter RAM - * Section 4.5.12.3 - * - * c_mask_l should be 0xF0B8 for 16-bit CRC, 0xdebb for 32-bit CRC - * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC - */ -typedef struct { - rtems_unsigned16 rcrc_l; /* Temp Receive CRC Low */ - rtems_unsigned16 rcrc_h; /* Temp Receive CRC High */ - rtems_unsigned16 c_mask_l; /* CRC Mask Low */ - rtems_unsigned16 c_mask_h; /* CRC Mask High */ - rtems_unsigned16 tcrc_l; /* Temp Transmit CRC Low */ - rtems_unsigned16 tcrc_h; /* Temp Transmit CRC High */ - - rtems_unsigned16 disfc; /* Discard Frame Counter */ - rtems_unsigned16 crcec; /* CRC Error Counter */ - rtems_unsigned16 abtsc; /* Abort Sequence Counter */ - rtems_unsigned16 nmarc; /* Nonmatching Address Received Cntr */ - rtems_unsigned16 retrc; /* Frame Retransmission Counter */ - - rtems_unsigned16 mflr; /* Maximum Frame Length Register */ - rtems_unsigned16 max_cnt; /* Maximum_Length Counter */ - - rtems_unsigned16 hmask; /* User Defined Frame Address Mask */ - rtems_unsigned16 haddr1; /* User Defined Frame Address */ - rtems_unsigned16 haddr2; /* " */ - rtems_unsigned16 haddr3; /* " */ - rtems_unsigned16 haddr4; /* " */ -} m302_SCC_HdlcSpecific_t; -/* - * HDLC receiver buffer descriptor bit definitions - * Section 4.5.12.10 - */ -#define RBIT_HDLC_EMPTY_BIT 0x8000 /* buffer associated with BD is empty */ -#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in a frame */ -#define RBIT_HDLC_FIRST_BIT 0x0400 /* buffer is first in a frame */ -#define RBIT_HDLC_FRAME_LEN 0x0020 /* receiver frame length violation */ -#define RBIT_HDLC_NONOCT_Rx 0x0010 /* received non-octet aligned frame */ -#define RBIT_HDLC_ABORT_SEQ 0x0008 /* received abort sequence */ -#define RBIT_HDLC_CRC_ERROR 0x0004 /* frame contains a CRC error */ -#define RBIT_HDLC_OVERRUN 0x0002 /* receiver overrun occurred */ -#define RBIT_HDLC_CD_LOST 0x0001 /* carrier detect lost */ - -/* - * HDLC transmit buffer descriptor bit definitions - * Section 4.5.12.11 - */ -#define RBIT_HDLC_READY_BIT 0x8000 /* buffer is ready to transmit */ -#define RBIT_HDLC_EXT_BUFFER 0x4000 /* buffer is in external memory */ -#define RBIT_HDLC_WRAP_BIT 0x2000 /* last buffer in bd table, so wrap */ -#define RBIT_HDLC_WAKE_UP 0x1000 /* interrupt when buffer serviced */ -#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in the frame */ -#define RBIT_HDLC_TxCRC_BIT 0x0400 /* transmit a CRC sequence */ -#define RBIT_HDLC_UNDERRUN 0x0002 /* transmitter underrun */ -#define RBIT_HDLC_CTS_LOST 0x0001 /* CTS lost */ - -/* - * HDLC event register bit definitions - * Section 4.5.12.12 - */ -#define RBIT_HDLC_CTS 0x80 /* CTS status changed */ -#define RBIT_HDLC_CD 0x40 /* carrier detect status changed */ -#define RBIT_HDLC_IDL 0x20 /* IDLE sequence status changed */ -#define RBIT_HDLC_TXE 0x10 /* transmit error */ -#define RBIT_HDLC_RXF 0x08 /* received frame */ -#define RBIT_HDLC_BSY 0x04 /* frame rcvd and discarded due to - * lack of buffers - */ -#define RBIT_HDLC_TXB 0x02 /* buffer has been transmitted */ -#define RBIT_HDLC_RXB 0x01 /* received buffer */ - - - -typedef struct { - m302_SCC_bd_table_t bd; /* +000 Buffer Descriptor Table */ - m302_SCC_parameters_t parm; /* +080 Common Parameter RAM */ - union { /* +09C Protocol-Specific Parm RAM */ - m302_SCC_UartSpecific_t uart; - m302_SCC_HdlcSpecific_t hdlc; - } prot; - rtems_unsigned8 res[0x040]; /* +0C0 reserved, (not implemented) */ -} m302_SCC_t; - - -/* - * Common SCC Registers - */ -typedef struct { - rtems_unsigned16 res1; - rtems_unsigned16 scon; /* SCC Configuration Register 4.5.2 */ - rtems_unsigned16 scm; /* SCC Mode Register 4.5.3 */ - rtems_unsigned16 dsr; /* SCC Data Synchronization Register 4.5.4 */ - rtems_unsigned8 scce; /* SCC Event Register 4.5.8.1 */ - rtems_unsigned8 res2; - rtems_unsigned8 sccm; /* SCC Mask Register 4.5.8.2 */ - rtems_unsigned8 res3; - rtems_unsigned8 sccs; /* SCC Status Register 4.5.8.3 */ - rtems_unsigned8 res4; - rtems_unsigned16 res5; -} m302_SCC_Registers_t; - -/* - * SCON - SCC Configuration Register - * Section 4.5.2 - */ -#define RBIT_SCON_WOMS (1<<15) /* Wired-OR Mode Select (NMSI mode only) - * When set, the TXD driver is an - * open-drain output */ -#define RBIT_SCON_EXTC (1<<14) /* External Clock Source */ -#define RBIT_SCON_TCS (1<<13) /* Transmit Clock Source */ -#define RBIT_SCON_RCS (1<<12) /* Receive Clock Source */ - -/* - * SCM - SCC Mode Register bit definitions - * Section 4.5.3 - * The parameter-specific mode bits occupy bits 15 through 6. - */ -#define RBIT_SCM_ENR (1<<3) /* Enable receiver */ -#define RBIT_SCM_ENT (1<<2) /* Enable transmitter */ - - -/* - * Internal MC68302 Registers - * starts at offset 0x800 from dual-port RAM base - * Section 2.8 - */ -typedef struct { - /* offset +800 */ - rtems_unsigned16 res0; - rtems_unsigned16 cmr; /* IDMA Channel Mode Register */ - rtems_unsigned32 sapr; /* IDMA Source Address Pointer */ - rtems_unsigned32 dapr; /* IDMA Destination Address Pointer */ - rtems_unsigned16 bcr; /* IDMA Byte Count Register */ - rtems_unsigned8 csr; /* IDMA Channel Status Register */ - rtems_unsigned8 res1; - rtems_unsigned8 fcr; /* IDMA Function Code Register */ - rtems_unsigned8 res2; - - /* offset +812 */ - rtems_unsigned16 gimr; /* Global Interrupt Mode Register */ - rtems_unsigned16 ipr; /* Interrupt Pending Register */ - rtems_unsigned16 imr; /* Interrupt Mask Register */ - rtems_unsigned16 isr; /* Interrupt In-Service Register */ - rtems_unsigned16 res3; - rtems_unsigned16 res4; - - /* offset +81e */ - rtems_unsigned16 pacnt; /* Port A Control Register */ - rtems_unsigned16 paddr; /* Port A Data Direction Register */ - rtems_unsigned16 padat; /* Port A Data Register */ - rtems_unsigned16 pbcnt; /* Port B Control Register */ - rtems_unsigned16 pbddr; /* Port B Data Direction Register */ - rtems_unsigned16 pbdat; /* Port B Data Register */ - rtems_unsigned16 res5; - - /* offset +82c */ - rtems_unsigned16 res6; - rtems_unsigned16 res7; - - rtems_unsigned16 br0; /* Base Register (CS0) */ - rtems_unsigned16 or0; /* Option Register (CS0) */ - rtems_unsigned16 br1; /* Base Register (CS1) */ - rtems_unsigned16 or1; /* Option Register (CS1) */ - rtems_unsigned16 br2; /* Base Register (CS2) */ - rtems_unsigned16 or2; /* Option Register (CS2) */ - rtems_unsigned16 br3; /* Base Register (CS3) */ - rtems_unsigned16 or3; /* Option Register (CS3) */ - - /* offset +840 */ - rtems_unsigned16 tmr1; /* Timer Unit 1 Mode Register */ - rtems_unsigned16 trr1; /* Timer Unit 1 Reference Register */ - rtems_unsigned16 tcr1; /* Timer Unit 1 Capture Register */ - rtems_unsigned16 tcn1; /* Timer Unit 1 Counter */ - rtems_unsigned8 res8; - rtems_unsigned8 ter1; /* Timer Unit 1 Event Register */ - rtems_unsigned16 wrr; /* Watchdog Reference Register */ - rtems_unsigned16 wcn; /* Watchdog Counter */ - rtems_unsigned16 res9; - rtems_unsigned16 tmr2; /* Timer Unit 2 Mode Register */ - rtems_unsigned16 trr2; /* Timer Unit 2 Reference Register */ - rtems_unsigned16 tcr2; /* Timer Unit 2 Capture Register */ - rtems_unsigned16 tcn2; /* Timer Unit 2 Counter */ - rtems_unsigned8 resa; - rtems_unsigned8 ter2; /* Timer Unit 2 Event Register */ - rtems_unsigned16 resb; - rtems_unsigned16 resc; - rtems_unsigned16 resd; - - /* offset +860 */ - rtems_unsigned8 cr; /* Command Register */ - rtems_unsigned8 rese[0x1f]; - - /* offset +880, +890, +8a0 */ - m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */ - - /* offset +8b0 */ - rtems_unsigned16 spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ - rtems_unsigned16 simask; /* Serial Interface Mask Register */ - rtems_unsigned16 simode; /* Serial Interface Mode Register */ -} m302_internalReg_t ; - - -/* - * MC68302 dual-port RAM structure. - * (Includes System RAM, Parameter RAM, and Internal Registers). - * Section 2.8 - */ -typedef struct { - rtems_unsigned8 mem[0x240]; /* +000 User Data Memory */ - rtems_unsigned8 res1[0x1c0]; /* +240 reserved, (not implemented) */ - m302_SCC_t scc1; /* +400 SCC1 */ - m302_SCC_t scc2; /* +500 SCC2 */ - m302_SCC_t scc3; /* +600 SCC3 */ - rtems_unsigned8 res2[0x100]; /* +700 reserved, (not implemented) */ - m302_internalReg_t reg; /* +800 68302 Internal Registers */ -} m302_dualPortRAM_t; - -/* some useful defines the some of the registers above */ - - -/* ---- - MC68302 Chip Select Registers - p3-46 2nd Edition - - */ -#define BR_ENABLED 1 -#define BR_DISABLED 0 -#define BR_FC_NULL 0 -#define BR_READ_ONLY 0 -#define BR_READ_WRITE 2 -#define OR_DTACK_0 0x0000 -#define OR_DTACK_1 0x2000 -#define OR_DTACK_2 0x4000 -#define OR_DTACK_3 0x6000 -#define OR_DTACK_4 0x8000 -#define OR_DTACK_5 0xA000 -#define OR_DTACK_6 0xC000 -#define OR_DTACK_EXT 0xE000 -#define OR_SIZE_64K 0x1FE0 -#define OR_SIZE_128K 0x1FC0 -#define OR_SIZE_256K 0x1F80 -#define OR_SIZE_512K 0x1F00 -#define OR_SIZE_1M 0x1E00 -#define OR_SIZE_2M 0x1C00 -#define OR_MASK_RW 0x0000 -#define OR_NO_MASK_RW 0x0002 -#define OR_MASK_FC 0x0000 -#define OR_NO_MASK_FC 0x0001 - -#define MAKE_BR(base_address, enable, rw, fc) \ - ((base_address >> 11) | fc | rw | enable) - -#define MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask) \ - (DtAck | ((~(bsize - 1) & 0x00FFFFFF) >> 11) | FC_Mask | RW_Mask) - -#define __REG_CAT(r, n) r ## n -#define WRITE_BR(csel, base_address, enable, rw, fc) \ - __REG_CAT(m302.reg.br, csel) = MAKE_BR(base_address, enable, rw, fc) -#define WRITE_OR(csel, bsize, DtAck, RW_Mask, FC_Mask) \ - __REG_CAT(m302.reg.or, csel) = MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask) - -/* ---- - MC68302 Watchdog Timer Enable Bit - - */ -#define WATCHDOG_ENABLE (1) -#define WATCHDOG_TRIGGER() (m302.reg.wrr = 0x10 | WATCHDOG_ENABLE, m302.reg.wcn = 0) -#define WATCHDOG_TOGGLE() (m302.reg.wcn = WATCHDOG_TIMEOUT_PERIOD) -#define DISABLE_WATCHDOG() (m302.reg.wrr = 0) - -/* - * Declare the variable that's used to reference the variables in - * the dual-port RAM. - */ -extern volatile m302_dualPortRAM_t m302; - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/m68k/m68360.h b/c/src/exec/score/cpu/m68k/m68360.h deleted file mode 100644 index fd78fa1104..0000000000 --- a/c/src/exec/score/cpu/m68k/m68360.h +++ /dev/null @@ -1,889 +0,0 @@ -/* - ************************************************************************** - ************************************************************************** - ** ** - ** MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC) ** - ** ** - ** HARDWARE DECLARATIONS ** - ** ** - ** ** - ** Submitted By: ** - ** ** - ** W. Eric Norum ** - ** Saskatchewan Accelerator Laboratory ** - ** University of Saskatchewan ** - ** 107 North Road ** - ** Saskatoon, Saskatchewan, CANADA ** - ** S7N 5C6 ** - ** ** - ** eric@skatter.usask.ca ** - ** ** - ** $Id$ ** - ** ** - ************************************************************************** - ************************************************************************** - */ - -#ifndef __MC68360_h -#define __MC68360_h - -/* - ************************************************************************* - * REGISTER SUBBLOCKS * - ************************************************************************* - */ - -/* - * Memory controller registers - */ -typedef struct m360MEMCRegisters_ { - unsigned long br; - unsigned long or; - unsigned long _pad[2]; -} m360MEMCRegisters_t; - -/* - * Serial Communications Controller registers - */ -typedef struct m360SCCRegisters_ { - unsigned long gsmr_l; - unsigned long gsmr_h; - unsigned short psmr; - unsigned short _pad0; - unsigned short todr; - unsigned short dsr; - unsigned short scce; - unsigned short _pad1; - unsigned short sccm; - unsigned char _pad2; - unsigned char sccs; - unsigned long _pad3[2]; -} m360SCCRegisters_t; - -/* - * Serial Management Controller registers - */ -typedef struct m360SMCRegisters_ { - unsigned short _pad0; - unsigned short smcmr; - unsigned short _pad1; - unsigned char smce; - unsigned char _pad2; - unsigned short _pad3; - unsigned char smcm; - unsigned char _pad4; - unsigned long _pad5; -} m360SMCRegisters_t; - - -/* - ************************************************************************* - * Miscellaneous Parameters * - ************************************************************************* - */ -typedef struct m360MiscParms_ { - unsigned short rev_num; - unsigned short _res1; - unsigned long _res2; - unsigned long _res3; -} m360MiscParms_t; - -/* - ************************************************************************* - * RISC Timers * - ************************************************************************* - */ -typedef struct m360TimerParms_ { - unsigned short tm_base; - unsigned short _tm_ptr; - unsigned short _r_tmr; - unsigned short _r_tmv; - unsigned long tm_cmd; - unsigned long tm_cnt; -} m360TimerParms_t; - -/* - * RISC Controller Configuration Register (RCCR) - * All other bits in this register are either reserved or - * used only with a Motorola-supplied RAM microcode packge. - */ -#define M360_RCCR_TIME (1<<15) /* Enable timer */ -#define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ - -/* - * Command register - * Set up this register before issuing a M360_CR_OP_SET_TIMER command. - */ -#define M360_TM_CMD_V (1<<31) /* Set to enable timer */ -#define M360_TM_CMD_R (1<<30) /* Set for automatic restart */ -#define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ -#define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ - -/* - ************************************************************************* - * DMA Controllers * - ************************************************************************* - */ -typedef struct m360IDMAparms_ { - unsigned short ibase; - unsigned short ibptr; - unsigned long _istate; - unsigned long _itemp; -} m360IDMAparms_t; - -/* - ************************************************************************* - * Serial Communication Controllers * - ************************************************************************* - */ -typedef struct m360SCCparms_ { - unsigned short rbase; - unsigned short tbase; - unsigned char rfcr; - unsigned char tfcr; - unsigned short mrblr; - unsigned long _rstate; - unsigned long _pad0; - unsigned short _rbptr; - unsigned short _pad1; - unsigned long _pad2; - unsigned long _tstate; - unsigned long _pad3; - unsigned short _tbptr; - unsigned short _pad4; - unsigned long _pad5; - unsigned long _rcrc; - unsigned long _tcrc; - union { - struct { - unsigned long _res0; - unsigned long _res1; - unsigned short max_idl; - unsigned short _idlc; - unsigned short brkcr; - unsigned short parec; - unsigned short frmec; - unsigned short nosec; - unsigned short brkec; - unsigned short brklen; - unsigned short uaddr[2]; - unsigned short _rtemp; - unsigned short toseq; - unsigned short character[8]; - unsigned short rccm; - unsigned short rccr; - unsigned short rlbc; - } uart; - struct { - unsigned long crc_p; - unsigned long crc_c; - } transparent; - - } un; -} m360SCCparms_t; - -typedef struct m360SCCENparms_ { - unsigned short rbase; - unsigned short tbase; - unsigned char rfcr; - unsigned char tfcr; - unsigned short mrblr; - unsigned long _rstate; - unsigned long _pad0; - unsigned short _rbptr; - unsigned short _pad1; - unsigned long _pad2; - unsigned long _tstate; - unsigned long _pad3; - unsigned short _tbptr; - unsigned short _pad4; - unsigned long _pad5; - unsigned long _rcrc; - unsigned long _tcrc; - union { - struct { - unsigned long _res0; - unsigned long _res1; - unsigned short max_idl; - unsigned short _idlc; - unsigned short brkcr; - unsigned short parec; - unsigned short frmec; - unsigned short nosec; - unsigned short brkec; - unsigned short brklen; - unsigned short uaddr[2]; - unsigned short _rtemp; - unsigned short toseq; - unsigned short character[8]; - unsigned short rccm; - unsigned short rccr; - unsigned short rlbc; - } uart; - struct { - unsigned long c_pres; - unsigned long c_mask; - unsigned long crcec; - unsigned long alec; - unsigned long disfc; - unsigned short pads; - unsigned short ret_lim; - unsigned short _ret_cnt; - unsigned short mflr; - unsigned short minflr; - unsigned short maxd1; - unsigned short maxd2; - unsigned short _maxd; - unsigned short dma_cnt; - unsigned short _max_b; - unsigned short gaddr1; - unsigned short gaddr2; - unsigned short gaddr3; - unsigned short gaddr4; - unsigned long _tbuf0data0; - unsigned long _tbuf0data1; - unsigned long _tbuf0rba0; - unsigned long _tbuf0crc; - unsigned short _tbuf0bcnt; - unsigned short paddr_h; - unsigned short paddr_m; - unsigned short paddr_l; - unsigned short p_per; - unsigned short _rfbd_ptr; - unsigned short _tfbd_ptr; - unsigned short _tlbd_ptr; - unsigned long _tbuf1data0; - unsigned long _tbuf1data1; - unsigned long _tbuf1rba0; - unsigned long _tbuf1crc; - unsigned short _tbuf1bcnt; - unsigned short _tx_len; - unsigned short iaddr1; - unsigned short iaddr2; - unsigned short iaddr3; - unsigned short iaddr4; - unsigned short _boff_cnt; - unsigned short taddr_l; - unsigned short taddr_m; - unsigned short taddr_h; - } ethernet; - struct { - unsigned long crc_p; - unsigned long crc_c; - } transparent; - } un; -} m360SCCENparms_t; - -/* - * Receive and transmit function code register bits - * These apply to the function code registers of all devices, not just SCC. - */ -#define M360_RFCR_MOT (1<<4) -#define M360_RFCR_DMA_SPACE 0x8 -#define M360_TFCR_MOT (1<<4) -#define M360_TFCR_DMA_SPACE 0x8 - -/* - ************************************************************************* - * Serial Management Controllers * - ************************************************************************* - */ -typedef struct m360SMCparms_ { - unsigned short rbase; - unsigned short tbase; - unsigned char rfcr; - unsigned char tfcr; - unsigned short mrblr; - unsigned long _rstate; - unsigned long _pad0; - unsigned short _rbptr; - unsigned short _pad1; - unsigned long _pad2; - unsigned long _tstate; - unsigned long _pad3; - unsigned short _tbptr; - unsigned short _pad4; - unsigned long _pad5; - union { - struct { - unsigned short max_idl; - unsigned short _pad0; - unsigned short brklen; - unsigned short brkec; - unsigned short brkcr; - unsigned short _r_mask; - } uart; - struct { - unsigned short _pad0[5]; - } transparent; - } un; -} m360SMCparms_t; - -/* - * Mode register - */ -#define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */ -#define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */ -#define M360_SMCMR_PARITY (1<<9) /* Enable parity */ -#define M360_SMCMR_EVEN (1<<8) /* Even parity */ -#define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */ -#define M360_SMCMR_SM_UART (2<<4) /* UART Mode */ -#define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ -#define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ -#define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */ -#define M360_SMCMR_TEN (1<<1) /* Enable transmitter */ -#define M360_SMCMR_REN (1<<0) /* Enable receiver */ - -/* - * Event and mask registers (SMCE, SMCM) - */ -#define M360_SMCE_BRK (1<<4) -#define M360_SMCE_BSY (1<<2) -#define M360_SMCE_TX (1<<1) -#define M360_SMCE_RX (1<<0) - -/* - ************************************************************************* - * Serial Peripheral Interface * - ************************************************************************* - */ -typedef struct m360SPIparms_ { - unsigned short rbase; - unsigned short tbase; - unsigned char rfcr; - unsigned char tfcr; - unsigned short mrblr; - unsigned long _rstate; - unsigned long _pad0; - unsigned short _rbptr; - unsigned short _pad1; - unsigned long _pad2; - unsigned long _tstate; - unsigned long _pad3; - unsigned short _tbptr; - unsigned short _pad4; - unsigned long _pad5; -} m360SPIparms_t; - -/* - * Mode register (SPMODE) - */ -#define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */ -#define M360_SPMODE_CI (1<<13) /* Clock invert */ -#define M360_SPMODE_CP (1<<12) /* Clock phase */ -#define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ -#define M360_SPMODE_REV (1<<10) /* Reverse data */ -#define M360_SPMODE_MASTER (1<<9) /* SPI is master */ -#define M360_SPMODE_EN (1<<8) /* Enable SPI */ -#define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */ -#define M360_SPMODE_PM(x) (x) /* Prescaler modulus */ - -/* - * Mode register (SPCOM) - */ -#define M360_SPCOM_STR (1<<7) /* Start transmit */ - -/* - * Event and mask registers (SPIE, SPIM) - */ -#define M360_SPIE_MME (1<<5) /* Multi-master error */ -#define M360_SPIE_TXE (1<<4) /* Tx error */ -#define M360_SPIE_BSY (1<<2) /* Busy condition*/ -#define M360_SPIE_TXB (1<<1) /* Tx buffer */ -#define M360_SPIE_RXB (1<<0) /* Rx buffer */ - -/* - ************************************************************************* - * SDMA (SCC, SMC, SPI) Buffer Descriptors * - ************************************************************************* - */ -typedef struct m360BufferDescriptor_ { - unsigned short status; - unsigned short length; - volatile void *buffer; -} m360BufferDescriptor_t; - -/* - * Bits in receive buffer descriptor status word - */ -#define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M360_BD_LAST (1<<11) /* Ethernet, SPI */ -#define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */ -#define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ -#define M360_BD_ADDRESS (1<<10) /* SCC UART */ -#define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ -#define M360_BD_MISS (1<<8) /* Ethernet */ -#define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */ -#define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ -#define M360_BD_LONG (1<<5) /* Ethernet */ -#define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */ -#define M360_BD_NONALIGNED (1<<4) /* Ethernet */ -#define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ -#define M360_BD_SHORT (1<<3) /* Ethernet */ -#define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ -#define M360_BD_CRC_ERROR (1<<2) /* Ethernet */ -#define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M360_BD_COLLISION (1<<0) /* Ethernet */ -#define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */ -#define M360_BD_MASTER_ERROR (1<<0) /* SPI */ - -/* - * Bits in transmit buffer descriptor status word - * Many bits have the same meaning as those in receiver buffer descriptors. - */ -#define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ -#define M360_BD_PAD (1<<14) /* Ethernet */ -#define M360_BD_CTS_REPORT (1<<11) /* SCC UART */ -#define M360_BD_TX_CRC (1<<10) /* Ethernet */ -#define M360_BD_DEFER (1<<9) /* Ethernet */ -#define M360_BD_HEARTBEAT (1<<8) /* Ethernet */ -#define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ -#define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */ -#define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */ -#define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */ -#define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ -#define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ -#define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */ -#define M360_BD_CTS_LOST (1<<0) /* SCC UART */ - -/* - ************************************************************************* - * IDMA Buffer Descriptors * - ************************************************************************* - */ -typedef struct m360IDMABufferDescriptor_ { - unsigned short status; - unsigned short _pad; - unsigned long length; - void *source; - void *destination; -} m360IDMABufferDescriptor_t; - -/* - ************************************************************************* - * RISC Communication Processor Module Command Register (CR) * - ************************************************************************* - */ -#define M360_CR_RST (1<<15) /* Reset communication processor */ -#define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ -#define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ -#define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ -#define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ -#define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ -#define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */ -#define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */ -#define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ -#define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ -#define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ -#define M360_CR_OP_SET_TIMER (8<<8) /* Timer */ -#define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ -#define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */ -#define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ -#define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */ -#define M360_CR_CHAN_SCC2 (4<<4) -#define M360_CR_CHAN_SPI (5<<4) -#define M360_CR_CHAN_TIMER (5<<4) -#define M360_CR_CHAN_SCC3 (8<<4) -#define M360_CR_CHAN_SMC1 (9<<4) -#define M360_CR_CHAN_IDMA1 (9<<4) -#define M360_CR_CHAN_SCC4 (12<<4) -#define M360_CR_CHAN_SMC2 (13<<4) -#define M360_CR_CHAN_IDMA2 (13<<4) -#define M360_CR_FLG (1<<0) /* Command flag */ - -/* - ************************************************************************* - * System Protection Control Register (SYPCR) * - ************************************************************************* - */ -#define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */ -#define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */ -#define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */ -#define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */ -#define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */ -#define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */ -#define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */ -#define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */ - -/* - ************************************************************************* - * Memory Control Registers * - ************************************************************************* - */ -#define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */ -#define M360_GMR_RFEN (1<<23) /* Refresh enable */ -#define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */ -#define M360_GMR_PGS(x) ((x)<<18) /* Page size */ -#define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */ -#define M360_GMR_DPS_16BIT (1<<16) -#define M360_GMR_DPS_8BIT (2<<16) -#define M360_GMR_DPS_DSACK (3<<16) -#define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */ -#define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */ -#define M360_GMR_SYNC (1<<13) /* Synchronous external access */ -#define M360_GMR_EMWS (1<<12) /* External master wait state */ -#define M360_GMR_OPAR (1<<11) /* Odd parity */ -#define M360_GMR_PBEE (1<<10) /* Parity bus error enable */ -#define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */ -#define M360_GMR_NCS (1<<8) /* No CPU space */ -#define M360_GMR_DWQ (1<<7) /* Delay write for 360 */ -#define M360_GMR_DW40 (1<<6) /* Delay write for 040 */ -#define M360_GMR_GAMX (1<<5) /* Global address mux enable */ - -#define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */ -#define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */ -#define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */ -#define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */ -#define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */ -#define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */ -#define M360_MEMC_BR_WP (1<<1) /* Write Protect */ -#define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */ - -#define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */ -#define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1) -#define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */ -#define M360_MEMC_OR_4KB 0x0FFFF000 -#define M360_MEMC_OR_8KB 0x0FFFE000 -#define M360_MEMC_OR_16KB 0x0FFFC000 -#define M360_MEMC_OR_32KB 0x0FFF8000 -#define M360_MEMC_OR_64KB 0x0FFF0000 -#define M360_MEMC_OR_128KB 0x0FFE0000 -#define M360_MEMC_OR_256KB 0x0FFC0000 -#define M360_MEMC_OR_512KB 0x0FF80000 -#define M360_MEMC_OR_1MB 0x0FF00000 -#define M360_MEMC_OR_2MB 0x0FE00000 -#define M360_MEMC_OR_4MB 0x0FC00000 -#define M360_MEMC_OR_8MB 0x0F800000 -#define M360_MEMC_OR_16MB 0x0F000000 -#define M360_MEMC_OR_32MB 0x0E000000 -#define M360_MEMC_OR_64MB 0x0C000000 -#define M360_MEMC_OR_128MB 0x08000000 -#define M360_MEMC_OR_256MB 0x00000000 -#define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */ -#define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */ -#define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */ -#define M360_MEMC_OR_32BIT (0<<1) /* Port size */ -#define M360_MEMC_OR_16BIT (1<<1) -#define M360_MEMC_OR_8BIT (2<<1) -#define M360_MEMC_OR_DSACK (3<<1) -#define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */ - -/* - ************************************************************************* - * SI Mode Register (SIMODE) * - ************************************************************************* - */ -#define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ -#define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ -#define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ -#define M360_SI_SMC2_BRG2 (1<<28) -#define M360_SI_SMC2_BRG3 (2<<28) -#define M360_SI_SMC2_BRG4 (3<<28) -#define M360_SI_SMC2_CLK5 (0<<28) -#define M360_SI_SMC2_CLK6 (1<<28) -#define M360_SI_SMC2_CLK7 (2<<28) -#define M360_SI_SMC2_CLK8 (3<<28) -#define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ -#define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ -#define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ -#define M360_SI_SMC1_BRG2 (1<<12) -#define M360_SI_SMC1_BRG3 (2<<12) -#define M360_SI_SMC1_BRG4 (3<<12) -#define M360_SI_SMC1_CLK1 (0<<12) -#define M360_SI_SMC1_CLK2 (1<<12) -#define M360_SI_SMC1_CLK3 (2<<12) -#define M360_SI_SMC1_CLK4 (3<<12) - -/* - ************************************************************************* - * SDMA Configuration Register (SDMA) * - ************************************************************************* - */ -#define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */ -#define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */ -#define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */ -#define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */ -#define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */ - -/* - ************************************************************************* - * Baud (sic) Rate Generators * - ************************************************************************* - */ -#define M360_BRG_RST (1<<17) /* Reset generator */ -#define M360_BRG_EN (1<<16) /* Enable generator */ -#define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ -#define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ -#define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ -#define M360_BRG_ATB (1<<13) /* Autobaud */ -#define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */ -#define M360_BRG_57600 (26<<1) -#define M360_BRG_38400 (40<<1) -#define M360_BRG_19200 (80<<1) -#define M360_BRG_9600 (162<<1) -#define M360_BRG_4800 (324<<1) -#define M360_BRG_2400 (650<<1) -#define M360_BRG_1200 (1301<<1) -#define M360_BRG_600 (2603<<1) -#define M360_BRG_300 ((324<<1) | 1) -#define M360_BRG_150 ((650<<1) | 1) -#define M360_BRG_75 ((1301<<1) | 1) - -/* - ************************************************************************* - * MC68360 DUAL-PORT RAM AND REGISTERS * - ************************************************************************* - */ -typedef struct m360_ { - /* - * Dual-port RAM - */ - unsigned char dpram0[0x400]; /* Microcode program */ - unsigned char dpram1[0x200]; - unsigned char dpram2[0x100]; /* Microcode scratch */ - unsigned char dpram3[0x100]; /* Not on REV A or B masks */ - unsigned char _rsv0[0xC00-0x800]; - m360SCCENparms_t scc1p; - unsigned char _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)]; - m360MiscParms_t miscp; - unsigned char _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)]; - m360SCCparms_t scc2p; - unsigned char _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)]; - m360SPIparms_t spip; - unsigned char _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)]; - m360TimerParms_t tmp; - unsigned char _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)]; - m360SCCparms_t scc3p; - unsigned char _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)]; - m360IDMAparms_t idma1p; - unsigned char _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)]; - m360SMCparms_t smc1p; - unsigned char _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)]; - m360SCCparms_t scc4p; - unsigned char _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)]; - m360IDMAparms_t idma2p; - unsigned char _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)]; - m360SMCparms_t smc2p; - unsigned char _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)]; - - /* - * SIM Block - */ - unsigned long mcr; - unsigned long _pad00; - unsigned char avr; - unsigned char rsr; - unsigned short _pad01; - unsigned char clkocr; - unsigned char _pad02; - unsigned short _pad03; - unsigned short pllcr; - unsigned short _pad04; - unsigned short cdvcr; - unsigned short pepar; - unsigned long _pad05[2]; - unsigned short _pad06; - unsigned char sypcr; - unsigned char swiv; - unsigned short _pad07; - unsigned short picr; - unsigned short _pad08; - unsigned short pitr; - unsigned short _pad09; - unsigned char _pad10; - unsigned char swsr; - unsigned long bkar; - unsigned long bcar; - unsigned long _pad11[2]; - - /* - * MEMC Block - */ - unsigned long gmr; - unsigned short mstat; - unsigned short _pad12; - unsigned long _pad13[2]; - m360MEMCRegisters_t memc[8]; - unsigned char _pad14[0xF0-0xD0]; - unsigned char _pad15[0x100-0xF0]; - unsigned char _pad16[0x500-0x100]; - - /* - * IDMA1 Block - */ - unsigned short iccr; - unsigned short _pad17; - unsigned short cmr1; - unsigned short _pad18; - unsigned long sapr1; - unsigned long dapr1; - unsigned long bcr1; - unsigned char fcr1; - unsigned char _pad19; - unsigned char cmar1; - unsigned char _pad20; - unsigned char csr1; - unsigned char _pad21; - unsigned short _pad22; - - /* - * SDMA Block - */ - unsigned char sdsr; - unsigned char _pad23; - unsigned short sdcr; - unsigned long sdar; - - /* - * IDMA2 Block - */ - unsigned short _pad24; - unsigned short cmr2; - unsigned long sapr2; - unsigned long dapr2; - unsigned long bcr2; - unsigned char fcr2; - unsigned char _pad26; - unsigned char cmar2; - unsigned char _pad27; - unsigned char csr2; - unsigned char _pad28; - unsigned short _pad29; - unsigned long _pad30; - - /* - * CPIC Block - */ - unsigned long cicr; - unsigned long cipr; - unsigned long cimr; - unsigned long cisr; - - /* - * Parallel I/O Block - */ - unsigned short padir; - unsigned short papar; - unsigned short paodr; - unsigned short padat; - unsigned long _pad31[2]; - unsigned short pcdir; - unsigned short pcpar; - unsigned short pcso; - unsigned short pcdat; - unsigned short pcint; - unsigned short _pad32; - unsigned long _pad33[5]; - - /* - * TIMER Block - */ - unsigned short tgcr; - unsigned short _pad34; - unsigned long _pad35[3]; - unsigned short tmr1; - unsigned short tmr2; - unsigned short trr1; - unsigned short trr2; - unsigned short tcr1; - unsigned short tcr2; - unsigned short tcn1; - unsigned short tcn2; - unsigned short tmr3; - unsigned short tmr4; - unsigned short trr3; - unsigned short trr4; - unsigned short tcr3; - unsigned short tcr4; - unsigned short tcn3; - unsigned short tcn4; - unsigned short ter1; - unsigned short ter2; - unsigned short ter3; - unsigned short ter4; - unsigned long _pad36[2]; - - /* - * CP Block - */ - unsigned short cr; - unsigned short _pad37; - unsigned short rccr; - unsigned short _pad38; - unsigned long _pad39[3]; - unsigned short _pad40; - unsigned short rter; - unsigned short _pad41; - unsigned short rtmr; - unsigned long _pad42[5]; - - /* - * BRG Block - */ - unsigned long brgc1; - unsigned long brgc2; - unsigned long brgc3; - unsigned long brgc4; - - /* - * SCC Block - */ - m360SCCRegisters_t scc1; - m360SCCRegisters_t scc2; - m360SCCRegisters_t scc3; - m360SCCRegisters_t scc4; - - /* - * SMC Block - */ - m360SMCRegisters_t smc1; - m360SMCRegisters_t smc2; - - /* - * SPI Block - */ - unsigned short spmode; - unsigned short _pad43[2]; - unsigned char spie; - unsigned char _pad44; - unsigned short _pad45; - unsigned char spim; - unsigned char _pad46[2]; - unsigned char spcom; - unsigned short _pad47[2]; - - /* - * PIP Block - */ - unsigned short pipc; - unsigned short _pad48; - unsigned short ptpr; - unsigned long pbdir; - unsigned long pbpar; - unsigned short _pad49; - unsigned short pbodr; - unsigned long pbdat; - unsigned long _pad50[6]; - - /* - * SI Block - */ - unsigned long simode; - unsigned char sigmr; - unsigned char _pad51; - unsigned char sistr; - unsigned char sicmr; - unsigned long _pad52; - unsigned long sicr; - unsigned short _pad53; - unsigned short sirp[2]; - unsigned short _pad54; - unsigned long _pad55[2]; - unsigned char siram[256]; -} m360_t; - -extern volatile m360_t m360; - -#endif /* __MC68360_h */ diff --git a/c/src/exec/score/cpu/m68k/memcpy.c b/c/src/exec/score/cpu/m68k/memcpy.c deleted file mode 100644 index 3948411f4b..0000000000 --- a/c/src/exec/score/cpu/m68k/memcpy.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * C library memcpy routine - * - * This routine has code to optimize performance on the CPU32+ - * and another version for other 68k machines. - * - * It could be optimized more for machines with MOVE16 instructions. - * - * The routine is placed in this source directory to ensure that it - * is picked up by all applications. - * - * W. Eric Norum - * Saskatchewan Accelerator Laboratory - * University of Saskatchewan - * Saskatoon, Saskatchewan, CANADA - * eric@skatter.usask.ca - */ - -#include <string.h> -#include <rtems/score/m68k.h> - -#if defined(__mcpu32__) -#define COPYSETUP(n) n-- -#define COPY(to,from,n,size) \ - asm volatile ("1:\n" \ - "\tmove." size " (%0)+,(%1)+\n" \ - "\tdbf %2,1b\n" \ - "\tsub.l #0x10000,%2\n" \ - "\tbpl.b 1b\n" : \ - "=a" (from), "=a" (to), "=d" (n) :\ - "0" (from), "1" (to), "2" (n) : \ - "cc", "memory") -#else -#define COPYSETUP(n) -#define COPY(to,from,n,size) \ - asm volatile ("1:\n" \ - "\tmove." size " (%0)+,(%1)+\n" \ - "\tsubq.l #1,%2\n\tbne.b 1b\n" : \ - "=a" (from), "=a" (to), "=d" (n) :\ - "0" (from), "1" (to), "2" (n) : \ - "cc", "memory") -#endif - -void * -memcpy(void *s1, const void *s2, size_t n) -{ - char *p1 = s1; - const char *p2 = s2; - - if (n) { - if (n < 16) { - COPYSETUP (n); - COPY (p1, p2, n, "b"); - } - else { - int nbyte; - int nl; - nbyte = (int)p1 & 0x3; - if (nbyte) { - nbyte = 4 - nbyte; - n -= nbyte; - COPYSETUP (nbyte); - COPY (p1, p2, nbyte, "b"); - } -#if (M68K_HAS_MISALIGNED == 0) - /* - * Take care of machines that can't - * handle misaligned references. - */ - if ((int)p2 & 0x1) { - COPYSETUP (n); - COPY (p1, p2, n, "b"); - return s1; - } -#endif - nl = (unsigned int)n >> 2; - COPYSETUP (nl); - COPY (p1, p2, nl, "l"); - nbyte = (int)n & 0x3; - if (nbyte) { - COPYSETUP (nbyte); - COPY (p1, p2, nbyte, "b"); - } - } - } - return s1; -} diff --git a/c/src/exec/score/cpu/m68k/qsm.h b/c/src/exec/score/cpu/m68k/qsm.h deleted file mode 100644 index 9853978115..0000000000 --- a/c/src/exec/score/cpu/m68k/qsm.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - *------------------------------------------------------------------- - * - * QSM -- Queued Serial Module - * - * The QSM contains two serial interfaces: (a) the queued serial - * peripheral interface (QSPI) and the serial communication interface - * (SCI). The QSPI provides peripheral expansion and/or interprocessor - * communication through a full-duplex, synchronous, three-wire bus. A - * self contained RAM queue permits serial data transfers without CPU - * intervention and automatic continuous sampling. The SCI provides a - * standard non-return to zero mark/space format with wakeup functions - * to allow the CPU to run uninterrupted until woken - * - * For more information, refer to Motorola's "Modular Microcontroller - * Family Queued Serial Module Reference Manual" (Motorola document - * QSMRM/AD). - * - * This file has been created by John S. Gwynne for support of - * Motorola's 68332 MCU in the efi332 project. - * - * Redistribution and use in source and binary forms are permitted - * provided that the following conditions are met: - * 1. Redistribution of source code and documentation must retain - * the above authorship, this list of conditions and the - * following disclaimer. - * 2. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * This software is provided "AS IS" without warranty of any kind, - * either expressed or implied, including, but not limited to, the - * implied warranties of merchantability, title and fitness for a - * particular purpose. - * - *------------------------------------------------------------------ - * - * $Id$ - */ - -#ifndef _QSM_H_ -#define _QSM_H_ - -/* SAM-- shift and mask */ -#undef SAM -#define SAM(a,b,c) ((a << b) & c) - - -/* QSM_CRB (QSM Control Register Block) base address of the QSM - control registers */ -#if SIM_MM == 0 -#define QSM_CRB 0x7ffc00 -#else -#undef SIM_MM -#define SIM_MM 1 -#define QSM_CRB 0xfffc00 -#endif - - -#define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB) - /* QSM Configuration Register */ -#define STOP 0x8000 /* Stop Enable */ -#define FRZ 0x6000 /* Freeze Control */ -#define SUPV 0x0080 /* Supervisor/Unrestricted */ -#define IARB 0x000f /* Inerrupt Arbitration */ - - -#define QTEST (volatile unsigned short int * const)(0x02 + QSM_CRB) - /* QSM Test Register */ -/* Used only for factor testing */ - - -#define QILR (volatile unsigned char * const)(0x04 + QSM_CRB) - /* QSM Interrupt Level Register */ -#define ILQSPI 0x38 /* Interrupt Level for QSPI */ -#define ILSCI 0x07 /* Interrupt Level for SCI */ - - -#define QIVR (volatile unsigned char * const)(0x05 + QSM_CRB) - /* QSM Interrupt Vector Register */ -#define INTV 0xff /* Interrupt Vector Number */ - - -#define SCCR0 (volatile unsigned short int * const)(0x08 + QSM_CRB) - /* SCI Control Register 0 */ -#define SCBR 0x1fff /* SCI Baud Rate */ - - -#define SCCR1 (volatile unsigned short int * const)(0x0a + QSM_CRB) - /* SCI Control Register 1 */ -#define LOOPS 0x4000 /* Loop Mode */ -#define WOMS 0x2000 /* Wired-OR Mode for SCI Pins */ -#define ILT 0x1000 /* Idle-Line Detect Type */ -#define PT 0x0800 /* Parity Type */ -#define PE 0x0400 /* Parity Enable */ -#define M 0x0200 /* Mode Select */ -#define WAKE 0x0100 /* Wakeup by Address Mark */ -#define TIE 0x0080 /* Transmit Complete Interrupt Enable */ -#define TCIE 0x0040 /* Transmit Complete Interrupt Enable */ -#define RIE 0x0020 /* Receiver Interrupt Enable */ -#define ILIE 0x0010 /* Idle-Line Interrupt Enable */ -#define TE 0x0008 /* Transmitter Enable */ -#define RE 0x0004 /* Receiver Enable */ -#define RWU 0x0002 /* Receiver Wakeup */ -#define SBK 0x0001 /* Send Break */ - - -#define SCSR (volatile unsigned short int * const)(0x0c + QSM_CRB) - /* SCI Status Register */ -#define TDRE 0x0100 /* Transmit Data Register Empty */ -#define TC 0x0080 /* Transmit Complete */ -#define RDRF 0x0040 /* Receive Data Register Full */ -#define RAF 0x0020 /* Receiver Active */ -#define IDLE 0x0010 /* Idle-Line Detected */ -#define OR 0x0008 /* Overrun Error */ -#define NF 0x0004 /* Noise Error Flag */ -#define FE 0x0002 /* Framing Error */ -#define PF 0x0001 /* Parity Error */ - - -#define SCDR (volatile unsigned short int * const)(0x0e + QSM_CRB) - /* SCI Data Register */ - - -#define PORTQS (volatile unsigned char * const)(0x15 + QSM_CRB) - /* Port QS Data Register */ - -#define PQSPAR (volatile unsigned char * const)(0x16 + QSM_CRB) - /* PORT QS Pin Assignment Rgister */ -/* Any bit cleared (zero) defines the corresponding pin to be an I/O - pin. Any bit set defines the corresponding pin to be a QSPI - signal. */ -/* note: PQS2 is a digital I/O pin unless the SPI is enabled in which - case it becomes the SPI serial clock SCK. */ -/* note: PQS7 is a digital I/O pin unless the SCI transmitter is - enabled in which case it becomes the SCI serial output TxD. */ -#define QSMFun 0x0 -#define QSMDis 0x1 -/* - * PQSPAR Field | QSM Function | Discrete I/O pin - *------------------+--------------+------------------ */ -#define PQSPA0 0 /* MISO | PQS0 */ -#define PQSPA1 1 /* MOSI | PQS1 */ -#define PQSPA2 2 /* SCK | PQS2 (see note)*/ -#define PQSPA3 3 /* PCSO/!SS | PQS3 */ -#define PQSPA4 4 /* PCS1 | PQS4 */ -#define PQSPA5 5 /* PCS2 | PQS5 */ -#define PQSPA6 6 /* PCS3 | PQS6 */ -#define PQSPA7 7 /* TxD | PQS7 (see note)*/ - - -#define DDRQS (volatile unsigned char * const)(0x17 + QSM_CRB) - /* PORT QS Data Direction Register */ -/* Clearing a bit makes the corresponding pin an input; setting a bit - makes the pin an output. */ - - -#define SPCR0 (volatile unsigned short int * const)(0x18 + QSM_CRB) - /* QSPI Control Register 0 */ -#define MSTR 0x8000 /* Master/Slave Mode Select */ -#define WOMQ 0x4000 /* Wired-OR Mode for QSPI Pins */ -#define BITS 0x3c00 /* Bits Per Transfer */ -#define CPOL 0x0200 /* Clock Polarity */ -#define CPHA 0x0100 /* Clock Phase */ -#define SPBR 0x00ff /* Serial Clock Baud Rate */ - - -#define SPCR1 (volatile unsigned short int * const)(0x1a + QSM_CRB) - /* QSPI Control Register 1 */ -#define SPE 0x8000 /* QSPI Enable */ -#define DSCKL 0x7f00 /* Delay before SCK */ -#define DTL 0x00ff /* Length of Delay after Transfer */ - - -#define SPCR2 (volatile unsigned short int * const)(0x1c + QSM_CRB) - /* QSPI Control Register 2 */ -#define SPIFIE 0x8000 /* SPI Finished Interrupt Enable */ -#define WREN 0x4000 /* Wrap Enable */ -#define WRTO 0x2000 /* Wrap To */ -#define ENDQP 0x0f00 /* Ending Queue Pointer */ -#define NEWQP 0x000f /* New Queue Pointer Value */ - - -#define SPCR3 (volatile unsigned char * const)(0x1e + QSM_CRB) - /* QSPI Control Register 3 */ -#define LOOPQ 0x0400 /* QSPI Loop Mode */ -#define HMIE 0x0200 /* HALTA and MODF Interrupt Enable */ -#define HALT 0x0100 /* Halt */ - - -#define SPSR (volatile unsigned char * const)(0x1f + QSM_CRB) - /* QSPI Status Register */ -#define SPIF 0x0080 /* QSPI Finished Flag */ -#define MODF 0x0040 /* Mode Fault Flag */ -#define HALTA 0x0020 /* Halt Acknowlwdge Flag */ -#define CPTQP x0000f /* Completed Queue Pointer */ - -#define QSPIRR (volatile unsigned char * const)(0x100 + QSM_CRB) - /* QSPI Receive Data RAM */ -#define QSPITR (volatile unsigned char * const)(0x120 + QSM_CRB) - /* QSPI Transmit Data RAM */ -#define QSPIcR (volatile unsigned char * const)(0x140 + QSM_CRB) - /* QSPI Command RAM */ - -#endif /* _QSM_H_ */ diff --git a/c/src/exec/score/cpu/m68k/rtems/.cvsignore b/c/src/exec/score/cpu/m68k/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/m68k/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/m68k/rtems/score/.cvsignore b/c/src/exec/score/cpu/m68k/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/m68k/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/m68k/rtems/score/cpu.h b/c/src/exec/score/cpu/m68k/rtems/score/cpu.h deleted file mode 100644 index d988b4e4eb..0000000000 --- a/c/src/exec/score/cpu/m68k/rtems/score/cpu.h +++ /dev/null @@ -1,678 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the Motorola - * m68xxx processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/m68k.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE -#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE - -/* - * Use the m68k's hardware interrupt stack support and have the - * interrupt manager allocate the memory for it. - */ - -#if ( M68K_HAS_SEPARATE_STACKS == 1) -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0 -#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1 -#else -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1 -#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0 -#endif -#define CPU_ALLOCATE_INTERRUPT_STACK 1 - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Some family members have no FP, some have an FPU such as the - * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040). - * - * NOTE: If on a CPU without hardware FP, then one can use software - * emulation. The gcc software FP emulation code has data which - * must be contexted switched on a per task basis. - */ - -#if ( M68K_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE -#else -#define CPU_HARDWARE_FP FALSE -#if defined(__GNUC__) -#define CPU_SOFTWARE_FP TRUE -#else -#define CPU_SOFTWARE_FP FALSE -#endif -#endif - -/* - * All tasks are not by default floating point tasks on this CPU. - * The IDLE task does not have a floating point context on this CPU. - * It is safe to use the deferred floating point context switch - * algorithm on this CPU. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE -#define CPU_IDLE_TASK_IS_FP FALSE -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE -#define CPU_STACK_GROWS_UP FALSE -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -#ifndef ASM -/* structures */ - -/* - * Basic integer context for the m68k family. - */ - -typedef struct { - unsigned32 sr; /* (sr) status register */ - unsigned32 d2; /* (d2) data register 2 */ - unsigned32 d3; /* (d3) data register 3 */ - unsigned32 d4; /* (d4) data register 4 */ - unsigned32 d5; /* (d5) data register 5 */ - unsigned32 d6; /* (d6) data register 6 */ - unsigned32 d7; /* (d7) data register 7 */ - void *a2; /* (a2) address register 2 */ - void *a3; /* (a3) address register 3 */ - void *a4; /* (a4) address register 4 */ - void *a5; /* (a5) address register 5 */ - void *a6; /* (a6) address register 6 */ - void *a7_msp; /* (a7) master stack pointer */ -} Context_Control; - -/* - * Floating point context ares - */ - -#if (CPU_SOFTWARE_FP == TRUE) - -/* - * This is the same as gcc's view of the software FP condition code - * register _fpCCR. The implementation of the emulation code is - * in the gcc-VERSION/config/m68k directory. This structure is - * correct as of gcc 2.7.2.2. - */ - -typedef struct { - unsigned16 _exception_bits; - unsigned16 _trap_enable_bits; - unsigned16 _sticky_bits; - unsigned16 _rounding_mode; - unsigned16 _format; - unsigned16 _last_operation; - union { - float sf; - double df; - } _operand1; - union { - float sf; - double df; - } _operand2; -} Context_Control_fp; - -#else - -/* - * FP context save area for the M68881/M68882 numeric coprocessors. - */ - -typedef struct { - unsigned8 fp_save_area[332]; /* 216 bytes for FSAVE/FRESTORE */ - /* 96 bytes for FMOVEM FP0-7 */ - /* 12 bytes for FMOVEM CREGS */ - /* 4 bytes for non-null flag */ -} Context_Control_fp; -#endif - -/* - * The following structures define the set of information saved - * on the current stack by RTEMS upon receipt of each exc/interrupt. - * These are not used by m68k handlers. - * The exception frame is for rdbg. - */ - -typedef struct { - unsigned32 vecnum; /* vector number */ -} CPU_Interrupt_frame; - -typedef struct { - unsigned32 vecnum; /* vector number */ - unsigned32 sr; /* status register */ - unsigned32 pc; /* program counter */ - unsigned32 d0, d1, d2, d3, d4, d5, d6, d7; - unsigned32 a0, a1, a2, a3, a4, a5, a6, a7; -} CPU_Exception_frame; - -/* - * The following table contains the information required to configure - * the m68k specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - - m68k_isr *interrupt_vector_table; -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access M68K specific additions to the CPU Table - */ - -#define rtems_cpu_configuration_get_interrupt_vector_table() \ - (_CPU_Table.interrupt_vector_table) - -/* variables */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -extern char _VBR[]; - -#if ( M68K_HAS_VBR == 0 ) - -/* - * Table of ISR handler entries that resides in RAM. The FORMAT/ID is - * pushed onto the stack. This is not is the same order as VBR processors. - * The ISR handler takes the format and uses it for dispatching the user - * handler. - * - * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS - * - */ - -typedef struct { - unsigned16 move_a7; /* move #FORMAT_ID,%a7@- */ - unsigned16 format_id; - unsigned16 jmp; /* jmp _ISR_Handlers */ - unsigned32 isr_handler; -} _CPU_ISR_handler_entry; - -#define M68K_MOVE_A7 0x3F3C -#define M68K_JMP 0x4EF9 - - /* points to jsr-exception-table in targets wo/ VBR register */ -SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; - -#endif /* M68K_HAS_VBR */ -#endif /* ASM */ - -/* constants */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */ - -/* - * context size area for floating point - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * m68k family supports 256 distinct vectors. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Minimum size of a thread's stack. - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -/* - * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries. - */ - -#define CPU_ALIGNMENT 4 -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * On m68k thread stacks require no further alignment after allocation - * from the Workspace. - */ - -#define CPU_STACK_ALIGNMENT 0 - -#ifndef ASM - -/* macros */ - -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -#define _CPU_Initialize_vectors() - -#define _CPU_ISR_Disable( _level ) \ - m68k_disable_interrupts( _level ) - -#define _CPU_ISR_Enable( _level ) \ - m68k_enable_interrupts( _level ) - -#define _CPU_ISR_Flash( _level ) \ - m68k_flash_interrupts( _level ) - -#define _CPU_ISR_Set_level( _newlevel ) \ - m68k_set_interrupt_level( _newlevel ) - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - */ - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - do { \ - unsigned32 _stack; \ - \ - (_the_context)->sr = 0x3000 | ((_isr) << 8); \ - _stack = (unsigned32)(_stack_base) + (_size) - 4; \ - (_the_context)->a7_msp = (void *)_stack; \ - *(void **)_stack = (void *)(_entry_point); \ - } while ( 0 ) - -#define _CPU_Context_Restart_self( _the_context ) \ - { asm volatile( "movew %0,%%sr ; " \ - "moval %1,%%a7 ; " \ - "rts" \ - : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \ - : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \ - } - -/* - * Floating Point Context Area Support routines - */ - -#if (CPU_SOFTWARE_FP == TRUE) - -/* - * This software FP implementation is only for GCC. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ((void *) _Addresses_Add_offset( (_base), (_offset) ) ) - - -#define _CPU_Context_Initialize_fp( _fp_area ) \ - { \ - Context_Control_fp *_fp; \ - _fp = *(Context_Control_fp **)_fp_area; \ - _fp->_exception_bits = 0; \ - _fp->_trap_enable_bits = 0; \ - _fp->_sticky_bits = 0; \ - _fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \ - _fp->_format = 0; /* NIL */ \ - _fp->_last_operation = 0; /* NOOP */ \ - _fp->_operand1.df = 0; \ - _fp->_operand2.df = 0; \ - } -#else -#define _CPU_Context_Fp_start( _base, _offset ) \ - ((void *) \ - _Addresses_Add_offset( \ - (_base), \ - (_offset) + CPU_CONTEXT_FP_SIZE - 4 \ - ) \ - ) - -#define _CPU_Context_Initialize_fp( _fp_area ) \ - { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \ - \ - *(--(_fp_context)) = 0; \ - *(_fp_area) = (unsigned8 *)(_fp_context); \ - } -#endif - -/* end of Context handler macros */ - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -#if ( M68K_COLDFIRE_ARCH == 1 ) -#define _CPU_Fatal_halt( _error ) \ - { asm volatile( "move.w %%sr,%%d0\n\t" \ - "or.l %2,%%d0\n\t" \ - "move.w %%d0,%%sr\n\t" \ - "move.l %1,%%d0\n\t" \ - "move.l #0xDEADBEEF,%%d1\n\t" \ - "halt" \ - : "=g" (_error) \ - : "0" (_error), "d"(0x0700) \ - : "d0", "d1" ); \ - } -#else -#define _CPU_Fatal_halt( _error ) \ - { asm volatile( "movl %0,%%d0; " \ - "orw #0x0700,%%sr; " \ - "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ - } -#endif - -/* end of Fatal Error manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - * - * NOTE: - * - * It appears that on the M68020 bitfield are always 32 bits wide - * when in a register. This code forces the bitfield to be in - * memory (it really always is anyway). This allows us to - * have a real 16 bit wide bitfield which operates "correctly." - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE -#define CPU_USE_GENERIC_BITFIELD_DATA FALSE - -#if ( M68K_HAS_BFFFO == 1 ) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value)); -#else - -/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in - _CPU_Priority_bits_index is not needed), handles the 0 case, and - does not molest _value -- jsg */ -#if ( M68K_COLDFIRE_ARCH == 1 ) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - extern const unsigned char __BFFFOtable[256]; \ - register int dumby; \ - \ - asm volatile ( \ - " clr.l %1\n" \ - " move.w %2,%1\n" \ - " lsr.l #8,%1\n" \ - " beq.s 1f\n" \ - " move.b (%3,%1),%0\n" \ - " bra.s 0f\n" \ - "1: move.w %2,%1\n" \ - " move.b (%3,%1),%0\n" \ - " addq.l #8,%0\n" \ - "0: and.l #0xff,%0\n" \ - : "=&d" ((_output)), "=&d" ((dumby)) \ - : "d" ((_value)), "ao" ((__BFFFOtable)) \ - : "cc" ) ; \ - } -#elif ( M68K_HAS_EXTB_L == 1 ) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - extern const unsigned char __BFFFOtable[256]; \ - register int dumby; \ - \ - asm volatile ( " move.w %2,%1\n" \ - " lsr.w #8,%1\n" \ - " beq.s 1f\n" \ - " move.b (%3,%1.w),%0\n" \ - " extb.l %0\n" \ - " bra.s 0f\n" \ - "1: moveq.l #8,%0\n" \ - " add.b (%3,%2.w),%0\n" \ - "0:\n" \ - : "=&d" ((_output)), "=&d" ((dumby)) \ - : "d" ((_value)), "ao" ((__BFFFOtable)) \ - : "cc" ) ; \ - } -#else -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - extern const unsigned char __BFFFOtable[256]; \ - register int dumby; \ - \ - asm volatile ( " move.w %2,%1\n" \ - " lsr.w #8,%1\n" \ - " beq.s 1f\n" \ - " move.b (%3,%1.w),%0\n" \ - " and.l #0x000000ff,%0\n"\ - " bra.s 0f\n" \ - "1: moveq.l #8,%0\n" \ - " add.b (%3,%2.w),%0\n" \ - "0:\n" \ - : "=&d" ((_output)), "=&d" ((dumby)) \ - : "d" ((_value)), "ao" ((__BFFFOtable)) \ - : "cc" ) ; \ - } -#endif - -#endif - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x8000 >> (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -#if (M68K_HAS_FPSP_PACKAGE == 1) -/* - * Hooks for the Floating Point Support Package (FPSP) provided by Motorola - * - * NOTES: - * - * Motorola 68k family CPU's before the 68040 used a coprocessor - * (68881 or 68882) to handle floating point. The 68040 has internal - * floating point support -- but *not* the complete support provided by - * the 68881 or 68882. The leftover functions are taken care of by the - * M68040 Floating Point Support Package. Quoting from the MC68040 - * Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040): - * - * "When used with the M68040FPSP, the MC68040 FPU is fully - * compliant with IEEE floating-point standards." - * - * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and - * is invoked early in the application code to insure that proper FP - * behavior is installed. This is not left to the BSP to call, since - * this would force all applications using that BSP to use FPSP which - * is not necessarily desirable. - * - * There is a similar package for the 68060 but RTEMS does not yet - * support the 68060. - */ - -void M68KFPSPInstallExceptionHandlers (void); - -SCORE_EXTERN int (*_FPSP_install_raw_handler)( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -#endif - - -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/m68k/rtems/score/m68k.h b/c/src/exec/score/cpu/m68k/rtems/score/m68k.h deleted file mode 100644 index 62055d803e..0000000000 --- a/c/src/exec/score/cpu/m68k/rtems/score/m68k.h +++ /dev/null @@ -1,416 +0,0 @@ -/* m68k.h - * - * This include file contains information pertaining to the Motorola - * m68xxx processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __M68k_h -#define __M68k_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section contains the information required to build - * RTEMS for a particular member of the Motorola MC68xxx - * family. It does this by setting variables to indicate - * which implementation dependent features are present in - * a particular member of the family. - * - * Currently recognized: - * -m68000 - * -m68000 -msoft-float - * -m68020 - * -m68020 -msoft-float - * -m68030 - * -m68040 -msoft-float - * -m68040 - * -m68040 -msoft-float - * -m68060 - * -m68060 -msoft-float - * -m68302 (no FP) (deprecated, use -m68000) - * -m68332 (no FP) (deprecated, use -mcpu32) - * -mcpu32 (no FP) - * -m5200 (no FP) - * - * As of gcc 2.8.1 and egcs 1.1, there is no distinction made between - * the CPU32 and CPU32+. The option -mcpu32 generates code which can - * be run on either core. RTEMS distinguishes between these two cores - * because they have different alignment rules which impact performance. - * If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should - * be defined in your custom file (see make/custom/gen68360.cfg for an - * example of how to do this. If gcc ever distinguishes between these - * two cores, then RTEMS__mcpu32p__ usage will be replaced with the - * appropriate compiler defined predefine. - * - * Here is some information on the 040 variants (courtesy of Doug McBride, - * mcbride@rodin.colorado.edu): - * - * "The 68040 is a superset of the 68EC040 and the 68LC040. The - * 68EC040 and 68LC040 do not have FPU's. The 68LC040 and the - * 68EC040 have renamed the DLE pin as JS0 which must be tied to - * Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1. The - * 68EC040 has access control units instead of memory management units. - * The 68EC040 should not have the PFLUSH or PTEST instructions executed - * (cause an indeterminate result). The 68EC040 and 68LC040 do not - * implement the DLE or multiplexed bus modes. The 68EC040 does not - * implement the output buffer impedance selection mode of operation." - * - * M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction - * which is not available for 68000 or 68ec000 cores (68000, 68001, 68008, - * 68010, 68302, 68306, 68307). This instruction is available on the 68020 - * up and the cpu32 based models. - * - * M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned - * data access (68020, 68030, 68040, 68060, CPU32+). - * - * NOTE: - * Eventually it would be nice to evaluate doing a lot of this section - * by having each model specify which core it uses and then go from there. - */ - -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. Notice the only exception to this is that - * gcc does not distinguish between CPU32 and CPU32+. This - * feature selection logic is setup such that if RTEMS__mcpu32p__ - * is defined, then CPU32+ rules are used. Otherwise, the safe - * but less efficient CPU32 rules are used for the CPU32+. - */ - -#if defined(__mc68020__) - -#define CPU_MODEL_NAME "m68020" -#define M68K_HAS_VBR 1 -#define M68K_HAS_SEPARATE_STACKS 1 -#define M68K_HAS_BFFFO 1 -#define M68K_HAS_PREINDEXING 1 -#define M68K_HAS_EXTB_L 1 -#define M68K_HAS_MISALIGNED 1 -# if defined (__HAVE_68881__) -# define M68K_HAS_FPU 1 -# define M68K_HAS_FPSP_PACKAGE 0 -# else -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 -# endif - -#elif defined(__mc68030__) - -#define CPU_MODEL_NAME "m68030" -#define M68K_HAS_VBR 1 -#define M68K_HAS_SEPARATE_STACKS 1 -#define M68K_HAS_BFFFO 1 -#define M68K_HAS_PREINDEXING 1 -#define M68K_HAS_EXTB_L 1 -#define M68K_HAS_MISALIGNED 1 -# if defined (__HAVE_68881__) -# define M68K_HAS_FPU 1 -# define M68K_HAS_FPSP_PACKAGE 0 -# else -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 -# endif - -#elif defined(__mc68040__) - -#define CPU_MODEL_NAME "m68040" -#define M68K_HAS_VBR 1 -#define M68K_HAS_SEPARATE_STACKS 1 -#define M68K_HAS_BFFFO 1 -#define M68K_HAS_PREINDEXING 1 -#define M68K_HAS_EXTB_L 1 -#define M68K_HAS_MISALIGNED 1 -# if defined (__HAVE_68881__) -# define M68K_HAS_FPU 1 -# define M68K_HAS_FPSP_PACKAGE 1 -# else -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 -# endif - -#elif defined(__mc68060__) - -#define CPU_MODEL_NAME "m68060" -#define M68K_HAS_VBR 1 -#define M68K_HAS_SEPARATE_STACKS 0 -#define M68K_HAS_BFFFO 1 -#define M68K_HAS_PREINDEXING 1 -#define M68K_HAS_EXTB_L 1 -#define M68K_HAS_MISALIGNED 1 -# if defined (__HAVE_68881__) -# define M68K_HAS_FPU 1 -# define M68K_HAS_FPSP_PACKAGE 0 -# else -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 -# endif - -#elif defined(__mc68302__) - -#define CPU_MODEL_NAME "m68302" -#define M68K_HAS_VBR 0 -#define M68K_HAS_SEPARATE_STACKS 0 -#define M68K_HAS_BFFFO 0 -#define M68K_HAS_PREINDEXING 0 -#define M68K_HAS_EXTB_L 0 -#define M68K_HAS_MISALIGNED 0 -#define M68K_HAS_FPU 0 -#define M68K_HAS_FPSP_PACKAGE 0 - - /* gcc and egcs do not distinguish between CPU32 and CPU32+ */ -#elif defined(RTEMS__mcpu32p__) - -#define CPU_MODEL_NAME "mcpu32+" -#define M68K_HAS_VBR 1 -#define M68K_HAS_SEPARATE_STACKS 0 -#define M68K_HAS_BFFFO 0 -#define M68K_HAS_PREINDEXING 1 -#define M68K_HAS_EXTB_L 1 -#define M68K_HAS_MISALIGNED 1 -#define M68K_HAS_FPU 0 -#define M68K_HAS_FPSP_PACKAGE 0 - -#elif defined(__mcpu32__) - -#define CPU_MODEL_NAME "mcpu32" -#define M68K_HAS_VBR 1 -#define M68K_HAS_SEPARATE_STACKS 0 -#define M68K_HAS_BFFFO 0 -#define M68K_HAS_PREINDEXING 1 -#define M68K_HAS_EXTB_L 1 -#define M68K_HAS_MISALIGNED 0 -#define M68K_HAS_FPU 0 -#define M68K_HAS_FPSP_PACKAGE 0 - -#elif defined(__mcf5200__) -/* Motorola ColdFire V2 core - RISC/68020 hybrid */ -#define CPU_MODEL_NAME "m5200" -#define M68K_HAS_VBR 1 -#define M68K_HAS_BFFFO 0 -#define M68K_HAS_SEPARATE_STACKS 0 -#define M68K_HAS_PREINDEXING 0 -#define M68K_HAS_EXTB_L 1 -#define M68K_HAS_MISALIGNED 1 -#define M68K_HAS_FPU 0 -#define M68K_HAS_FPSP_PACKAGE 0 -#define M68K_COLDFIRE_ARCH 1 - -#elif defined(__mc68000__) - -#define CPU_MODEL_NAME "m68000" -#define M68K_HAS_VBR 0 -#define M68K_HAS_SEPARATE_STACKS 0 -#define M68K_HAS_BFFFO 0 -#define M68K_HAS_PREINDEXING 0 -#define M68K_HAS_EXTB_L 0 -#define M68K_HAS_MISALIGNED 0 -# if defined (__HAVE_68881__) -# define M68K_HAS_FPU 1 -# define M68K_HAS_FPSP_PACKAGE 0 -# else -# define M68K_HAS_FPU 0 -# define M68K_HAS_FPSP_PACKAGE 0 -# endif - -#else - -#error "Unsupported CPU model -- are you sure you're running a 68k compiler?" - -#endif - -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* - * If the above did not specify a ColdFire architecture, then set - * this flag to indicate that it is not a ColdFire CPU. - */ - -#if !defined(M68K_COLDFIRE_ARCH) -#define M68K_COLDFIRE_ARCH 0 -#endif - -/* - * Define the name of the CPU family. - */ - -#if ( M68K_COLDFIRE_ARCH == 1 ) - #define CPU_NAME "Motorola ColdFire" -#else - #define CPU_NAME "Motorola MC68xxx" -#endif - -#ifndef ASM - -#if ( M68K_COLDFIRE_ARCH == 1 ) -#define m68k_disable_interrupts( _level ) \ - do { register unsigned32 _tmpsr = 0x0700; \ - asm volatile ( "move.w %%sr,%0\n\t" \ - "or.l %0,%1\n\t" \ - "move.w %1,%%sr" \ - : "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) ); \ - } while( 0 ) -#else -#define m68k_disable_interrupts( _level ) \ - asm volatile ( "move.w %%sr,%0\n\t" \ - "or.w #0x0700,%%sr" \ - : "=d" (_level)) -#endif - -#define m68k_enable_interrupts( _level ) \ - asm volatile ( "move.w %0,%%sr " : : "d" (_level)); - -#if ( M68K_COLDFIRE_ARCH == 1 ) -#define m68k_flash_interrupts( _level ) \ - do { register unsigned32 _tmpsr = 0x0700; \ - asm volatile ( "move.w %2,%%sr\n\t" \ - "or.l %2,%1\n\t" \ - "move.w %1,%%sr" \ - : "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) ); \ - } while( 0 ) -#else -#define m68k_flash_interrupts( _level ) \ - asm volatile ( "move.w %0,%%sr\n\t" \ - "or.w #0x0700,%%sr" \ - : : "d" (_level)) -#endif - -#define m68k_get_interrupt_level( _level ) \ - do { \ - register unsigned32 _tmpsr; \ - \ - asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ - _level = (_tmpsr & 0x0700) >> 8; \ - } while (0) - -#define m68k_set_interrupt_level( _newlevel ) \ - do { \ - register unsigned32 _tmpsr; \ - \ - asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ - _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \ - asm volatile( "move.w %0,%%sr" : : "d" (_tmpsr)); \ - } while (0) - -#if ( M68K_HAS_VBR == 1 && M68K_COLDFIRE_ARCH == 0 ) -#define m68k_get_vbr( vbr ) \ - asm volatile ( "movec %%vbr,%0 " : "=r" (vbr)) - -#define m68k_set_vbr( vbr ) \ - asm volatile ( "movec %0,%%vbr " : : "r" (vbr)) - -#elif ( M68K_COLDFIRE_ARCH == 1 ) -#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR - -#define m68k_set_vbr( _vbr ) \ - asm volatile ("move.l %%a7,%%d1 \n\t" \ - "move.l %0,%%a7\n\t" \ - "movec %%a7,%%vbr\n\t" \ - "move.l %%d1,%%a7\n\t" \ - : : "d" (_vbr) : "d1" ); - -#else -#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR -#define m68k_set_vbr( _vbr ) -#endif - -/* - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - */ -#if ( M68K_COLDFIRE_ARCH == 1 ) - -/* There are no rotate commands in Coldfire architecture. We will use - * generic implementation of endian swapping for Coldfire. - */ -static inline unsigned int m68k_swap_u32( - unsigned int value - ) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -static inline unsigned int m68k_swap_u16( - unsigned int value -) -{ - return (((value & 0xff) << 8) | ((value >> 8) & 0xff)); -} - -#else - -static inline unsigned int m68k_swap_u32( - unsigned int value -) -{ - unsigned int swapped = value; - - asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); - asm volatile( "swap %0" : "=d" (swapped) : "0" (swapped) ); - asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); - - return( swapped ); -} - -static inline unsigned int m68k_swap_u16( - unsigned int value -) -{ - unsigned short swapped = value; - - asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); - - return( swapped ); -} -#endif - -#define CPU_swap_u32( value ) m68k_swap_u32( value ) -#define CPU_swap_u16( value ) m68k_swap_u16( value ) - - -/* - * _CPU_virtual_to_physical - * - * DESCRIPTION: - * - * This function is used to map virtual addresses to physical - * addresses. - * - * FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE - * PHYSICAL ADDRESSES - */ -static inline void * _CPU_virtual_to_physical ( - const void * d_addr ) -{ - return (void *) d_addr; -} - - -#endif /* !ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* __M68K_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/m68k/rtems/score/types.h b/c/src/exec/score/cpu/m68k/rtems/score/types.h deleted file mode 100644 index 7b1a1c643e..0000000000 --- a/c/src/exec/score/cpu/m68k/rtems/score/types.h +++ /dev/null @@ -1,57 +0,0 @@ -/* m68ktypes.h - * - * This include file contains type definitions pertaining to the Motorola - * m68xxx processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __M68k_TYPES_h -#define __M68k_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void m68k_isr; - -typedef void ( *m68k_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/m68k/sim.h b/c/src/exec/score/cpu/m68k/sim.h deleted file mode 100644 index db2ec89d3a..0000000000 --- a/c/src/exec/score/cpu/m68k/sim.h +++ /dev/null @@ -1,334 +0,0 @@ -/* - *------------------------------------------------------------------- - * - * SIM -- System Integration Module - * - * The system integration module (SIM) is used on many Motorola 16- - * and 32-bit MCUs for the following functions: - * - * () System configuration and protection. Bus and software watchdog - * monitors are provided in addition to periodic interrupt generators. - * - * () Clock signal generation for other intermodule bus (IMB) members - * and external devices. - * - * () The generation of chip-select signals that simplify external - * circuitry interface. - * - * () Data ports that are available for general purpose input and - * output. - * - * () A system test block that is intended only for factory tests. - * - * For more information, refer to Motorola's "Modular Microcontroller - * Family System Integration Module Reference Manual" (Motorola document - * SIMRM/AD). - * - * This file has been created by John S. Gwynne for support of - * Motorola's 68332 MCU in the efi332 project. - * - * Redistribution and use in source and binary forms are permitted - * provided that the following conditions are met: - * 1. Redistribution of source code and documentation must retain - * the above authorship, this list of conditions and the - * following disclaimer. - * 2. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * This software is provided "AS IS" without warranty of any kind, - * either expressed or implied, including, but not limited to, the - * implied warranties of merchantability, title and fitness for a - * particular purpose. - * - *------------------------------------------------------------------ - * - * $Id$ - */ - -#ifndef _SIM_H_ -#define _SIM_H_ - - -/* SAM-- shift and mask */ -#undef SAM -#define SAM(a,b,c) ((a << b) & c) - -/* - * These macros make this file usable from assembly. - */ - -#ifdef ASM -#define SIM_VOLATILE_USHORT_POINTER -#define SIM_VOLATILE_UCHAR_POINTER -#else -#define SIM_VOLATILE_USHORT_POINTER (volatile unsigned short int * const) -#define SIM_VOLATILE_UCHAR_POINTER (volatile unsigned char * const) -#endif - -/* SIM_CRB (SIM Control Register Block) base address of the SIM - control registers */ -#ifndef SIM_CRB -#if SIM_MM == 0 -#define SIM_CRB 0x7ffa00 -#else /* SIM_MM */ -#undef SIM_MM -#define SIM_MM 1 -#define SIM_CRB 0xfffa00 -#endif /* SIM_MM */ -#endif /* SIM_CRB */ - - -#define SIMCR SIM_VOLATILE_USHORT_POINTER(0x00 + SIM_CRB) - /* Module Configuration Register */ -#define EXOFF 0x8000 /* External Clock Off */ -#define FRZSW 0x4000 /* Freeze Software Enable */ -#define FRZBM 0x2000 /* Freeze Bus Monitor Enable */ -#define SLVEN 0x0800 /* Factory Test Model Enabled (ro)*/ -#define SHEN 0x0300 /* Show Cycle Enable */ -#define SUPV 0x0080 /* Supervisor/Unrestricted Data Space */ -#define MM 0x0040 /* Module Mapping */ -#define IARB 0x000f /* Interrupt Arbitration Field */ - - - -#define SIMTR SIM_VOLATILE_USHORT_POINTER(0x02 + SIM_CRB) - /* SIM Test Register */ -/* Used only for factor testing */ - - - -#define SYNCR SIM_VOLATILE_USHORT_POINTER(0x04 + SIM_CRB) - /* Clock Synthesizer Control Register */ -#define VCO 0x8000 /* Frequency Control (VCO) */ -#define PRESCALE 0x4000 /* Frequency Control Bit (Prescale) */ -#define COUNTER 0x3f00 /* Frequency Control Counter */ -#define EDIV 0x0080 /* ECLK Divide Rate */ -#define SLIMP 0x0010 /* Limp Mode Status */ -#define SLOCK 0x0008 /* Synthesizer Lock */ -#define RSTEN 0x0004 /* Reset Enable */ -#define STSIM 0x0002 /* Stop Mode SIM Clock */ -#define STEXT 0x0001 /* Stop Mode External Clock */ - - - -#define RSR SIM_VOLATILE_UCHAR_POINTER(0x07 + SIM_CRB) - /* Reset Status Register */ -#define EXT 0x0080 /* External Reset */ -#define POW 0x0040 /* Power-On Reset */ -#define SW 0x0020 /* Software Watchdog Reset */ -#define DBF 0x0010 /* Double Bus Fault Reset */ -#define LOC 0x0004 /* Loss of Clock Reset */ -#define SYS 0x0002 /* System Reset */ -#define TST 0x0001 /* Test Submodule Reset */ - - - -#define SIMTRE SIM_VOLATILE_USHORT_POINTER(0x08 + SIM_CRB) - /* System Integration Test Register */ -/* Used only for factor testing */ - - - -#define PORTE0 SIM_VOLATILE_UCHAR_POINTER(0x11 + SIM_CRB) -#define PORTE1 SIM_VOLATILE_UCHAR_POINTER(0x13 + SIM_CRB) - /* Port E Data Register */ -#define DDRE SIM_VOLATILE_UCHAR_POINTER(0x15 + SIM_CRB) - /* Port E Data Direction Register */ -#define PEPAR SIM_VOLATILE_UCHAR_POINTER(0x17 + SIM_CRB) - /* Port E Pin Assignment Register */ -/* Any bit cleared (zero) defines the corresponding pin to be an I/O - pin. Any bit set defines the corresponding pin to be a bus control - signal. */ - - - -#define PORTF0 SIM_VOLATILE_UCHAR_POINTER(0x19 + SIM_CRB) -#define PORTF1 SIM_VOLATILE_UCHAR_POINTER(0x1b + SIM_CRB) - /* Port F Data Register */ -#define DDRF SIM_VOLATILE_UCHAR_POINTER(0x1d + SIM_CRB) - /* Port E Data Direction Register */ -#define PFPAR SIM_VOLATILE_UCHAR_POINTER(0x1f + SIM_CRB) -/* Any bit cleared (zero) defines the corresponding pin to be an I/O - pin. Any bit set defines the corresponding pin to be a bus control - signal. */ - - - -#define SYPCR SIM_VOLATILE_UCHAR_POINTER(0x21 + SIM_CRB) -/* !!! can write to only once after reset !!! */ - /* System Protection Control Register */ -#define SWE 0x80 /* Software Watch Enable */ -#define SWP 0x40 /* Software Watchdog Prescale */ -#define SWT 0x30 /* Software Watchdog Timing */ -#define HME 0x08 /* Halt Monitor Enable */ -#define BME 0x04 /* Bus Monitor External Enable */ -#define BMT 0x03 /* Bus Monitor Timing */ - - - -#define PICR SIM_VOLATILE_USHORT_POINTER(0x22 + SIM_CRB) - /* Periodic Interrupt Control Reg. */ -#define PIRQL 0x0700 /* Periodic Interrupt Request Level */ -#define PIV 0x00ff /* Periodic Interrupt Level */ - - - -#define PITR SIM_VOLATILE_USHORT_POINTER(0x24 + SIM_CRB) - /* Periodic Interrupt Timer Register */ -#define PTP 0x0100 /* Periodic Timer Prescaler Control */ -#define PITM 0x00ff /* Periodic Interrupt Timing Modulus */ - - - -#define SWSR SIM_VOLATILE_UCHAR_POINTER(0x27 + SIM_CRB) - /* Software Service Register */ -/* write 0x55 then 0xaa to service the software watchdog */ - - - -#define TSTMSRA SIM_VOLATILE_USHORT_POINTER(0x30 + SIM_CRB) - /* Test Module Master Shift A */ -#define TSTMSRB SIM_VOLATILE_USHORT_POINTER(0x32 + SIM_CRB) - /* Test Module Master Shift A */ -#define TSTSC SIM_VOLATILE_USHORT_POINTER(0x34 + SIM_CRB) - /* Test Module Shift Count */ -#define TSTRC SIM_VOLATILE_USHORT_POINTER(0x36 + SIM_CRB) - /* Test Module Repetition Counter */ -#define CREG SIM_VOLATILE_USHORT_POINTER(0x38 + SIM_CRB) - /* Test Module Control */ -#define DREG SIM_VOLATILE_USHORT_POINTER(0x3a + SIM_CRB) - /* Test Module Distributed */ -/* Used only for factor testing */ - - - -#define PORTC SIM_VOLATILE_UCHAR_POINTER(0x41 + SIM_CRB) - /* Port C Data */ - - - -#define CSPAR0 SIM_VOLATILE_USHORT_POINTER(0x44 + SIM_CRB) - /* Chip Select Pin Assignment - Resgister 0 */ -/* CSPAR0 contains seven two-bit fields that determine the functions - of corresponding chip-select pins. CSPAR0[15:14] are not - used. These bits always read zero; write have no effect. CSPAR0 bit - 1 always reads one; writes to CSPAR0 bit 1 have no effect. */ -#define CSPAR1 SIM_VOLATILE_USHORT_POINTER(0x46 + SIM_CRB) - /* Chip Select Pin Assignment - Register 1 */ -/* CSPAR1 contains five two-bit fields that determine the finctions of - corresponding chip-select pins. CSPAR1[15:10] are not used. These - bits always read zero; writes have no effect. */ -/* - * - * Bit Field | Description - * ------------+--------------- - * 00 | Discrete Output - * 01 | Alternate Function - * 10 | Chip Select (8-bit port) - * 11 | Chip Select (16-bit port) - */ -#define DisOut 0x0 -#define AltFun 0x1 -#define CS8bit 0x2 -#define CS16bit 0x3 -/* - * - * CSPARx Field |Chip Select Signal | Alternate Signal | Discrete Output - *-----------------+--------------------+--------------------+---------------*/ -#define CS_5 12 /* !CS5 | FC2 | PC2 */ -#define CS_4 10 /* !CS4 | FC1 | PC1 */ -#define CS_3 8 /* !CS3 | FC0 | PC0 */ -#define CS_2 6 /* !CS2 | !BGACK | */ -#define CS_1 4 /* !CS1 | !BG | */ -#define CS_0 2 /* !CS0 | !BR | */ -#define CSBOOT 0 /* !CSBOOT | | */ -/* | | | */ -#define CS_10 8 /* !CS10 | ADDR23 | ECLK */ -#define CS_9 6 /* !CS9 | ADDR22 | PC6 */ -#define CS_8 4 /* !CS8 | ADDR21 | PC5 */ -#define CS_7 2 /* !CS7 | ADDR20 | PC4 */ -#define CS_6 0 /* !CS6 | ADDR19 | PC3 */ - -#define BS_2K 0x0 -#define BS_8K 0x1 -#define BS_16K 0x2 -#define BS_64K 0x3 -#define BS_128K 0x4 -#define BS_256K 0x5 -#define BS_512K 0x6 -#define BS_1M 0x7 - -#define CSBARBT SIM_VOLATILE_USHORT_POINTER(0x48 + SIM_CRB) -#define CSBAR0 SIM_VOLATILE_USHORT_POINTER(0x4c + SIM_CRB) -#define CSBAR1 SIM_VOLATILE_USHORT_POINTER(0x50 + SIM_CRB) -#define CSBAR2 SIM_VOLATILE_USHORT_POINTER(0x54 + SIM_CRB) -#define CSBAR3 SIM_VOLATILE_USHORT_POINTER(0x58 + SIM_CRB) -#define CSBAR4 SIM_VOLATILE_USHORT_POINTER(0x5c + SIM_CRB) -#define CSBAR5 SIM_VOLATILE_USHORT_POINTER(0x60 + SIM_CRB) -#define CSBAR6 SIM_VOLATILE_USHORT_POINTER(0x64 + SIM_CRB) -#define CSBAR7 SIM_VOLATILE_USHORT_POINTER(0x68 + SIM_CRB) -#define CSBAR8 SIM_VOLATILE_USHORT_POINTER(0x6c + SIM_CRB) -#define CSBAR9 SIM_VOLATILE_USHORT_POINTER(0x70 + SIM_CRB) -#define CSBAR10 SIM_VOLATILE_USHORT_POINTER(0x74 + SIM_CRB) - -#define MODE 0x8000 -#define Disable 0 -#define LowerByte 0x2000 -#define UpperByte 0x4000 -#define BothBytes 0x6000 -#define ReadOnly 0x0800 -#define WriteOnly 0x1000 -#define ReadWrite 0x1800 -#define SyncAS 0x0 -#define SyncDS 0x0400 - -#define WaitStates_0 (0x0 << 6) -#define WaitStates_1 (0x1 << 6) -#define WaitStates_2 (0x2 << 6) -#define WaitStates_3 (0x3 << 6) -#define WaitStates_4 (0x4 << 6) -#define WaitStates_5 (0x5 << 6) -#define WaitStates_6 (0x6 << 6) -#define WaitStates_7 (0x7 << 6) -#define WaitStates_8 (0x8 << 6) -#define WaitStates_9 (0x9 << 6) -#define WaitStates_10 (0xa << 6) -#define WaitStates_11 (0xb << 6) -#define WaitStates_12 (0xc << 6) -#define WaitStates_13 (0xd << 6) -#define FastTerm (0xe << 6) -#define External (0xf << 6) - -#define CPUSpace (0x0 << 4) -#define UserSpace (0x1 << 4) -#define SupSpace (0x2 << 4) -#define UserSupSpace (0x3 << 4) - -#define IPLevel_any 0x0 -#define IPLevel_1 0x2 -#define IPLevel_2 0x4 -#define IPLevel_3 0x6 -#define IPLevel_4 0x8 -#define IPLevel_5 0xa -#define IPLevel_6 0xc -#define IPLevel_7 0xe - -#define AVEC 1 - -#define CSORBT SIM_VOLATILE_USHORT_POINTER(0x4a + SIM_CRB) -#define CSOR0 SIM_VOLATILE_USHORT_POINTER(0x4e + SIM_CRB) -#define CSOR1 SIM_VOLATILE_USHORT_POINTER(0x52 + SIM_CRB) -#define CSOR2 SIM_VOLATILE_USHORT_POINTER(0x56 + SIM_CRB) -#define CSOR3 SIM_VOLATILE_USHORT_POINTER(0x5a + SIM_CRB) -#define CSOR4 SIM_VOLATILE_USHORT_POINTER(0x5e + SIM_CRB) -#define CSOR5 SIM_VOLATILE_USHORT_POINTER(0x62 + SIM_CRB) -#define CSOR6 SIM_VOLATILE_USHORT_POINTER(0x66 + SIM_CRB) -#define CSOR7 SIM_VOLATILE_USHORT_POINTER(0x6a + SIM_CRB) -#define CSOR8 SIM_VOLATILE_USHORT_POINTER(0x6e + SIM_CRB) -#define CSOR9 SIM_VOLATILE_USHORT_POINTER(0x72 + SIM_CRB) -#define CSOR10 SIM_VOLATILE_USHORT_POINTER(0x76 + SIM_CRB) - -#endif /* _SIM_h_ */ diff --git a/c/src/exec/score/cpu/mips/.cvsignore b/c/src/exec/score/cpu/mips/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/mips/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/mips/ChangeLog b/c/src/exec/score/cpu/mips/ChangeLog deleted file mode 100644 index 0480a7d542..0000000000 --- a/c/src/exec/score/cpu/mips/ChangeLog +++ /dev/null @@ -1,355 +0,0 @@ -2002-07-16 Greg Menke <gregory.menke@gsfc.nasa.gov> - - * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled - deadlock caused by interrupt arriving while dispatching. - -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/mipstypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-03-20 Greg Menke <gregory.menke@gsfc.nasa.gov> - - * cpu_asm.S: Now compiles on 4600 and 4650. - -2002-03-13 Greg Menke <gregory.menke@gsfc.nasa.gov> - - * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug. - * rtems/score/cpu.h: Fixed register numbering in comments and made - interrupt enable/disable more robust. - -2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov> - * cpu_asm.S: Added support for the debug exception vector, cleaned - up the exception processing & exception return stuff. Re-added - EPC in the task context structure so the gdb stub will know where - a thread is executing. Should've left it there in the first place... - * idtcpu.h: Added support for the debug exception vector. - * cpu.c: Added ___exceptionTaskStack to hold a pointer to the - stack frame in an interrupt so context switch code can get the - userspace EPC when scheduling. - * rtems/score/cpu.h: Re-added EPC to the task context. - -2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov> - - * cpu_asm.S: Fixed exception return address, modified FP context - switch so FPU is properly enabled and also doesn't screw up the - exception FP handling. - * idtcpu.h: Added C0_TAR, the MIPS target address register used for - returning from exceptions. - * iregdef.h: Added R_TAR to the stack frame so the target address - can be saved on a per-exception basis. The new entry is past the - end of the frame gdb cares about, so doesn't affect gdb or cpu.h - stuff. - * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it - to obtain FPU defines without syntax errors generated by the C - defintions. - * cpu.c: Improved interrupt level saves & restores. - -2002-02-08 Joel Sherrill <joel@OARcorp.com> - - * iregdef.h, rtems/score/cpu.h: Reordered register in the - exception stack frame to better match gdb's expectations. - -2001-02-05 Joel Sherrill <joel@OARcorp.com> - - * cpu_asm.S: Enhanced to save/restore more registers on - exceptions. - * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every - register individually and document when it is saved. - * idtcpu.h: Added constants for the coprocessor 1 registers - revision and status. - -2001-02-05 Joel Sherrill <joel@OARcorp.com> - - * rtems/Makefile.am, rtems/score/Makefile.am: Removed again. - -2001-02-04 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: IDLE task should not be FP. This was a mistake - in the previous patch that has now been confirmed. - -2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov> - - * cpu.c: Enhancements and fixes for modifying the SR when changing - the interrupt level. - * cpu_asm.S: Fixed handling of FP enable bit so it is properly - managed on a per-task basis, improved handling of interrupt levels, - and made deferred FP contexts work on the MIPS. - * rtems/score/cpu.h: Modified to support above changes. - -2002-01-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2002-02-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * asm.h: Remove #include <rtems/score/targopts.h>. - Add #include <rtems/score/cpuopts.h>. - * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP). - - -2001-12-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use RTEMS_ENV_RTEMSCPU. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-12 Joel Sherrill <joel@OARcorp.com> - - * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional - compilation block with (CPU_HARDWARE_FP == FALSE). Reported by - Wayne Bullaughey <wayne@wmi.com>. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-07-03 Joel Sherrill <joel@OARcorp.com> - - * cpu.c: Fixed typo. - -2000-05-24 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/mips.h: Added constants for MIPS exception numbers. - All exceptions should be given low numbers and thus can be installed - and processed in a uniform manner. Variances between various MIPS - ISA levels were not accounted for. - -2001-05-24 Greg Menke <gregory.menke@gsfc.nasa.gov> - - * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>. - * cpu_asm.S: Now works on Mongoose-V. Missed in previous patch. - -2001-05-22 Greg Menke <gregory.menke@gsfc.nasa.gov> - - * rtems/score/cpu.h: Add the interrupt stack structure and enhance - the context initialization to account for floating point tasks. - * rtems/score/mips.h: Added the routines mips_set_cause(), - mips_get_fcr31(), and mips_set_fcr31(). - * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>. - -2001-05-07 Joel Sherrill <joel@OARcorp.com> - - * cpu_asm.S: Merged patches from Gregory Menke - <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up - stack usage and include nops in the delay slots. - -2001-04-20 Joel Sherrill <joel@OARcorp.com> - - * cpu_asm.S: Added code to save and restore SR and EPC to - properly support nested interrupts. Note that the ISR - (not RTEMS) enables interrupts allowing the nesting to occur. - -2001-03-14 Joel Sherrill <joel@OARcorp.com> - - * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: - Removed unused variable _CPU_Thread_dispatch_pointer - and cleaned numerous comments. - -2001-03-13 Joel Sherrill <joel@OARcorp.com> - - * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h: - Merged MIPS1 and MIPS3 code reducing the number of lines of assembly. - Also reimplemented some assembly routines in C further reducing - the amount of assembly and increasing maintainability. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-12 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected - register constraints from "general" to "register". - -2001-01-09 Joel Sherrill <joel@OARcorp.com> - - * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants - to make it easier to conditionalize the code for various ISA levels. - -2001-01-08 Joel Sherrill <joel@OARcorp.com> - - * idtcpu.h: Commented out definition of "wait". It was stupid to - use such a common word as a macro. - * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3. - * rtems/score/mips.h: Added include of <idtcpu.h>. - * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN. - -2000-12-19 Joel Sherrill <joel@OARcorp.com> - - * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register. - Previous code resulting in the interrupted immediately returning - to the caller of the routine it was inside. - -2000-12-19 Joel Sherrill <joel@OARcorp.com> - - * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here - because it has not been allocated yet. - -2000-12-13 Joel Sherrill <joel@OARcorp.com> - - * cpu.c: Removed duplicate declaration for _ISR_Vector_table. - * cpu_asm.S: Removed assembly language to vector ISR handler - on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP. - * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No - longer a constant -- get the real value from libcpu. - -2000-12-13 Joel Sherrill <joel@OARcorp.com> - - * cpu_asm.h: Removed. - * Makefile.am: Remove cpu_asm.h. - * rtems/score/mips64orion.h: Renamed mips.h. - * rtems/score/mips.h: New file, formerly mips64orion.h. - Header rewritten. - (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask, - mips_disable_in_interrupt_mask): New macros. - * rtems/score/Makefile.am: Reflect renaming mips64orion.h. - * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the - few defines that were in <cpu_asm.h>. - * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine. - MIPS ISA 3 is still in assembly for now. - (_CPU_Thread_Idle_body): Rewrote in C. - * cpu_asm.S: Rewrote file header. - (FRAME,ENDFRAME) now in asm.h. - (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C. - (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C. - (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and - leaves other bits in SR alone on task switch. - (mips_enable_interrupts,mips_disable_interrupts, - mips_enable_global_interrupts,mips_disable_global_interrupts, - disable_int, enable_int): Removed. - (mips_get_sr): Rewritten as C macro. - (_CPU_Thread_Idle_body): Rewritten in C. - (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and - placed in libcpu. - (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved - to libcpu/mips/shared/interrupts. - (general): Cleaned up comment blocks and #if 0 areas. - * idtcpu.h: Made ifdef report an error. - * iregdef.h: Removed warning. - * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable - number defined by libcpu. - (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines - to access SR. - (_CPU_ISR_Set_level): Rewritten as macro for ISA I. - (_CPU_Context_Initialize): Honor ISR level in task initialization. - (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro. - -2000-12-06 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: When mips ISA level is 1, registers in the - context should be 32 not 64 bits. - -2000-11-30 Joel Sherrill <joel@OARcorp.com> - - * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to - correct name of _CPU_Context_switch_restore. Added dummy - version of exc_utlb_code() so applications would link. - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-10-24 Alan Cudmore <alanc@linuxstart.com> and - Joel Sherrill <joel@OARcorp.com> - - * This is a major reworking of the mips64orion port to use - gcc predefines as much as possible and a big push to multilib - the mips port. The mips64orion port was copied/renamed to mips - to be more like other GNU tools. Alan did most of the technical - work of determining how to map old macro names used by the mips64orion - port to standard compiler macro definitions. Joel did the merge - with CVS magic to keep individual file history and did the BSP - modifications. Details follow: - * Makefile.am: idtmon.h in mips64orion port not present. - * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added. - * cpu.c: Comments added. - * cpu_asm.S: Conditionals changed. MIPS ISA level 1 support added. - First attempt at exception/interrupt processing for ISA level 1 - and minus any use of IDT/MON added. - * idtcpu.h: Conditionals changed to use gcc predefines. - * iregdef.h: Ditto. - * cpu_asm.h: No real change. Merger required commit. - * rtems/Makefile.am: Ditto. - * rtems/score/Makefile.am: Ditto. - * rtems/score/cpu.h: Change MIPS64ORION to MIPS. - * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS. Convert - from using RTEMS_CPU_MODEL to gcc predefines to figre things out. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/mips/Makefile.am b/c/src/exec/score/cpu/mips/Makefile.am deleted file mode 100644 index 27cd509d53..0000000000 --- a/c/src/exec/score/cpu/mips/Makefile.am +++ /dev/null @@ -1,54 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h idtcpu.h iregdef.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/mips.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/mips/asm.h b/c/src/exec/score/cpu/mips/asm.h deleted file mode 100644 index 509678fad3..0000000000 --- a/c/src/exec/score/cpu/mips/asm.h +++ /dev/null @@ -1,159 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ -/* @(#)asm.h 03/15/96 1.1 */ - -#ifndef __NO_CPU_ASM_h -#define __NO_CPU_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/mips.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -/* - * Debugger macros for assembly language routines. Allows the - * programmer to set up the necessary stack frame info - * required by debuggers to do stack traces. - */ - -#ifndef XDS -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl name; \ - .ent name; \ -name:; \ - .frame frm_reg,offset,ret_reg -#define ENDFRAME(name) \ - .end name -#else -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl _##name;\ -_##name: -#define ENDFRAME(name) -#endif XDS - -/* - * Hardware Floating Point Registers - */ - -#define R_FP0 0 -#define R_FP1 1 -#define R_FP2 2 -#define R_FP3 3 -#define R_FP4 4 -#define R_FP5 5 -#define R_FP6 6 -#define R_FP7 7 -#define R_FP8 8 -#define R_FP9 9 -#define R_FP10 10 -#define R_FP11 11 -#define R_FP12 12 -#define R_FP13 13 -#define R_FP14 14 -#define R_FP15 15 -#define R_FP16 16 -#define R_FP17 17 -#define R_FP18 18 -#define R_FP19 19 -#define R_FP20 20 -#define R_FP21 21 -#define R_FP22 22 -#define R_FP23 23 -#define R_FP24 24 -#define R_FP25 25 -#define R_FP26 26 -#define R_FP27 27 -#define R_FP28 28 -#define R_FP29 29 -#define R_FP30 30 -#define R_FP31 31 - -#endif -/* end of include file */ - diff --git a/c/src/exec/score/cpu/mips/configure.ac b/c/src/exec/score/cpu/mips/configure.ac deleted file mode 100644 index 093249bc70..0000000000 --- a/c/src/exec/score/cpu/mips/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-mips],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/mips/cpu.c b/c/src/exec/score/cpu/mips/cpu.c deleted file mode 100644 index 7777680655..0000000000 --- a/c/src/exec/score/cpu/mips/cpu.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Mips CPU Dependent Source - * - * 2002: Greg Menke (gregory.menke@gsfc.nasa.gov) - * Overhauled interrupt level and interrupt enable/disable code - * to more exactly support MIPS. Our mods were for MIPS1 processors - * MIPS3 ports are affected, though apps written to the old behavior - * should still work OK. - * - * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and - * Joel Sherrill <joel@OARcorp.com>. - * - * These changes made the code conditional on standard cpp predefines, - * merged the mips1 and mips3 code sequences as much as possible, - * and moved some of the assembly code to C. Alan did much of the - * initial analysis and rework. Joel took over from there and - * wrote the JMR3904 BSP so this could be tested. Joel also - * added the new interrupt vectoring support in libcpu and - * tried to better support the various interrupt controllers. - * - * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the - * suitability of this software for any purpose. - * - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> - - - - -/* -** local dword used in cpu_asm to pass the exception stack frame to the -** context switch code. -*/ -unsigned __exceptionStackFrame = 0; - - - - - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * This routine returns the current interrupt level. - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned int sr; - - mips_get_sr(sr); - - //printf("current sr=%08X, ",sr); - -#if __mips == 3 -/* EXL bit and shift down hardware ints into bits 1 thru 6 */ - sr = ((sr & SR_EXL) >> 1) | ((sr & 0xfc00) >> 9); - -#elif __mips == 1 -/* IEC bit and shift down hardware ints into bits 1 thru 6 */ - sr = (sr & SR_IEC) | ((sr & 0xfc00) >> 9); - -#else -#error "CPU ISR level: unknown MIPS level for SR handling" -#endif - //printf("intlevel=%02X\n",sr); - return sr; -} - - -void _CPU_ISR_Set_level( unsigned32 new_level ) -{ - unsigned int sr, srbits; - - /* - ** mask off the int level bits only so we can - ** preserve software int settings and FP enable - ** for this thread. Note we don't force software ints - ** enabled when changing level, they were turned on - ** when this task was created, but may have been turned - ** off since, so we'll just leave them alone. - */ - - new_level &= 0xff; - - mips_get_sr(sr); - -#if __mips == 3 - mips_set_sr( (sr & ~SR_IE) ); /* first disable ie bit (recommended) */ - - srbits = sr & ~(0xfc00 | SR_EXL | SR_IE); - - sr = srbits | ((new_level==0)? (0xfc00 | SR_EXL | SR_IE): \ - (((new_level<<9) & 0xfc00) | \ - (new_level & 1)?(SR_EXL | SR_IE):0)); -/* - if ( (new_level & SR_EXL) == (sr & SR_EXL) ) - return; - - if ( (new_level & SR_EXL) == 0 ) { - sr &= ~SR_EXL; * clear the EXL bit * - mips_set_sr(sr); - } else { - - sr |= SR_EXL|SR_IE; * enable exception level * - mips_set_sr(sr); * first disable ie bit (recommended) * - } -*/ - -#elif __mips == 1 - mips_set_sr( (sr & ~SR_IEC) ); - srbits = sr & ~(0xfc00 | SR_IEC); - //printf("current sr=%08X, newlevel=%02X, srbits=%08X, ",sr,new_level,srbits); - sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \ - (new_level & SR_IEC))); - //printf("new sr=%08X\n",sr); -#else -#error "CPU ISR level: unknown MIPS level for SR handling" -#endif - mips_set_sr( sr ); -} - - - -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - * - * Because all interrupts are vectored through the same exception handler - * this is not necessary on thi sport. - */ -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -/* we don't support this yet */ -} - -/*PAGE - * - * _CPU_Internal_threads_Idle_thread_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -void _CPU_Thread_Idle_body( void ) -{ -#if __mips == 3 - for( ; ; ) - asm volatile("wait"); /* use wait to enter low power mode */ -#elif __mips == 1 - for( ; ; ) - ; -#else -#error "IDLE: __mips not set to 1 or 3" -#endif -} diff --git a/c/src/exec/score/cpu/mips/cpu_asm.S b/c/src/exec/score/cpu/mips/cpu_asm.S deleted file mode 100644 index 9614705e44..0000000000 --- a/c/src/exec/score/cpu/mips/cpu_asm.S +++ /dev/null @@ -1,1051 +0,0 @@ -/* - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * History: - * Baseline: no_cpu - * 1996: Ported to MIPS64ORION by Craig Lebakken <craigl@transition.com> - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * To anyone who acknowledges that the modifications to this file to - * port it to the MIPS64ORION are provided "AS IS" without any - * express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. Transition - * Networks makes no representations about the suitability - * of this software for any purpose. - * 2000: Reworked by Alan Cudmore <alanc@linuxstart.com> to become - * the baseline of the more general MIPS port. - * 2001: Joel Sherrill <joel@OARcorp.com> continued this rework, - * rewriting as much as possible in C and added the JMR3904 BSP - * so testing could be performed on a simulator. - * 2001: Greg Menke <gregory.menke@gsfc.nasa.gov>, bench tested ISR - * performance, tweaking this code and the isr vectoring routines - * to reduce overhead & latencies. Added optional - * instrumentation as well. - * 2002: Greg Menke <gregory.menke@gsfc.nasa.gov>, overhauled cpu_asm.S, - * cpu.c and cpu.h to manage FP vs int only tasks, interrupt levels - * and deferred FP contexts. - * 2002: Joel Sherrill <joel@OARcorp.com> enhanced the exception processing - * by increasing the amount of context saved/restored. - * - * COPYRIGHT (c) 1989-2002. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <asm.h> -#include "iregdef.h" -#include "idtcpu.h" - -#define ASSEMBLY_ONLY -#include <rtems/score/cpu.h> - - -/* enable debugging shadow writes to misc ram, this is a vestigal -* Mongoose-ism debug tool- but may be handy in the future so we -* left it in... -*/ - -/* #define INSTRUMENT_ISR_VECTORING */ -/* #define INSTRUMENT_EXECUTING_THREAD */ - - - -/* Ifdefs prevent the duplication of code for MIPS ISA Level 3 ( R4xxx ) - * and MIPS ISA Level 1 (R3xxx). - */ - -#if __mips == 3 -/* 64 bit register operations */ -#define NOP -#define ADD dadd -#define STREG sd -#define LDREG ld -#define MFCO dmfc0 -#define MTCO dmtc0 -#define ADDU addu -#define ADDIU addiu -#define R_SZ 8 -#define F_SZ 8 -#define SZ_INT 8 -#define SZ_INT_POW2 3 - -/* XXX if we don't always want 64 bit register ops, then another ifdef */ - -#elif __mips == 1 -/* 32 bit register operations*/ -#define NOP nop -#define ADD add -#define STREG sw -#define LDREG lw -#define MFCO mfc0 -#define MTCO mtc0 -#define ADDU add -#define ADDIU addi -#define R_SZ 4 -#define F_SZ 4 -#define SZ_INT 4 -#define SZ_INT_POW2 2 -#else -#error "mips assembly: what size registers do I deal with?" -#endif - - -#define ISR_VEC_SIZE 4 -#define EXCP_STACK_SIZE (NREGS*R_SZ) - - -#ifdef __GNUC__ -#define ASM_EXTERN(x,size) .extern x,size -#else -#define ASM_EXTERN(x,size) -#endif - -/* NOTE: these constants must match the Context_Control structure in cpu.h */ -#define S0_OFFSET 0 -#define S1_OFFSET 1 -#define S2_OFFSET 2 -#define S3_OFFSET 3 -#define S4_OFFSET 4 -#define S5_OFFSET 5 -#define S6_OFFSET 6 -#define S7_OFFSET 7 -#define SP_OFFSET 8 -#define FP_OFFSET 9 -#define RA_OFFSET 10 -#define C0_SR_OFFSET 11 -#define C0_EPC_OFFSET 12 - -/* NOTE: these constants must match the Context_Control_fp structure in cpu.h */ -#define FP0_OFFSET 0 -#define FP1_OFFSET 1 -#define FP2_OFFSET 2 -#define FP3_OFFSET 3 -#define FP4_OFFSET 4 -#define FP5_OFFSET 5 -#define FP6_OFFSET 6 -#define FP7_OFFSET 7 -#define FP8_OFFSET 8 -#define FP9_OFFSET 9 -#define FP10_OFFSET 10 -#define FP11_OFFSET 11 -#define FP12_OFFSET 12 -#define FP13_OFFSET 13 -#define FP14_OFFSET 14 -#define FP15_OFFSET 15 -#define FP16_OFFSET 16 -#define FP17_OFFSET 17 -#define FP18_OFFSET 18 -#define FP19_OFFSET 19 -#define FP20_OFFSET 20 -#define FP21_OFFSET 21 -#define FP22_OFFSET 22 -#define FP23_OFFSET 23 -#define FP24_OFFSET 24 -#define FP25_OFFSET 25 -#define FP26_OFFSET 26 -#define FP27_OFFSET 27 -#define FP28_OFFSET 28 -#define FP29_OFFSET 29 -#define FP30_OFFSET 30 -#define FP31_OFFSET 31 - - -ASM_EXTERN(__exceptionStackFrame, SZ_INT) - - - -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - -/* void _CPU_Context_save_fp( - * void **fp_context_ptr - * ); - */ - -#if ( CPU_HARDWARE_FP == TRUE ) -FRAME(_CPU_Context_save_fp,sp,0,ra) - .set noreorder - .set noat - - /* - ** Make sure the FPU is on before we save state. This code - ** is here because the FPU context switch might occur when an - ** integer task is switching out with a FP task switching in. - */ - MFC0 t0,C0_SR - li t2,SR_CU1 - move t1,t0 - or t0,t2 /* turn on the fpu */ -#if __mips == 3 - li t2,SR_EXL | SR_IE -#elif __mips == 1 - li t2,SR_IEC -#endif - not t2 - and t0,t2 /* turn off interrupts */ - MTC0 t0,C0_SR - - ld a1,(a0) - move t0,ra - jal _CPU_Context_save_fp_from_exception - NOP - - /* - ** Reassert the task's state because we've not saved it yet. - */ - MTC0 t1,C0_SR - j t0 - NOP - - .globl _CPU_Context_save_fp_from_exception -_CPU_Context_save_fp_from_exception: - swc1 $f0,FP0_OFFSET*F_SZ(a1) - swc1 $f1,FP1_OFFSET*F_SZ(a1) - swc1 $f2,FP2_OFFSET*F_SZ(a1) - swc1 $f3,FP3_OFFSET*F_SZ(a1) - swc1 $f4,FP4_OFFSET*F_SZ(a1) - swc1 $f5,FP5_OFFSET*F_SZ(a1) - swc1 $f6,FP6_OFFSET*F_SZ(a1) - swc1 $f7,FP7_OFFSET*F_SZ(a1) - swc1 $f8,FP8_OFFSET*F_SZ(a1) - swc1 $f9,FP9_OFFSET*F_SZ(a1) - swc1 $f10,FP10_OFFSET*F_SZ(a1) - swc1 $f11,FP11_OFFSET*F_SZ(a1) - swc1 $f12,FP12_OFFSET*F_SZ(a1) - swc1 $f13,FP13_OFFSET*F_SZ(a1) - swc1 $f14,FP14_OFFSET*F_SZ(a1) - swc1 $f15,FP15_OFFSET*F_SZ(a1) - swc1 $f16,FP16_OFFSET*F_SZ(a1) - swc1 $f17,FP17_OFFSET*F_SZ(a1) - swc1 $f18,FP18_OFFSET*F_SZ(a1) - swc1 $f19,FP19_OFFSET*F_SZ(a1) - swc1 $f20,FP20_OFFSET*F_SZ(a1) - swc1 $f21,FP21_OFFSET*F_SZ(a1) - swc1 $f22,FP22_OFFSET*F_SZ(a1) - swc1 $f23,FP23_OFFSET*F_SZ(a1) - swc1 $f24,FP24_OFFSET*F_SZ(a1) - swc1 $f25,FP25_OFFSET*F_SZ(a1) - swc1 $f26,FP26_OFFSET*F_SZ(a1) - swc1 $f27,FP27_OFFSET*F_SZ(a1) - swc1 $f28,FP28_OFFSET*F_SZ(a1) - swc1 $f29,FP29_OFFSET*F_SZ(a1) - swc1 $f30,FP30_OFFSET*F_SZ(a1) - swc1 $f31,FP31_OFFSET*F_SZ(a1) - j ra - NOP - .set at -ENDFRAME(_CPU_Context_save_fp) -#endif - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - -/* void _CPU_Context_restore_fp( - * void **fp_context_ptr - * ) - */ - -#if ( CPU_HARDWARE_FP == TRUE ) -FRAME(_CPU_Context_restore_fp,sp,0,ra) - .set noat - .set noreorder - - /* - ** Make sure the FPU is on before we retrieve state. This code - ** is here because the FPU context switch might occur when an - ** integer task is switching out with a FP task switching in. - */ - MFC0 t0,C0_SR - li t2,SR_CU1 - move t1,t0 - or t0,t2 /* turn on the fpu */ -#if __mips == 3 - li t2,SR_EXL | SR_IE -#elif __mips == 1 - li t2,SR_IEC -#endif - not t2 - and t0,t2 /* turn off interrupts */ - MTC0 t0,C0_SR - - ld a1,(a0) - move t0,ra - jal _CPU_Context_restore_fp_from_exception - NOP - - /* - ** Reassert the old task's state because we've not restored the - ** new one yet. - */ - MTC0 t1,C0_SR - j t0 - NOP - - .globl _CPU_Context_restore_fp_from_exception -_CPU_Context_restore_fp_from_exception: - lwc1 $f0,FP0_OFFSET*4(a1) - lwc1 $f1,FP1_OFFSET*4(a1) - lwc1 $f2,FP2_OFFSET*4(a1) - lwc1 $f3,FP3_OFFSET*4(a1) - lwc1 $f4,FP4_OFFSET*4(a1) - lwc1 $f5,FP5_OFFSET*4(a1) - lwc1 $f6,FP6_OFFSET*4(a1) - lwc1 $f7,FP7_OFFSET*4(a1) - lwc1 $f8,FP8_OFFSET*4(a1) - lwc1 $f9,FP9_OFFSET*4(a1) - lwc1 $f10,FP10_OFFSET*4(a1) - lwc1 $f11,FP11_OFFSET*4(a1) - lwc1 $f12,FP12_OFFSET*4(a1) - lwc1 $f13,FP13_OFFSET*4(a1) - lwc1 $f14,FP14_OFFSET*4(a1) - lwc1 $f15,FP15_OFFSET*4(a1) - lwc1 $f16,FP16_OFFSET*4(a1) - lwc1 $f17,FP17_OFFSET*4(a1) - lwc1 $f18,FP18_OFFSET*4(a1) - lwc1 $f19,FP19_OFFSET*4(a1) - lwc1 $f20,FP20_OFFSET*4(a1) - lwc1 $f21,FP21_OFFSET*4(a1) - lwc1 $f22,FP22_OFFSET*4(a1) - lwc1 $f23,FP23_OFFSET*4(a1) - lwc1 $f24,FP24_OFFSET*4(a1) - lwc1 $f25,FP25_OFFSET*4(a1) - lwc1 $f26,FP26_OFFSET*4(a1) - lwc1 $f27,FP27_OFFSET*4(a1) - lwc1 $f28,FP28_OFFSET*4(a1) - lwc1 $f29,FP29_OFFSET*4(a1) - lwc1 $f30,FP30_OFFSET*4(a1) - lwc1 $f31,FP31_OFFSET*4(a1) - j ra - NOP - .set at -ENDFRAME(_CPU_Context_restore_fp) -#endif - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - */ - -/* void _CPU_Context_switch( - * Context_Control *run, - * Context_Control *heir - * ) - */ - -FRAME(_CPU_Context_switch,sp,0,ra) - .set noreorder - - MFC0 t0,C0_SR -#if __mips == 3 - li t1,SR_EXL | SR_IE -#elif __mips == 1 - li t1,SR_IEC -#endif - STREG t0,C0_SR_OFFSET*R_SZ(a0) /* save the task's SR */ - not t1 - and t0,t1 /* mask off interrupts while we context switch */ - MTC0 t0,C0_SR - NOP - - STREG ra,RA_OFFSET*R_SZ(a0) /* save current context */ - STREG sp,SP_OFFSET*R_SZ(a0) - STREG fp,FP_OFFSET*R_SZ(a0) - STREG s0,S0_OFFSET*R_SZ(a0) - STREG s1,S1_OFFSET*R_SZ(a0) - STREG s2,S2_OFFSET*R_SZ(a0) - STREG s3,S3_OFFSET*R_SZ(a0) - STREG s4,S4_OFFSET*R_SZ(a0) - STREG s5,S5_OFFSET*R_SZ(a0) - STREG s6,S6_OFFSET*R_SZ(a0) - STREG s7,S7_OFFSET*R_SZ(a0) - - - /* - ** this code grabs the userspace EPC if we're dispatching from - ** an interrupt frame or fakes an address as the EPC if we're - ** not. This is for the gdbstub's benefit so it can know - ** where each thread is running. - ** - ** Its value is only set when calling threadDispatch from - ** the interrupt handler and is cleared immediately when this - ** routine gets it. - */ - - la t0,__exceptionStackFrame /* see if we're coming in from an exception */ - LDREG t1, (t0) - NOP - beqz t1,1f - - STREG zero, (t0) /* and clear it */ - NOP - LDREG t0,R_EPC*R_SZ(t1) /* get the userspace EPC from the frame */ - b 2f - -1: la t0,_Thread_Dispatch /* if ==0, we're switched out */ - -2: STREG t0,C0_EPC_OFFSET*R_SZ(a0) - - -_CPU_Context_switch_restore: - LDREG ra,RA_OFFSET*R_SZ(a1) /* restore context */ - LDREG sp,SP_OFFSET*R_SZ(a1) - LDREG fp,FP_OFFSET*R_SZ(a1) - LDREG s0,S0_OFFSET*R_SZ(a1) - LDREG s1,S1_OFFSET*R_SZ(a1) - LDREG s2,S2_OFFSET*R_SZ(a1) - LDREG s3,S3_OFFSET*R_SZ(a1) - LDREG s4,S4_OFFSET*R_SZ(a1) - LDREG s5,S5_OFFSET*R_SZ(a1) - LDREG s6,S6_OFFSET*R_SZ(a1) - LDREG s7,S7_OFFSET*R_SZ(a1) - - LDREG t0, C0_SR_OFFSET*R_SZ(a1) - -// NOP -//#if __mips == 3 -// andi t0,SR_EXL -// bnez t0,_CPU_Context_1 /* set exception level from restore context */ -// li t0,~SR_EXL -// MFC0 t1,C0_SR -// NOP -// and t1,t0 -// MTC0 t1,C0_SR -// -//#elif __mips == 1 -// -// andi t0,(SR_INTERRUPT_ENABLE_BITS) /* we know 0 disabled */ -// beq t0,$0,_CPU_Context_1 /* set level from restore context */ -// MFC0 t0,C0_SR -// NOP -// or t0,(SR_INTERRUPT_ENABLE_BITS) /* new_sr = old sr with enabled */ -// MTC0 t0,C0_SR /* set with enabled */ -// NOP - - -/* -** Incorporate the new task's FP coprocessor state and interrupt mask/enable -** into the status register. We jump thru the requisite hoops to ensure we -** maintain all other SR bits as global values. -** -** Get the thread's FPU enable, int mask & int enable bits. Although we keep the -** software int enables on a per-task basis, the rtems_task_create -** Interrupt Level & int level manipulation functions cannot enable/disable them, -** so they are automatically enabled for all tasks. To turn them off, a thread -** must itself manipulate the SR register. -** -** Although something of a hack on this processor, we treat the SR register -** int enables as the RTEMS interrupt level. We use the int level -** value as a bitmask, not as any sort of greater than/less than metric. -** Manipulation of a task's interrupt level directly corresponds to manipulation -** of that task's SR bits, as seen in cpu.c -** -** Note, interrupts are disabled before context is saved, though the thread's -** interrupt enable state is recorded. The task swapping in will apply its -** specific SR bits, including interrupt enable. If further task-specific -** SR bits are arranged, it is this code, the cpu.c interrupt level stuff and -** cpu.h task initialization code that will be affected. -*/ - - li t2,SR_CU1 - or t2,SR_IMASK - - /* int enable bits */ -#if __mips == 3 - or t2,SR_EXL + SR_IE -#elif __mips == 1 - or t2,SR_IEC + SR_IEP + SR_IEO /* save current & previous int enable */ -#endif - and t0,t2 /* keep only the per-task bits */ - - MFC0 t1,C0_SR /* grab the current SR */ - not t2 - and t1,t2 /* mask off the old task's bits */ - or t1,t0 /* or in the new task's bits */ - MTC0 t1,C0_SR /* and load the new SR */ - NOP - -/* _CPU_Context_1: */ - j ra - NOP -ENDFRAME(_CPU_Context_switch) - - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * void _CPU_Context_restore( - * Context_Control *new_context - * ); - */ - -FRAME(_CPU_Context_restore,sp,0,ra) - .set noreorder - move a1,a0 - j _CPU_Context_switch_restore - NOP - -ENDFRAME(_CPU_Context_restore) - - -ASM_EXTERN(_ISR_Nest_level, SZ_INT) -ASM_EXTERN(_Thread_Dispatch_disable_level,SZ_INT) -ASM_EXTERN(_Context_Switch_necessary,SZ_INT) -ASM_EXTERN(_ISR_Signals_to_thread_executing,SZ_INT) -ASM_EXTERN(_Thread_Executing,SZ_INT) - -.extern _Thread_Dispatch -.extern _ISR_Vector_table - - - - - -/* void _DBG_Handler() - * - * This routine services the (at least) MIPS1 debug vector, - * only used the the hardware debugging features. This code, - * while optional, is best located here because its intrinsically - * associated with exceptions in general & thus tied pretty - * closely to _ISR_Handler. - * - */ - - -FRAME(_DBG_Handler,sp,0,ra) - .set noreorder - la k0,_ISR_Handler - j k0 - NOP - .set reorder -ENDFRAME(_DBG_Handler) - - - - - -/* void __ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * void _ISR_Handler() - * - * - * This discussion ignores a lot of the ugly details in a real - * implementation such as saving enough registers/state to be - * able to do something real. Keep in mind that the goal is - * to invoke a user's ISR handler which is written in C and - * uses a certain set of registers. - * - * Also note that the exact order is to a large extent flexible. - * Hardware will dictate a sequence for a certain subset of - * _ISR_Handler while requirements for setting - * - * At entry to "common" _ISR_Handler, the vector number must be - * available. On some CPUs the hardware puts either the vector - * number or the offset into the vector table for this ISR in a - * known place. If the hardware does not give us this information, - * then the assembly portion of RTEMS for this port will contain - * a set of distinct interrupt entry points which somehow place - * the vector number in a known place (which is safe if another - * interrupt nests this one) and branches to _ISR_Handler. - * - */ - -FRAME(_ISR_Handler,sp,0,ra) - .set noreorder - - /* Q: _ISR_Handler, not using IDT/SIM ...save extra regs? */ - - /* wastes a lot of stack space for context?? */ - ADDIU sp,sp,-EXCP_STACK_SIZE - - STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */ - STREG v0, R_V0*R_SZ(sp) - STREG v1, R_V1*R_SZ(sp) - STREG a0, R_A0*R_SZ(sp) - STREG a1, R_A1*R_SZ(sp) - STREG a2, R_A2*R_SZ(sp) - STREG a3, R_A3*R_SZ(sp) - STREG t0, R_T0*R_SZ(sp) - STREG t1, R_T1*R_SZ(sp) - STREG t2, R_T2*R_SZ(sp) - STREG t3, R_T3*R_SZ(sp) - STREG t4, R_T4*R_SZ(sp) - STREG t5, R_T5*R_SZ(sp) - STREG t6, R_T6*R_SZ(sp) - STREG t7, R_T7*R_SZ(sp) - mflo t0 - STREG t8, R_T8*R_SZ(sp) - STREG t0, R_MDLO*R_SZ(sp) - STREG t9, R_T9*R_SZ(sp) - mfhi t0 - STREG gp, R_GP*R_SZ(sp) - STREG t0, R_MDHI*R_SZ(sp) - STREG fp, R_FP*R_SZ(sp) - - .set noat - STREG AT, R_AT*R_SZ(sp) - .set at - - MFC0 t0,C0_SR - MFC0 t1,C0_EPC - STREG t0,R_SR*R_SZ(sp) - STREG t1,R_EPC*R_SZ(sp) - - -#ifdef INSTRUMENT_EXECUTING_THREAD - lw t2, _Thread_Executing - NOP - sw t2, 0x8001FFF0 -#endif - - /* determine if an interrupt generated this exception */ - - MFC0 t0,C0_CAUSE - NOP - - and t1,t0,CAUSE_EXCMASK - beq t1, 0, _ISR_Handler_1 - -_ISR_Handler_Exception: - - /* - sw t0,0x8001FF00 - sw t1,0x8001FF04 - */ - - /* If we return from the exception, it is assumed nothing - * bad is going on and we can continue to run normally. - * But we want to save the entire CPU context so exception - * handlers can look at it and change it. - * - * NOTE: This is the path the debugger stub will take. - */ - - /* already got t0 = cause in the interrupt test above */ - STREG t0,R_CAUSE*R_SZ(sp) - - STREG sp, R_SP*R_SZ(sp) - - STREG s0,R_S0*R_SZ(sp) /* save s0 - s7 */ - STREG s1,R_S1*R_SZ(sp) - STREG s2,R_S2*R_SZ(sp) - STREG s3,R_S3*R_SZ(sp) - STREG s4,R_S4*R_SZ(sp) - STREG s5,R_S5*R_SZ(sp) - STREG s6,R_S6*R_SZ(sp) - STREG s7,R_S7*R_SZ(sp) - - /* CP0 special registers */ - -#if __mips == 1 - MFC0 t0,C0_TAR -#endif - MFC0 t1,C0_BADVADDR - -#if __mips == 1 - STREG t0,R_TAR*R_SZ(sp) -#else - NOP -#endif - STREG t1,R_BADVADDR*R_SZ(sp) - -#if ( CPU_HARDWARE_FP == TRUE ) - MFC0 t0,C0_SR /* FPU is enabled, save state */ - NOP - srl t0,t0,16 - andi t0,t0,(SR_CU1 >> 16) - beqz t0, 1f - NOP - - la a1,R_F0*R_SZ(sp) - jal _CPU_Context_save_fp_from_exception - NOP - MFC1 t0,C1_REVISION - MFC1 t1,C1_STATUS - STREG t0,R_FEIR*R_SZ(sp) - STREG t1,R_FCSR*R_SZ(sp) - -1: -#endif - - move a0,sp - jal mips_vector_exceptions - NOP - - - /* - ** note, if the exception vector returns, rely on it to have - ** adjusted EPC so we will return to some correct address. If - ** this is not done, we might get stuck in an infinite loop because - ** we'll return to the instruction where the exception occured and - ** it could throw again. - ** - ** It is expected the only code using the exception processing is - ** either the gdb stub or some user code which is either going to - ** panic or do something useful. - */ - - -/* ********************************************************************* - * compute the address of the instruction we'll return to * - - LDREG t1, R_CAUSE*R_SZ(sp) - LDREG t0, R_EPC*R_SZ(sp) - - * first see if the exception happened in the delay slot * - li t3,CAUSE_BD - AND t4,t1,t3 - beqz t4,excnodelay - NOP - - * it did, now see if the branch occured or not * - li t3,CAUSE_BT - AND t4,t1,t3 - beqz t4,excnobranch - NOP - - * branch was taken, we resume at the branch target * - LDREG t0, R_TAR*R_SZ(sp) - j excreturn - NOP - -excnobranch: - ADDU t0,R_SZ - -excnodelay: - ADDU t0,R_SZ - -excreturn: - STREG t0, R_EPC*R_SZ(sp) - NOP -********************************************************************* */ - - - /* if we're returning into mips_break, move to the next instruction */ - - LDREG t0,R_EPC*R_SZ(sp) - la t1,mips_break - xor t2,t0,t1 - bnez t2,3f - - addu t0,R_SZ - STREG t0,R_EPC*R_SZ(sp) - NOP -3: - - - - -#if ( CPU_HARDWARE_FP == TRUE ) - MFC0 t0,C0_SR /* FPU is enabled, restore state */ - NOP - srl t0,t0,16 - andi t0,t0,(SR_CU1 >> 16) - beqz t0, 2f - NOP - - la a1,R_F0*R_SZ(sp) - jal _CPU_Context_restore_fp_from_exception - NOP - LDREG t0,R_FEIR*R_SZ(sp) - LDREG t1,R_FCSR*R_SZ(sp) - MTC1 t0,C1_REVISION - MTC1 t1,C1_STATUS -2: -#endif - LDREG s0,R_S0*R_SZ(sp) /* restore s0 - s7 */ - LDREG s1,R_S1*R_SZ(sp) - LDREG s2,R_S2*R_SZ(sp) - LDREG s3,R_S3*R_SZ(sp) - LDREG s4,R_S4*R_SZ(sp) - LDREG s5,R_S5*R_SZ(sp) - LDREG s6,R_S6*R_SZ(sp) - LDREG s7,R_S7*R_SZ(sp) - - /* do NOT restore the sp as this could mess up the world */ - /* do NOT restore the cause as this could mess up the world */ - - j _ISR_Handler_exit - NOP - -_ISR_Handler_1: - - MFC0 t1,C0_SR - and t0,CAUSE_IPMASK - and t0,t1 - - /* external interrupt not enabled, ignore */ - /* but if it's not an exception or an interrupt, */ - /* Then where did it come from??? */ - - beq t0,zero,_ISR_Handler_exit - - - - - /* - * save some or all context on stack - * may need to save some special interrupt information for exit - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * if ( _ISR_Nest_level == 0 ) - * switch to software interrupt stack - * #endif - */ - - /* - * _ISR_Nest_level++; - */ - LDREG t0,_ISR_Nest_level - NOP - ADD t0,t0,1 - STREG t0,_ISR_Nest_level - /* - * _Thread_Dispatch_disable_level++; - */ - LDREG t1,_Thread_Dispatch_disable_level - NOP - ADD t1,t1,1 - STREG t1,_Thread_Dispatch_disable_level - - /* - * Call the CPU model or BSP specific routine to decode the - * interrupt source and actually vector to device ISR handlers. - */ - -#ifdef INSTRUMENT_ISR_VECTORING - NOP - li t1, 1 - sw t1, 0x8001e000 -#endif - - move a0,sp - jal mips_vector_isr_handlers - NOP - -#ifdef INSTRUMENT_ISR_VECTORING - li t1, 0 - sw t1, 0x8001e000 - NOP -#endif - - /* - * --_ISR_Nest_level; - */ - LDREG t2,_ISR_Nest_level - NOP - ADD t2,t2,-1 - STREG t2,_ISR_Nest_level - /* - * --_Thread_Dispatch_disable_level; - */ - LDREG t1,_Thread_Dispatch_disable_level - NOP - ADD t1,t1,-1 - STREG t1,_Thread_Dispatch_disable_level - /* - * if ( _Thread_Dispatch_disable_level || _ISR_Nest_level ) - * goto the label "exit interrupt (simple case)" - */ - or t0,t2,t1 - bne t0,zero,_ISR_Handler_exit - NOP - - - - - /* - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * restore stack - * #endif - * - * if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing ) - * goto the label "exit interrupt (simple case)" - */ - LDREG t0,_Context_Switch_necessary - LDREG t1,_ISR_Signals_to_thread_executing - NOP - or t0,t0,t1 - beq t0,zero,_ISR_Handler_exit - NOP - - - -#ifdef INSTRUMENT_EXECUTING_THREAD - lw t0,_Thread_Executing - NOP - sw t0,0x8001FFF4 -#endif - -/* -** Turn on interrupts before entering Thread_Dispatch which -** will run for a while, thus allowing new interrupts to -** be serviced. Observe the Thread_Dispatch_disable_level interlock -** that prevents recursive entry into Thread_Dispatch. -*/ - - MFC0 t0, C0_SR -#if __mips == 3 - li t1,SR_EXL | SR_IE -#elif __mips == 1 - li t1,SR_IEC -#endif - or t0, t1 - MTC0 t0, C0_SR - NOP - - /* save off our stack frame so the context switcher can get to it */ - la t0,__exceptionStackFrame - STREG sp,(t0) - - jal _Thread_Dispatch - NOP - - /* and make sure its clear in case we didn't dispatch. if we did, its - ** already cleared */ - la t0,__exceptionStackFrame - STREG zero,(t0) - NOP - -/* -** turn interrupts back off while we restore context so -** a badly timed interrupt won't accidentally mess things up -*/ - MFC0 t0, C0_SR -#if __mips == 3 - li t1,SR_EXL | SR_IE -#elif __mips == 1 - /* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */ - li t1,SR_IEC | SR_KUP | SR_KUC -#endif - not t1 - and t0, t1 - -#if __mips == 1 - /* make sure previous int enable is on because we're returning from an interrupt - ** which means interrupts have to be enabled - */ - li t1,SR_IEP - or t0,t1 -#endif - MTC0 t0, C0_SR - NOP - -#ifdef INSTRUMENT_EXECUTING_THREAD - lw t0,_Thread_Executing - NOP - sw t0,0x8001FFF8 -#endif - - - /* - * prepare to get out of interrupt - * return from interrupt (maybe to _ISR_Dispatch) - * - * LABEL "exit interrupt (simple case):" - * prepare to get out of interrupt - * return from interrupt - */ - -_ISR_Handler_exit: -/* -** Skip the SR restore because its a global register. _CPU_Context_switch_restore -** adjusts it according to each task's configuration. If we didn't dispatch, the -** SR value isn't changed, so all we need to do is return. -** -*/ - /* restore context from stack */ - -#ifdef INSTRUMENT_EXECUTING_THREAD - lw t0,_Thread_Executing - NOP - sw t0, 0x8001FFFC -#endif - - LDREG t8, R_MDLO*R_SZ(sp) - LDREG t0, R_T0*R_SZ(sp) - mtlo t8 - LDREG t8, R_MDHI*R_SZ(sp) - LDREG t1, R_T1*R_SZ(sp) - mthi t8 - LDREG t2, R_T2*R_SZ(sp) - LDREG t3, R_T3*R_SZ(sp) - LDREG t4, R_T4*R_SZ(sp) - LDREG t5, R_T5*R_SZ(sp) - LDREG t6, R_T6*R_SZ(sp) - LDREG t7, R_T7*R_SZ(sp) - LDREG t8, R_T8*R_SZ(sp) - LDREG t9, R_T9*R_SZ(sp) - LDREG gp, R_GP*R_SZ(sp) - LDREG fp, R_FP*R_SZ(sp) - LDREG ra, R_RA*R_SZ(sp) - LDREG a0, R_A0*R_SZ(sp) - LDREG a1, R_A1*R_SZ(sp) - LDREG a2, R_A2*R_SZ(sp) - LDREG a3, R_A3*R_SZ(sp) - LDREG v1, R_V1*R_SZ(sp) - LDREG v0, R_V0*R_SZ(sp) - - LDREG k1, R_EPC*R_SZ(sp) - - .set noat - LDREG AT, R_AT*R_SZ(sp) - .set at - - ADDIU sp,sp,EXCP_STACK_SIZE - j k1 - rfe - NOP - - .set reorder -ENDFRAME(_ISR_Handler) - - - - -FRAME(mips_break,sp,0,ra) - .set noreorder - break 0x0 /* this statement must be first in this function, assumed so by mips-stub.c */ - NOP - j ra - NOP - .set reorder -ENDFRAME(mips_break) - diff --git a/c/src/exec/score/cpu/mips/idtcpu.h b/c/src/exec/score/cpu/mips/idtcpu.h deleted file mode 100644 index 3ff31aa8c8..0000000000 --- a/c/src/exec/score/cpu/mips/idtcpu.h +++ /dev/null @@ -1,478 +0,0 @@ -/* - -Based upon IDT provided code with the following release: - -This source code has been made available to you by IDT on an AS-IS -basis. Anyone receiving this source is licensed under IDT copyrights -to use it in any way he or she deems fit, including copying it, -modifying it, compiling it, and redistributing it either with or -without modifications. No license under IDT patents or patent -applications is to be implied by the copyright license. - -Any user of this software should understand that IDT cannot provide -technical support for this software and will not be responsible for -any consequences resulting from the use of this software. - -Any person who transfers this source code or any derivative work must -include the IDT copyright notice, this paragraph, and the preceeding -two paragraphs in the transferred software. - -COPYRIGHT IDT CORPORATION 1996 -LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - - $Id$ -*/ - -/* -** idtcpu.h -- cpu related defines -*/ - -#ifndef _IDTCPU_H__ -#define _IDTCPU_H__ - -/* - * 950313: Ketan added Register definition for XContext reg. - * added define for WAIT instruction. - * 950421: Ketan added Register definition for Config reg (R3081) - */ - -/* -** memory configuration and mapping -*/ -#define K0BASE 0x80000000 -#define K0SIZE 0x20000000 -#define K1BASE 0xa0000000 -#define K1SIZE 0x20000000 -#define K2BASE 0xc0000000 -#define K2SIZE 0x20000000 -#if __mips == 3 -#define KSBASE 0xe0000000 -#define KSSIZE 0x20000000 -#endif - -#define KUBASE 0 -#define KUSIZE 0x80000000 - -/* -** Exception Vectors -*/ -#if __mips == 1 -#define UT_VEC K0BASE /* utlbmiss vector */ -#define DB_VEC (K0BASE+0x40) /* debug vector */ -#define E_VEC (K0BASE+0x80) /* exception vector */ -#elif __mips == 3 -#define T_VEC (K0BASE+0x000) /* tlbmiss vector */ -#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ -#define C_VEC (K0BASE+0x100) /* cache error vector */ -#define E_VEC (K0BASE+0x180) /* exception vector */ -#else -#error "EXCEPTION VECTORS: unknown ISA level" -#endif -#define R_VEC (K1BASE+0x1fc00000) /* reset vector */ - -/* -** Address conversion macros -*/ -#ifdef CLANGUAGE -#define CAST(as) (as) -#else -#define CAST(as) -#endif -#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */ -#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */ -#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */ -#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */ -#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to kseg0 */ -#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to kseg1 */ - -/* -** Cache size constants -*/ -#define MINCACHE 0x200 /* 512 For 3041. */ -#define MAXCACHE 0x40000 /* 256*1024 256k */ - -#if __mips == 3 -/* R4000 configuration register definitions */ -#define CFG_CM 0x80000000 /* Master-Checker mode */ -#define CFG_ECMASK 0x70000000 /* System Clock Ratio */ -#define CFG_ECBY2 0x00000000 /* divide by 2 */ -#define CFG_ECBY3 0x10000000 /* divide by 3 */ -#define CFG_ECBY4 0x20000000 /* divide by 4 */ -#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */ -#define CFG_EPD 0x00000000 /* D */ -#define CFG_EPDDX 0x01000000 /* DDX */ -#define CFG_EPDDXX 0x02000000 /* DDXX */ -#define CFG_EPDXDX 0x03000000 /* DXDX */ -#define CFG_EPDDXXX 0x04000000 /* DDXXX */ -#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */ -#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */ -#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */ -#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */ -#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */ -#define CFG_SBSHIFT 22 -#define CFG_SB4 0x00000000 /* 4 words */ -#define CFG_SB8 0x00400000 /* 8 words */ -#define CFG_SB16 0x00800000 /* 16 words */ -#define CFG_SB32 0x00c00000 /* 32 words */ -#define CFG_SS 0x00200000 /* Split secondary cache */ -#define CFG_SW 0x00100000 /* Secondary cache port width */ -#define CFG_EWMASK 0x000c0000 /* System port width */ -#define CFG_EWSHIFT 18 -#define CFG_EW64 0x00000000 /* 64 bit */ -#define CFG_EW32 0x00010000 /* 32 bit */ -#define CFG_SC 0x00020000 /* Secondary cache absent */ -#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */ -#define CFG_BE 0x00008000 /* Big Endian */ -#define CFG_EM 0x00004000 /* ECC mode enable */ -#define CFG_EB 0x00002000 /* Block ordering */ -#define CFG_ICMASK 0x00000e00 /* Instruction cache size */ -#define CFG_ICSHIFT 9 -#define CFG_DCMASK 0x000001c0 /* Data cache size */ -#define CFG_DCSHIFT 6 -#define CFG_IB 0x00000020 /* Instruction cache block size */ -#define CFG_DB 0x00000010 /* Data cache block size */ -#define CFG_CU 0x00000008 /* Update on Store Conditional */ -#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */ - -/* - * R4000 primary cache mode - */ -#define CFG_C_UNCACHED 2 -#define CFG_C_NONCOHERENT 3 -#define CFG_C_COHERENTXCL 4 -#define CFG_C_COHERENTXCLW 5 -#define CFG_C_COHERENTUPD 6 - -/* - * R4000 cache operations (should be in assembler...?) - */ -#define Index_Invalidate_I 0x0 /* 0 0 */ -#define Index_Writeback_Inv_D 0x1 /* 0 1 */ -#define Index_Invalidate_SI 0x2 /* 0 2 */ -#define Index_Writeback_Inv_SD 0x3 /* 0 3 */ -#define Index_Load_Tag_I 0x4 /* 1 0 */ -#define Index_Load_Tag_D 0x5 /* 1 1 */ -#define Index_Load_Tag_SI 0x6 /* 1 2 */ -#define Index_Load_Tag_SD 0x7 /* 1 3 */ -#define Index_Store_Tag_I 0x8 /* 2 0 */ -#define Index_Store_Tag_D 0x9 /* 2 1 */ -#define Index_Store_Tag_SI 0xA /* 2 2 */ -#define Index_Store_Tag_SD 0xB /* 2 3 */ -#define Create_Dirty_Exc_D 0xD /* 3 1 */ -#define Create_Dirty_Exc_SD 0xF /* 3 3 */ -#define Hit_Invalidate_I 0x10 /* 4 0 */ -#define Hit_Invalidate_D 0x11 /* 4 1 */ -#define Hit_Invalidate_SI 0x12 /* 4 2 */ -#define Hit_Invalidate_SD 0x13 /* 4 3 */ -#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ -#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ -#define Fill_I 0x14 /* 5 0 */ -#define Hit_Writeback_D 0x19 /* 6 1 */ -#define Hit_Writeback_SD 0x1B /* 6 3 */ -#define Hit_Writeback_I 0x18 /* 6 0 */ -#define Hit_Set_Virtual_SI 0x1E /* 7 2 */ -#define Hit_Set_Virtual_SD 0x1F /* 7 3 */ - -#ifndef WAIT -#define WAIT .word 0x42000020 -#endif WAIT - -/* Disabled by joel -- horrible overload of common word. -#ifndef wait -#define wait .word 0x42000020 -#endif wait -*/ - -#endif - -/* -** TLB resource defines -*/ -#if __mips == 1 -#define N_TLB_ENTRIES 64 -#define TLB_PGSIZE 0x1000 -#define RANDBASE 8 -#define TLBLO_PFNMASK 0xfffff000 -#define TLBLO_PFNSHIFT 12 -#define TLBLO_N 0x800 /* non-cacheable */ -#define TLBLO_D 0x400 /* writeable */ -#define TLBLO_V 0x200 /* valid bit */ -#define TLBLO_G 0x100 /* global access bit */ - -#define TLBHI_VPNMASK 0xfffff000 -#define TLBHI_VPNSHIFT 12 -#define TLBHI_PIDMASK 0xfc0 -#define TLBHI_PIDSHIFT 6 -#define TLBHI_NPID 64 - -#define TLBINX_PROBE 0x80000000 -#define TLBINX_INXMASK 0x00003f00 -#define TLBINX_INXSHIFT 8 - -#define TLBRAND_RANDMASK 0x00003f00 -#define TLBRAND_RANDSHIFT 8 - -#define TLBCTXT_BASEMASK 0xffe00000 -#define TLBCTXT_BASESHIFT 21 - -#define TLBCTXT_VPNMASK 0x001ffffc -#define TLBCTXT_VPNSHIFT 2 -#endif -#if __mips == 3 -#define N_TLB_ENTRIES 48 - -#define TLBHI_VPN2MASK 0xffffe000 -#define TLBHI_PIDMASK 0x000000ff -#define TLBHI_NPID 256 - -#define TLBLO_PFNMASK 0x3fffffc0 -#define TLBLO_PFNSHIFT 6 -#define TLBLO_D 0x00000004 /* writeable */ -#define TLBLO_V 0x00000002 /* valid bit */ -#define TLBLO_G 0x00000001 /* global access bit */ -#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */ -#define TLBLO_CSHIFT 3 - -#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT) -#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT) -#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT) -#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT) -#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT) - -#define TLBINX_PROBE 0x80000000 -#define TLBINX_INXMASK 0x0000003f - -#define TLBRAND_RANDMASK 0x0000003f - -#define TLBCTXT_BASEMASK 0xff800000 -#define TLBCTXT_BASESHIFT 23 - -#define TLBCTXT_VPN2MASK 0x007ffff0 -#define TLBCTXT_VPN2SHIFT 4 - -#define TLBPGMASK_MASK 0x01ffe000 -#endif - -#if __mips == 1 - - -/* definitions for Debug and Cache Invalidate control (DCIC) register bits */ -#define DCIC_TR 0x80000000 /* Trap enable */ -#define DCIC_UD 0x40000000 /* User debug enable */ -#define DCIC_KD 0x20000000 /* Kernel debug enable */ -#define DCIC_TE 0x10000000 /* Trace enable */ -#define DCIC_DW 0x08000000 /* Enable data breakpoints on write */ -#define DCIC_DR 0x04000000 /* Enable data breakpoints on read */ -#define DCIC_DAE 0x02000000 /* Enable data addresss breakpoints */ -#define DCIC_PCE 0x01000000 /* Enable instruction breakpoints */ -#define DCIC_DE 0x00800000 /* Debug enable */ -#define DCIC_DL 0x00008000 /* Data cache line invalidate */ -#define DCIC_IL 0x00004000 /* Instruction cache line invalidate */ -#define DCIC_D 0x00002000 /* Data cache invalidate enable */ -#define DCIC_I 0x00001000 /* Instr. cache invalidate enable */ -#define DCIC_T 0x00000020 /* Trace, set by CPU */ -#define DCIC_W 0x00000010 /* Write reference, set by CPU */ -#define DCIC_R 0x00000008 /* Read reference, set by CPU */ -#define DCIC_DA 0x00000004 /* Data address, set by CPU */ -#define DCIC_PC 0x00000002 /* Program counter, set by CPU */ -#define DCIC_DB 0x00000001 /* Debug, set by CPU */ - - - - -#define SR_CUMASK 0xf0000000 /* coproc usable bits */ -#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ -#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ -#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ -#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ - -#define SR_BEV 0x00400000 /* use boot exception vectors */ - -/* Cache control bits */ -#define SR_TS 0x00200000 /* TLB shutdown */ -#define SR_PE 0x00100000 /* cache parity error */ -#define SR_CM 0x00080000 /* cache miss */ -#define SR_PZ 0x00040000 /* cache parity zero */ -#define SR_SWC 0x00020000 /* swap cache */ -#define SR_ISC 0x00010000 /* Isolate data cache */ - -/* -** status register interrupt masks and bits -*/ - -#define SR_IMASK 0x0000ff00 /* Interrupt mask */ -#define SR_IMASK8 0x00000000 /* mask level 8 */ -#define SR_IMASK7 0x00008000 /* mask level 7 */ -#define SR_IMASK6 0x0000c000 /* mask level 6 */ -#define SR_IMASK5 0x0000e000 /* mask level 5 */ -#define SR_IMASK4 0x0000f000 /* mask level 4 */ -#define SR_IMASK3 0x0000f800 /* mask level 3 */ -#define SR_IMASK2 0x0000fc00 /* mask level 2 */ -#define SR_IMASK1 0x0000fe00 /* mask level 1 */ -#define SR_IMASK0 0x0000ff00 /* mask level 0 */ - -#define SR_IMASKSHIFT 8 - -#define SR_IBIT8 0x00008000 /* bit level 8 */ -#define SR_IBIT7 0x00004000 /* bit level 7 */ -#define SR_IBIT6 0x00002000 /* bit level 6 */ -#define SR_IBIT5 0x00001000 /* bit level 5 */ -#define SR_IBIT4 0x00000800 /* bit level 4 */ -#define SR_IBIT3 0x00000400 /* bit level 3 */ -#define SR_IBIT2 0x00000200 /* bit level 2 */ -#define SR_IBIT1 0x00000100 /* bit level 1 */ - -#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */ -#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */ -#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */ -#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */ -#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */ -#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ -#endif - -#if __mips == 3 -#define SR_CUMASK 0xf0000000 /* coproc usable bits */ -#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ -#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ -#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ -#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ - -#define SR_RP 0x08000000 /* Reduced power operation */ -#define SR_FR 0x04000000 /* Additional floating point registers */ -#define SR_RE 0x02000000 /* Reverse endian in user mode */ - -#define SR_BEV 0x00400000 /* Use boot exception vectors */ -#define SR_TS 0x00200000 /* TLB shutdown */ -#define SR_SR 0x00100000 /* Soft reset */ -#define SR_CH 0x00040000 /* Cache hit */ -#define SR_CE 0x00020000 /* Use cache ECC */ -#define SR_DE 0x00010000 /* Disable cache exceptions */ - -/* -** status register interrupt masks and bits -*/ - -#define SR_IMASK 0x0000ff00 /* Interrupt mask */ -#define SR_IMASK8 0x00000000 /* mask level 8 */ -#define SR_IMASK7 0x00008000 /* mask level 7 */ -#define SR_IMASK6 0x0000c000 /* mask level 6 */ -#define SR_IMASK5 0x0000e000 /* mask level 5 */ -#define SR_IMASK4 0x0000f000 /* mask level 4 */ -#define SR_IMASK3 0x0000f800 /* mask level 3 */ -#define SR_IMASK2 0x0000fc00 /* mask level 2 */ -#define SR_IMASK1 0x0000fe00 /* mask level 1 */ -#define SR_IMASK0 0x0000ff00 /* mask level 0 */ - -#define SR_IMASKSHIFT 8 - -#define SR_IBIT8 0x00008000 /* bit level 8 */ -#define SR_IBIT7 0x00004000 /* bit level 7 */ -#define SR_IBIT6 0x00002000 /* bit level 6 */ -#define SR_IBIT5 0x00001000 /* bit level 5 */ -#define SR_IBIT4 0x00000800 /* bit level 4 */ -#define SR_IBIT3 0x00000400 /* bit level 3 */ -#define SR_IBIT2 0x00000200 /* bit level 2 */ -#define SR_IBIT1 0x00000100 /* bit level 1 */ - -#define SR_KSMASK 0x00000018 /* Kernel mode mask */ -#define SR_KSUSER 0x00000010 /* User mode */ -#define SR_KSSUPER 0x00000008 /* Supervisor mode */ -#define SR_KSKERNEL 0x00000000 /* Kernel mode */ -#define SR_ERL 0x00000004 /* Error level */ -#define SR_EXL 0x00000002 /* Exception level */ -#define SR_IE 0x00000001 /* Interrupts enabled */ -#endif - - - -/* - * Cause Register - */ -#define CAUSE_BD 0x80000000 /* Branch delay slot */ -#define CAUSE_BT 0x40000000 /* Branch Taken */ -#define CAUSE_CEMASK 0x30000000 /* coprocessor error */ -#define CAUSE_CESHIFT 28 - - -#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */ -#define CAUSE_IPSHIFT 8 - -#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */ -#define CAUSE_EXCSHIFT 2 - -#ifndef XDS -/* -** Coprocessor 0 registers -*/ -#define C0_INX $0 /* tlb index */ -#define C0_RAND $1 /* tlb random */ -#if __mips == 1 -#define C0_TLBLO $2 /* tlb entry low */ -#endif -#if __mips == 3 -#define C0_TLBLO0 $2 /* tlb entry low 0 */ -#define C0_TLBLO1 $3 /* tlb entry low 1 */ -#endif - -#define C0_CTXT $4 /* tlb context */ - -#if __mips == 3 -#define C0_PAGEMASK $5 /* tlb page mask */ -#define C0_WIRED $6 /* number of wired tlb entries */ -#endif - -#if __mips == 1 -#define C0_TAR $6 -#endif - -#define C0_BADVADDR $8 /* bad virtual address */ - -#if __mips == 3 -#define C0_COUNT $9 /* cycle count */ -#endif - -#define C0_TLBHI $10 /* tlb entry hi */ - -#if __mips == 3 -#define C0_COMPARE $11 /* cyccle count comparator */ -#endif - -#define C0_SR $12 /* status register */ -#define C0_CAUSE $13 /* exception cause */ -#define C0_EPC $14 /* exception pc */ -#define C0_PRID $15 /* revision identifier */ - -#if __mips == 1 -#define C0_CONFIG $3 /* configuration register R3081*/ -#endif - -#if __mips == 3 -#define C0_CONFIG $16 /* configuration register */ -#define C0_LLADDR $17 /* linked load address */ -#define C0_WATCHLO $18 /* watchpoint trap register */ -#define C0_WATCHHI $19 /* watchpoint trap register */ -#define C0_XCTXT $20 /* extended tlb context */ -#define C0_ECC $26 /* secondary cache ECC control */ -#define C0_CACHEERR $27 /* cache error status */ -#define C0_TAGLO $28 /* cache tag lo */ -#define C0_TAGHI $29 /* cache tag hi */ -#define C0_ERRPC $30 /* cache error pc */ -#endif - -#define C1_REVISION $0 -#define C1_STATUS $31 - -#endif XDS - -#ifdef R4650 -#define IWATCH $18 -#define DWATCH $19 -#define IBASE $0 -#define IBOUND $1 -#define DBASE $2 -#define DBOUND $3 -#define CALG $17 -#endif - -#endif /* _IDTCPU_H__ */ - diff --git a/c/src/exec/score/cpu/mips/iregdef.h b/c/src/exec/score/cpu/mips/iregdef.h deleted file mode 100644 index 3584325e07..0000000000 --- a/c/src/exec/score/cpu/mips/iregdef.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - -Based upon IDT provided code with the following release: - -This source code has been made available to you by IDT on an AS-IS -basis. Anyone receiving this source is licensed under IDT copyrights -to use it in any way he or she deems fit, including copying it, -modifying it, compiling it, and redistributing it either with or -without modifications. No license under IDT patents or patent -applications is to be implied by the copyright license. - -Any user of this software should understand that IDT cannot provide -technical support for this software and will not be responsible for -any consequences resulting from the use of this software. - -Any person who transfers this source code or any derivative work must -include the IDT copyright notice, this paragraph, and the preceeding -two paragraphs in the transferred software. - -COPYRIGHT IDT CORPORATION 1996 -LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - - $Id$ -*/ - -/* -** iregdef.h - IDT R3000 register structure header file -** -** Copyright 1989 Integrated Device Technology, Inc -** All Rights Reserved -** -*/ -#ifndef __IREGDEF_H__ -#define __IREGDEF_H__ - -/* - * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves - * added Register definition for XContext reg. - * Look towards end of this file. - */ -/* -** register names -*/ -#define r0 $0 -#define r1 $1 -#define r2 $2 -#define r3 $3 -#define r4 $4 -#define r5 $5 -#define r6 $6 -#define r7 $7 -#define r8 $8 -#define r9 $9 -#define r10 $10 -#define r11 $11 -#define r12 $12 -#define r13 $13 - -#define r14 $14 -#define r15 $15 -#define r16 $16 -#define r17 $17 -#define r18 $18 -#define r19 $19 -#define r20 $20 -#define r21 $21 -#define r22 $22 -#define r23 $23 -#define r24 $24 -#define r25 $25 -#define r26 $26 -#define r27 $27 -#define r28 $28 -#define r29 $29 -#define r30 $30 -#define r31 $31 - -#define fp0 $f0 -#define fp1 $f1 -#define fp2 $f2 -#define fp3 $f3 -#define fp4 $f4 -#define fp5 $f5 -#define fp6 $f6 -#define fp7 $f7 -#define fp8 $f8 -#define fp9 $f9 -#define fp10 $f10 -#define fp11 $f11 -#define fp12 $f12 -#define fp13 $f13 -#define fp14 $f14 -#define fp15 $f15 -#define fp16 $f16 -#define fp17 $f17 -#define fp18 $f18 -#define fp19 $f19 -#define fp20 $f20 -#define fp21 $f21 -#define fp22 $f22 -#define fp23 $f23 -#define fp24 $f24 -#define fp25 $f25 -#define fp26 $f26 -#define fp27 $f27 -#define fp28 $f28 -#define fp29 $f29 -#define fp30 $f30 -#define fp31 $f31 - -#define fcr0 $0 -#define fcr30 $30 -#define fcr31 $31 - -#define zero $0 /* wired zero */ -#define AT $at /* assembler temp */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers a0-a3 */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved t0-t9 */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved s0-s8 */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 -#define t9 $25 -#define k0 $26 /* kernel usage */ -#define k1 $27 /* kernel usage */ -#define gp $28 /* sdata pointer */ -#define sp $29 /* stack pointer */ -#define s8 $30 /* yet another saved reg for the callee */ -#define fp $30 /* frame pointer - this is being phased out by MIPS */ -#define ra $31 /* return address */ - - -/* -** relative position of registers in interrupt/exception frame -*/ -#define R_R0 0 -#define R_R1 1 -#define R_R2 2 -#define R_R3 3 -#define R_R4 4 -#define R_R5 5 -#define R_R6 6 -#define R_R7 7 -#define R_R8 8 -#define R_R9 9 -#define R_R10 10 -#define R_R11 11 -#define R_R12 12 -#define R_R13 13 -#define R_R14 14 -#define R_R15 15 -#define R_R16 16 -#define R_R17 17 -#define R_R18 18 -#define R_R19 19 -#define R_R20 20 -#define R_R21 21 -#define R_R22 22 -#define R_R23 23 -#define R_R24 24 -#define R_R25 25 -#define R_R26 26 -#define R_R27 27 -#define R_R28 28 -#define R_R29 29 -#define R_R30 30 -#define R_R31 31 - -#define R_SR 32 -#define R_MDLO 33 -#define R_MDHI 34 -#define R_BADVADDR 35 -#define R_CAUSE 36 -#define R_EPC 37 - -#define R_F0 38 -#define R_F1 39 -#define R_F2 40 -#define R_F3 41 -#define R_F4 42 -#define R_F5 43 -#define R_F6 44 -#define R_F7 45 -#define R_F8 46 -#define R_F9 47 -#define R_F10 48 -#define R_F11 49 -#define R_F12 50 -#define R_F13 41 -#define R_F14 42 -#define R_F15 43 -#define R_F16 44 -#define R_F17 45 -#define R_F18 56 -#define R_F19 57 -#define R_F20 58 -#define R_F21 59 -#define R_F22 60 -#define R_F23 61 -#define R_F24 62 -#define R_F25 63 -#define R_F26 64 -#define R_F27 65 -#define R_F28 66 -#define R_F29 67 -#define R_F30 68 -#define R_F31 69 -#define R_FCSR 70 -#define R_FEIR 71 -#define R_TLBHI 72 - -#if __mips == 1 -#define R_TLBLO 73 -#endif -#if __mips == 3 -#define R_TLBLO0 73 -#endif - -#define R_INX 74 -#define R_RAND 75 -#define R_CTXT 76 -#define R_EXCTYPE 77 -#define R_MODE 78 -#define R_PRID 79 -#define R_TAR 80 -#if __mips == 1 -#define NREGS 81 -#endif -#if __mips == 3 -#define R_TLBLO1 81 -#define R_PAGEMASK 82 -#define R_WIRED 83 -#define R_COUNT 84 -#define R_COMPARE 85 -#define R_CONFIG 86 -#define R_LLADDR 87 -#define R_WATCHLO 88 -#define R_WATCHHI 89 -#define R_ECC 90 -#define R_CACHEERR 91 -#define R_TAGLO 92 -#define R_TAGHI 93 -#define R_ERRPC 94 -#define R_XCTXT 95 /* Ketan added from SIM64bit */ - -#define NREGS 96 -#endif - -/* -** For those who like to think in terms of the compiler names for the regs -*/ -#define R_ZERO R_R0 -#define R_AT R_R1 -#define R_V0 R_R2 -#define R_V1 R_R3 -#define R_A0 R_R4 -#define R_A1 R_R5 -#define R_A2 R_R6 -#define R_A3 R_R7 -#define R_T0 R_R8 -#define R_T1 R_R9 -#define R_T2 R_R10 -#define R_T3 R_R11 -#define R_T4 R_R12 -#define R_T5 R_R13 -#define R_T6 R_R14 -#define R_T7 R_R15 -#define R_S0 R_R16 -#define R_S1 R_R17 -#define R_S2 R_R18 -#define R_S3 R_R19 -#define R_S4 R_R20 -#define R_S5 R_R21 -#define R_S6 R_R22 -#define R_S7 R_R23 -#define R_T8 R_R24 -#define R_T9 R_R25 -#define R_K0 R_R26 -#define R_K1 R_R27 -#define R_GP R_R28 -#define R_SP R_R29 -#define R_FP R_R30 -#define R_RA R_R31 - -/* disabled for RTEMS */ -#if 0 -/* Ketan added the following */ -#if __mips == 1 -#define sreg sw -#define lreg lw -#define rmfc0 mfc0 -#define rmtc0 mtc0 -#define R_SZ 4 -#endif /* __mips == 1 */ - -/* #ifdef __mips == 3 */ -#if __mips < 3 -#define sreg sw -#define lreg lw -#define rmfc0 mfc0 -#define rmtc0 mtc0 -#define R_SZ 4 -#else -#define sreg sd -#define lreg ld -#define rmfc0 dmfc0 -#define rmtc0 dmtc0 -#define R_SZ 8 -#endif -/* #endif __mips == 3 */ -/* Ketan till here */ -#endif - -#endif /* __IREGDEF_H__ */ - diff --git a/c/src/exec/score/cpu/mips/rtems/.cvsignore b/c/src/exec/score/cpu/mips/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/mips/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/mips/rtems/score/.cvsignore b/c/src/exec/score/cpu/mips/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/mips/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/mips/rtems/score/cpu.h b/c/src/exec/score/cpu/mips/rtems/score/cpu.h deleted file mode 100644 index 43c7c33975..0000000000 --- a/c/src/exec/score/cpu/mips/rtems/score/cpu.h +++ /dev/null @@ -1,1202 +0,0 @@ -/* - * Mips CPU Dependent Header File - * - * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and - * Joel Sherrill <joel@OARcorp.com>. - * - * These changes made the code conditional on standard cpp predefines, - * merged the mips1 and mips3 code sequences as much as possible, - * and moved some of the assembly code to C. Alan did much of the - * initial analysis and rework. Joel took over from there and - * wrote the JMR3904 BSP so this could be tested. Joel also - * added the new interrupt vectoring support in libcpu and - * tried to better support the various interrupt controllers. - * - * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/mips.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 1 - - - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "MIPS_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( MIPS_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -/* we can use the low power wait instruction for the IDLE thread */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -/* our stack grows down */ -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -/* our cache line size is 16 bytes */ -#if __GNUC__ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) -#else -#define CPU_STRUCTURE_ALIGNMENT -#endif - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x000000ff - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -#ifndef ASSEMBLY_ONLY - -/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ -#if __mips == 1 -#define __MIPS_REGISTER_TYPE unsigned32 -#define __MIPS_FPU_REGISTER_TYPE unsigned32 -#elif __mips == 3 -#define __MIPS_REGISTER_TYPE unsigned64 -#define __MIPS_FPU_REGISTER_TYPE unsigned64 -#else -#error "mips register size: unknown architecture level!!" -#endif -typedef struct { - __MIPS_REGISTER_TYPE s0; - __MIPS_REGISTER_TYPE s1; - __MIPS_REGISTER_TYPE s2; - __MIPS_REGISTER_TYPE s3; - __MIPS_REGISTER_TYPE s4; - __MIPS_REGISTER_TYPE s5; - __MIPS_REGISTER_TYPE s6; - __MIPS_REGISTER_TYPE s7; - __MIPS_REGISTER_TYPE sp; - __MIPS_REGISTER_TYPE fp; - __MIPS_REGISTER_TYPE ra; - __MIPS_REGISTER_TYPE c0_sr; - __MIPS_REGISTER_TYPE c0_epc; -} Context_Control; - -/* WARNING: If this structure is modified, the constants in cpu.h - * must also be updated. - */ - -typedef struct { -#if ( CPU_HARDWARE_FP == TRUE ) - __MIPS_FPU_REGISTER_TYPE fp0; - __MIPS_FPU_REGISTER_TYPE fp1; - __MIPS_FPU_REGISTER_TYPE fp2; - __MIPS_FPU_REGISTER_TYPE fp3; - __MIPS_FPU_REGISTER_TYPE fp4; - __MIPS_FPU_REGISTER_TYPE fp5; - __MIPS_FPU_REGISTER_TYPE fp6; - __MIPS_FPU_REGISTER_TYPE fp7; - __MIPS_FPU_REGISTER_TYPE fp8; - __MIPS_FPU_REGISTER_TYPE fp9; - __MIPS_FPU_REGISTER_TYPE fp10; - __MIPS_FPU_REGISTER_TYPE fp11; - __MIPS_FPU_REGISTER_TYPE fp12; - __MIPS_FPU_REGISTER_TYPE fp13; - __MIPS_FPU_REGISTER_TYPE fp14; - __MIPS_FPU_REGISTER_TYPE fp15; - __MIPS_FPU_REGISTER_TYPE fp16; - __MIPS_FPU_REGISTER_TYPE fp17; - __MIPS_FPU_REGISTER_TYPE fp18; - __MIPS_FPU_REGISTER_TYPE fp19; - __MIPS_FPU_REGISTER_TYPE fp20; - __MIPS_FPU_REGISTER_TYPE fp21; - __MIPS_FPU_REGISTER_TYPE fp22; - __MIPS_FPU_REGISTER_TYPE fp23; - __MIPS_FPU_REGISTER_TYPE fp24; - __MIPS_FPU_REGISTER_TYPE fp25; - __MIPS_FPU_REGISTER_TYPE fp26; - __MIPS_FPU_REGISTER_TYPE fp27; - __MIPS_FPU_REGISTER_TYPE fp28; - __MIPS_FPU_REGISTER_TYPE fp29; - __MIPS_FPU_REGISTER_TYPE fp30; - __MIPS_FPU_REGISTER_TYPE fp31; -#endif -} Context_Control_fp; - -/* - * This struct reflects the stack frame employed in ISR_Handler. Note - * that the ISR routine save some of the registers to this frame for - * all interrupts and exceptions. Other registers are saved only on - * exceptions, while others are not touched at all. The untouched - * registers are not normally disturbed by high-level language - * programs so they can be accessed when required. - * - * The registers and their ordering in this struct must directly - * correspond to the layout and ordering of * shown in iregdef.h, - * as cpu_asm.S uses those definitions to fill the stack frame. - * This struct provides access to the stack frame for C code. - * - * Similarly, this structure is used by debugger stubs and exception - * processing routines so be careful when changing the format. - * - * NOTE: The comments with this structure and cpu_asm.S should be kept - * in sync. When in doubt, look in the code to see if the - * registers you're interested in are actually treated as expected. - * The order of the first portion of this structure follows the - * order of registers expected by gdb. - */ - -typedef struct -{ - __MIPS_REGISTER_TYPE r0; /* 0 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE at; /* 1 -- saved always */ - __MIPS_REGISTER_TYPE v0; /* 2 -- saved always */ - __MIPS_REGISTER_TYPE v1; /* 3 -- saved always */ - __MIPS_REGISTER_TYPE a0; /* 4 -- saved always */ - __MIPS_REGISTER_TYPE a1; /* 5 -- saved always */ - __MIPS_REGISTER_TYPE a2; /* 6 -- saved always */ - __MIPS_REGISTER_TYPE a3; /* 7 -- saved always */ - __MIPS_REGISTER_TYPE t0; /* 8 -- saved always */ - __MIPS_REGISTER_TYPE t1; /* 9 -- saved always */ - __MIPS_REGISTER_TYPE t2; /* 10 -- saved always */ - __MIPS_REGISTER_TYPE t3; /* 11 -- saved always */ - __MIPS_REGISTER_TYPE t4; /* 12 -- saved always */ - __MIPS_REGISTER_TYPE t5; /* 13 -- saved always */ - __MIPS_REGISTER_TYPE t6; /* 14 -- saved always */ - __MIPS_REGISTER_TYPE t7; /* 15 -- saved always */ - __MIPS_REGISTER_TYPE s0; /* 16 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s1; /* 17 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s2; /* 18 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s3; /* 19 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s4; /* 20 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s5; /* 21 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s6; /* 22 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s7; /* 23 -- saved on exceptions */ - __MIPS_REGISTER_TYPE t8; /* 24 -- saved always */ - __MIPS_REGISTER_TYPE t9; /* 25 -- saved always */ - __MIPS_REGISTER_TYPE k0; /* 26 -- NOT FILLED IN, kernel tmp reg */ - __MIPS_REGISTER_TYPE k1; /* 27 -- NOT FILLED IN, kernel tmp reg */ - __MIPS_REGISTER_TYPE gp; /* 28 -- saved always */ - __MIPS_REGISTER_TYPE sp; /* 29 -- saved on exceptions NOT RESTORED */ - __MIPS_REGISTER_TYPE fp; /* 30 -- saved always */ - __MIPS_REGISTER_TYPE ra; /* 31 -- saved always */ - __MIPS_REGISTER_TYPE c0_sr; /* 32 -- saved always, some bits are */ - /* manipulated per-thread */ - __MIPS_REGISTER_TYPE mdlo; /* 33 -- saved always */ - __MIPS_REGISTER_TYPE mdhi; /* 34 -- saved always */ - __MIPS_REGISTER_TYPE badvaddr; /* 35 -- saved on exceptions, read-only */ - __MIPS_REGISTER_TYPE cause; /* 36 -- saved on exceptions NOT restored */ - __MIPS_REGISTER_TYPE epc; /* 37 -- saved always, read-only register */ - /* but logically restored */ - __MIPS_FPU_REGISTER_TYPE f0; /* 38 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f1; /* 39 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f2; /* 40 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f3; /* 41 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f4; /* 42 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f5; /* 43 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f6; /* 44 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f7; /* 45 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f8; /* 46 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f9; /* 47 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f10; /* 48 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f11; /* 49 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f12; /* 50 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f13; /* 51 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f14; /* 52 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f15; /* 53 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f16; /* 54 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f17; /* 55 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f18; /* 56 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f19; /* 57 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f20; /* 58 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f21; /* 59 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f22; /* 60 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f23; /* 61 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f24; /* 62 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f25; /* 63 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f26; /* 64 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f27; /* 65 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f28; /* 66 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f29; /* 67 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f30; /* 68 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f31; /* 69 -- saved if FP enabled */ - __MIPS_REGISTER_TYPE fcsr; /* 70 -- saved on exceptions */ - /* (oddly not documented on MGV) */ - __MIPS_REGISTER_TYPE feir; /* 71 -- saved on exceptions */ - /* (oddly not documented on MGV) */ - - /* GDB does not seem to care about anything past this point */ - - __MIPS_REGISTER_TYPE tlbhi; /* 72 - NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ -#if __mips == 1 - __MIPS_REGISTER_TYPE tlblo; /* 73 - NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ -#endif -#if __mips == 3 - __MIPS_REGISTER_TYPE tlblo0; /* 73 - NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ -#endif - - __MIPS_REGISTER_TYPE inx; /* 74 -- NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ - __MIPS_REGISTER_TYPE rand; /* 75 -- NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ - __MIPS_REGISTER_TYPE ctxt; /* 76 -- NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ - __MIPS_REGISTER_TYPE exctype; /* 77 -- NOT FILLED IN (not enough info) */ - __MIPS_REGISTER_TYPE mode; /* 78 -- NOT FILLED IN (not enough info) */ - __MIPS_REGISTER_TYPE prid; /* 79 -- NOT FILLED IN (not need to do so) */ - __MIPS_REGISTER_TYPE tar ; /* 80 -- target address register, filled on exceptions */ - /* end of __mips == 1 so NREGS == 81 */ -#if __mips == 3 - __MIPS_REGISTER_TYPE tlblo1; /* 81 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE pagemask; /* 82 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE wired; /* 83 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE count; /* 84 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE compare; /* 85 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE config; /* 86 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE lladdr; /* 87 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE watchlo; /* 88 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE watchhi; /* 89 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE ecc; /* 90 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE cacheerr; /* 91 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE taglo; /* 92 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE taghi; /* 93 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE errpc; /* 94 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE xctxt; /* 95 -- NOT FILLED IN */ - /* end of __mips == 3 so NREGS == 96 */ -#endif - -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the mips processor specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - - unsigned32 clicks_per_microsecond; -} rtems_cpu_table; - - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access MIPS specific additions to the CPU Table - */ - -#define rtems_cpu_configuration_get_clicks_per_microsecond() \ - (_CPU_Table.clicks_per_microsecond) - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - * - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - * - * NOTE: Not needed on this port. - */ - - - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -extern unsigned int mips_interrupt_number_of_vectors; -#define CPU_INTERRUPT_NUMBER_OF_VECTORS (mips_interrupt_number_of_vectors) -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (2048*sizeof(unsigned32)) - - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level ) \ - do { \ - unsigned int _scratch; \ - mips_get_sr( _scratch ); \ - mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \ - _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \ - } while(0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - do { \ - unsigned int _scratch; \ - mips_get_sr( _scratch ); \ - mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \ - } while(0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _xlevel ) \ - do { \ - unsigned int _scratch2 = _xlevel; \ - _CPU_ISR_Enable( _scratch2 ); \ - _CPU_ISR_Disable( _scratch2 ); \ - _xlevel = _scratch2; \ - } while(0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * On the MIPS, 0 is all on. Non-zero is all off. This only - * manipulates the IEC. - */ - -unsigned32 _CPU_ISR_Get_level( void ); /* in cpu.c */ - -void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */ - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * The per-thread status register holds the interrupt enable, FP enable - * and global interrupt enable for that thread. It means each thread can - * enable its own set of interrupts. If interrupts are disabled, RTEMS - * can still dispatch via blocking calls. This is the function of the - * "Interrupt Level", and on the MIPS, it controls the IEC bit and all - * the hardware interrupts as defined in the SR. Software ints - * are automatically enabled for all threads, as they will only occur under - * program control anyhow. Besides, the interrupt level parm is only 8 bits, - * and controlling the software ints plus the others would require 9. - * - * If the Interrupt Level is 0, all ints are on. Otherwise, the - * Interrupt Level should supply a bit pattern to impose on the SR - * interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6 - * apply to the SR register Intr bits from bit 10 thru bit 15. Bit 7 of - * the Interrupt Level parameter is unused at this time. - * - * These are the only per-thread SR bits, the others are maintained - * globally & explicitly preserved by the Context Switch code in cpu_asm.s - */ - - -#if __mips == 3 -#define _INTON (SR_EXL | SR_IE) -#define _EXTRABITS 0 -#endif -#if __mips == 1 -#define _INTON SR_IEC -#define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */ -#endif - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, _isr, _entry_point, _is_fp ) \ - { \ - unsigned32 _stack_tmp = \ - (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \ - unsigned32 _intlvl = _isr & 0xff; \ - _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \ - (_the_context)->sp = _stack_tmp; \ - (_the_context)->fp = _stack_tmp; \ - (_the_context)->ra = (unsigned64)_entry_point; \ - (_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \ - 0x300 | \ - ((_intlvl & 1)?_INTON:0)) ) | \ - SR_CU0 | ((_is_fp)?SR_CU1:0) | _EXTRABITS; \ - } - - - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * A floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#if ( CPU_HARDWARE_FP == TRUE ) -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - do { \ - unsigned int _level; \ - _CPU_ISR_Disable(_level); \ - loop: goto loop; \ - } while (0) - - -extern void mips_break( int error ); - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - - -#endif - - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/mips/rtems/score/mips.h b/c/src/exec/score/cpu/mips/rtems/score/mips.h deleted file mode 100644 index ea5a4b545d..0000000000 --- a/c/src/exec/score/cpu/mips/rtems/score/mips.h +++ /dev/null @@ -1,272 +0,0 @@ -/* mips.h - * - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ -/* @(#)mips64orion.h 08/29/96 1.3 */ - -#ifndef _INCLUDE_MIPS_h -#define _INCLUDE_MIPS_h - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef ASM -#include <idtcpu.h> -#endif - -/* - * SR bits that enable/disable interrupts - * - * NOTE: XXX what about SR_ERL? - */ - -#if __mips == 3 -#ifdef ASM -#define SR_INTERRUPT_ENABLE_BITS 0x01 -#else -#define SR_INTERRUPT_ENABLE_BITS SR_IE -#endif - -#elif __mips == 1 -#define SR_INTERRUPT_ENABLE_BITS SR_IEC - -#else -#error "mips interrupt enable bits: unknown architecture level!" -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "no cpu" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -#if defined(__mips_soft_float) -#define MIPS_HAS_FPU 0 -#else -#define MIPS_HAS_FPU 1 -#endif - -#if (__mips == 1) -#define CPU_MODEL_NAME "ISA Level 1 or 2" -#elif (__mips == 3) -#if defined(__mips64) -#define CPU_MODEL_NAME "ISA Level 4" -#else -#define CPU_MODEL_NAME "ISA Level 3" -#endif -#else -#error "Unknown MIPS ISA level" -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "MIPS" - -/* - * RTEMS Vector numbers for exception conditions. This is a direct - * map to the causes. - */ - -#define MIPS_EXCEPTION_BASE 0 - -#define MIPS_EXCEPTION_INT MIPS_EXCEPTION_BASE+0 -#define MIPS_EXCEPTION_MOD MIPS_EXCEPTION_BASE+1 -#define MIPS_EXCEPTION_TLBL MIPS_EXCEPTION_BASE+2 -#define MIPS_EXCEPTION_TLBS MIPS_EXCEPTION_BASE+3 -#define MIPS_EXCEPTION_ADEL MIPS_EXCEPTION_BASE+4 -#define MIPS_EXCEPTION_ADES MIPS_EXCEPTION_BASE+5 -#define MIPS_EXCEPTION_IBE MIPS_EXCEPTION_BASE+6 -#define MIPS_EXCEPTION_DBE MIPS_EXCEPTION_BASE+7 -#define MIPS_EXCEPTION_SYSCALL MIPS_EXCEPTION_BASE+8 -#define MIPS_EXCEPTION_BREAK MIPS_EXCEPTION_BASE+9 -#define MIPS_EXCEPTION_RI MIPS_EXCEPTION_BASE+10 -#define MIPS_EXCEPTION_CPU MIPS_EXCEPTION_BASE+11 -#define MIPS_EXCEPTION_OVERFLOW MIPS_EXCEPTION_BASE+12 -#define MIPS_EXCEPTION_TRAP MIPS_EXCEPTION_BASE+13 -#define MIPS_EXCEPTION_VCEI MIPS_EXCEPTION_BASE+14 -/* FPE only on mips2 and higher */ -#define MIPS_EXCEPTION_FPE MIPS_EXCEPTION_BASE+15 -#define MIPS_EXCEPTION_C2E MIPS_EXCEPTION_BASE+16 -/* 17-22 reserved */ -#define MIPS_EXCEPTION_WATCH MIPS_EXCEPTION_BASE+23 -/* 24-30 reserved */ -#define MIPS_EXCEPTION_VCED MIPS_EXCEPTION_BASE+31 - -#define MIPS_INTERRUPT_BASE MIPS_EXCEPTION_BASE+32 - -/* - * Some macros to access registers - */ - -#define mips_get_sr( _x ) \ - do { \ - asm volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \ - } while (0) - -#define mips_set_sr( _x ) \ - do { \ - register unsigned int __x = (_x); \ - asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \ - } while (0) - - -/* - * Access the Cause register - */ - -#define mips_get_cause( _x ) \ - do { \ - asm volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \ - } while (0) - - -#define mips_set_cause( _x ) \ - do { \ - register unsigned int __x = (_x); \ - asm volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \ - } while (0) - - - - -/* - * Access the Debug Cache Invalidate Control register - */ - -#define mips_get_dcic( _x ) \ - do { \ - asm volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \ - } while (0) - - -#define mips_set_dcic( _x ) \ - do { \ - register unsigned int __x = (_x); \ - asm volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \ - } while (0) - - - - -/* - * Access the Breakpoint Program Counter & Mask registers - * (_x for BPC, _y for mask) - */ - -#define mips_get_bpcrm( _x, _y ) \ - do { \ - asm volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \ - asm volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \ - } while (0) - - -#define mips_set_bpcrm( _x, _y ) \ - do { \ - register unsigned int __x = (_x); \ - register unsigned int __y = (_y); \ - asm volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \ - asm volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \ - } while (0) - - - - - - -/* - * Access the Breakpoint Data Address & Mask registers - * (_x for BDA, _y for mask) - */ - -#define mips_get_bdarm( _x, _y ) \ - do { \ - asm volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \ - asm volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \ - } while (0) - - -#define mips_set_bdarm( _x, _y ) \ - do { \ - register unsigned int __x = (_x); \ - register unsigned int __y = (_y); \ - asm volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \ - asm volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \ - } while (0) - - - - - - - -/* - * Access FCR31 - */ - -#define mips_get_fcr31( _x ) \ - do { \ - asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \ - } while(0) - - -#define mips_set_fcr31( _x ) \ - do { \ - register unsigned int __x = (_x); \ - asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \ - } while(0) - - -/* - * Manipulate interrupt mask - * - * mips_unmask_interrupt( _mask) - * enables interrupts - mask is positioned so it only needs to be or'ed - * into the status reg. This also does some other things !!!! Caution - * should be used if invoking this while in the middle of a debugging - * session where the client may have nested interrupts. - * - * mips_mask_interrupt( _mask ) - * disable the interrupt - mask is the complement of the bits to be - * cleared - i.e. to clear ext int 5 the mask would be - 0xffff7fff - * - * - * NOTE: mips_mask_interrupt() used to be disable_int(). - * mips_unmask_interrupt() used to be enable_int(). - * - */ - -#define mips_enable_in_interrupt_mask( _mask ) \ - do { \ - unsigned int _sr; \ - mips_get_sr( _sr ); \ - _sr |= (_mask); \ - mips_set_sr( _sr ); \ - } while (0) - -#define mips_disable_in_interrupt_mask( _mask ) \ - do { \ - unsigned int _sr; \ - mips_get_sr( _sr ); \ - _sr &= ~(_mask); \ - mips_set_sr( _sr ); \ - } while (0) - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_MIPS_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/mips/rtems/score/types.h b/c/src/exec/score/cpu/mips/rtems/score/types.h deleted file mode 100644 index 3720032a76..0000000000 --- a/c/src/exec/score/cpu/mips/rtems/score/types.h +++ /dev/null @@ -1,57 +0,0 @@ -/* mipstypes.h - * - * This include file contains type definitions pertaining to the MIPS - * processor family. - * - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ -/* @(#)mipstypes.h 08/20/96 1.4 */ - -#ifndef __MIPS_TYPES_h -#define __MIPS_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void mips_isr; -typedef void ( *mips_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/mips64orion/.cvsignore b/c/src/exec/score/cpu/mips64orion/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/mips64orion/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/mips64orion/ChangeLog b/c/src/exec/score/cpu/mips64orion/ChangeLog deleted file mode 100644 index 198463b655..0000000000 --- a/c/src/exec/score/cpu/mips64orion/ChangeLog +++ /dev/null @@ -1,107 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * asm.h: Use cpuopts.h instead of targopts.h. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/mipstypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-04-11 Joel Sherrill <joel@OARcorp.com> - - * cpu.c: Removed duplicate declaration for _ISR_Vector_table. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/mips64orion/Makefile.am b/c/src/exec/score/cpu/mips64orion/Makefile.am deleted file mode 100644 index 7d384affb7..0000000000 --- a/c/src/exec/score/cpu/mips64orion/Makefile.am +++ /dev/null @@ -1,54 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h cpu_asm.h idtcpu.h idtmon.h iregdef.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/mips64orion.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/mips64orion/asm.h b/c/src/exec/score/cpu/mips64orion/asm.h deleted file mode 100644 index 747f2d2358..0000000000 --- a/c/src/exec/score/cpu/mips64orion/asm.h +++ /dev/null @@ -1,100 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ -/* @(#)asm.h 03/15/96 1.1 */ - -#ifndef __MIPS64ORION_ASM_h -#define __MIPS64ORION_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/mips64orion.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/mips64orion/configure.ac b/c/src/exec/score/cpu/mips64orion/configure.ac deleted file mode 100644 index 33a6f79fd4..0000000000 --- a/c/src/exec/score/cpu/mips64orion/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-mips64orion],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/mips64orion/cpu.c b/c/src/exec/score/cpu/mips64orion/cpu.c deleted file mode 100644 index 57e047fa4a..0000000000 --- a/c/src/exec/score/cpu/mips64orion/cpu.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Mips CPU Dependent Source - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from source copyrighted as follows: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -/* - * Rather than deleting this, it is commented out to (hopefully) help - * the submitter send updates. - * - * static char _sccsid[] = "@(#)cpu.c 08/20/96 1.5\n"; - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> - - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - - -void null_handler( void ) -{ -} - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - unsigned int i = ISR_NUMBER_OF_VECTORS; - - while ( i-- ) - { - _ISR_Vector_table[i] = (ISR_Handler_entry)null_handler; - } - - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; - - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ - - _CPU_Table = *cpu_table; - -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -#if 0 /* located in cpu_asm.S */ -unsigned32 _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ -} -#endif - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ - -#if 0 /* not necessary */ -/* use IDT/Sim to set interrupt vector. Needed to co-exist with debugger. */ - add_ext_int_func( vector, new_handler ); -#endif -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -/* we don't support this yet */ -} - -/*PAGE - * - * _CPU_Internal_threads_Idle_thread_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -#if 0 /* located in cpu_asm.S */ -void _CPU_Thread_Idle_body( void ) -{ - - for( ; ; ) - /* insert your "halt" instruction here */ ; -} -#endif - -extern void mips_break( int error ); - -#include <stdio.h> - -void mips_fatal_error( int error ) -{ - printf("fatal error 0x%x %d\n",error,error); - mips_break( error ); -} diff --git a/c/src/exec/score/cpu/mips64orion/cpu_asm.S b/c/src/exec/score/cpu/mips64orion/cpu_asm.S deleted file mode 100644 index 9770a5f2f9..0000000000 --- a/c/src/exec/score/cpu/mips64orion/cpu_asm.S +++ /dev/null @@ -1,971 +0,0 @@ -/* cpu_asm.S - * - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from source copyrighted as follows: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ -/* @(#)cpu_asm.S 08/20/96 1.15 */ - -#include "cpu_asm.h" - -#include "iregdef.h" -#include "idtcpu.h" - -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl name; \ - .ent name; \ -name:; \ - .frame frm_reg,offset,ret_reg -#define ENDFRAME(name) \ - .end name - - -#define EXCP_STACK_SIZE (NREGS*R_SZ) - -#if __ghs__ -#define sd sw -#define ld lw -#define dmtc0 mtc0 -#define dsll sll -#define dmfc0 mfc0 -#endif - -#if 1 /* 32 bit unsigned32 types */ -#define sint sw -#define lint lw -#define stackadd addiu -#define intadd addu -#define SZ_INT 4 -#define SZ_INT_POW2 2 -#else /* 64 bit unsigned32 types */ -#define sint dw -#define lint dw -#define stackadd daddiu -#define intadd daddu -#define SZ_INT 8 -#define SZ_INT_POW2 3 -#endif - -#ifdef __GNUC__ -#define EXTERN(x,size) .extern x,size -#else -#define EXTERN(x,size) -#endif - -/* NOTE: these constants must match the Context_Control structure in cpu.h */ -#define S0_OFFSET 0 -#define S1_OFFSET 1 -#define S2_OFFSET 2 -#define S3_OFFSET 3 -#define S4_OFFSET 4 -#define S5_OFFSET 5 -#define S6_OFFSET 6 -#define S7_OFFSET 7 -#define SP_OFFSET 8 -#define FP_OFFSET 9 -#define RA_OFFSET 10 -#define C0_SR_OFFSET 11 -#define C0_EPC_OFFSET 12 - -/* NOTE: these constants must match the Context_Control_fp structure in cpu.h */ -#define FP0_OFFSET 0 -#define FP1_OFFSET 1 -#define FP2_OFFSET 2 -#define FP3_OFFSET 3 -#define FP4_OFFSET 4 -#define FP5_OFFSET 5 -#define FP6_OFFSET 6 -#define FP7_OFFSET 7 -#define FP8_OFFSET 8 -#define FP9_OFFSET 9 -#define FP10_OFFSET 10 -#define FP11_OFFSET 11 -#define FP12_OFFSET 12 -#define FP13_OFFSET 13 -#define FP14_OFFSET 14 -#define FP15_OFFSET 15 -#define FP16_OFFSET 16 -#define FP17_OFFSET 17 -#define FP18_OFFSET 18 -#define FP19_OFFSET 19 -#define FP20_OFFSET 20 -#define FP21_OFFSET 21 -#define FP22_OFFSET 22 -#define FP23_OFFSET 23 -#define FP24_OFFSET 24 -#define FP25_OFFSET 25 -#define FP26_OFFSET 26 -#define FP27_OFFSET 27 -#define FP28_OFFSET 28 -#define FP29_OFFSET 29 -#define FP30_OFFSET 30 -#define FP31_OFFSET 31 - - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -#if 0 -unsigned32 _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ -} -#endif -/* return the current exception level for the 4650 */ -FRAME(_CPU_ISR_Get_level,sp,0,ra) - mfc0 v0,C0_SR - nop - andi v0,SR_EXL - srl v0,1 - j ra -ENDFRAME(_CPU_ISR_Get_level) - -FRAME(_CPU_ISR_Set_level,sp,0,ra) - nop - mfc0 v0,C0_SR - nop - andi v0,SR_EXL - beqz v0,_CPU_ISR_Set_1 /* normalize v0 */ - nop - li v0,1 -_CPU_ISR_Set_1: - beq v0,a0,_CPU_ISR_Set_exit /* if (current_level != new_level ) */ - nop - bnez a0,_CPU_ISR_Set_2 - nop - nop - mfc0 t0,C0_SR - nop - li t1,~SR_EXL - and t0,t1 - nop - mtc0 t0,C0_SR /* disable exception level */ - nop - j ra - nop -_CPU_ISR_Set_2: - nop - mfc0 t0,C0_SR - nop - li t1,~SR_IE - and t0,t1 - nop - mtc0 t0,C0_SR /* first disable ie bit (recommended) */ - nop - ori t0,SR_EXL|SR_IE /* enable exception level */ - nop - mtc0 t0,C0_SR - nop -_CPU_ISR_Set_exit: - j ra - nop -ENDFRAME(_CPU_ISR_Set_level) - -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - -/* void _CPU_Context_save_fp( - * void **fp_context_ptr - * ) - * { - * } - */ - -FRAME(_CPU_Context_save_fp,sp,0,ra) - .set noat - ld a1,(a0) - swc1 $f0,FP0_OFFSET*4(a1) - swc1 $f1,FP1_OFFSET*4(a1) - swc1 $f2,FP2_OFFSET*4(a1) - swc1 $f3,FP3_OFFSET*4(a1) - swc1 $f4,FP4_OFFSET*4(a1) - swc1 $f5,FP5_OFFSET*4(a1) - swc1 $f6,FP6_OFFSET*4(a1) - swc1 $f7,FP7_OFFSET*4(a1) - swc1 $f8,FP8_OFFSET*4(a1) - swc1 $f9,FP9_OFFSET*4(a1) - swc1 $f10,FP10_OFFSET*4(a1) - swc1 $f11,FP11_OFFSET*4(a1) - swc1 $f12,FP12_OFFSET*4(a1) - swc1 $f13,FP13_OFFSET*4(a1) - swc1 $f14,FP14_OFFSET*4(a1) - swc1 $f15,FP15_OFFSET*4(a1) - swc1 $f16,FP16_OFFSET*4(a1) - swc1 $f17,FP17_OFFSET*4(a1) - swc1 $f18,FP18_OFFSET*4(a1) - swc1 $f19,FP19_OFFSET*4(a1) - swc1 $f20,FP20_OFFSET*4(a1) - swc1 $f21,FP21_OFFSET*4(a1) - swc1 $f22,FP22_OFFSET*4(a1) - swc1 $f23,FP23_OFFSET*4(a1) - swc1 $f24,FP24_OFFSET*4(a1) - swc1 $f25,FP25_OFFSET*4(a1) - swc1 $f26,FP26_OFFSET*4(a1) - swc1 $f27,FP27_OFFSET*4(a1) - swc1 $f28,FP28_OFFSET*4(a1) - swc1 $f29,FP29_OFFSET*4(a1) - swc1 $f30,FP30_OFFSET*4(a1) - swc1 $f31,FP31_OFFSET*4(a1) - j ra - nop - .set at -ENDFRAME(_CPU_Context_save_fp) - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - -/* void _CPU_Context_restore_fp( - * void **fp_context_ptr - * ) - * { - * } - */ - -FRAME(_CPU_Context_restore_fp,sp,0,ra) - .set noat - ld a1,(a0) - lwc1 $f0,FP0_OFFSET*4(a1) - lwc1 $f1,FP1_OFFSET*4(a1) - lwc1 $f2,FP2_OFFSET*4(a1) - lwc1 $f3,FP3_OFFSET*4(a1) - lwc1 $f4,FP4_OFFSET*4(a1) - lwc1 $f5,FP5_OFFSET*4(a1) - lwc1 $f6,FP6_OFFSET*4(a1) - lwc1 $f7,FP7_OFFSET*4(a1) - lwc1 $f8,FP8_OFFSET*4(a1) - lwc1 $f9,FP9_OFFSET*4(a1) - lwc1 $f10,FP10_OFFSET*4(a1) - lwc1 $f11,FP11_OFFSET*4(a1) - lwc1 $f12,FP12_OFFSET*4(a1) - lwc1 $f13,FP13_OFFSET*4(a1) - lwc1 $f14,FP14_OFFSET*4(a1) - lwc1 $f15,FP15_OFFSET*4(a1) - lwc1 $f16,FP16_OFFSET*4(a1) - lwc1 $f17,FP17_OFFSET*4(a1) - lwc1 $f18,FP18_OFFSET*4(a1) - lwc1 $f19,FP19_OFFSET*4(a1) - lwc1 $f20,FP20_OFFSET*4(a1) - lwc1 $f21,FP21_OFFSET*4(a1) - lwc1 $f22,FP22_OFFSET*4(a1) - lwc1 $f23,FP23_OFFSET*4(a1) - lwc1 $f24,FP24_OFFSET*4(a1) - lwc1 $f25,FP25_OFFSET*4(a1) - lwc1 $f26,FP26_OFFSET*4(a1) - lwc1 $f27,FP27_OFFSET*4(a1) - lwc1 $f28,FP28_OFFSET*4(a1) - lwc1 $f29,FP29_OFFSET*4(a1) - lwc1 $f30,FP30_OFFSET*4(a1) - lwc1 $f31,FP31_OFFSET*4(a1) - j ra - nop - .set at -ENDFRAME(_CPU_Context_restore_fp) - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - */ - -/* void _CPU_Context_switch( - * Context_Control *run, - * Context_Control *heir - * ) - * { - * } - */ - -FRAME(_CPU_Context_switch,sp,0,ra) - - mfc0 t0,C0_SR - li t1,~SR_IE - sd t0,C0_SR_OFFSET*8(a0) /* save status register */ - and t0,t1 - mtc0 t0,C0_SR /* first disable ie bit (recommended) */ - ori t0,SR_EXL|SR_IE /* enable exception level to disable interrupts */ - mtc0 t0,C0_SR - - sd ra,RA_OFFSET*8(a0) /* save current context */ - sd sp,SP_OFFSET*8(a0) - sd fp,FP_OFFSET*8(a0) - sd s0,S0_OFFSET*8(a0) - sd s1,S1_OFFSET*8(a0) - sd s2,S2_OFFSET*8(a0) - sd s3,S3_OFFSET*8(a0) - sd s4,S4_OFFSET*8(a0) - sd s5,S5_OFFSET*8(a0) - sd s6,S6_OFFSET*8(a0) - sd s7,S7_OFFSET*8(a0) - dmfc0 t0,C0_EPC - sd t0,C0_EPC_OFFSET*8(a0) - -_CPU_Context_switch_restore: - ld s0,S0_OFFSET*8(a1) /* restore context */ - ld s1,S1_OFFSET*8(a1) - ld s2,S2_OFFSET*8(a1) - ld s3,S3_OFFSET*8(a1) - ld s4,S4_OFFSET*8(a1) - ld s5,S5_OFFSET*8(a1) - ld s6,S6_OFFSET*8(a1) - ld s7,S7_OFFSET*8(a1) - ld fp,FP_OFFSET*8(a1) - ld sp,SP_OFFSET*8(a1) - ld ra,RA_OFFSET*8(a1) - ld t0,C0_EPC_OFFSET*8(a1) - dmtc0 t0,C0_EPC - ld t0,C0_SR_OFFSET*8(a1) - andi t0,SR_EXL - bnez t0,_CPU_Context_1 /* set exception level from restore context */ - li t0,~SR_EXL - mfc0 t1,C0_SR - nop - and t1,t0 - mtc0 t1,C0_SR -_CPU_Context_1: - j ra - nop -ENDFRAME(_CPU_Context_switch) - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -#if 0 -void _CPU_Context_restore( - Context_Control *new_context -) -{ -} -#endif - -FRAME(_CPU_Context_restore,sp,0,ra) - dadd a1,a0,zero - j _CPU_Context_switch_restore - nop -ENDFRAME(_CPU_Context_restore) - -EXTERN(_ISR_Nest_level, SZ_INT) -EXTERN(_Thread_Dispatch_disable_level,SZ_INT) -EXTERN(_Context_Switch_necessary,SZ_INT) -EXTERN(_ISR_Signals_to_thread_executing,SZ_INT) -.extern _Thread_Dispatch -.extern _ISR_Vector_table - -/* void __ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - */ - -#if 0 -void _ISR_Handler() -{ - /* - * This discussion ignores a lot of the ugly details in a real - * implementation such as saving enough registers/state to be - * able to do something real. Keep in mind that the goal is - * to invoke a user's ISR handler which is written in C and - * uses a certain set of registers. - * - * Also note that the exact order is to a large extent flexible. - * Hardware will dictate a sequence for a certain subset of - * _ISR_Handler while requirements for setting - */ - - /* - * At entry to "common" _ISR_Handler, the vector number must be - * available. On some CPUs the hardware puts either the vector - * number or the offset into the vector table for this ISR in a - * known place. If the hardware does not give us this information, - * then the assembly portion of RTEMS for this port will contain - * a set of distinct interrupt entry points which somehow place - * the vector number in a known place (which is safe if another - * interrupt nests this one) and branches to _ISR_Handler. - * - */ -#endif -FRAME(_ISR_Handler,sp,0,ra) -.set noreorder -#if USE_IDTKIT -/* IDT/Kit incorrectly adds 4 to EPC before returning. This compensates */ - lreg k0, R_EPC*R_SZ(sp) - daddiu k0,k0,-4 - sreg k0, R_EPC*R_SZ(sp) - lreg k0, R_CAUSE*R_SZ(sp) - li k1, ~CAUSE_BD - and k0, k1 - sreg k0, R_CAUSE*R_SZ(sp) -#endif - -/* save registers not already saved by IDT/sim */ - stackadd sp,sp,-EXCP_STACK_SIZE /* store ra on the stack */ - - sreg ra, R_RA*R_SZ(sp) - sreg v0, R_V0*R_SZ(sp) - sreg v1, R_V1*R_SZ(sp) - sreg a0, R_A0*R_SZ(sp) - sreg a1, R_A1*R_SZ(sp) - sreg a2, R_A2*R_SZ(sp) - sreg a3, R_A3*R_SZ(sp) - sreg t0, R_T0*R_SZ(sp) - sreg t1, R_T1*R_SZ(sp) - sreg t2, R_T2*R_SZ(sp) - sreg t3, R_T3*R_SZ(sp) - sreg t4, R_T4*R_SZ(sp) - sreg t5, R_T5*R_SZ(sp) - sreg t6, R_T6*R_SZ(sp) - sreg t7, R_T7*R_SZ(sp) - mflo k0 - sreg t8, R_T8*R_SZ(sp) - sreg k0, R_MDLO*R_SZ(sp) - sreg t9, R_T9*R_SZ(sp) - mfhi k0 - sreg gp, R_GP*R_SZ(sp) - sreg fp, R_FP*R_SZ(sp) - sreg k0, R_MDHI*R_SZ(sp) - .set noat - sreg AT, R_AT*R_SZ(sp) - .set at - - stackadd sp,sp,-40 /* store ra on the stack */ - sd ra,32(sp) - -/* determine if an interrupt generated this exception */ - mfc0 k0,C0_CAUSE - and k1,k0,CAUSE_EXCMASK - bnez k1,_ISR_Handler_prom_exit /* not an external interrupt, pass exception to Monitor */ - mfc0 k1,C0_SR - and k0,k1 - and k0,CAUSE_IPMASK - beq k0,zero,_ISR_Handler_quick_exit /* external interrupt not enabled, ignore */ - nop - - /* - * save some or all context on stack - * may need to save some special interrupt information for exit - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * if ( _ISR_Nest_level == 0 ) - * switch to software interrupt stack - * #endif - */ -#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - lint t0,_ISR_Nest_level - beq t0, zero, _ISR_Handler_1 - nop - /* switch stacks */ -_ISR_Handler_1: -#else - lint t0,_ISR_Nest_level -#endif - /* - * _ISR_Nest_level++; - */ - addi t0,t0,1 - sint t0,_ISR_Nest_level - /* - * _Thread_Dispatch_disable_level++; - */ - lint t1,_Thread_Dispatch_disable_level - addi t1,t1,1 - sint t1,_Thread_Dispatch_disable_level -#if 0 - nop - j _ISR_Handler_4 - nop - /* - * while ( interrupts_pending(cause_reg) ) { - * vector = BITFIELD_TO_INDEX(cause_reg); - * (*_ISR_Vector_table[ vector ])( vector ); - * } - */ -_ISR_Handler_2: -/* software interrupt priorities can be applied here */ - li t1,-1 -/* convert bit field into interrupt index */ -_ISR_Handler_3: - andi t2,t0,1 - addi t1,1 - beql t2,zero,_ISR_Handler_3 - dsrl t0,1 - li t1,7 - dsll t1,3 /* convert index to byte offset (*8) */ - la t3,_ISR_Vector_table - intadd t1,t3 - lint t1,(t1) - jalr t1 - nop - j _ISR_Handler_5 - nop -_ISR_Handler_4: - mfc0 t0,C0_CAUSE - andi t0,CAUSE_IPMASK - bne t0,zero,_ISR_Handler_2 - dsrl t0,t0,8 -_ISR_Handler_5: -#else - nop - li t1,7 - dsll t1,t1,SZ_INT_POW2 - la t3,_ISR_Vector_table - intadd t1,t3 - lint t1,(t1) - jalr t1 - nop -#endif - /* - * --_ISR_Nest_level; - */ - lint t2,_ISR_Nest_level - addi t2,t2,-1 - sint t2,_ISR_Nest_level - /* - * --_Thread_Dispatch_disable_level; - */ - lint t1,_Thread_Dispatch_disable_level - addi t1,t1,-1 - sint t1,_Thread_Dispatch_disable_level - /* - * if ( _Thread_Dispatch_disable_level || _ISR_Nest_level ) - * goto the label "exit interrupt (simple case)" - */ - or t0,t2,t1 - bne t0,zero,_ISR_Handler_exit - nop - /* - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * restore stack - * #endif - * - * if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing ) - * goto the label "exit interrupt (simple case)" - */ - lint t0,_Context_Switch_necessary - lint t1,_ISR_Signals_to_thread_executing - or t0,t0,t1 - beq t0,zero,_ISR_Handler_exit - nop - - /* - * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch - */ - jal _Thread_Dispatch - nop - /* - * prepare to get out of interrupt - * return from interrupt (maybe to _ISR_Dispatch) - * - * LABEL "exit interrupt (simple case): - * prepare to get out of interrupt - * return from interrupt - */ -_ISR_Handler_exit: - ld ra,32(sp) - stackadd sp,sp,40 - -/* restore interrupt context from stack */ - lreg k0, R_MDLO*R_SZ(sp) - mtlo k0 - lreg k0, R_MDHI*R_SZ(sp) - lreg a2, R_A2*R_SZ(sp) - mthi k0 - lreg a3, R_A3*R_SZ(sp) - lreg t0, R_T0*R_SZ(sp) - lreg t1, R_T1*R_SZ(sp) - lreg t2, R_T2*R_SZ(sp) - lreg t3, R_T3*R_SZ(sp) - lreg t4, R_T4*R_SZ(sp) - lreg t5, R_T5*R_SZ(sp) - lreg t6, R_T6*R_SZ(sp) - lreg t7, R_T7*R_SZ(sp) - lreg t8, R_T8*R_SZ(sp) - lreg t9, R_T9*R_SZ(sp) - lreg gp, R_GP*R_SZ(sp) - lreg fp, R_FP*R_SZ(sp) - lreg ra, R_RA*R_SZ(sp) - lreg a0, R_A0*R_SZ(sp) - lreg a1, R_A1*R_SZ(sp) - lreg v1, R_V1*R_SZ(sp) - lreg v0, R_V0*R_SZ(sp) - .set noat - lreg AT, R_AT*R_SZ(sp) - .set at - - stackadd sp,sp,EXCP_STACK_SIZE /* store ra on the stack */ - -#if USE_IDTKIT -/* we handled exception, so return non-zero value */ - li v0,1 -#endif - -_ISR_Handler_quick_exit: -#ifdef USE_IDTKIT - j ra -#else - eret -#endif - nop - -_ISR_Handler_prom_exit: -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif - -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif - j k0 - nop - - .set reorder - -ENDFRAME(_ISR_Handler) - - -FRAME(mips_enable_interrupts,sp,0,ra) - mfc0 t0,C0_SR /* get status reg */ - nop - or t0,t0,a0 - mtc0 t0,C0_SR /* save updated status reg */ - j ra - nop -ENDFRAME(mips_enable_interrupts) - -FRAME(mips_disable_interrupts,sp,0,ra) - mfc0 v0,C0_SR /* get status reg */ - li t1,SR_IMASK /* t1 = load interrupt mask word */ - not t0,t1 /* t0 = ~t1 */ - and t0,v0 /* clear imask bits */ - mtc0 t0,C0_SR /* save status reg */ - and v0,t1 /* mask return value (only return imask bits) */ - jr ra - nop -ENDFRAME(mips_disable_interrupts) - -FRAME(mips_enable_global_interrupts,sp,0,ra) - mfc0 t0,C0_SR /* get status reg */ - nop - ori t0,SR_IE - mtc0 t0,C0_SR /* save updated status reg */ - j ra - nop -ENDFRAME(mips_enable_global_interrupts) - -FRAME(mips_disable_global_interrupts,sp,0,ra) - li t1,SR_IE - mfc0 t0,C0_SR /* get status reg */ - not t1 - and t0,t1 - mtc0 t0,C0_SR /* save updated status reg */ - j ra - nop -ENDFRAME(mips_disable_global_interrupts) - -/* return the value of the status register in v0. Used for debugging */ -FRAME(mips_get_sr,sp,0,ra) - mfc0 v0,C0_SR - j ra - nop -ENDFRAME(mips_get_sr) - -FRAME(mips_break,sp,0,ra) -#if 1 - break 0x0 - j mips_break -#else - j ra -#endif - nop -ENDFRAME(mips_break) - -/*PAGE - * - * _CPU_Internal_threads_Idle_thread_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -FRAME(_CPU_Thread_Idle_body,sp,0,ra) - wait /* enter low power mode */ - j _CPU_Thread_Idle_body - nop -ENDFRAME(_CPU_Thread_Idle_body) - -#define VEC_CODE_LENGTH 10*4 - -/************************************************************************** -** -** init_exc_vecs() - moves the exception code into the addresses -** reserved for exception vectors -** -** UTLB Miss exception vector at address 0x80000000 -** -** General exception vector at address 0x80000080 -** -** RESET exception vector is at address 0xbfc00000 -** -***************************************************************************/ - -#define INITEXCFRM ((2*4)+4) /* ra + 2 arguments */ -FRAME(init_exc_vecs,sp,0,ra) -/* This code yanked from SIM */ -#if defined(CPU_R3000) - .set noreorder - la t1,exc_utlb_code - la t2,exc_norm_code - li t3,UT_VEC - li t4,E_VEC - li t5,VEC_CODE_LENGTH -1: - lw t6,0(t1) - lw t7,0(t2) - sw t6,0(t3) - sw t7,0(t4) - addiu t1,4 - addiu t3,4 - addiu t4,4 - subu t5,4 - bne t5,zero,1b - addiu t2,4 - move t5,ra # assumes clear_cache doesnt use t5 - li a0,UT_VEC - jal clear_cache - li a1,VEC_CODE_LENGTH - nop - li a0,E_VEC - jal clear_cache - li a1,VEC_CODE_LENGTH - move ra,t5 # restore ra - j ra - nop - .set reorder -#endif -#if defined(CPU_R4000) - .set reorder - move t5,ra # assumes clear_cache doesnt use t5 - - /* TLB exception vector */ - la t1,exc_tlb_code - li t2,T_VEC |K1BASE - li t3,VEC_CODE_LENGTH -1: - lw t6,0(t1) - addiu t1,4 - subu t3,4 - sw t6,0(t2) - addiu t2,4 - bne t3,zero,1b - - li a0,T_VEC - li a1,VEC_CODE_LENGTH - jal clear_cache - - la t1,exc_xtlb_code - li t2,X_VEC |K1BASE - li t3,VEC_CODE_LENGTH -1: - lw t6,0(t1) - addiu t1,4 - subu t3,4 - sw t6,0(t2) - addiu t2,4 - bne t3,zero,1b - - /* extended TLB exception vector */ - li a0,X_VEC - li a1,VEC_CODE_LENGTH - jal clear_cache - - /* cache error exception vector */ - la t1,exc_cache_code - li t2,C_VEC |K1BASE - li t3,VEC_CODE_LENGTH -1: - lw t6,0(t1) - addiu t1,4 - subu t3,4 - sw t6,0(t2) - addiu t2,4 - bne t3,zero,1b - - li a0,C_VEC - li a1,VEC_CODE_LENGTH - jal clear_cache - - /* normal exception vector */ - la t1,exc_norm_code - li t2,E_VEC |K1BASE - li t3,VEC_CODE_LENGTH -1: - lw t6,0(t1) - addiu t1,4 - subu t3,4 - sw t6,0(t2) - addiu t2,4 - bne t3,zero,1b - - li a0,E_VEC - li a1,VEC_CODE_LENGTH - jal clear_cache - - move ra,t5 # restore ra - j ra -#endif -ENDFRAME(init_exc_vecs) - - -#if defined(CPU_R4000) -FRAME(exc_tlb_code,sp,0,ra) -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif - -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif - j k0 - nop - -ENDFRAME(exc_tlb_code) - - -FRAME(exc_xtlb_code,sp,0,ra) -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif - -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif - j k0 - nop - -ENDFRAME(exc_xtlb_code) - - -FRAME(exc_cache_code,sp,0,ra) -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif - -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif - j k0 - nop - -ENDFRAME(exc_cache_code) - - -FRAME(exc_norm_code,sp,0,ra) - la k0, _ISR_Handler /* generic external int hndlr */ - j k0 - nop - subu sp, EXCP_STACK_SIZE /* set up local stack frame */ -ENDFRAME(exc_norm_code) -#endif - -/************************************************************************** -** -** enable_int(mask) - enables interrupts - mask is positioned so it only -** needs to be or'ed into the status reg. This -** also does some other things !!!! caution should -** be used if invoking this while in the middle -** of a debugging session where the client may have -** nested interrupts. -** -****************************************************************************/ -FRAME(enable_int,sp,0,ra) - .set noreorder - mfc0 t0,C0_SR - or a0,1 - or t0,a0 - mtc0 t0,C0_SR - j ra - nop - .set reorder -ENDFRAME(enable_int) - - -/*************************************************************************** -** -** disable_int(mask) - disable the interrupt - mask is the complement -** of the bits to be cleared - i.e. to clear ext int -** 5 the mask would be - 0xffff7fff -** -****************************************************************************/ -FRAME(disable_int,sp,0,ra) - .set noreorder - mfc0 t0,C0_SR - nop - and t0,a0 - mtc0 t0,C0_SR - j ra - nop -ENDFRAME(disable_int) - - diff --git a/c/src/exec/score/cpu/mips64orion/cpu_asm.h b/c/src/exec/score/cpu/mips64orion/cpu_asm.h deleted file mode 100644 index 08fc0975d9..0000000000 --- a/c/src/exec/score/cpu/mips64orion/cpu_asm.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * cpu_asm.h - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from source copyrighted as follows: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ -/* @(#)cpu_asm.h 08/20/96 1.2 */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - -/* pull in the generated offsets */ - -/* #include <rtems/score/offsets.h> */ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -#define R_FP0 0 -#define R_FP1 1 -#define R_FP2 2 -#define R_FP3 3 -#define R_FP4 4 -#define R_FP5 5 -#define R_FP6 6 -#define R_FP7 7 -#define R_FP8 8 -#define R_FP9 9 -#define R_FP10 10 -#define R_FP11 11 -#define R_FP12 12 -#define R_FP13 13 -#define R_FP14 14 -#define R_FP15 15 -#define R_FP16 16 -#define R_FP17 17 -#define R_FP18 18 -#define R_FP19 19 -#define R_FP20 20 -#define R_FP21 21 -#define R_FP22 22 -#define R_FP23 23 -#define R_FP24 24 -#define R_FP25 25 -#define R_FP26 26 -#define R_FP27 27 -#define R_FP28 28 -#define R_FP29 29 -#define R_FP30 30 -#define R_FP31 31 - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/c/src/exec/score/cpu/mips64orion/idtcpu.h b/c/src/exec/score/cpu/mips64orion/idtcpu.h deleted file mode 100644 index f921e85ef6..0000000000 --- a/c/src/exec/score/cpu/mips64orion/idtcpu.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - -Based upon IDT provided code with the following release: - -This source code has been made available to you by IDT on an AS-IS -basis. Anyone receiving this source is licensed under IDT copyrights -to use it in any way he or she deems fit, including copying it, -modifying it, compiling it, and redistributing it either with or -without modifications. No license under IDT patents or patent -applications is to be implied by the copyright license. - -Any user of this software should understand that IDT cannot provide -technical support for this software and will not be responsible for -any consequences resulting from the use of this software. - -Any person who transfers this source code or any derivative work must -include the IDT copyright notice, this paragraph, and the preceeding -two paragraphs in the transferred software. - -COPYRIGHT IDT CORPORATION 1996 -LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - - $Id$ -*/ - -/* -** idtcpu.h -- cpu related defines -*/ - -#ifndef _IDTCPU_H__ -#define _IDTCPU_H__ - -/* - * 950313: Ketan added Register definition for XContext reg. - * added define for WAIT instruction. - * 950421: Ketan added Register definition for Config reg (R3081) - */ - -/* -** memory configuration and mapping -*/ -#define K0BASE 0x80000000 -#define K0SIZE 0x20000000 -#define K1BASE 0xa0000000 -#define K1SIZE 0x20000000 -#define K2BASE 0xc0000000 -#define K2SIZE 0x20000000 -#if defined(CPU_R4000) -#define KSBASE 0xe0000000 -#define KSSIZE 0x20000000 -#endif - -#define KUBASE 0 -#define KUSIZE 0x80000000 - -/* -** Exception Vectors -*/ -#if defined(CPU_R3000) -#define UT_VEC K0BASE /* utlbmiss vector */ -#define E_VEC (K0BASE+0x80) /* exception vevtor */ -#endif -#if defined(CPU_R4000) -#define T_VEC (K0BASE+0x000) /* tlbmiss vector */ -#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ -#define C_VEC (K0BASE+0x100) /* cache error vector */ -#define E_VEC (K0BASE+0x180) /* exception vector */ -#endif -#define R_VEC (K1BASE+0x1fc00000) /* reset vector */ - -/* -** Address conversion macros -*/ -#ifdef CLANGUAGE -#define CAST(as) (as) -#else -#define CAST(as) -#endif -#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */ -#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */ -#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */ -#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */ -#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to kseg0 */ -#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to kseg1 */ - -/* -** Cache size constants -*/ -#define MINCACHE 0x200 /* 512 For 3041. */ -#define MAXCACHE 0x40000 /* 256*1024 256k */ - -#if defined(CPU_R4000) -/* R4000 configuration register definitions */ -#define CFG_CM 0x80000000 /* Master-Checker mode */ -#define CFG_ECMASK 0x70000000 /* System Clock Ratio */ -#define CFG_ECBY2 0x00000000 /* divide by 2 */ -#define CFG_ECBY3 0x10000000 /* divide by 3 */ -#define CFG_ECBY4 0x20000000 /* divide by 4 */ -#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */ -#define CFG_EPD 0x00000000 /* D */ -#define CFG_EPDDX 0x01000000 /* DDX */ -#define CFG_EPDDXX 0x02000000 /* DDXX */ -#define CFG_EPDXDX 0x03000000 /* DXDX */ -#define CFG_EPDDXXX 0x04000000 /* DDXXX */ -#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */ -#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */ -#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */ -#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */ -#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */ -#define CFG_SBSHIFT 22 -#define CFG_SB4 0x00000000 /* 4 words */ -#define CFG_SB8 0x00400000 /* 8 words */ -#define CFG_SB16 0x00800000 /* 16 words */ -#define CFG_SB32 0x00c00000 /* 32 words */ -#define CFG_SS 0x00200000 /* Split secondary cache */ -#define CFG_SW 0x00100000 /* Secondary cache port width */ -#define CFG_EWMASK 0x000c0000 /* System port width */ -#define CFG_EWSHIFT 18 -#define CFG_EW64 0x00000000 /* 64 bit */ -#define CFG_EW32 0x00010000 /* 32 bit */ -#define CFG_SC 0x00020000 /* Secondary cache absent */ -#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */ -#define CFG_BE 0x00008000 /* Big Endian */ -#define CFG_EM 0x00004000 /* ECC mode enable */ -#define CFG_EB 0x00002000 /* Block ordering */ -#define CFG_ICMASK 0x00000e00 /* Instruction cache size */ -#define CFG_ICSHIFT 9 -#define CFG_DCMASK 0x000001c0 /* Data cache size */ -#define CFG_DCSHIFT 6 -#define CFG_IB 0x00000020 /* Instruction cache block size */ -#define CFG_DB 0x00000010 /* Data cache block size */ -#define CFG_CU 0x00000008 /* Update on Store Conditional */ -#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */ - -/* - * R4000 primary cache mode - */ -#define CFG_C_UNCACHED 2 -#define CFG_C_NONCOHERENT 3 -#define CFG_C_COHERENTXCL 4 -#define CFG_C_COHERENTXCLW 5 -#define CFG_C_COHERENTUPD 6 - -/* - * R4000 cache operations (should be in assembler...?) - */ -#define Index_Invalidate_I 0x0 /* 0 0 */ -#define Index_Writeback_Inv_D 0x1 /* 0 1 */ -#define Index_Invalidate_SI 0x2 /* 0 2 */ -#define Index_Writeback_Inv_SD 0x3 /* 0 3 */ -#define Index_Load_Tag_I 0x4 /* 1 0 */ -#define Index_Load_Tag_D 0x5 /* 1 1 */ -#define Index_Load_Tag_SI 0x6 /* 1 2 */ -#define Index_Load_Tag_SD 0x7 /* 1 3 */ -#define Index_Store_Tag_I 0x8 /* 2 0 */ -#define Index_Store_Tag_D 0x9 /* 2 1 */ -#define Index_Store_Tag_SI 0xA /* 2 2 */ -#define Index_Store_Tag_SD 0xB /* 2 3 */ -#define Create_Dirty_Exc_D 0xD /* 3 1 */ -#define Create_Dirty_Exc_SD 0xF /* 3 3 */ -#define Hit_Invalidate_I 0x10 /* 4 0 */ -#define Hit_Invalidate_D 0x11 /* 4 1 */ -#define Hit_Invalidate_SI 0x12 /* 4 2 */ -#define Hit_Invalidate_SD 0x13 /* 4 3 */ -#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ -#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ -#define Fill_I 0x14 /* 5 0 */ -#define Hit_Writeback_D 0x19 /* 6 1 */ -#define Hit_Writeback_SD 0x1B /* 6 3 */ -#define Hit_Writeback_I 0x18 /* 6 0 */ -#define Hit_Set_Virtual_SI 0x1E /* 7 2 */ -#define Hit_Set_Virtual_SD 0x1F /* 7 3 */ - -#ifndef WAIT -#define WAIT .word 0x42000020 -#endif WAIT - -#ifndef wait -#define wait .word 0x42000020 -#endif wait - -#endif - -/* -** TLB resource defines -*/ -#if defined(CPU_R3000) -#define N_TLB_ENTRIES 64 -#define TLB_PGSIZE 0x1000 -#define RANDBASE 8 -#define TLBLO_PFNMASK 0xfffff000 -#define TLBLO_PFNSHIFT 12 -#define TLBLO_N 0x800 /* non-cacheable */ -#define TLBLO_D 0x400 /* writeable */ -#define TLBLO_V 0x200 /* valid bit */ -#define TLBLO_G 0x100 /* global access bit */ - -#define TLBHI_VPNMASK 0xfffff000 -#define TLBHI_VPNSHIFT 12 -#define TLBHI_PIDMASK 0xfc0 -#define TLBHI_PIDSHIFT 6 -#define TLBHI_NPID 64 - -#define TLBINX_PROBE 0x80000000 -#define TLBINX_INXMASK 0x00003f00 -#define TLBINX_INXSHIFT 8 - -#define TLBRAND_RANDMASK 0x00003f00 -#define TLBRAND_RANDSHIFT 8 - -#define TLBCTXT_BASEMASK 0xffe00000 -#define TLBCTXT_BASESHIFT 21 - -#define TLBCTXT_VPNMASK 0x001ffffc -#define TLBCTXT_VPNSHIFT 2 -#endif -#if defined(CPU_R4000) -#define N_TLB_ENTRIES 48 - -#define TLBHI_VPN2MASK 0xffffe000 -#define TLBHI_PIDMASK 0x000000ff -#define TLBHI_NPID 256 - -#define TLBLO_PFNMASK 0x3fffffc0 -#define TLBLO_PFNSHIFT 6 -#define TLBLO_D 0x00000004 /* writeable */ -#define TLBLO_V 0x00000002 /* valid bit */ -#define TLBLO_G 0x00000001 /* global access bit */ -#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */ -#define TLBLO_CSHIFT 3 - -#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT) -#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT) -#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT) -#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT) -#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT) - -#define TLBINX_PROBE 0x80000000 -#define TLBINX_INXMASK 0x0000003f - -#define TLBRAND_RANDMASK 0x0000003f - -#define TLBCTXT_BASEMASK 0xff800000 -#define TLBCTXT_BASESHIFT 23 - -#define TLBCTXT_VPN2MASK 0x007ffff0 -#define TLBCTXT_VPN2SHIFT 4 - -#define TLBPGMASK_MASK 0x01ffe000 -#endif - -#if defined(CPU_R3000) -#define SR_CUMASK 0xf0000000 /* coproc usable bits */ -#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ -#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ -#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ -#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ - -#define SR_BEV 0x00400000 /* use boot exception vectors */ - -/* Cache control bits */ -#define SR_TS 0x00200000 /* TLB shutdown */ -#define SR_PE 0x00100000 /* cache parity error */ -#define SR_CM 0x00080000 /* cache miss */ -#define SR_PZ 0x00040000 /* cache parity zero */ -#define SR_SWC 0x00020000 /* swap cache */ -#define SR_ISC 0x00010000 /* Isolate data cache */ - -/* -** status register interrupt masks and bits -*/ - -#define SR_IMASK 0x0000ff00 /* Interrupt mask */ -#define SR_IMASK8 0x00000000 /* mask level 8 */ -#define SR_IMASK7 0x00008000 /* mask level 7 */ -#define SR_IMASK6 0x0000c000 /* mask level 6 */ -#define SR_IMASK5 0x0000e000 /* mask level 5 */ -#define SR_IMASK4 0x0000f000 /* mask level 4 */ -#define SR_IMASK3 0x0000f800 /* mask level 3 */ -#define SR_IMASK2 0x0000fc00 /* mask level 2 */ -#define SR_IMASK1 0x0000fe00 /* mask level 1 */ -#define SR_IMASK0 0x0000ff00 /* mask level 0 */ - -#define SR_IMASKSHIFT 8 - -#define SR_IBIT8 0x00008000 /* bit level 8 */ -#define SR_IBIT7 0x00004000 /* bit level 7 */ -#define SR_IBIT6 0x00002000 /* bit level 6 */ -#define SR_IBIT5 0x00001000 /* bit level 5 */ -#define SR_IBIT4 0x00000800 /* bit level 4 */ -#define SR_IBIT3 0x00000400 /* bit level 3 */ -#define SR_IBIT2 0x00000200 /* bit level 2 */ -#define SR_IBIT1 0x00000100 /* bit level 1 */ - -#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */ -#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */ -#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */ -#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */ -#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */ -#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ -#endif - -#if defined(CPU_R4000) -#define SR_CUMASK 0xf0000000 /* coproc usable bits */ -#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ -#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ -#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ -#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ - -#define SR_RP 0x08000000 /* Reduced power operation */ -#define SR_FR 0x04000000 /* Additional floating point registers */ -#define SR_RE 0x02000000 /* Reverse endian in user mode */ - -#define SR_BEV 0x00400000 /* Use boot exception vectors */ -#define SR_TS 0x00200000 /* TLB shutdown */ -#define SR_SR 0x00100000 /* Soft reset */ -#define SR_CH 0x00040000 /* Cache hit */ -#define SR_CE 0x00020000 /* Use cache ECC */ -#define SR_DE 0x00010000 /* Disable cache exceptions */ - -/* -** status register interrupt masks and bits -*/ - -#define SR_IMASK 0x0000ff00 /* Interrupt mask */ -#define SR_IMASK8 0x00000000 /* mask level 8 */ -#define SR_IMASK7 0x00008000 /* mask level 7 */ -#define SR_IMASK6 0x0000c000 /* mask level 6 */ -#define SR_IMASK5 0x0000e000 /* mask level 5 */ -#define SR_IMASK4 0x0000f000 /* mask level 4 */ -#define SR_IMASK3 0x0000f800 /* mask level 3 */ -#define SR_IMASK2 0x0000fc00 /* mask level 2 */ -#define SR_IMASK1 0x0000fe00 /* mask level 1 */ -#define SR_IMASK0 0x0000ff00 /* mask level 0 */ - -#define SR_IMASKSHIFT 8 - -#define SR_IBIT8 0x00008000 /* bit level 8 */ -#define SR_IBIT7 0x00004000 /* bit level 7 */ -#define SR_IBIT6 0x00002000 /* bit level 6 */ -#define SR_IBIT5 0x00001000 /* bit level 5 */ -#define SR_IBIT4 0x00000800 /* bit level 4 */ -#define SR_IBIT3 0x00000400 /* bit level 3 */ -#define SR_IBIT2 0x00000200 /* bit level 2 */ -#define SR_IBIT1 0x00000100 /* bit level 1 */ - -#define SR_KSMASK 0x00000018 /* Kernel mode mask */ -#define SR_KSUSER 0x00000010 /* User mode */ -#define SR_KSSUPER 0x00000008 /* Supervisor mode */ -#define SR_KSKERNEL 0x00000000 /* Kernel mode */ -#define SR_ERL 0x00000004 /* Error level */ -#define SR_EXL 0x00000002 /* Exception level */ -#define SR_IE 0x00000001 /* Interrupts enabled */ -#endif - - - -/* - * Cause Register - */ -#define CAUSE_BD 0x80000000 /* Branch delay slot */ -#define CAUSE_CEMASK 0x30000000 /* coprocessor error */ -#define CAUSE_CESHIFT 28 - - -#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */ -#define CAUSE_IPSHIFT 8 - -#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */ -#define CAUSE_EXCSHIFT 2 - -#ifndef XDS -/* -** Coprocessor 0 registers -*/ -#define C0_INX $0 /* tlb index */ -#define C0_RAND $1 /* tlb random */ -#if defined(CPU_R3000) -#define C0_TLBLO $2 /* tlb entry low */ -#endif -#if defined(CPU_R4000) -#define C0_TLBLO0 $2 /* tlb entry low 0 */ -#define C0_TLBLO1 $3 /* tlb entry low 1 */ -#endif - -#define C0_CTXT $4 /* tlb context */ - -#if defined(CPU_R4000) -#define C0_PAGEMASK $5 /* tlb page mask */ -#define C0_WIRED $6 /* number of wired tlb entries */ -#endif - -#define C0_BADVADDR $8 /* bad virtual address */ - -#if defined(CPU_R4000) -#define C0_COUNT $9 /* cycle count */ -#endif - -#define C0_TLBHI $10 /* tlb entry hi */ - -#if defined(CPU_R4000) -#define C0_COMPARE $11 /* cyccle count comparator */ -#endif - -#define C0_SR $12 /* status register */ -#define C0_CAUSE $13 /* exception cause */ -#define C0_EPC $14 /* exception pc */ -#define C0_PRID $15 /* revision identifier */ - -#if defined(CPU_R3000) -#define C0_CONFIG $3 /* configuration register R3081*/ -#endif - -#if defined(CPU_R4000) -#define C0_CONFIG $16 /* configuration register */ -#define C0_LLADDR $17 /* linked load address */ -#define C0_WATCHLO $18 /* watchpoint trap register */ -#define C0_WATCHHI $19 /* watchpoint trap register */ -#define C0_XCTXT $20 /* extended tlb context */ -#define C0_ECC $26 /* secondary cache ECC control */ -#define C0_CACHEERR $27 /* cache error status */ -#define C0_TAGLO $28 /* cache tag lo */ -#define C0_TAGHI $29 /* cache tag hi */ -#define C0_ERRPC $30 /* cache error pc */ -#endif - -#endif XDS - -#ifdef R4650 -#define IWATCH $18 -#define DWATCH $19 -#define IBASE $0 -#define IBOUND $1 -#define DBASE $2 -#define DBOUND $3 -#define CALG $17 -#endif - -#endif /* _IDTCPU_H__ */ - diff --git a/c/src/exec/score/cpu/mips64orion/idtmon.h b/c/src/exec/score/cpu/mips64orion/idtmon.h deleted file mode 100644 index 2dacfe052e..0000000000 --- a/c/src/exec/score/cpu/mips64orion/idtmon.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - -Based upon IDT provided code with the following release: - -This source code has been made available to you by IDT on an AS-IS -basis. Anyone receiving this source is licensed under IDT copyrights -to use it in any way he or she deems fit, including copying it, -modifying it, compiling it, and redistributing it either with or -without modifications. No license under IDT patents or patent -applications is to be implied by the copyright license. - -Any user of this software should understand that IDT cannot provide -technical support for this software and will not be responsible for -any consequences resulting from the use of this software. - -Any person who transfers this source code or any derivative work must -include the IDT copyright notice, this paragraph, and the preceeding -two paragraphs in the transferred software. - -COPYRIGHT IDT CORPORATION 1996 -LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - - $Id$ -*/ - -/* -** idtmon.h - General header file for the IDT Prom Monitor -** -** Copyright 1989 Integrated Device Technology, Inc. -** All Rights Reserved. -** -** June 1989 - D.Cahoon -*/ -#ifndef __IDTMON_H__ -#define __IDTMON_H__ - -/* -** P_STACKSIZE is the size of the Prom Stack. -** the prom stack grows downward -*/ -#define P_STACKSIZE 0x2000 /* sets stack size to 8k */ - -/* -** M_BUSWIDTH -** Memory bus width (including bank interleaving) in bytes -** used when doing memory sizing to prevent bus capacitance -** reporting ghost memory locations -*/ -#if defined(CPU_R3000) -#define M_BUSWIDTH 8 /* 32bit memory bank interleaved */ -#endif -#if defined(CPU_R4000) -#define M_BUSWIDTH 16 /* 64 bit memory bank interleaved */ -#endif - -/* -** this is the default value for the number of bytes to add in calculating -** the checksums in the checksum command -*/ -#define CHK_SUM_CNT 0x20000 /* number of bytes to calc chksum for */ - -/* -** Monitor modes -*/ -#define MODE_MONITOR 5 /* IDT Prom Monitor is executing */ -#define MODE_USER 0xa /* USER is executing */ - -/* -** memory reference widths -*/ -#define SW_BYTE 1 -#define SW_HALFWORD 2 -#define SW_WORD 4 -#define SW_TRIBYTEL 12 -#define SW_TRIBYTER 20 - -#ifdef CPU_R4000 -/* -** definitions for select_cache call -*/ -#define DCACHE 0 -#define ICACHE 1 -#define SCACHE 2 - -#endif - -#ifndef ASM -typedef struct { - unsigned int mem_size; - unsigned int icache_size; - unsigned int dcache_size; -#ifdef CPU_R4000 - unsigned int scache_size; -#endif - - } mem_config; - -#endif - -/* -** general equates for diagnostics and boolean functions -*/ -#define PASS 0 -#define FAIL 1 - -#ifndef TRUE -#define TRUE 1 -#endif TRUE -#ifndef NULL -#define NULL 0 -#endif NULL - -#ifndef FALSE -#define FALSE 0 -#endif FALSE - - -/* -** portablility equates -*/ - -#ifndef BOOL -#define BOOL unsigned int -#endif BOOL - -#ifndef GLOBAL -#define GLOBAL /**/ -#endif GLOBAL - -#ifndef MLOCAL -#define MLOCAL static -#endif MLOCAL - - -#ifdef XDS -#define CONST const -#else -#define CONST -#endif XDS - -#define u_char unsigned char -#define u_short unsigned short -#define u_int unsigned int -/* -** assembly instructions for compatability between xds and mips -*/ -#ifndef XDS -#define sllv sll -#define srlv srl -#endif XDS -/* -** debugger macros for assembly language routines. Allows the -** programmer to set up the necessary stack frame info -** required by debuggers to do stack traces. -*/ - -#ifndef XDS -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl name; \ - .ent name; \ -name:; \ - .frame frm_reg,offset,ret_reg -#define ENDFRAME(name) \ - .end name -#else -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl _##name;\ -_##name: -#define ENDFRAME(name) -#endif XDS -#endif /* __IDTMON_H__ */ diff --git a/c/src/exec/score/cpu/mips64orion/iregdef.h b/c/src/exec/score/cpu/mips64orion/iregdef.h deleted file mode 100644 index f0953da852..0000000000 --- a/c/src/exec/score/cpu/mips64orion/iregdef.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - -Based upon IDT provided code with the following release: - -This source code has been made available to you by IDT on an AS-IS -basis. Anyone receiving this source is licensed under IDT copyrights -to use it in any way he or she deems fit, including copying it, -modifying it, compiling it, and redistributing it either with or -without modifications. No license under IDT patents or patent -applications is to be implied by the copyright license. - -Any user of this software should understand that IDT cannot provide -technical support for this software and will not be responsible for -any consequences resulting from the use of this software. - -Any person who transfers this source code or any derivative work must -include the IDT copyright notice, this paragraph, and the preceeding -two paragraphs in the transferred software. - -COPYRIGHT IDT CORPORATION 1996 -LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - - $Id$ -*/ - -/* -** iregdef.h - IDT R3000 register structure header file -** -** Copyright 1989 Integrated Device Technology, Inc -** All Rights Reserved -** -*/ -#ifndef __IREGDEF_H__ -#define __IREGDEF_H__ - -/* - * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves - * added Register definition for XContext reg. - * Look towards end of this file. - */ -/* -** register names -*/ -#define r0 $0 -#define r1 $1 -#define r2 $2 -#define r3 $3 -#define r4 $4 -#define r5 $5 -#define r6 $6 -#define r7 $7 -#define r8 $8 -#define r9 $9 -#define r10 $10 -#define r11 $11 -#define r12 $12 -#define r13 $13 - -#define r14 $14 -#define r15 $15 -#define r16 $16 -#define r17 $17 -#define r18 $18 -#define r19 $19 -#define r20 $20 -#define r21 $21 -#define r22 $22 -#define r23 $23 -#define r24 $24 -#define r25 $25 -#define r26 $26 -#define r27 $27 -#define r28 $28 -#define r29 $29 -#define r30 $30 -#define r31 $31 - -#define fp0 $f0 -#define fp1 $f1 -#define fp2 $f2 -#define fp3 $f3 -#define fp4 $f4 -#define fp5 $f5 -#define fp6 $f6 -#define fp7 $f7 -#define fp8 $f8 -#define fp9 $f9 -#define fp10 $f10 -#define fp11 $f11 -#define fp12 $f12 -#define fp13 $f13 -#define fp14 $f14 -#define fp15 $f15 -#define fp16 $f16 -#define fp17 $f17 -#define fp18 $f18 -#define fp19 $f19 -#define fp20 $f20 -#define fp21 $f21 -#define fp22 $f22 -#define fp23 $f23 -#define fp24 $f24 -#define fp25 $f25 -#define fp26 $f26 -#define fp27 $f27 -#define fp28 $f28 -#define fp29 $f29 -#define fp30 $f30 -#define fp31 $f31 - -#define fcr0 $0 -#define fcr30 $30 -#define fcr31 $31 - -#define zero $0 /* wired zero */ -#define AT $at /* assembler temp */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers a0-a3 */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved t0-t9 */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved s0-s8 */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 -#define t9 $25 -#define k0 $26 /* kernel usage */ -#define k1 $27 /* kernel usage */ -#define gp $28 /* sdata pointer */ -#define sp $29 /* stack pointer */ -#define s8 $30 /* yet another saved reg for the callee */ -#define fp $30 /* frame pointer - this is being phased out by MIPS */ -#define ra $31 /* return address */ - - -/* -** relative position of registers in save reg area -*/ -#define R_R0 0 -#define R_R1 1 -#define R_R2 2 -#define R_R3 3 -#define R_R4 4 -#define R_R5 5 -#define R_R6 6 -#define R_R7 7 -#define R_R8 8 -#define R_R9 9 -#define R_R10 10 -#define R_R11 11 -#define R_R12 12 -#define R_R13 13 -#define R_R14 14 -#define R_R15 15 -#define R_R16 16 -#define R_R17 17 -#define R_R18 18 -#define R_R19 19 -#define R_R20 20 -#define R_R21 21 -#define R_R22 22 -#define R_R23 23 -#define R_R24 24 -#define R_R25 25 -#define R_R26 26 -#define R_R27 27 -#define R_R28 28 -#define R_R29 29 -#define R_R30 30 -#define R_R31 31 -#define R_F0 32 -#define R_F1 33 -#define R_F2 34 -#define R_F3 35 -#define R_F4 36 -#define R_F5 37 -#define R_F6 38 -#define R_F7 39 -#define R_F8 40 -#define R_F9 41 -#define R_F10 42 -#define R_F11 43 -#define R_F12 44 -#define R_F13 45 -#define R_F14 46 -#define R_F15 47 -#define R_F16 48 -#define R_F17 49 -#define R_F18 50 -#define R_F19 51 -#define R_F20 52 -#define R_F21 53 -#define R_F22 54 -#define R_F23 55 -#define R_F24 56 -#define R_F25 57 -#define R_F26 58 -#define R_F27 59 -#define R_F28 60 -#define R_F29 61 -#define R_F30 62 -#define R_F31 63 -#define NCLIENTREGS 64 -#define R_EPC 64 -#define R_MDHI 65 -#define R_MDLO 66 -#define R_SR 67 -#define R_CAUSE 68 -#define R_TLBHI 69 -#if defined(CPU_R3000) -#define R_TLBLO 70 -#endif -#if defined(CPU_R4000) -#define R_TLBLO0 70 -#endif -#define R_BADVADDR 71 -#define R_INX 72 -#define R_RAND 73 -#define R_CTXT 74 -#define R_EXCTYPE 75 -#define R_MODE 76 -#define R_PRID 77 -#define R_FCSR 78 -#define R_FEIR 79 -#if defined(CPU_R3000) -#define NREGS 80 -#endif -#if defined(CPU_R4000) -#define R_TLBLO1 80 -#define R_PAGEMASK 81 -#define R_WIRED 82 -#define R_COUNT 83 -#define R_COMPARE 84 -#define R_CONFIG 85 -#define R_LLADDR 86 -#define R_WATCHLO 87 -#define R_WATCHHI 88 -#define R_ECC 89 -#define R_CACHEERR 90 -#define R_TAGLO 91 -#define R_TAGHI 92 -#define R_ERRPC 93 -#define R_XCTXT 94 /* Ketan added from SIM64bit */ - -#define NREGS 95 -#endif - -/* -** For those who like to think in terms of the compiler names for the regs -*/ -#define R_ZERO R_R0 -#define R_AT R_R1 -#define R_V0 R_R2 -#define R_V1 R_R3 -#define R_A0 R_R4 -#define R_A1 R_R5 -#define R_A2 R_R6 -#define R_A3 R_R7 -#define R_T0 R_R8 -#define R_T1 R_R9 -#define R_T2 R_R10 -#define R_T3 R_R11 -#define R_T4 R_R12 -#define R_T5 R_R13 -#define R_T6 R_R14 -#define R_T7 R_R15 -#define R_S0 R_R16 -#define R_S1 R_R17 -#define R_S2 R_R18 -#define R_S3 R_R19 -#define R_S4 R_R20 -#define R_S5 R_R21 -#define R_S6 R_R22 -#define R_S7 R_R23 -#define R_T8 R_R24 -#define R_T9 R_R25 -#define R_K0 R_R26 -#define R_K1 R_R27 -#define R_GP R_R28 -#define R_SP R_R29 -#define R_FP R_R30 -#define R_RA R_R31 - -/* Ketan added the following */ -#ifdef CPU_R3000 -#define sreg sw -#define lreg lw -#define rmfc0 mfc0 -#define rmtc0 mtc0 -#define R_SZ 4 -#endif CPU_R3000 - -#ifdef CPU_R4000 -#if __mips < 3 -#define sreg sw -#define lreg lw -#define rmfc0 mfc0 -#define rmtc0 mtc0 -#define R_SZ 4 -#else -#define sreg sd -#define lreg ld -#define rmfc0 dmfc0 -#define rmtc0 dmtc0 -#define R_SZ 8 -#endif -#endif CPU_R4000 -/* Ketan till here */ - -#endif /* __IREGDEF_H__ */ - diff --git a/c/src/exec/score/cpu/mips64orion/rtems/.cvsignore b/c/src/exec/score/cpu/mips64orion/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/mips64orion/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/mips64orion/rtems/score/.cvsignore b/c/src/exec/score/cpu/mips64orion/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/mips64orion/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/mips64orion/rtems/score/cpu.h b/c/src/exec/score/cpu/mips64orion/rtems/score/cpu.h deleted file mode 100644 index 3138e331f1..0000000000 --- a/c/src/exec/score/cpu/mips64orion/rtems/score/cpu.h +++ /dev/null @@ -1,996 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the IDT 4650 - * processor. - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from source copyrighted as follows: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ -/* @(#)cpu.h 08/29/96 1.7 */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/mips64orion.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -extern int mips_disable_interrupts( void ); -extern void mips_enable_interrupts( int _level ); -extern int mips_disable_global_interrupts( void ); -extern void mips_enable_global_interrupts( void ); -extern void mips_fatal_error ( int error ); - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "MIPS64ORION_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( MIPS64ORION_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -/* we can use the low power wait instruction for the IDLE thread */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -/* our stack grows down */ -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -/* our cache line size is 16 bytes */ -#if __GNUC__ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) -#else -#define CPU_STRUCTURE_ALIGNMENT -#endif - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ -typedef struct { - unsigned64 s0; - unsigned64 s1; - unsigned64 s2; - unsigned64 s3; - unsigned64 s4; - unsigned64 s5; - unsigned64 s6; - unsigned64 s7; - unsigned64 sp; - unsigned64 fp; - unsigned64 ra; - unsigned64 c0_sr; - unsigned64 c0_epc; -} Context_Control; - -/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ -typedef struct { - unsigned32 fp0; - unsigned32 fp1; - unsigned32 fp2; - unsigned32 fp3; - unsigned32 fp4; - unsigned32 fp5; - unsigned32 fp6; - unsigned32 fp7; - unsigned32 fp8; - unsigned32 fp9; - unsigned32 fp10; - unsigned32 fp11; - unsigned32 fp12; - unsigned32 fp13; - unsigned32 fp14; - unsigned32 fp15; - unsigned32 fp16; - unsigned32 fp17; - unsigned32 fp18; - unsigned32 fp19; - unsigned32 fp20; - unsigned32 fp21; - unsigned32 fp22; - unsigned32 fp23; - unsigned32 fp24; - unsigned32 fp25; - unsigned32 fp26; - unsigned32 fp27; - unsigned32 fp28; - unsigned32 fp29; - unsigned32 fp30; - unsigned32 fp31; -} Context_Control_fp; - -typedef struct { - unsigned32 special_interrupt_register; -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the mips processor specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - - unsigned32 clicks_per_microsecond; -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access MIPS64ORION specific additions to the CPU Table - */ - -#define rtems_cpu_configuration_get_clicks_per_microsecond() \ - (_CPU_Table.clicks_per_microsecond) - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 8 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (2048*sizeof(unsigned32)) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _int_level ) \ - do{ \ - _int_level = mips_disable_interrupts(); \ - }while(0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - do{ \ - mips_enable_interrupts(_level); \ - }while(0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _xlevel ) \ - do{ \ - int _scratch; \ - _CPU_ISR_Enable( _xlevel ); \ - _CPU_ISR_Disable( _scratch ); \ - }while(0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ -extern void _CPU_ISR_Set_level( unsigned32 _new_level ); - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - */ - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - { \ - unsigned32 _stack_tmp = (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \ - _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \ - (_the_context)->sp = _stack_tmp; \ - (_the_context)->fp = _stack_tmp; \ - (_the_context)->ra = (unsigned64)_entry_point; \ - (_the_context)->c0_sr = 0; \ - } - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * A floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - { \ - mips_disable_global_interrupts(); \ - mips_fatal_error(_error); \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -/* - * Miscellaneous prototypes - * - * NOTE: The names should have mips64orion in them. - */ - -void disable_int( unsigned32 mask ); -void enable_int( unsigned32 mask ); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/mips64orion/rtems/score/mips64orion.h b/c/src/exec/score/cpu/mips64orion/rtems/score/mips64orion.h deleted file mode 100644 index 2ec96da0a4..0000000000 --- a/c/src/exec/score/cpu/mips64orion/rtems/score/mips64orion.h +++ /dev/null @@ -1,83 +0,0 @@ -/* mips64orion.h - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from source copyrighted as follows: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ -/* @(#)mips64orion.h 08/29/96 1.3 */ - -#ifndef _INCLUDE_MIPS64ORION_h -#define _INCLUDE_MIPS64ORION_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "no cpu" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define MIPS64ORION_HAS_FPU 1 - -#elif defined(R4650) - -#define CPU_MODEL_NAME "R4650" -#define MIPS64ORION_HAS_FPU 1 - -#elif defined(R4600) - -#define CPU_MODEL_NAME "R4600" -#define MIPS64ORION_HAS_FPU 1 - -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "MIPS R46xxx" - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_MIPS64ORION_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/mips64orion/rtems/score/types.h b/c/src/exec/score/cpu/mips64orion/rtems/score/types.h deleted file mode 100644 index 9d82f2a5d0..0000000000 --- a/c/src/exec/score/cpu/mips64orion/rtems/score/types.h +++ /dev/null @@ -1,72 +0,0 @@ -/* mipstypes.h - * - * This include file contains type definitions pertaining to the IDT 4650 - * processor family. - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ -/* @(#)mipstypes.h 08/20/96 1.4 */ - -#ifndef __MIPS_TYPES_h -#define __MIPS_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void mips_isr; -typedef void ( *mips_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/no_cpu/.cvsignore b/c/src/exec/score/cpu/no_cpu/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/no_cpu/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/no_cpu/ChangeLog b/c/src/exec/score/cpu/no_cpu/ChangeLog deleted file mode 100644 index 235265ac83..0000000000 --- a/c/src/exec/score/cpu/no_cpu/ChangeLog +++ /dev/null @@ -1,105 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/no_cputypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-25 Joel Sherrill <joel.sherrill@OARcorp.com> - - * rtems/score/no_cpu.h: Modified so there are fewer and - more consistent variations on "no cpu" so it is easier - to sed the source as the starting point for a new port. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/no_cpu/Makefile.am b/c/src/exec/score/cpu/no_cpu/Makefile.am deleted file mode 100644 index a9752fc567..0000000000 --- a/c/src/exec/score/cpu/no_cpu/Makefile.am +++ /dev/null @@ -1,52 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/no_cpu.h \ - rtems/score/cpu_asm.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c cpu_asm.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.c - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/no_cpu/asm.h b/c/src/exec/score/cpu/no_cpu/asm.h deleted file mode 100644 index 3e9164a28c..0000000000 --- a/c/src/exec/score/cpu/no_cpu/asm.h +++ /dev/null @@ -1,101 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __NO_CPU_ASM_h -#define __NO_CPU_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/no_cpu.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/no_cpu/configure.ac b/c/src/exec/score/cpu/no_cpu/configure.ac deleted file mode 100644 index b0e8644da5..0000000000 --- a/c/src/exec/score/cpu/no_cpu/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-no_cpu],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.c]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/no_cpu/cpu.c b/c/src/exec/score/cpu/no_cpu/cpu.c deleted file mode 100644 index 9df97623ba..0000000000 --- a/c/src/exec/score/cpu/no_cpu/cpu.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * XXX CPU Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; - - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ - - return 0; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Install_interrupt_stack( void ) -{ -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Thread_Idle_body( void ) -{ - - for( ; ; ) - /* insert your "halt" instruction here */ ; -} diff --git a/c/src/exec/score/cpu/no_cpu/cpu_asm.c b/c/src/exec/score/cpu/no_cpu/cpu_asm.c deleted file mode 100644 index 2ee4067f6c..0000000000 --- a/c/src/exec/score/cpu/no_cpu/cpu_asm.c +++ /dev/null @@ -1,183 +0,0 @@ -/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s - * - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * NOTE: This is supposed to be a .S or .s file NOT a C file. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -/* - * This is supposed to be an assembly file. This means that system.h - * and cpu.h should not be included in a "real" cpu_asm file. An - * implementation in assembly should include "cpu_asm.h> - */ - -#include <rtems/system.h> -#include <rtems/score/cpu.h> -/* #include "cpu_asm.h> */ - -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -) -{ -} - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -) -{ -} - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -) -{ -} - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore( - Context_Control *new_context -) -{ -} - -/* void __ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _ISR_Handler() -{ - /* - * This discussion ignores a lot of the ugly details in a real - * implementation such as saving enough registers/state to be - * able to do something real. Keep in mind that the goal is - * to invoke a user's ISR handler which is written in C and - * uses a certain set of registers. - * - * Also note that the exact order is to a large extent flexible. - * Hardware will dictate a sequence for a certain subset of - * _ISR_Handler while requirements for setting - */ - - /* - * At entry to "common" _ISR_Handler, the vector number must be - * available. On some CPUs the hardware puts either the vector - * number or the offset into the vector table for this ISR in a - * known place. If the hardware does not give us this information, - * then the assembly portion of RTEMS for this port will contain - * a set of distinct interrupt entry points which somehow place - * the vector number in a known place (which is safe if another - * interrupt nests this one) and branches to _ISR_Handler. - * - * save some or all context on stack - * may need to save some special interrupt information for exit - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * if ( _ISR_Nest_level == 0 ) - * switch to software interrupt stack - * #endif - * - * _ISR_Nest_level++; - * - * _Thread_Dispatch_disable_level++; - * - * (*_ISR_Vector_table[ vector ])( vector ); - * - * --_ISR_Nest_level; - * - * if ( _ISR_Nest_level ) - * goto the label "exit interrupt (simple case)" - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * restore stack - * #endif - * - * if ( !_Context_Switch_necessary ) - * goto the label "exit interrupt (simple case)" - * - * if ( !_ISR_Signals_to_thread_executing ) - * _ISR_Signals_to_thread_executing = FALSE; - * goto the label "exit interrupt (simple case)" - * - * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch - * - * prepare to get out of interrupt - * return from interrupt (maybe to _ISR_Dispatch) - * - * LABEL "exit interrupt (simple case): - * prepare to get out of interrupt - * return from interrupt - */ -} - diff --git a/c/src/exec/score/cpu/no_cpu/rtems/.cvsignore b/c/src/exec/score/cpu/no_cpu/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/no_cpu/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/no_cpu/rtems/score/.cvsignore b/c/src/exec/score/cpu/no_cpu/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/no_cpu/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/no_cpu/rtems/score/cpu.h b/c/src/exec/score/cpu/no_cpu/rtems/score/cpu.h deleted file mode 100644 index 795a9ba734..0000000000 --- a/c/src/exec/score/cpu/no_cpu/rtems/score/cpu.h +++ /dev/null @@ -1,1137 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the XXX - * processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/no_cpu.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * The CPU_SOFTWARE_FP is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if ( NO_CPU_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALL_TASKS_ARE_FP TRUE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_GROWS_UP TRUE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -typedef struct { - unsigned32 some_integer_register; - unsigned32 some_system_register; -} Context_Control; - -typedef struct { - double some_float_register; -} Context_Control_fp; - -typedef struct { - unsigned32 special_interrupt_register; -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the XXX processor specific parameters. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* - * Macros to access NO_CPU specific additions to the CPU Table - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - { \ - (_isr_cookie) = 0; /* do something to prevent warnings */ \ - } - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - { \ - } - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - { \ - } - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Set_level( new_level ) \ - { \ - } - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - { \ - } - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Fatal_halt( _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/no_cpu/rtems/score/cpu_asm.h b/c/src/exec/score/cpu/no_cpu/rtems/score/cpu_asm.h deleted file mode 100644 index b5f3673d61..0000000000 --- a/c/src/exec/score/cpu/no_cpu/rtems/score/cpu_asm.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * cpu_asm.h - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/c/src/exec/score/cpu/no_cpu/rtems/score/no_cpu.h b/c/src/exec/score/cpu/no_cpu/rtems/score/no_cpu.h deleted file mode 100644 index d8dce74c59..0000000000 --- a/c/src/exec/score/cpu/no_cpu/rtems/score/no_cpu.h +++ /dev/null @@ -1,70 +0,0 @@ -/* no_cpu.h - * - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specified to the NO CPU port. - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ - -#ifndef _INCLUDE_NO_CPU_h -#define _INCLUDE_NO_CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the NO CPU family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define NOCPU_HAS_FPU 1 - -#elif defined(no_cpu) - -#define CPU_MODEL_NAME "no_cpu_model" -#define NOCPU_HAS_FPU 1 - -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "NO CPU" - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_NO_CPU_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/no_cpu/rtems/score/types.h b/c/src/exec/score/cpu/no_cpu/rtems/score/types.h deleted file mode 100644 index 6dea57ebf3..0000000000 --- a/c/src/exec/score/cpu/no_cpu/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/* no_cputypes.h - * - * This include file contains type definitions pertaining to the Intel - * no_cpu processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __NO_CPU_TYPES_h -#define __NO_CPU_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void no_cpu_isr; -typedef void ( *no_cpu_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/or16/.cvsignore b/c/src/exec/score/cpu/or16/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/or16/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/or16/ChangeLog b/c/src/exec/score/cpu/or16/ChangeLog deleted file mode 100644 index 7f8fcf3765..0000000000 --- a/c/src/exec/score/cpu/or16/ChangeLog +++ /dev/null @@ -1,103 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/or16types.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2001-02-05 Joel Sherrill <joel@OARcorp.com> - - * rtems/Makefile.am, rtems/score/Makefile.am: Removed again. - -2002-01-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-11 Joel Sherrill <joel@OARcorp.com> - - * Shell added for or16 port based on no_cpu port with names replaced. diff --git a/c/src/exec/score/cpu/or16/Makefile.am b/c/src/exec/score/cpu/or16/Makefile.am deleted file mode 100644 index ec0abd1338..0000000000 --- a/c/src/exec/score/cpu/or16/Makefile.am +++ /dev/null @@ -1,52 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS= asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/types.h \ - rtems/score/or16.h \ - rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c cpu_asm.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.c - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/or16/asm.h b/c/src/exec/score/cpu/or16/asm.h deleted file mode 100644 index 6970e6a5fc..0000000000 --- a/c/src/exec/score/cpu/or16/asm.h +++ /dev/null @@ -1,101 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __OR16_ASM_h -#define __OR16_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/or16.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/or16/configure.ac b/c/src/exec/score/cpu/or16/configure.ac deleted file mode 100644 index aa3b4525b4..0000000000 --- a/c/src/exec/score/cpu/or16/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-or16],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.c]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/or16/cpu.c b/c/src/exec/score/cpu/or16/cpu.c deleted file mode 100644 index 809e94a598..0000000000 --- a/c/src/exec/score/cpu/or16/cpu.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * XXX CPU Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; - - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ - - return 0; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Install_interrupt_stack( void ) -{ -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Thread_Idle_body( void ) -{ - - for( ; ; ) - /* insert your "halt" instruction here */ ; -} diff --git a/c/src/exec/score/cpu/or16/cpu_asm.c b/c/src/exec/score/cpu/or16/cpu_asm.c deleted file mode 100644 index ca21d7caa0..0000000000 --- a/c/src/exec/score/cpu/or16/cpu_asm.c +++ /dev/null @@ -1,183 +0,0 @@ -/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s - * - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * NOTE: This is supposed to be a .S or .s file NOT a C file. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -/* - * This is supposed to be an assembly file. This means that system.h - * and cpu.h should not be included in a "real" cpu_asm file. An - * implementation in assembly should include "cpu_asm.h> - */ - -#include <rtems/system.h> -#include <rtems/score/cpu.h> -/* #include "cpu_asm.h> */ - -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -) -{ -} - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -) -{ -} - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -) -{ -} - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore( - Context_Control *new_context -) -{ -} - -/* void __ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _ISR_Handler() -{ - /* - * This discussion ignores a lot of the ugly details in a real - * implementation such as saving enough registers/state to be - * able to do something real. Keep in mind that the goal is - * to invoke a user's ISR handler which is written in C and - * uses a certain set of registers. - * - * Also note that the exact order is to a large extent flexible. - * Hardware will dictate a sequence for a certain subset of - * _ISR_Handler while requirements for setting - */ - - /* - * At entry to "common" _ISR_Handler, the vector number must be - * available. On some CPUs the hardware puts either the vector - * number or the offset into the vector table for this ISR in a - * known place. If the hardware does not give us this information, - * then the assembly portion of RTEMS for this port will contain - * a set of distinct interrupt entry points which somehow place - * the vector number in a known place (which is safe if another - * interrupt nests this one) and branches to _ISR_Handler. - * - * save some or all context on stack - * may need to save some special interrupt information for exit - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * if ( _ISR_Nest_level == 0 ) - * switch to software interrupt stack - * #endif - * - * _ISR_Nest_level++; - * - * _Thread_Dispatch_disable_level++; - * - * (*_ISR_Vector_table[ vector ])( vector ); - * - * --_ISR_Nest_level; - * - * if ( _ISR_Nest_level ) - * goto the label "exit interrupt (simple case)" - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * restore stack - * #endif - * - * if ( !_Context_Switch_necessary ) - * goto the label "exit interrupt (simple case)" - * - * if ( !_ISR_Signals_to_thread_executing ) - * _ISR_Signals_to_thread_executing = FALSE; - * goto the label "exit interrupt (simple case)" - * - * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch - * - * prepare to get out of interrupt - * return from interrupt (maybe to _ISR_Dispatch) - * - * LABEL "exit interrupt (simple case): - * prepare to get out of interrupt - * return from interrupt - */ -} - diff --git a/c/src/exec/score/cpu/or16/rtems/.cvsignore b/c/src/exec/score/cpu/or16/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/or16/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/or16/rtems/score/.cvsignore b/c/src/exec/score/cpu/or16/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/or16/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/or16/rtems/score/cpu.h b/c/src/exec/score/cpu/or16/rtems/score/cpu.h deleted file mode 100644 index 71da86570a..0000000000 --- a/c/src/exec/score/cpu/or16/rtems/score/cpu.h +++ /dev/null @@ -1,1137 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the XXX - * processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/or16.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "OR16_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * The CPU_SOFTWARE_FP is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if ( OR16_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALL_TASKS_ARE_FP TRUE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_GROWS_UP TRUE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -typedef struct { - unsigned32 some_integer_register; - unsigned32 some_system_register; -} Context_Control; - -typedef struct { - double some_float_register; -} Context_Control_fp; - -typedef struct { - unsigned32 special_interrupt_register; -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the XXX processor specific parameters. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* - * Macros to access OR16 specific additions to the CPU Table - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - { \ - (_isr_cookie) = 0; /* do something to prevent warnings */ \ - } - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - { \ - } - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - { \ - } - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Set_level( new_level ) \ - { \ - } - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - { \ - } - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Fatal_halt( _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * OR16 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/or16/rtems/score/cpu_asm.h b/c/src/exec/score/cpu/or16/rtems/score/cpu_asm.h deleted file mode 100644 index b5f3673d61..0000000000 --- a/c/src/exec/score/cpu/or16/rtems/score/cpu_asm.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * cpu_asm.h - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/c/src/exec/score/cpu/or16/rtems/score/or16.h b/c/src/exec/score/cpu/or16/rtems/score/or16.h deleted file mode 100644 index 993cc2d202..0000000000 --- a/c/src/exec/score/cpu/or16/rtems/score/or16.h +++ /dev/null @@ -1,70 +0,0 @@ -/* or16.h - * - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specified to the OPENCORES.ORG OR16 port. - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ - -#ifndef _INCLUDE_OR16_h -#define _INCLUDE_OR16_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the OPENCORES.ORG OR16 family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define OR16_HAS_FPU 1 - -#elif defined(or16) - -#define CPU_MODEL_NAME "or16_model" -#define OR16_HAS_FPU 1 - -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "OPENCORES.ORG OR16" - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_OR16_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/or16/rtems/score/types.h b/c/src/exec/score/cpu/or16/rtems/score/types.h deleted file mode 100644 index 43eba2287d..0000000000 --- a/c/src/exec/score/cpu/or16/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/* or16types.h - * - * This include file contains type definitions pertaining to the Intel - * or16 processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __OR16_TYPES_h -#define __OR16_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void or16_isr; -typedef void ( *or16_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/or32/.cvsignore b/c/src/exec/score/cpu/or32/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/or32/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/or32/ChangeLog b/c/src/exec/score/cpu/or32/ChangeLog deleted file mode 100644 index cc0e1a7083..0000000000 --- a/c/src/exec/score/cpu/or32/ChangeLog +++ /dev/null @@ -1,107 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/or32types.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2001-02-27 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Fix conditional to match current GCC. - -2001-02-05 Joel Sherrill <joel@OARcorp.com> - - * rtems/Makefile.am, rtems/score/Makefile.am: Removed again. - -2002-01-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-11 Joel Sherrill <joel@OARcorp.com> - - * Shell added for or32 port based on no_cpu port with names replaced. diff --git a/c/src/exec/score/cpu/or32/Makefile.am b/c/src/exec/score/cpu/or32/Makefile.am deleted file mode 100644 index f84868af34..0000000000 --- a/c/src/exec/score/cpu/or32/Makefile.am +++ /dev/null @@ -1,52 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS= asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/types.h \ - rtems/score/or32.h \ - rtems/score/cpu_asm.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c cpu_asm.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.c - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/or32/asm.h b/c/src/exec/score/cpu/or32/asm.h deleted file mode 100644 index d98e2c3f2e..0000000000 --- a/c/src/exec/score/cpu/or32/asm.h +++ /dev/null @@ -1,101 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __OR32_ASM_h -#define __OR32_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/or32.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/or32/configure.ac b/c/src/exec/score/cpu/or32/configure.ac deleted file mode 100644 index 9837e3bf91..0000000000 --- a/c/src/exec/score/cpu/or32/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-or32],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.c]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/or32/cpu.c b/c/src/exec/score/cpu/or32/cpu.c deleted file mode 100644 index ca0e499125..0000000000 --- a/c/src/exec/score/cpu/or32/cpu.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * XXX CPU Dependent Source - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; - - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ - - return 0; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Install_interrupt_stack( void ) -{ -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Thread_Idle_body( void ) -{ - - for( ; ; ) - /* insert your "halt" instruction here */ ; -} diff --git a/c/src/exec/score/cpu/or32/cpu_asm.c b/c/src/exec/score/cpu/or32/cpu_asm.c deleted file mode 100644 index 2e7623fb69..0000000000 --- a/c/src/exec/score/cpu/or32/cpu_asm.c +++ /dev/null @@ -1,183 +0,0 @@ -/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s - * - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * NOTE: This is supposed to be a .S or .s file NOT a C file. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -/* - * This is supposed to be an assembly file. This means that system.h - * and cpu.h should not be included in a "real" cpu_asm file. An - * implementation in assembly should include "cpu_asm.h> - */ - -#include <rtems/system.h> -#include <rtems/score/cpu.h> -/* #include "cpu_asm.h> */ - -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -) -{ -} - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -) -{ -} - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -) -{ -} - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore( - Context_Control *new_context -) -{ -} - -/* void __ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _ISR_Handler() -{ - /* - * This discussion ignores a lot of the ugly details in a real - * implementation such as saving enough registers/state to be - * able to do something real. Keep in mind that the goal is - * to invoke a user's ISR handler which is written in C and - * uses a certain set of registers. - * - * Also note that the exact order is to a large extent flexible. - * Hardware will dictate a sequence for a certain subset of - * _ISR_Handler while requirements for setting - */ - - /* - * At entry to "common" _ISR_Handler, the vector number must be - * available. On some CPUs the hardware puts either the vector - * number or the offset into the vector table for this ISR in a - * known place. If the hardware does not give us this information, - * then the assembly portion of RTEMS for this port will contain - * a set of distinct interrupt entry points which somehow place - * the vector number in a known place (which is safe if another - * interrupt nests this one) and branches to _ISR_Handler. - * - * save some or all context on stack - * may need to save some special interrupt information for exit - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * if ( _ISR_Nest_level == 0 ) - * switch to software interrupt stack - * #endif - * - * _ISR_Nest_level++; - * - * _Thread_Dispatch_disable_level++; - * - * (*_ISR_Vector_table[ vector ])( vector ); - * - * --_ISR_Nest_level; - * - * if ( _ISR_Nest_level ) - * goto the label "exit interrupt (simple case)" - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * restore stack - * #endif - * - * if ( !_Context_Switch_necessary ) - * goto the label "exit interrupt (simple case)" - * - * if ( !_ISR_Signals_to_thread_executing ) - * _ISR_Signals_to_thread_executing = FALSE; - * goto the label "exit interrupt (simple case)" - * - * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch - * - * prepare to get out of interrupt - * return from interrupt (maybe to _ISR_Dispatch) - * - * LABEL "exit interrupt (simple case): - * prepare to get out of interrupt - * return from interrupt - */ -} - diff --git a/c/src/exec/score/cpu/or32/rtems/.cvsignore b/c/src/exec/score/cpu/or32/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/or32/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/or32/rtems/score/.cvsignore b/c/src/exec/score/cpu/or32/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/or32/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/or32/rtems/score/cpu.h b/c/src/exec/score/cpu/or32/rtems/score/cpu.h deleted file mode 100644 index 16efc9d6a2..0000000000 --- a/c/src/exec/score/cpu/or32/rtems/score/cpu.h +++ /dev/null @@ -1,1137 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the XXX - * processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/or32.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "OR32_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * The CPU_SOFTWARE_FP is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if ( OR32_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALL_TASKS_ARE_FP TRUE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_GROWS_UP TRUE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STRUCTURE_ALIGNMENT - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -typedef struct { - unsigned32 some_integer_register; - unsigned32 some_system_register; -} Context_Control; - -typedef struct { - double some_float_register; -} Context_Control_fp; - -typedef struct { - unsigned32 special_interrupt_register; -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the XXX processor specific parameters. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* - * Macros to access OR32 specific additions to the CPU Table - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - { \ - (_isr_cookie) = 0; /* do something to prevent warnings */ \ - } - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - { \ - } - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - { \ - } - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Set_level( new_level ) \ - { \ - } - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - { \ - } - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Fatal_halt( _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * OR32 Specific Information: - * - * XXX document implementation including references if appropriate - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/or32/rtems/score/cpu_asm.h b/c/src/exec/score/cpu/or32/rtems/score/cpu_asm.h deleted file mode 100644 index b5f3673d61..0000000000 --- a/c/src/exec/score/cpu/or32/rtems/score/cpu_asm.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * cpu_asm.h - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/c/src/exec/score/cpu/or32/rtems/score/or32.h b/c/src/exec/score/cpu/or32/rtems/score/or32.h deleted file mode 100644 index 1aadcfc286..0000000000 --- a/c/src/exec/score/cpu/or32/rtems/score/or32.h +++ /dev/null @@ -1,70 +0,0 @@ -/* or32.h - * - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specified to the OPENCORES.ORG OR32 port. - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - * - */ - -#ifndef _INCLUDE_OR32_h -#define _INCLUDE_OR32_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the OPENCORES.ORG OR32 family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define OR32_HAS_FPU 1 - -#elif defined(__or1k__) || defined(__OR1K__) - -#define CPU_MODEL_NAME "or32_model" -#define OR32_HAS_FPU 1 - -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "OPENCORES.ORG OR32" - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_OR32_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/or32/rtems/score/types.h b/c/src/exec/score/cpu/or32/rtems/score/types.h deleted file mode 100644 index c20aa2068a..0000000000 --- a/c/src/exec/score/cpu/or32/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/* or32types.h - * - * This include file contains type definitions pertaining to the Intel - * or32 processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __OR32_TYPES_h -#define __OR32_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void or32_isr; -typedef void ( *or32_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/powerpc/.cvsignore b/c/src/exec/score/cpu/powerpc/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/powerpc/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/powerpc/ChangeLog b/c/src/exec/score/cpu/powerpc/ChangeLog deleted file mode 100644 index d25f14e2b1..0000000000 --- a/c/src/exec/score/cpu/powerpc/ChangeLog +++ /dev/null @@ -1,164 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-05-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/ppc.h: Remove PPC_DEBUG_MODEL. - -2001-05-14 Till Straumann <strauman@slac.stanford.edu> - - * rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add - support for the MPC74000 (AKA G4); there is no AltiVec support yet, - however. -2002-04-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/ppc.h: Remove rtems_multilib. - Add mpc555 (Based on comments from Sergei Organov <osv@javad.ru>). - * rtems/old-exceptions/cpu.h: Remove _CPU_Data_Cache_Block_Flush. - Remove _CPU_Data_Cache_Block_Invalidate. - -2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * asm.h: Include cpuopts.h instead of targopts.h. - * rtems/new-exceptions/cpu.h: Relocated from - libbsp/powerpc/support/new_exception_processing/rtems/score/cpu.h - * rtems/old-exceptions/cpu.h: Relocated from - c/src/lib/libbsp/powerpc/support/old_exception_processing/rtems/score/cpu.h - * rtems/powerpc/registers.h: Relocated and renamed from - libcpu/powerpc/shared/include/cpu.h. - * rtems/score/cpu.h: New. - * Makefile.am: Reflect changes above. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/ppctypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Reflect changes from 2002-01-23. - -2002-01-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - AC_CONFIG_SRCDIR(asm.h). - -2002-01-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: New. - * rtems/.cvsignore: New. - * rtems/score/Makefile.am: New. - * rtems/score/.cvsignore: New. - * rtems/score/ppc.h: Relocated from shared/. - * rtems/score/ppctypes.h: Relocated from shared/. - * asm.h: Relocated from shared/. - * shared/Makefile.am: Removed. - * shared/asm.h: Removed. - * shared/ppc.h: Removed. - * shared/ppctypes.h: Removed. - * shared/.cvsignore: Removed. - * Makefile.am: Reflect changes above. - * configure.ac: Reflect changes above. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-11-14 Joel Sherrill <joel@OARcorp.com> - - * shared/ppc.h: The mpc8260 uses the new exception processing model - and thus does not need to define PPC_USE_SPRG. - -2001-11-14 Andrew Dachs <A.Dachs@SSTL.co.uk> - - * shared/ppc.h: mpc8260 has double FPU not single FPU. - -2001-11-08 Dennis Ehlin (ECS) <Dennis.Ehlin@ecs.ericsson.se> - - This modification is part of the submitted modifications necessary to - support the IBM PPC405 family. This submission was reviewed by - Thomas Doerfler <Thomas.Doerfler@imd-systems.de> who ensured it did - not negatively impact the ppc403 BSPs. The submission and tracking - process was captured as PR50. - * shared/asm.h, shared/ppc.h: Added PPC405 support. - -2001-10-22 Andy Dachs <a.dachs@sstl.co.uk> - - * shared/ppc.h: Added mpc8260 support. - -2001-10-12 Joel Sherrill <joel@OARcorp.com> - - * shared/ppctypes.h: Fixed typo. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * shared/Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-10-20 Joel Sherrill <joel@OARcorp.com> - - * shared/ppc.h: For multilibs, derive PPC_HAS_FPU from _SOFT_FLOAT. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/powerpc/Makefile.am b/c/src/exec/score/cpu/powerpc/Makefile.am deleted file mode 100644 index 4c7146f274..0000000000 --- a/c/src/exec/score/cpu/powerpc/Makefile.am +++ /dev/null @@ -1,76 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) \ - $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/ppc.h \ - rtems/score/types.h -include_rtems_score_HEADERS += rtems/score/cpu.h - -$(PROJECT_INCLUDE)/rtems/old-exceptions: - $(mkinstalldirs) $@ - -include_rtems_old_exceptionsdir = $(includedir)/rtems/old-exceptions -include_rtems_old_exceptions_HEADERS = rtems/old-exceptions/cpu.h - -$(PROJECT_INCLUDE)/rtems/new-exceptions: - $(mkinstalldirs) $@ - -include_rtems_new_exceptionsdir = $(includedir)/rtems/new-exceptions -include_rtems_new_exceptions_HEADERS = rtems/new-exceptions/cpu.h - - -$(PROJECT_INCLUDE)/rtems/powerpc: - $(mkinstalldirs) $@ - -include_rtems_powerpcdir = $(includedir)/rtems/powerpc -include_rtems_powerpc_HEADERS = rtems/powerpc/registers.h - -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/old-exceptions \ - $(include_rtems_old_exceptions_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/new-exceptions \ - $(include_rtems_new_exceptions_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/powerpc \ - $(include_rtems_powerpc_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -# $(PROJECT_RELEASE)/lib$(MULTISUBDIR)/rtems$(LIB_VARIANT).o: $(ARCH)/rtems.o -# $(INSTALL_DATA) $< $@ - -# $(REL): $(rtems_cpu_rel_OBJECTS) -# $(make-rel) - - -# TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib$(MULTISUBDIR)/rtems$(LIB_VARIANT).o - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/powerpc/asm.h b/c/src/exec/score/cpu/powerpc/asm.h deleted file mode 100644 index 419202eb26..0000000000 --- a/c/src/exec/score/cpu/powerpc/asm.h +++ /dev/null @@ -1,292 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1995. - * i-cubed ltd. - * - * COPYRIGHT (c) 1994. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __PPC_ASM_h -#define __PPC_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/ppc.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#ifndef __FLOAT_REGISTER_PREFIX__ -#define __FLOAT_REGISTER_PREFIX__ __REGISTER_PREFIX__ -#endif - -#if (PPC_ABI == PPC_ABI_POWEROPEN) -#ifndef __PROC_LABEL_PREFIX__ -#define __PROC_LABEL_PREFIX__ . -#endif -#endif - -#ifndef __PROC_LABEL_PREFIX__ -#define __PROC_LABEL_PREFIX__ __USER_LABEL_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for procedure labels. */ - -#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* Use the right prefix for floating point registers. */ - -#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG(0) -#define r1 REG(1) -#define r2 REG(2) -#define r3 REG(3) -#define r4 REG(4) -#define r5 REG(5) -#define r6 REG(6) -#define r7 REG(7) -#define r8 REG(8) -#define r9 REG(9) -#define r10 REG(10) -#define r11 REG(11) -#define r12 REG(12) -#define r13 REG(13) -#define r14 REG(14) -#define r15 REG(15) -#define r16 REG(16) -#define r17 REG(17) -#define r18 REG(18) -#define r19 REG(19) -#define r20 REG(20) -#define r21 REG(21) -#define r22 REG(22) -#define r23 REG(23) -#define r24 REG(24) -#define r25 REG(25) -#define r26 REG(26) -#define r27 REG(27) -#define r28 REG(28) -#define r29 REG(29) -#define r30 REG(30) -#define r31 REG(31) -#define f0 FREG(0) -#define f1 FREG(1) -#define f2 FREG(2) -#define f3 FREG(3) -#define f4 FREG(4) -#define f5 FREG(5) -#define f6 FREG(6) -#define f7 FREG(7) -#define f8 FREG(8) -#define f9 FREG(9) -#define f10 FREG(10) -#define f11 FREG(11) -#define f12 FREG(12) -#define f13 FREG(13) -#define f14 FREG(14) -#define f15 FREG(15) -#define f16 FREG(16) -#define f17 FREG(17) -#define f18 FREG(18) -#define f19 FREG(19) -#define f20 FREG(20) -#define f21 FREG(21) -#define f22 FREG(22) -#define f23 FREG(23) -#define f24 FREG(24) -#define f25 FREG(25) -#define f26 FREG(26) -#define f27 FREG(27) -#define f28 FREG(28) -#define f29 FREG(29) -#define f30 FREG(30) -#define f31 FREG(31) - -/* - * Some special purpose registers (SPRs). - */ -#define srr0 0x01a -#define srr1 0x01b -#if defined(ppc403) || defined(ppc405) -#define srr2 0x3de /* IBM 400 series only */ -#define srr3 0x3df /* IBM 400 series only */ -#endif /* ppc403 or ppc405 */ - -#define sprg0 0x110 -#define sprg1 0x111 -#define sprg2 0x112 -#define sprg3 0x113 - -#define dar 0x013 /* Data Address Register */ -#define dec 0x016 /* Decrementer Register */ - -#if defined(ppc403) || defined(ppc405) -/* the following SPR/DCR registers exist only in IBM 400 series */ -#define dear 0x3d5 -#define evpr 0x3d6 /* SPR: exception vector prefix register */ -#define iccr 0x3fb /* SPR: instruction cache control reg. */ -#define dccr 0x3fa /* SPR: data cache control reg. */ - -#if defined (ppc403) -#define exisr 0x040 /* DCR: external interrupt status register */ -#define exier 0x042 /* DCR: external interrupt enable register */ -#endif /* ppc403 */ -#if defined(ppc405) -#define exisr 0x0C0 /* DCR: external interrupt status register */ -#define exier 0x0C2 /* DCR: external interrupt enable register */ -#endif /* ppc405 */ - -#define br0 0x080 /* DCR: memory bank register 0 */ -#define br1 0x081 /* DCR: memory bank register 1 */ -#define br2 0x082 /* DCR: memory bank register 2 */ -#define br3 0x083 /* DCR: memory bank register 3 */ -#define br4 0x084 /* DCR: memory bank register 4 */ -#define br5 0x085 /* DCR: memory bank register 5 */ -#define br6 0x086 /* DCR: memory bank register 6 */ -#define br7 0x087 /* DCR: memory bank register 7 */ -/* end of IBM400 series register definitions */ - -#elif defined(mpc860) || defined(mpc821) -/* The following registers are for the MPC8x0 */ -#define der 0x095 /* Debug Enable Register */ -#define ictrl 0x09E /* Instruction Support Control Register */ -#define immr 0x27E /* Internal Memory Map Register */ -/* end of MPC8x0 registers */ -#endif - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC_VAR(sym) .globl SYM (sym) -#define EXTERN_VAR(sym) .extern SYM (sym) -#define PUBLIC_PROC(sym) .globl PROC (sym) -#define EXTERN_PROC(sym) .extern PROC (sym) - -/* Other potentially assembler specific operations */ -#if PPC_ASM == PPC_ASM_ELF -#define ALIGN(n,p) .align p -#define DESCRIPTOR(x) \ - .section .descriptors,"aw"; \ - PUBLIC_VAR (x); \ -SYM (x):; \ - .long PROC (x); \ - .long s.got; \ - .long 0 - -#define EXT_SYM_REF(x) .long x -#define EXT_PROC_REF(x) .long x - -/* - * Define macros to handle section beginning and ends. - */ - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -#elif PPC_ASM == PPC_ASM_XCOFF -#define ALIGN(n,p) .align p -#define DESCRIPTOR(x) \ - .csect x[DS]; \ - .globl x[DS]; \ - .long PROC (x)[PR]; \ - .long TOC[tc0] - -#define EXT_SYM_REF(x) .long x[RW] -#define EXT_PROC_REF(x) .long x[DS] - -/* - * Define macros to handle section beginning and ends. - */ - -#define BEGIN_CODE_DCL .csect .text[PR] -#define END_CODE_DCL -#define BEGIN_DATA_DCL .csect .data[RW] -#define END_DATA_DCL -#define BEGIN_CODE .csect .text[PR] -#define END_CODE -#define BEGIN_DATA .csect .data[RW] -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -#else -#error "PPC_ASM_TYPE is not properly defined" -#endif -#ifndef PPC_ASM -#error "PPC_ASM_TYPE is not properly defined" -#endif - - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/powerpc/configure.ac b/c/src/exec/score/cpu/powerpc/configure.ac deleted file mode 100644 index 41f2aae44d..0000000000 --- a/c/src/exec/score/cpu/powerpc/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-powerpc],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([asm.h]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/powerpc/rtems/.cvsignore b/c/src/exec/score/cpu/powerpc/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/powerpc/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/powerpc/rtems/new-exceptions/cpu.h b/c/src/exec/score/cpu/powerpc/rtems/new-exceptions/cpu.h deleted file mode 100644 index 6b30c0ed0b..0000000000 --- a/c/src/exec/score/cpu/powerpc/rtems/new-exceptions/cpu.h +++ /dev/null @@ -1,979 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the PowerPC - * processor. - * - * Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk> - * Surrey Satellite Technology Limited (SSTL), 2001 - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/cpu.h: - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be found in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifndef _rtems_score_cpu_h -#error "You should include <rtems/score/cpu.h>" -#endif - -#include <rtems/powerpc/registers.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "PPC_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( PPC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Note, however that compilers may use floating point registers/ - * instructions for optimization or they may save/restore FP registers - * on the stack. You must not use deferred switching in these cases - * and on the PowerPC attempting to do so will raise a "FP unavailable" - * exception. - */ -/* - * ACB Note: This could make debugging tricky.. - */ - -/* conservative setting (FALSE); probably doesn't affect performance too much */ -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT \ - __attribute__ ((aligned (PPC_CACHE_ALIGNMENT))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -#ifndef ASM - -typedef struct { - unsigned32 gpr1; /* Stack pointer for all */ - unsigned32 gpr2; /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */ - unsigned32 gpr13; /* First non volatile PowerOpen, section ptr SVR4/EABI */ - unsigned32 gpr14; /* Non volatile for all */ - unsigned32 gpr15; /* Non volatile for all */ - unsigned32 gpr16; /* Non volatile for all */ - unsigned32 gpr17; /* Non volatile for all */ - unsigned32 gpr18; /* Non volatile for all */ - unsigned32 gpr19; /* Non volatile for all */ - unsigned32 gpr20; /* Non volatile for all */ - unsigned32 gpr21; /* Non volatile for all */ - unsigned32 gpr22; /* Non volatile for all */ - unsigned32 gpr23; /* Non volatile for all */ - unsigned32 gpr24; /* Non volatile for all */ - unsigned32 gpr25; /* Non volatile for all */ - unsigned32 gpr26; /* Non volatile for all */ - unsigned32 gpr27; /* Non volatile for all */ - unsigned32 gpr28; /* Non volatile for all */ - unsigned32 gpr29; /* Non volatile for all */ - unsigned32 gpr30; /* Non volatile for all */ - unsigned32 gpr31; /* Non volatile for all */ - unsigned32 cr; /* PART of the CR is non volatile for all */ - unsigned32 pc; /* Program counter/Link register */ - unsigned32 msr; /* Initial interrupt level */ -} Context_Control; - -typedef struct { - /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over - * procedure calls. However, this would mean that the interrupt - * frame had to hold f0-f13, and the fpscr. And as the majority - * of tasks will not have an FP context, we will save the whole - * context here. - */ -#if (PPC_HAS_DOUBLE == 1) - double f[32]; - double fpscr; -#else - float f[32]; - float fpscr; -#endif -} Context_Control_fp; - -typedef struct CPU_Interrupt_frame { - unsigned32 stacklink; /* Ensure this is a real frame (also reg1 save) */ - unsigned32 calleeLr; /* link register used by callees: SVR4/EABI */ - /* This is what is left out of the primary contexts */ - unsigned32 gpr0; - unsigned32 gpr2; /* play safe */ - unsigned32 gpr3; - unsigned32 gpr4; - unsigned32 gpr5; - unsigned32 gpr6; - unsigned32 gpr7; - unsigned32 gpr8; - unsigned32 gpr9; - unsigned32 gpr10; - unsigned32 gpr11; - unsigned32 gpr12; - unsigned32 gpr13; /* Play safe */ - unsigned32 gpr28; /* For internal use by the IRQ handler */ - unsigned32 gpr29; /* For internal use by the IRQ handler */ - unsigned32 gpr30; /* For internal use by the IRQ handler */ - unsigned32 gpr31; /* For internal use by the IRQ handler */ - unsigned32 cr; /* Bits of this are volatile, so no-one may save */ - unsigned32 ctr; - unsigned32 xer; - unsigned32 lr; - unsigned32 pc; - unsigned32 msr; - unsigned32 pad[3]; -} CPU_Interrupt_frame; - -/* - * The following table contains the information required to configure - * the PowerPC processor specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - - unsigned32 clicks_per_usec; /* Timer clicks per microsecond */ - boolean exceptions_in_RAM; /* TRUE if in RAM */ - -#if (defined(ppc403) || defined(mpc860) || defined(mpc821) || defined(mpc8260)) - unsigned32 serial_per_sec; /* Serial clocks per second */ - boolean serial_external_clock; - boolean serial_xon_xoff; - boolean serial_cts_rts; - unsigned32 serial_rate; - unsigned32 timer_average_overhead; /* Average overhead of timer in ticks */ - unsigned32 timer_least_valid; /* Least valid number from timer */ - boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */ -#endif - -#if (defined(mpc860) || defined(mpc821) || defined(mpc8260)) - unsigned32 clock_speed; /* Speed of CPU in Hz */ -#endif -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access PowerPC MPC750 specific additions to the CPU Table - */ - -#define rtems_cpu_configuration_get_clicks_per_usec() \ - (_CPU_Table.clicks_per_usec) - -#define rtems_cpu_configuration_get_exceptions_in_ram() \ - (_CPU_Table.exceptions_in_RAM) - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -/* EXTERN Context_Control_fp _CPU_Null_fp_context; */ - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -#endif /* ndef ASM */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - */ - -/* EXTERN void (*_CPU_Thread_dispatch_pointer)(); */ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -#ifndef ASM - -SCORE_EXTERN struct { - unsigned32 *Disable_level; - void *Stack; - volatile boolean *Switch_necessary; - boolean *Signal; - -} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; - -#endif /* ndef ASM */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * (Optional) # of bytes for libmisc/stackchk to check - * If not specifed, then it defaults to something reasonable - * for most architectures. - */ - -#define CPU_STACK_CHECK_SIZE (128) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS (PPC_INTERRUPT_MAX) -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) - -/* - * Needed for Interrupt stack - */ -#define CPU_MINIMUM_STACK_FRAME_SIZE 8 - - -/* - * ISR handler macros - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _isr_cookie. - */ - -#ifndef ASM - -static inline unsigned32 _CPU_ISR_Get_level( void ) -{ - register unsigned int msr; - _CPU_MSR_GET(msr); - if (msr & MSR_EE) return 0; - else return 1; -} - -static inline void _CPU_ISR_Set_level( unsigned32 level ) -{ - register unsigned int msr; - _CPU_MSR_GET(msr); - if (!(level & CPU_MODES_INTERRUPT_MASK)) { - msr |= MSR_EE; - } - else { - msr &= ~MSR_EE; - } - _CPU_MSR_SET(msr); -} - -#define _CPU_ISR_install_vector(irq, new, old) {BSP_panic("_CPU_ISR_install_vector called\n");} - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: Implemented as a subroutine for the SPARC port. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - unsigned32 *stack_base, - unsigned32 size, - unsigned32 new_level, - void *entry_point, - boolean is_fp -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - _BSP_Fatal_error(_error) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_Bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ - "1" ((_value))); \ - } - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x80000000 >> (_bit_number) ) - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ - -/* variables */ - -extern const unsigned32 _CPU_msrs[4]; - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -void _CPU_Fatal_error( - unsigned32 _error -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 swapped; - - asm volatile("rlwimi %0,%1,8,24,31;" - "rlwimi %0,%1,24,16,23;" - "rlwimi %0,%1,8,8,15;" - "rlwimi %0,%1,24,0,7;" : - "=&r" ((swapped)) : "r" ((value))); - - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#endif /* ndef ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/powerpc/rtems/old-exceptions/cpu.h b/c/src/exec/score/cpu/powerpc/rtems/old-exceptions/cpu.h deleted file mode 100644 index 4ab28fc368..0000000000 --- a/c/src/exec/score/cpu/powerpc/rtems/old-exceptions/cpu.h +++ /dev/null @@ -1,1198 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the PowerPC - * processor. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/cpu.h: - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifndef _rtems_score_cpu_h -#error "You should include <rtems/score/cpu.h>" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef ASM -struct CPU_Interrupt_frame; -typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * ); -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -/* - * ACB: This is a lie, but it gets us a handle on a call to set up - * a variable derived from the top of the interrupt stack. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "PPC_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( PPC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ -/* - * ACB Note: This could make debugging tricky.. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT \ - __attribute__ ((aligned (PPC_CACHE_ALIGNMENT))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * The interrupt level is bit mapped for the PowerPC family. The - * bits are set to 0 to indicate that a particular exception source - * enabled and 1 if it is disabled. This keeps with RTEMS convention - * that interrupt level 0 means all sources are enabled. - * - * The bits are assigned to correspond to enable bits in the MSR. - */ - -#define PPC_INTERRUPT_LEVEL_ME 0x01 -#define PPC_INTERRUPT_LEVEL_EE 0x02 -#define PPC_INTERRUPT_LEVEL_CE 0x04 - -/* XXX should these be maskable? */ -#if 0 -#define PPC_INTERRUPT_LEVEL_DE 0x08 -#define PPC_INTERRUPT_LEVEL_BE 0x10 -#define PPC_INTERRUPT_LEVEL_SE 0x20 -#endif - -#define CPU_MODES_INTERRUPT_MASK 0x00000007 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - unsigned32 gpr1; /* Stack pointer for all */ - unsigned32 gpr2; /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */ - unsigned32 gpr13; /* First non volatile PowerOpen, section ptr SVR4/EABI */ - unsigned32 gpr14; /* Non volatile for all */ - unsigned32 gpr15; /* Non volatile for all */ - unsigned32 gpr16; /* Non volatile for all */ - unsigned32 gpr17; /* Non volatile for all */ - unsigned32 gpr18; /* Non volatile for all */ - unsigned32 gpr19; /* Non volatile for all */ - unsigned32 gpr20; /* Non volatile for all */ - unsigned32 gpr21; /* Non volatile for all */ - unsigned32 gpr22; /* Non volatile for all */ - unsigned32 gpr23; /* Non volatile for all */ - unsigned32 gpr24; /* Non volatile for all */ - unsigned32 gpr25; /* Non volatile for all */ - unsigned32 gpr26; /* Non volatile for all */ - unsigned32 gpr27; /* Non volatile for all */ - unsigned32 gpr28; /* Non volatile for all */ - unsigned32 gpr29; /* Non volatile for all */ - unsigned32 gpr30; /* Non volatile for all */ - unsigned32 gpr31; /* Non volatile for all */ - unsigned32 cr; /* PART of the CR is non volatile for all */ - unsigned32 pc; /* Program counter/Link register */ - unsigned32 msr; /* Initial interrupt level */ -} Context_Control; - -typedef struct { - /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over - * procedure calls. However, this would mean that the interrupt - * frame had to hold f0-f13, and the fpscr. And as the majority - * of tasks will not have an FP context, we will save the whole - * context here. - */ -#if (PPC_HAS_DOUBLE == 1) - double f[32]; - double fpscr; -#else - float f[32]; - float fpscr; -#endif -} Context_Control_fp; - -typedef struct CPU_Interrupt_frame { - unsigned32 stacklink; /* Ensure this is a real frame (also reg1 save) */ -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) - unsigned32 dummy[13]; /* Used by callees: PowerOpen ABI */ -#else - unsigned32 dummy[1]; /* Used by callees: SVR4/EABI */ -#endif - /* This is what is left out of the primary contexts */ - unsigned32 gpr0; - unsigned32 gpr2; /* play safe */ - unsigned32 gpr3; - unsigned32 gpr4; - unsigned32 gpr5; - unsigned32 gpr6; - unsigned32 gpr7; - unsigned32 gpr8; - unsigned32 gpr9; - unsigned32 gpr10; - unsigned32 gpr11; - unsigned32 gpr12; - unsigned32 gpr13; /* Play safe */ - unsigned32 gpr28; /* For internal use by the IRQ handler */ - unsigned32 gpr29; /* For internal use by the IRQ handler */ - unsigned32 gpr30; /* For internal use by the IRQ handler */ - unsigned32 gpr31; /* For internal use by the IRQ handler */ - unsigned32 cr; /* Bits of this are volatile, so no-one may save */ - unsigned32 ctr; - unsigned32 xer; - unsigned32 lr; - unsigned32 pc; - unsigned32 msr; - unsigned32 pad[3]; -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the PowerPC processor specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - - unsigned32 clicks_per_usec; /* Timer clicks per microsecond */ - void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *); - boolean exceptions_in_RAM; /* TRUE if in RAM */ - -#if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821)) - unsigned32 serial_per_sec; /* Serial clocks per second */ - boolean serial_external_clock; - boolean serial_xon_xoff; - boolean serial_cts_rts; - unsigned32 serial_rate; - unsigned32 timer_average_overhead; /* Average overhead of timer in ticks */ - unsigned32 timer_least_valid; /* Least valid number from timer */ - boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */ -#endif - -#if (defined(mpc860) || defined(mpc821)) - unsigned32 clock_speed; /* Speed of CPU in Hz */ -#endif -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access PowerPC specific additions to the CPU Table - */ - -#define rtems_cpu_configuration_get_clicks_per_usec() \ - (_CPU_Table.clicks_per_usec) - -#define rtems_cpu_configuration_get_spurious_handler() \ - (_CPU_Table.spurious_handler) - -#define rtems_cpu_configuration_get_exceptions_in_ram() \ - (_CPU_Table.exceptions_in_RAM) - -#if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821)) - -#define rtems_cpu_configuration_get_serial_per_sec() \ - (_CPU_Table.serial_per_sec) - -#define rtems_cpu_configuration_get_serial_external_clock() \ - (_CPU_Table.serial_external_clock) - -#define rtems_cpu_configuration_get_serial_xon_xoff() \ - (_CPU_Table.serial_xon_xoff) - -#define rtems_cpu_configuration_get_serial_cts_rts() \ - (_CPU_Table.serial_cts_rts) - -#define rtems_cpu_configuration_get_serial_rate() \ - (_CPU_Table.serial_rate) - -#define rtems_cpu_configuration_get_timer_average_overhead() \ - (_CPU_Table.timer_average_overhead) - -#define rtems_cpu_configuration_get_timer_least_valid() \ - (_CPU_Table.timer_least_valid) - -#define rtems_cpu_configuration_get_timer_internal_clock() \ - (_CPU_Table.timer_internal_clock) - -#endif - -#if (defined(mpc860) || defined(mpc821)) -#define rtems_cpu_configuration_get_clock_speed() \ - (_CPU_Table.clock_speed) -#endif - - -/* - * The following type defines an entry in the PPC's trap table. - * - * NOTE: The instructions chosen are RTEMS dependent although one is - * obligated to use two of the four instructions to perform a - * long jump. The other instructions load one register with the - * trap type (a.k.a. vector) and another with the psr. - */ - -typedef struct { - unsigned32 stwu_r1; /* stwu %r1, -(??+IP_END)(%1)*/ - unsigned32 stw_r0; /* stw %r0, IP_0(%r1) */ - unsigned32 li_r0_IRQ; /* li %r0, _IRQ */ - unsigned32 b_Handler; /* b PROC (_ISR_Handler) */ -} CPU_Trap_table_entry; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -/* EXTERN Context_Control_fp _CPU_Null_fp_context; */ - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - */ - -/* EXTERN void (*_CPU_Thread_dispatch_pointer)(); */ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - - -SCORE_EXTERN struct { - unsigned32 volatile* Nest_level; - unsigned32 volatile* Disable_level; - void *Vector_table; - void *Stack; -#if (PPC_ABI == PPC_ABI_POWEROPEN) - unsigned32 Dispatch_r2; -#else - unsigned32 Default_r2; -#if (PPC_ABI != PPC_ABI_GCC27) - unsigned32 Default_r13; -#endif -#endif - volatile boolean *Switch_necessary; - boolean *Signal; - - unsigned32 msr_initial; -} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * (Optional) # of bytes for libmisc/stackchk to check - * If not specifed, then it defaults to something reasonable - * for most architectures. - */ - -#define CPU_STACK_CHECK_SIZE (128) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS (PPC_INTERRUPT_MAX) -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) - -/* - * ISR handler macros - */ - -void _CPU_Initialize_vectors(void); - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _isr_cookie. - */ - -#define _CPU_MSR_Value( _msr_value ) \ - do { \ - _msr_value = 0; \ - asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ - } while (0) - -#define _CPU_MSR_SET( _msr_value ) \ -{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } - -#if 0 -#define _CPU_ISR_Disable( _isr_cookie ) \ - { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ - _isr_cookie = 0; \ - asm volatile ( - "mfmsr %0" : \ - "=r" ((_isr_cookie)) : \ - "0" ((_isr_cookie)) \ - ); \ - asm volatile ( - "andc %1,%0,%1" : \ - "=r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \ - "0" ((_isr_cookie)), "1" ((_disable_mask)) \ - ); \ - asm volatile ( - "mtmsr %1" : \ - "=r" ((_disable_mask)) : \ - "0" ((_disable_mask)) \ - ); \ - } -#endif - -#define _CPU_ISR_Disable( _isr_cookie ) \ - { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ - _isr_cookie = 0; \ - asm volatile ( \ - "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \ - "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \ - "0" ((_isr_cookie)), "1" ((_disable_mask)) \ - ); \ - } - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _isr_cookie is not modified. - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - { \ - asm volatile ( "mtmsr %0" : \ - "=r" ((_isr_cookie)) : \ - "0" ((_isr_cookie))); \ - } - -/* - * This temporarily restores the interrupt to _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _isr_cookie is not - * modified. - * - * NOTE: The version being used is not very optimized but it does - * not trip a problem in gcc where the disable mask does not - * get loaded. Check this for future (post 10/97 gcc versions. - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ - asm volatile ( \ - "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \ - "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \ - "0" ((_isr_cookie)), "1" ((_disable_mask)) \ - ); \ - } - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ - -unsigned32 _CPU_ISR_Calculate_level( - unsigned32 new_level -); - -void _CPU_ISR_Set_level( - unsigned32 new_level -); - -unsigned32 _CPU_ISR_Get_level( void ); - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* end of ISR handler macros */ - -/* - * Simple spin delay in microsecond units for device drivers. - * This is very dependent on the clock speed of the target. - */ - -#define CPU_Get_timebase_low( _value ) \ - asm volatile( "mftb %0" : "=r" (_value) ) - -#define rtems_bsp_delay( _microseconds ) \ - do { \ - unsigned32 start, ticks, now; \ - CPU_Get_timebase_low( start ) ; \ - ticks = (_microseconds) * _CPU_Table.clicks_per_usec; \ - do \ - CPU_Get_timebase_low( now ) ; \ - while (now - start < ticks); \ - } while (0) - -#define rtems_bsp_delay_in_bus_cycles( _cycles ) \ - do { \ - unsigned32 start, now; \ - CPU_Get_timebase_low( start ); \ - do \ - CPU_Get_timebase_low( now ); \ - while (now - start < (_cycles)); \ - } while (0) - - - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: Implemented as a subroutine for the SPARC port. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - unsigned32 *stack_base, - unsigned32 size, - unsigned32 new_level, - void *entry_point, - boolean is_fp -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - _CPU_Fatal_error(_error) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_Bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ - "1" ((_value))); \ - } - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x80000000 >> (_bit_number) ) - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ - -/* variables */ - -extern const unsigned32 _CPU_msrs[4]; - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -void _CPU_Fatal_error( - unsigned32 _error -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 swapped; - - asm volatile("rlwimi %0,%1,8,24,31;" - "rlwimi %0,%1,24,16,23;" - "rlwimi %0,%1,8,8,15;" - "rlwimi %0,%1,24,0,7;" : - "=&r" ((swapped)) : "r" ((value))); - - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -/* - * Routines to access the decrementer register - */ - -#define PPC_Set_decrementer( _clicks ) \ - do { \ - asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - -/* - * Routines to access the time base register - */ - -static inline unsigned64 PPC_Get_timebase_register( void ) -{ - unsigned32 tbr_low; - unsigned32 tbr_high; - unsigned32 tbr_high_old; - unsigned64 tbr; - - do { - asm volatile( "mftbu %0" : "=r" (tbr_high_old)); - asm volatile( "mftb %0" : "=r" (tbr_low)); - asm volatile( "mftbu %0" : "=r" (tbr_high)); - } while ( tbr_high_old != tbr_high ); - - tbr = tbr_high; - tbr <<= 32; - tbr |= tbr_low; - return tbr; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/powerpc/rtems/powerpc/registers.h b/c/src/exec/score/cpu/powerpc/rtems/powerpc/registers.h deleted file mode 100644 index cfc6362a21..0000000000 --- a/c/src/exec/score/cpu/powerpc/rtems/powerpc/registers.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * This file contains some powerpc MSR and registers access definitions. - * - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk> - * Surrey Satellite Technology Limited - * - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __rtems_powerpc_registers_h -#define __rtems_powerpc_registers_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* Bit encodings for Machine State Register (MSR) */ -#define MSR_POW (1<<18) /* Enable Power Management */ -#define MSR_TGPR (1<<17) /* TLB Update registers in use */ -#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */ -#define MSR_EE (1<<15) /* External Interrupt enable */ -#define MSR_PR (1<<14) /* Supervisor/User privilege */ -#define MSR_FP (1<<13) /* Floating Point enable */ -#define MSR_ME (1<<12) /* Machine Check enable */ -#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ -#define MSR_SE (1<<10) /* Single Step */ -#define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ -#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction MMU enable */ -#define MSR_DR (1<<4) /* Data MMU enable */ -#define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little-Endian enable */ - -#define MSR_ MSR_ME|MSR_RI -#define MSR_KERNEL MSR_|MSR_IR|MSR_DR -#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE - -/* Bit encodings for Hardware Implementation Register (HID0) - on PowerPC 603, 604, etc. processors (not 601). */ -#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ -#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ -#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ -#define HID0_SBCLK (1<<27) -#define HID0_EICE (1<<26) -#define HID0_ECLK (1<<25) -#define HID0_PAR (1<<24) -#define HID0_DOZE (1<<23) -#define HID0_NAP (1<<22) -#define HID0_SLEEP (1<<21) -#define HID0_DPM (1<<20) -#define HID0_ICE (1<<15) /* Instruction Cache Enable */ -#define HID0_DCE (1<<14) /* Data Cache Enable */ -#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ -#define HID0_DLOCK (1<<12) /* Data Cache Lock */ -#define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */ -#define HID0_DCI (1<<10) /* Data Cache Invalidate */ -#define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */ -#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache [Enable] */ -#define HID0_BHTE (1<<2) /* Branch History Table Enable */ -#define HID0_BTCD (1<<1) /* Branch target cache disable */ - -/* fpscr settings */ -#define FPSCR_FX (1<<31) -#define FPSCR_FEX (1<<30) - -#define _MACH_prep 1 -#define _MACH_Pmac 2 /* pmac or pmac clone (non-chrp) */ -#define _MACH_chrp 4 /* chrp machine */ -#define _MACH_mbx 8 /* Motorola MBX board */ -#define _MACH_apus 16 /* amiga with phase5 powerup */ -#define _MACH_fads 32 /* Motorola FADS board */ - -/* see residual.h for these */ -#define _PREP_Motorola 0x01 /* motorola prep */ -#define _PREP_Firm 0x02 /* firmworks prep */ -#define _PREP_IBM 0x00 /* ibm prep */ -#define _PREP_Bull 0x03 /* bull prep */ - -/* these are arbitrary */ -#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ -#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ - -#define _GLOBAL(n)\ - .globl n;\ -n: - -#define TBRU 269 /* Time base Upper/Lower (Reading) */ -#define TBRL 268 -#define TBWU 284 /* Time base Upper/Lower (Writing) */ -#define TBWL 285 -#define XER 1 -#define LR 8 -#define CTR 9 -#define HID0 1008 /* Hardware Implementation */ -#define PVR 287 /* Processor Version */ -#define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */ -#define IBAT0L 529 -#define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */ -#define IBAT1L 531 -#define IBAT2U 532 /* Instruction BAT #2 Upper/Lower */ -#define IBAT2L 533 -#define IBAT3U 534 /* Instruction BAT #3 Upper/Lower */ -#define IBAT3L 535 -#define DBAT0U 536 /* Data BAT #0 Upper/Lower */ -#define DBAT0L 537 -#define DBAT1U 538 /* Data BAT #1 Upper/Lower */ -#define DBAT1L 539 -#define DBAT2U 540 /* Data BAT #2 Upper/Lower */ -#define DBAT2L 541 -#define DBAT3U 542 /* Data BAT #3 Upper/Lower */ -#define DBAT3L 543 -#define DMISS 976 /* TLB Lookup/Refresh registers */ -#define DCMP 977 -#define HASH1 978 -#define HASH2 979 -#define IMISS 980 -#define ICMP 981 -#define RPA 982 -#define SDR1 25 /* MMU hash base register */ -#define DAR 19 /* Data Address Register */ -#define SPR0 272 /* Supervisor Private Registers */ -#define SPRG0 272 -#define SPR1 273 -#define SPRG1 273 -#define SPR2 274 -#define SPRG2 274 -#define SPR3 275 -#define SPRG3 275 -#define DSISR 18 -#define SRR0 26 /* Saved Registers (exception) */ -#define SRR1 27 -#define IABR 1010 /* Instruction Address Breakpoint */ -#define DEC 22 /* Decrementer */ -#define EAR 282 /* External Address Register */ -#define L2CR 1017 /* PPC 750 L2 control register */ - -#define THRM1 1020 -#define THRM2 1021 -#define THRM3 1022 -#define THRM1_TIN 0x1 -#define THRM1_TIV 0x2 -#define THRM1_THRES (0x7f<<2) -#define THRM1_TID (1<<29) -#define THRM1_TIE (1<<30) -#define THRM1_V (1<<31) -#define THRM3_E (1<<31) - -/* Segment Registers */ -#define SR0 0 -#define SR1 1 -#define SR2 2 -#define SR3 3 -#define SR4 4 -#define SR5 5 -#define SR6 6 -#define SR7 7 -#define SR8 8 -#define SR9 9 -#define SR10 10 -#define SR11 11 -#define SR12 12 -#define SR13 13 -#define SR14 14 -#define SR15 15 - -#ifndef ASM -/* - * Routines to access the time base register - */ - -static inline unsigned long long PPC_Get_timebase_register( void ) -{ - unsigned long tbr_low; - unsigned long tbr_high; - unsigned long tbr_high_old; - unsigned long long tbr; - - do { - asm volatile( "mftbu %0" : "=r" (tbr_high_old)); - asm volatile( "mftb %0" : "=r" (tbr_low)); - asm volatile( "mftbu %0" : "=r" (tbr_high)); - } while ( tbr_high_old != tbr_high ); - - tbr = tbr_high; - tbr <<= 32; - tbr |= tbr_low; - return tbr; -} - -static inline void PPC_Set_timebase_register (unsigned long long tbr) -{ - unsigned long tbr_low; - unsigned long tbr_high; - - tbr_low = (tbr & 0xffffffff) ; - tbr_high = (tbr >> 32) & 0xffffffff; - asm volatile( "mtspr 284, %0" : : "r" (tbr_low)); - asm volatile( "mtspr 285, %0" : : "r" (tbr_high)); - -} -#endif - -#define _CPU_MSR_GET( _msr_value ) \ - do { \ - _msr_value = 0; \ - asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ - } while (0) - -#define _CPU_MSR_SET( _msr_value ) \ -{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } - -#define _CPU_ISR_Disable( _isr_cookie ) \ - { register unsigned int _disable_mask = MSR_EE; \ - _isr_cookie = 0; \ - asm volatile ( \ - "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \ - "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \ - "0" ((_isr_cookie)), "1" ((_disable_mask)) \ - ); \ - } - - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _isr_cookie is not modified. - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - { \ - asm volatile ( "mtmsr %0" : \ - "=r" ((_isr_cookie)) : \ - "0" ((_isr_cookie))); \ - } - -/* - * This temporarily restores the interrupt to _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _isr_cookie is not - * modified. - * - * NOTE: The version being used is not very optimized but it does - * not trip a problem in gcc where the disable mask does not - * get loaded. Check this for future (post 10/97 gcc versions. - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - { register unsigned int _disable_mask = MSR_EE; \ - asm volatile ( \ - "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \ - "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \ - "0" ((_isr_cookie)), "1" ((_disable_mask)) \ - ); \ - } - - -/* end of ISR handler macros */ - -/* - * Simple spin delay in microsecond units for device drivers. - * This is very dependent on the clock speed of the target. - */ - -#define CPU_Get_timebase_low( _value ) \ - asm volatile( "mftb %0" : "=r" (_value) ) - -#define rtems_bsp_delay( _microseconds ) \ - do { \ - unsigned32 start, ticks, now; \ - CPU_Get_timebase_low( start ) ; \ - ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \ - do \ - CPU_Get_timebase_low( now ) ; \ - while (now - start < ticks); \ - } while (0) - -#define rtems_bsp_delay_in_bus_cycles( _cycles ) \ - do { \ - unsigned32 start, now; \ - CPU_Get_timebase_low( start ); \ - do \ - CPU_Get_timebase_low( now ); \ - while (now - start < (_cycles)); \ - } while (0) - -#define PPC_Set_decrementer( _clicks ) \ - do { \ - asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - -#define PPC_Get_decrementer( _clicks ) \ - asm volatile( "mfdec %0" : "=r" (_clicks) ) - -#ifdef __cplusplus -} -#endif - -#endif /* __rtems_powerpc_registers_h */ diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/.cvsignore b/c/src/exec/score/cpu/powerpc/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/powerpc/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/cpu.h b/c/src/exec/score/cpu/powerpc/rtems/score/cpu.h deleted file mode 100644 index 7e181da7f8..0000000000 --- a/c/src/exec/score/cpu/powerpc/rtems/score/cpu.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * $Id$ - */ - -#ifndef _rtems_score_cpu_h -#define _rtems_score_cpu_h - -#include <rtems/score/ppc.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -#ifdef _OLD_EXCEPTIONS -#include <rtems/old-exceptions/cpu.h> -#else -#include <rtems/new-exceptions/cpu.h> -#endif - -#endif diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h b/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h deleted file mode 100644 index 6771919023..0000000000 --- a/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h +++ /dev/null @@ -1,733 +0,0 @@ -/* ppc.h - * - * This file contains definitions for the IBM/Motorola PowerPC - * family members. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com> - * MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk> - * Surrey Satellite Technology Limited - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * - * Note: - * This file is included by both C and assembler code ( -DASM ) - * - * $Id$ - */ - - -#ifndef _INCLUDE_PPC_h -#define _INCLUDE_PPC_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "PowerPC" - -/* - * This file contains the information required to build - * RTEMS for a particular member of the PowerPC family. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - * - * The following architectural feature definitions are defaulted - * unless specifically set by the model definition: - * - * + PPC_INTERRUPT_MAX - 16 - * + PPC_CACHE_ALIGNMENT - 32 - * + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE - * + PPC_HAS_EXCEPTION_PREFIX - 1 - * + PPC_HAS_FPU - 1 - * + PPC_HAS_DOUBLE - 1 if PPC_HAS_FPU, - * - 0 otherwise - * + PPC_USE_MULTIPLE - 0 - */ - -/* - * Define the low power mode models - * - * Standard: as defined for 603e - * Nap Mode: nap mode only (604) - * XXX 403GB, 603, 603e, 604, 821 - */ - -#define PPC_LOW_POWER_MODE_NONE 0 -#define PPC_LOW_POWER_MODE_STANDARD 1 - -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#if defined(ppc403) || defined(ppc405) -/* - * IBM 403 - * - * Developed for 403GA. Book checked for 403GB. - * - * Does not have user mode. - */ - -#if defined(ppc403) -#define CPU_MODEL_NAME "PowerPC 403" -#elif defined (ppc405) -#define CPU_MODEL_NAME "PowerPC 405" -#endif -#define PPC_ALIGNMENT 4 -#define PPC_CACHE_ALIGNMENT 16 -#define PPC_HAS_RFCI 1 -#define PPC_HAS_FPU 0 -#define PPC_USE_MULTIPLE 1 -#define PPC_I_CACHE 2048 -#define PPC_D_CACHE 1024 - -#define PPC_HAS_EXCEPTION_PREFIX 0 -#define PPC_HAS_EVPR 1 - -#elif defined(mpc555) - -#define CPU_MODEL_NAME "PowerPC 555" - -/* Copied from mpc505 */ -#define PPC_ALIGNMENT 4 -#define PPC_CACHE_ALIGNMENT 16 - -/* Based on comments by Sergei Organov <osv@Javad.RU> */ -#define PPC_I_CACHE 0 -#define PPC_D_CACHE 0 - -#elif defined(mpc505) || defined(mpc509) -/* - * Submitted by Sergei Organov <osv@Javad.RU> as a patch against - * 3.6.0 long after 4.0 was released. This is just an attempt - * to get the setting correct. - */ - -#define CPU_MODEL_NAME "PowerPC 505/509" - -#define PPC_ALIGNMENT 4 -#define PPC_CACHE_ALIGNMENT 16 -#define PPC_I_CACHE 4096 -#define PPC_D_CACHE 0 - - -#elif defined(ppc601) - -/* - * Submitted with original port -- book checked only. - */ - -#define CPU_MODEL_NAME "PowerPC 601" - -#define PPC_ALIGNMENT 8 -#define PPC_USE_MULTIPLE 1 -#define PPC_I_CACHE 0 -#define PPC_D_CACHE 32768 - -#elif defined(ppc602) -/* - * Submitted with original port -- book checked only. - */ - -#define CPU_MODEL_NAME "PowerPC 602" - -#define PPC_ALIGNMENT 4 -#define PPC_HAS_DOUBLE 0 -#define PPC_I_CACHE 4096 -#define PPC_D_CACHE 4096 - -#elif defined(ppc603) -/* - * Submitted with original port -- book checked only. - */ - -#define CPU_MODEL_NAME "PowerPC 603" - -#define PPC_ALIGNMENT 8 -#define PPC_I_CACHE 8192 -#define PPC_D_CACHE 8192 - -#elif defined(ppc603e) - -#define CPU_MODEL_NAME "PowerPC 603e" -/* - * Submitted with original port. - * - * Known to work on real hardware. - */ - -#define PPC_ALIGNMENT 8 -#define PPC_I_CACHE 16384 -#define PPC_D_CACHE 16384 - -#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD - -#elif defined(mpc604) -/* - * Submitted with original port -- book checked only. - */ - -#define CPU_MODEL_NAME "PowerPC 604" - -#define PPC_ALIGNMENT 8 -#define PPC_I_CACHE 16384 -#define PPC_D_CACHE 16384 - -#elif defined(mpc860) -/* - * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 - * with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca) - */ -#define CPU_MODEL_NAME "PowerPC MPC860" - -#define PPC_ALIGNMENT 4 -#define PPC_I_CACHE 4096 -#define PPC_D_CACHE 4096 -#define PPC_CACHE_ALIGNMENT 16 -#define PPC_INTERRUPT_MAX 71 -#define PPC_HAS_FPU 0 -#define PPC_HAS_DOUBLE 0 -#define PPC_USE_MULTIPLE 1 - -#define PPC_MSR_0 0x00009000 -#define PPC_MSR_1 0x00001000 -#define PPC_MSR_2 0x00001000 -#define PPC_MSR_3 0x00000000 - -#elif defined(mpc821) -/* - * Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999 - */ -#define CPU_MODEL_NAME "PowerPC MPC821" - -#define PPC_ALIGNMENT 4 -#define PPC_I_CACHE 4096 -#define PPC_D_CACHE 4096 -#define PPC_CACHE_ALIGNMENT 16 -#define PPC_INTERRUPT_MAX 71 -#define PPC_HAS_FPU 0 -#define PPC_HAS_DOUBLE 0 - -#define PPC_MSR_0 0x00009000 -#define PPC_MSR_1 0x00001000 -#define PPC_MSR_2 0x00001000 -#define PPC_MSR_3 0x00000000 - -#elif defined(mpc750) - -#define CPU_MODEL_NAME "PowerPC 750" - -#define PPC_ALIGNMENT 8 -#define PPC_I_CACHE 16384 -#define PPC_D_CACHE 16384 - -#elif defined(mpc7400) - -#define CPU_MODEL_NAME "PowerPC 7400" - -#define PPC_ALIGNMENT 8 -#define PPC_I_CACHE 32768 -#define PPC_D_CACHE 32768 - -#elif defined(mpc8260) -/* - * Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000 - */ -#define CPU_MODEL_NAME "PowerPC MPC8260" - -#define PPC_ALIGNMENT 4 -#define PPC_I_CACHE 16384 -#define PPC_D_CACHE 16384 -#define PPC_CACHE_ALIGNMENT 32 -#define PPC_INTERRUPT_MAX 125 -/*#define PPC_HAS_FPU 0 */ /* my 8260 is one the few with no FPU */ -#define PPC_HAS_FPU 1 /* the rest do have one */ -#define PPC_HAS_DOUBLE 1 -#define PPC_USE_MULTIPLE 1 -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Application binary interfaces. - * - * PPC_ABI MUST be defined as one of these. - * Only PPC_ABI_POWEROPEN is currently fully supported. - * Only EABI will be supported in the end when - * the tools are there. - * Only big endian is currently supported. - */ -/* - * PowerOpen ABI. This is Andy's hack of the - * PowerOpen ABI to ELF. ELF rather than a - * XCOFF assembler is used. This may work - * if PPC_ASM == PPC_ASM_XCOFF is defined. - */ -#define PPC_ABI_POWEROPEN 0 -/* - * GCC 2.7.0 munched version of EABI, with - * PowerOpen calling convention and stack frames, - * but EABI style indirect function calls. - */ -#define PPC_ABI_GCC27 1 -/* - * SVR4 ABI - */ -#define PPC_ABI_SVR4 2 -/* - * Embedded ABI - */ -#define PPC_ABI_EABI 3 - -/* - * Default to the EABI used by current GNU tools - */ - -#ifndef PPC_ABI -#define PPC_ABI PPC_ABI_EABI -#endif - -#if (PPC_ABI == PPC_ABI_POWEROPEN) -#define PPC_STACK_ALIGNMENT 8 -#elif (PPC_ABI == PPC_ABI_GCC27) -#define PPC_STACK_ALIGNMENT 8 -#elif (PPC_ABI == PPC_ABI_SVR4) -#define PPC_STACK_ALIGNMENT 16 -#elif (PPC_ABI == PPC_ABI_EABI) -#define PPC_STACK_ALIGNMENT 8 -#else -#error "PPC_ABI is not properly defined" -#endif -#ifndef PPC_ABI -#error "PPC_ABI is not properly defined" -#endif - -/* - * Assemblers. - * PPC_ASM MUST be defined as one of these. - * - * PPC_ASM_ELF: ELF assembler. Currently used for all ABIs. - * PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI. - * - * NOTE: Only PPC_ABI_ELF is currently fully supported. - */ - -#define PPC_ASM_ELF 0 -#define PPC_ASM_XCOFF 1 - -/* - * Default to the assembler format used by the current GNU tools. - */ - -#ifndef PPC_ASM -#define PPC_ASM PPC_ASM_ELF -#endif - -/* - * If the maximum number of exception sources has not been defined, - * then default it to 16. - */ - -#ifndef PPC_INTERRUPT_MAX -#define PPC_INTERRUPT_MAX 16 -#endif - -/* - * Unless specified otherwise, the cache line size is defaulted to 32. - * - * The derive the power of 2 the cache line is. - */ - -#ifndef PPC_CACHE_ALIGNMENT -#define PPC_CACHE_ALIGNMENT 32 -#endif - -#if (PPC_CACHE_ALIGNMENT == 16) -#define PPC_CACHE_ALIGN_POWER 4 -#elif (PPC_CACHE_ALIGNMENT == 32) -#define PPC_CACHE_ALIGN_POWER 5 -#else -#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT" -#endif - -/* - * Unless otherwise specified, assume the model has an IP/EP bit to - * set the exception address prefix. - */ - -#ifndef PPC_HAS_EXCEPTION_PREFIX -#define PPC_HAS_EXCEPTION_PREFIX 1 -#endif - -/* - * Unless otherwise specified, assume the model does NOT have - * 403 style EVPR register to set the exception address prefix. - */ - -#ifndef PPC_HAS_EVPR -#define PPC_HAS_EVPR 0 -#endif - -/* - * If no low power mode model was specified, then assume there is none. - */ - -#ifndef PPC_LOW_POWER_MODE -#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE -#endif - -/* - * Unless specified above, then assume the model has FP support. - */ - -#ifndef PPC_HAS_FPU -#define PPC_HAS_FPU 1 -#endif - -/* - * Unless specified above, If the model has FP support, it is assumed to - * support doubles (8-byte floating point numbers). - * - * If the model does NOT have FP support, then the model does - * NOT have double length FP registers. - */ - -#ifndef PPC_HAS_DOUBLE -#if (PPC_HAS_FPU) -#define PPC_HAS_DOUBLE 1 -#else -#define PPC_HAS_DOUBLE 0 -#endif -#endif - -/* - * Unless specified above, then assume the model does NOT have critical - * interrupt support. - */ - -#ifndef PPC_HAS_RFCI -#define PPC_HAS_RFCI 0 -#endif - -/* - * Unless specified above, do not use the load/store multiple instructions - * in a context switch. - */ - -#ifndef PPC_USE_MULTIPLE -#define PPC_USE_MULTIPLE 0 -#endif - -/* - * The following exceptions are not maskable, and are not - * necessarily predictable, so cannot be offered to RTEMS: - * Alignment exception - handled by the CPU module - * Data exceptions. - * Instruction exceptions. - */ - -/* - * Base Interrupt vectors supported on all models. - */ -#define PPC_IRQ_SYSTEM_RESET 0 /* 0x00100 - System reset. */ -#define PPC_IRQ_MCHECK 1 /* 0x00200 - Machine check */ -#define PPC_IRQ_PROTECT 2 /* 0x00300 - Protection violation */ -#define PPC_IRQ_ISI 3 /* 0x00400 - Instruction Fetch error */ -#define PPC_IRQ_EXTERNAL 4 /* 0x00500 - External interrupt */ -#define PPC_IRQ_ALIGNMENT 5 /* 0X00600 - Alignment exception */ -#define PPC_IRQ_PROGRAM 6 /* 0x00700 - Program exception */ -#define PPC_IRQ_NOFP 7 /* 0x00800 - Floating point unavailable */ -#define PPC_IRQ_DECREMENTER 8 /* 0x00900 - Decrementer interrupt */ -#define PPC_IRQ_RESERVED_A 9 /* 0x00a00 - Implementation Reserved */ -#define PPC_IRQ_RESERVED_B 10 /* 0x00b00 - Implementation Reserved */ -#define PPC_IRQ_SCALL 11 /* 0x00c00 - System call */ -#define PPC_IRQ_TRACE 12 /* 0x00d00 - Trace Exception */ -#define PPC_IRQ_FP_ASST 13 /* ox00e00 - Floating point assist */ -#define PPC_STD_IRQ_LAST PPC_IRQ_FP_ASST - -#define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET - -#if defined(ppc403) || defined(ppc405) - -#define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ -#define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ -#define PPC_IRQ_FIT (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer */ -#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer */ -#define PPC_IRQ_DEBUG (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions */ -#define PPC_IRQ_LAST PPC_IRQ_DEBUG - -#elif defined(mpc505) || defined(mpc509) -#define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ -#define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+ 2) -#define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+ 3) -#define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+ 4) -#define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+ 5) - -#elif defined(ppc601) -#define PPC_IRQ_TRACE (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/ -#define PPC_IRQ_LAST PPC_IRQ_TRACE - -#elif defined(ppc602) -#define PPC_IRQ_LAST (PPC_STD_IRQ_LAST) - -#elif defined(ppc603) -#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/ -#define PPC_IRQ_DATA_LOAD (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/ -#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss */ -#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */ -#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ -#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT - -#elif defined(ppc603e) -#define PPC_TLB_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/ -#define PPC_TLB_LOAD_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load */ -#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */ -#define PPC_IRQ_ADDRBRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */ -#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ -#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT - - -#elif defined(mpc604) -#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break */ -#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */ -#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT - -#elif defined(mpc860) || defined(mpc821) -#define PPC_IRQ_EMULATE (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation */ -#define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/ -#define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */ -#define PPC_IRQ_INST_ERR (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */ -#define PPC_IRQ_DATA_ERR (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */ -#define PPC_IRQ_DATA_BPNT (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */ -#define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */ -#define PPC_IRQ_IO_BPNT (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */ -#define PPC_IRQ_DEV_PORT (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */ -#define PPC_IRQ_IRQ0 (PPC_STD_IRQ_LAST + 10) -#define PPC_IRQ_LVL0 (PPC_STD_IRQ_LAST + 11) -#define PPC_IRQ_IRQ1 (PPC_STD_IRQ_LAST + 12) -#define PPC_IRQ_LVL1 (PPC_STD_IRQ_LAST + 13) -#define PPC_IRQ_IRQ2 (PPC_STD_IRQ_LAST + 14) -#define PPC_IRQ_LVL2 (PPC_STD_IRQ_LAST + 15) -#define PPC_IRQ_IRQ3 (PPC_STD_IRQ_LAST + 16) -#define PPC_IRQ_LVL3 (PPC_STD_IRQ_LAST + 17) -#define PPC_IRQ_IRQ4 (PPC_STD_IRQ_LAST + 18) -#define PPC_IRQ_LVL4 (PPC_STD_IRQ_LAST + 19) -#define PPC_IRQ_IRQ5 (PPC_STD_IRQ_LAST + 20) -#define PPC_IRQ_LVL5 (PPC_STD_IRQ_LAST + 21) -#define PPC_IRQ_IRQ6 (PPC_STD_IRQ_LAST + 22) -#define PPC_IRQ_LVL6 (PPC_STD_IRQ_LAST + 23) -#define PPC_IRQ_IRQ7 (PPC_STD_IRQ_LAST + 24) -#define PPC_IRQ_LVL7 (PPC_STD_IRQ_LAST + 25) -#define PPC_IRQ_CPM_ERROR (PPC_STD_IRQ_LAST + 26) -#define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 27) -#define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 28) -#define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 29) -#define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 30) -#define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 31) -#define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 32) -#define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 33) -#define PPC_IRQ_CPM_RESERVED_8 (PPC_STD_IRQ_LAST + 34) -#define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 35) -#define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 36) -#define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 37) -#define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 38) -#define PPC_IRQ_CPM_RESERVED_D (PPC_STD_IRQ_LAST + 39) -#define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 40) -#define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 41) -#define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 42) -#define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 43) -#define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 44) -#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45) -#define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 46) -#define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 47) -#define PPC_IRQ_CPM_SDMA_ERROR (PPC_STD_IRQ_LAST + 48) -#define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 49) -#define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 50) -#define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 51) -#define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 52) -#define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 53) -#define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 54) -#define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 55) -#define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 56) -#define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 57) - -#define PPC_IRQ_LAST PPC_IRQ_CPM_PC15 - -#elif defined(mpc8260) - -#define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/ -#define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */ -#define PPC_IRQ_DATA_L_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */ -#define PPC_IRQ_DATA_S_MISS (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */ -#define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */ -#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */ -/* 0x1600 - 0x2F00 reserved */ -#define PPC_IRQ_CPM_NONE (PPC_STD_IRQ_LAST + 50) -#define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 51) -#define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 52) -#define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 53) -#define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 54) -#define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 55) -#define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 56) -#define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 57) -#define PPC_IRQ_CPM_IDMA3 (PPC_STD_IRQ_LAST + 58) -#define PPC_IRQ_CPM_IDMA4 (PPC_STD_IRQ_LAST + 59) -#define PPC_IRQ_CPM_SDMA (PPC_STD_IRQ_LAST + 60) -#define PPC_IRQ_CPM_RES_A (PPC_STD_IRQ_LAST + 61) -#define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 62) -#define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 63) -#define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 64) -#define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 65) -#define PPC_IRQ_CPM_TMCNT (PPC_STD_IRQ_LAST + 66) -#define PPC_IRQ_CPM_PIT (PPC_STD_IRQ_LAST + 67) -#define PPC_IRQ_CPM_RES_B (PPC_STD_IRQ_LAST + 68) -#define PPC_IRQ_CPM_IRQ1 (PPC_STD_IRQ_LAST + 69) -#define PPC_IRQ_CPM_IRQ2 (PPC_STD_IRQ_LAST + 70) -#define PPC_IRQ_CPM_IRQ3 (PPC_STD_IRQ_LAST + 71) -#define PPC_IRQ_CPM_IRQ4 (PPC_STD_IRQ_LAST + 72) -#define PPC_IRQ_CPM_IRQ5 (PPC_STD_IRQ_LAST + 73) -#define PPC_IRQ_CPM_IRQ6 (PPC_STD_IRQ_LAST + 74) -#define PPC_IRQ_CPM_IRQ7 (PPC_STD_IRQ_LAST + 75) -#define PPC_IRQ_CPM_RES_C (PPC_STD_IRQ_LAST + 76) -#define PPC_IRQ_CPM_RES_D (PPC_STD_IRQ_LAST + 77) -#define PPC_IRQ_CPM_RES_E (PPC_STD_IRQ_LAST + 78) -#define PPC_IRQ_CPM_RES_F (PPC_STD_IRQ_LAST + 79) -#define PPC_IRQ_CPM_RES_G (PPC_STD_IRQ_LAST + 80) -#define PPC_IRQ_CPM_RES_H (PPC_STD_IRQ_LAST + 81) -#define PPC_IRQ_CPM_FCC1 (PPC_STD_IRQ_LAST + 82) -#define PPC_IRQ_CPM_FCC2 (PPC_STD_IRQ_LAST + 83) -#define PPC_IRQ_CPM_FCC3 (PPC_STD_IRQ_LAST + 84) -#define PPC_IRQ_CPM_RES_I (PPC_STD_IRQ_LAST + 85) -#define PPC_IRQ_CPM_MCC1 (PPC_STD_IRQ_LAST + 86) -#define PPC_IRQ_CPM_MCC2 (PPC_STD_IRQ_LAST + 87) -#define PPC_IRQ_CPM_RES_J (PPC_STD_IRQ_LAST + 88) -#define PPC_IRQ_CPM_RES_K (PPC_STD_IRQ_LAST + 89) -#define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 90) -#define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 91) -#define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 92) -#define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 93) -#define PPC_IRQ_CPM_RES_L (PPC_STD_IRQ_LAST + 94) -#define PPC_IRQ_CPM_RES_M (PPC_STD_IRQ_LAST + 95) -#define PPC_IRQ_CPM_RES_N (PPC_STD_IRQ_LAST + 96) -#define PPC_IRQ_CPM_RES_O (PPC_STD_IRQ_LAST + 97) -#define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 98) -#define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 99) -#define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 100) -#define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 101) -#define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 102) -#define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 103) -#define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 104) -#define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 105) -#define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 106) -#define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 107) -#define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 108) -#define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 109) -#define PPC_IRQ_CPM_PC3 (PPC_STD_IRQ_LAST + 110) -#define PPC_IRQ_CPM_PC2 (PPC_STD_IRQ_LAST + 111) -#define PPC_IRQ_CPM_PC1 (PPC_STD_IRQ_LAST + 112) -#define PPC_IRQ_CPM_PC0 (PPC_STD_IRQ_LAST + 113) - -#define PPC_IRQ_LAST PPC_IRQ_CPM_PC0 - -#endif - - -/* - * If the maximum number of exception sources is too low, - * then fix it - */ - -#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST -#undef PPC_INTERRUPT_MAX -#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1) -#endif - -/* - * Machine Status Register (MSR) Constants Used by RTEMS - */ - -/* - * Some PPC model manuals refer to the Exception Prefix (EP) bit as - * IP for no apparent reason. - */ - -#define PPC_MSR_RI 0x000000002 /* bit 30 - recoverable exception */ -#define PPC_MSR_DR 0x000000010 /* bit 27 - data address translation */ -#define PPC_MSR_IR 0x000000020 /* bit 26 - instruction addr translation*/ - -#if (PPC_HAS_EXCEPTION_PREFIX) -#define PPC_MSR_EP 0x000000040 /* bit 25 - exception prefix */ -#else -#define PPC_MSR_EP 0x000000000 /* bit 25 - exception prefix */ -#endif - -#if (PPC_HAS_FPU) -#define PPC_MSR_FP 0x000002000 /* bit 18 - floating point enable */ -#else -#define PPC_MSR_FP 0x000000000 /* bit 18 - floating point enable */ -#endif - -#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE) -#define PPC_MSR_POW 0x000000000 /* bit 13 - power management enable */ -#else -#define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */ -#endif - -#define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */ -#define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */ - -#if (PPC_HAS_RFCI) -#define PPC_MSR_CE 0x000020000 /* bit 14 - critical interrupt enable */ -#else -#define PPC_MSR_CE 0x000000000 /* bit 14 - critical interrupt enable */ -#endif - -#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE) - -/* - * Initial value for the FPSCR register - */ - -#define PPC_INIT_FPSCR 0x000000f8 - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_PPC_h */ -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/types.h b/c/src/exec/score/cpu/powerpc/rtems/score/types.h deleted file mode 100644 index 13fdf35538..0000000000 --- a/c/src/exec/score/cpu/powerpc/rtems/score/types.h +++ /dev/null @@ -1,72 +0,0 @@ -/* types.h - * - * This include file contains type definitions pertaining to the PowerPC - * processor family. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/no_cputypes.h: - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __PPC_TYPES_h -#define __PPC_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned32 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void ppc_isr; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/sh/.cvsignore b/c/src/exec/score/cpu/sh/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/sh/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/sh/ChangeLog b/c/src/exec/score/cpu/sh/ChangeLog deleted file mode 100644 index ba72b43eb6..0000000000 --- a/c/src/exec/score/cpu/sh/ChangeLog +++ /dev/null @@ -1,132 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-04-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Adaptation to gcc-3.0.x. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/shtypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-31 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Reflect 2002-01-23 changes. - -2002-01-31 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Reflect 2002-01-23 changes. - -2002-01-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-15 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * cpu.c: Fix #ifdefs, add missing #endif. - -2001-10-12 Joel Sherrill <joel@OARcorp.com> - - * asm.h, cpu.c, rtems.c, rtems/score/cpu.h, rtems/score/sh.h, - rtems/score/sh_io.h, rtems/score/shtypes.h: Consistency changes - and made sure there were no includes from the libcpu tree. - -2001-10-12 Alexandra Kossovsky <sasha@oktet.ru> - - * cpu.c, rtems/score/cpu.h, rtems/score/sh.h: Modified to - support SH4. Reviewed by Ralf Corsepius <corsepiu@faw.uni-ulm.de> - who did the original SH port. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-07-25 Radzislaw Galler <rgaller@et.put.poznan.pl> - - * cpu.c (_CPU_ISR_install_vector): Corrected interrupt range - checking which was SH1 specific. It didn't work for SH2 (has more - interrupt sources). - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/sh/Makefile.am b/c/src/exec/score/cpu/sh/Makefile.am deleted file mode 100644 index 9a7a81de82..0000000000 --- a/c/src/exec/score/cpu/sh/Makefile.am +++ /dev/null @@ -1,52 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS= asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/types.h \ - rtems/score/sh.h \ - rtems/score/sh_io.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/sh/asm.h b/c/src/exec/score/cpu/sh/asm.h deleted file mode 100644 index d4882bd4ba..0000000000 --- a/c/src/exec/score/cpu/sh/asm.h +++ /dev/null @@ -1,136 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_SH_ASM_h -#define __CPU_SH_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif - -#include <rtems/score/cpuopts.h> -#include <rtems/score/sh.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG (r0) -#define r1 REG (r1) -#define r2 REG (r2) -#define r3 REG (r3) -#define r4 REG (r4) -#define r5 REG (r5) -#define r6 REG (r6) -#define r7 REG (r7) -#define r8 REG (r8) -#define r9 REG (r9) -#define r10 REG (r10) -#define r11 REG (r11) -#define r12 REG (r12) -#define r13 REG (r13) -#define r14 REG (r14) -#define r15 REG (r15) -#define vbr REG (vbr) -#define gbr REG (gbr) -#define pr REG (pr) -#define mach REG (mach) -#define macl REG (macl) -#define sr REG (sr) -#define pc REG (pc) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .global SYM (sym) -#define EXTERN(sym) .global SYM (sym) - -#endif diff --git a/c/src/exec/score/cpu/sh/configure.ac b/c/src/exec/score/cpu/sh/configure.ac deleted file mode 100644 index cdaf06333f..0000000000 --- a/c/src/exec/score/cpu/sh/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-sh],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([asm.h]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/sh/cpu.c b/c/src/exec/score/cpu/sh/cpu.c deleted file mode 100644 index b83292e304..0000000000 --- a/c/src/exec/score/cpu/sh/cpu.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * This file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/sh_io.h> -#include <rtems/score/cpu.h> -#include <rtems/score/sh.h> - -/* referenced in start.S */ -extern proc_ptr vectab[] ; - -proc_ptr vectab[256] ; - -extern proc_ptr _Hardware_isr_Table[]; - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - register unsigned32 level = 0; - - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; - - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ - /* FIXME: When not to use SH4_FPSCR_PR ? */ -#ifdef __SH4__ - _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR; -#endif -#ifdef __SH3E__ - /* FIXME: Wild guess :) */ - _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM; -#endif - - _CPU_Table = *cpu_table; - - /* enable interrupts */ - _CPU_ISR_Set_level( level); -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ - - register unsigned32 _mask ; - - sh_get_interrupt_level( _mask ); - - return ( _mask); -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ - volatile proc_ptr *vbr ; - -#if SH_PARANOID_ISR - unsigned32 level ; - - sh_disable_interrupts( level ); -#endif - - /* get vbr */ - asm ( "stc vbr,%0" : "=r" (vbr) ); - - *old_handler = vbr[vector] ; - vbr[vector] = new_handler ; - -#if SH_PARANOID_ISR - sh_enable_interrupts( level ); -#endif -} - - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -#if defined(__sh1__) || defined(__sh2__) -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - proc_ptr ignored ; -#if 0 - if(( vector <= 113) && ( vector >= 11)) - { -#endif - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - _CPU_ISR_install_raw_handler(vector, - _Hardware_isr_Table[vector], - &ignored ); - - /* - * We put the actual user ISR address in '_ISR_Vector_table'. - * This will be used by __ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -#if 0 - } -#endif -} -#endif /* _CPU_ISR_install_vector */ - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) -void _CPU_Thread_Idle_body( void ) -{ - - for( ; ; ) - { - asm volatile("nop"); - } - /* insert your "halt" instruction here */ ; -} -#endif - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -unsigned8 _bit_set_table[16] = - { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0}; - - -#endif - -void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - unsigned32 _size, - unsigned32 _isr, - void (*_entry_point)(void), - int _is_fp ) -{ - _the_context->r15 = (unsigned32*) ((unsigned32) (_stack_base) + (_size) ); -#if defined(__sh1__) || defined(__sh2__) - _the_context->sr = (_isr << 4) & 0x00f0 ; -#else - _the_context->sr = SH4_SR_MD | ((_isr << 4) & 0x00f0); -#endif - _the_context->pr = (unsigned32*) _entry_point ; - - -#if 0 && SH_HAS_FPU - /* Disable FPU if it is non-fp task */ - if(!_is_fp) - _the_context->sr |= SH4_SR_FD; -#endif -} - diff --git a/c/src/exec/score/cpu/sh/rtems/.cvsignore b/c/src/exec/score/cpu/sh/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/sh/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/sh/rtems/score/.cvsignore b/c/src/exec/score/cpu/sh/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/sh/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/sh/rtems/score/cpu.h b/c/src/exec/score/cpu/sh/rtems/score/cpu.h deleted file mode 100644 index 40c39b4444..0000000000 --- a/c/src/exec/score/cpu/sh/rtems/score/cpu.h +++ /dev/null @@ -1,952 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef _SH_CPU_h -#define _SH_CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/sh.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif -#if 0 && defined(__SH4__) -#include <rtems/score/sh4_regs.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * We define the interrupt stack in the linker script - */ -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * We currently support sh1 only, which has no FPU, other SHes have an FPU - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if SH_HAS_FPU -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE -#else -#define CPU_SOFTWARE_FP FALSE -#define CPU_HARDWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#if SH_HAS_FPU -#define CPU_ALL_TASKS_ARE_FP TRUE -#else -#define CPU_ALL_TASKS_ARE_FP FALSE -#endif - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#if SH_HAS_FPU -#define CPU_IDLE_TASK_IS_FP TRUE -#else -#define CPU_IDLE_TASK_IS_FP FALSE -#endif - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#if SH_HAS_FPU -#define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else -#define CPU_USE_DEFERRED_FP_SWITCH TRUE -#endif - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: SHes can be big or little endian, the default is big endian - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE - -/* __LITTLE_ENDIAN__ is defined if -ml is given to gcc */ -#if defined(__LITTLE_ENDIAN__) -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE -#else -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE -#endif - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x0000000f - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - unsigned32 *r15; /* stack pointer */ - - unsigned32 macl; - unsigned32 mach; - unsigned32 *pr; - - unsigned32 *r14; /* frame pointer/call saved */ - - unsigned32 r13; /* call saved */ - unsigned32 r12; /* call saved */ - unsigned32 r11; /* call saved */ - unsigned32 r10; /* call saved */ - unsigned32 r9; /* call saved */ - unsigned32 r8; /* call saved */ - - unsigned32 *r7; /* arg in */ - unsigned32 *r6; /* arg in */ - -#if 0 - unsigned32 *r5; /* arg in */ - unsigned32 *r4; /* arg in */ -#endif - - unsigned32 *r3; /* scratch */ - unsigned32 *r2; /* scratch */ - unsigned32 *r1; /* scratch */ - - unsigned32 *r0; /* arg return */ - - unsigned32 gbr; - unsigned32 sr; - -} Context_Control; - -typedef struct { -#if SH_HAS_FPU -#ifdef SH4_USE_X_REGISTERS - union { - float f[16]; - double d[8]; - } x; -#endif - union { - float f[16]; - double d[8]; - } r; - float fpul; /* fp communication register */ - unsigned32 fpscr; /* fp control register */ -#endif /* SH_HAS_FPU */ -} Context_Control_fp; - -typedef struct { -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the SH processor specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - unsigned32 clicks_per_second ; /* cpu frequency in Hz */ -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access SH specific additions to the CPU Table - */ - -#define rtems_cpu_configuration_get_clicks_per_second() \ - (_CPU_Table.clicks_per_second) - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -#if SH_HAS_FPU -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -#endif - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ -SCORE_EXTERN void CPU_delay( unsigned32 microseconds ); - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - * We have been able to run the sptests with this value, but have not - * been able to run the tmtest suite. - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ -#if defined(__SH4__) -/* FIXME: sh3 and SH3E? */ -#define CPU_ALIGNMENT 8 -#else -#define CPU_ALIGNMENT 4 -#endif - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * SH Specific Information: NONE - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level) \ - sh_disable_interrupts( _level ) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level) \ - sh_enable_interrupts( _level) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level) \ - sh_flash_interrupts( _level) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ - -#define _CPU_ISR_Set_level( _newlevel) \ - sh_set_interrupt_level(_newlevel) - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - */ - -/* - * FIXME: defined as a function for debugging - should be a macro - */ -SCORE_EXTERN void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - unsigned32 _size, - unsigned32 _isr, - void (*_entry_point)(void), - int _is_fp ); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have. - */ - -#if SH_HAS_FPU -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\ - } while(0) -#else -#define _CPU_Context_Initialize_fp( _destination ) \ - { } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * FIXME: Trap32 ??? - * - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * invokes a Trap32 Instruction which returns to the breakpoint - * routine of cmon. - */ - -#ifdef BSP_FATAL_HALT - /* we manage the fatal error in the board support package */ - void bsp_fatal_halt( unsigned32 _error); -#define _CPU_Fatal_halt( _error ) bsp_fatal_halt( _error) -#else -#define _CPU_Fatal_halt( _error)\ -{ \ - asm volatile("mov.l %0,r0"::"m" (_error)); \ - asm volatile("mov #1, r4"); \ - asm volatile("trapa #34"); \ -} -#endif - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -extern unsigned8 _bit_set_table[]; - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - _output = 0;\ - if(_value > 0x00ff) \ - { _value >>= 8; _output = 8; } \ - if(_value > 0x000f) \ - { _output += 4; _value >>= 4; } \ - _output += _bit_set_table[ _value]; } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/sh/rtems/score/sh.h b/c/src/exec/score/cpu/sh/rtems/score/sh.h deleted file mode 100644 index a48dea97f0..0000000000 --- a/c/src/exec/score/cpu/sh/rtems/score/sh.h +++ /dev/null @@ -1,269 +0,0 @@ -/* sh.h - * - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef _sh_h -#define _sh_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "SH" family. - * - * It does this by setting variables to indicate which implementation - * dependent features are present in a particular member of the family. - */ - -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#if defined(__SH3E__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) - -/* - * Define this if you want to use XD-registers. - * Then this registers will be saved/restored on context switch. - * ! They will not be saved/restored on interrupts! - */ -#define SH4_USE_X_REGISTERS 0 - -#if defined(__LITTLE_ENDIAN__) -#define SH_HAS_FPU 1 -#else -/* FIXME: Context_Control_fp does not support big endian */ -#warning FPU not supported -#define SH_HAS_FPU 0 -#endif - -#elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__) -#define SH_HAS_FPU 0 -#else -#warning Cannot detect FPU support, assuming no FPU -#define SH_HAS_FPU 0 -#endif - -/* this should not be here */ -#ifndef CPU_MODEL_NAME -#define CPU_MODEL_NAME "SH-Multilib" -#endif - -/* - * If the following macro is set to 0 there will be no software irq stack - */ - -#ifndef SH_HAS_SEPARATE_STACKS -#define SH_HAS_SEPARATE_STACKS 1 -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "Hitachi SH" - -#ifndef ASM - -#if defined(__sh1__) || defined(__sh2__) - -/* - * Mask for disabling interrupts - */ -#define SH_IRQDIS_VALUE 0xf0 - -#define sh_disable_interrupts( _level ) \ - asm volatile ( \ - "stc sr,%0\n\t" \ - "ldc %1,sr\n\t"\ - : "=&r" (_level ) \ - : "r" (SH_IRQDIS_VALUE) ); - -#define sh_enable_interrupts( _level ) \ - asm volatile( "ldc %0,sr\n\t" \ - "nop\n\t" \ - :: "r" (_level) ); - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define sh_flash_interrupts( _level ) \ - asm volatile( \ - "ldc %1,sr\n\t" \ - "nop\n\t" \ - "ldc %0,sr\n\t" \ - "nop\n\t" \ - : : "r" (SH_IRQDIS_VALUE), "r" (_level) ); - -#else - -#define SH_IRQDIS_MASK 0xf0 - -#define sh_disable_interrupts( _level ) \ - asm volatile ( \ - "stc sr,%0\n\t" \ - "mov %0,r5\n\t" \ - "or %1,r5\n\t" \ - "ldc r5,sr\n\t"\ - : "=&r" (_level ) \ - : "r" (SH_IRQDIS_MASK) \ - : "r5" ); - -#define sh_enable_interrupts( _level ) \ - asm volatile( "ldc %0,sr\n\t" \ - "nop\n\t" \ - :: "r" (_level) ); - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define sh_flash_interrupts( _level ) \ - asm volatile( \ - "stc sr,r5\n\t" \ - "ldc %1,sr\n\t" \ - "nop\n\t" \ - "or %0,r5\n\t" \ - "ldc r5,sr\n\t" \ - "nop\n\t" \ - : : "r" (SH_IRQDIS_MASK), "r" (_level) : "r5"); - -#endif - -#define sh_get_interrupt_level( _level ) \ -{ \ - register unsigned32 _tmpsr ; \ - \ - asm volatile( "stc sr, %0" : "=r" (_tmpsr) ); \ - _level = (_tmpsr & 0xf0) >> 4 ; \ -} - -#define sh_set_interrupt_level( _newlevel ) \ -{ \ - register unsigned32 _tmpsr; \ - \ - asm volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \ - _tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \ - asm volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \ -} - -/* - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - */ - -static inline unsigned int sh_swap_u32( - unsigned int value -) -{ - register unsigned int swapped; - - asm volatile ( - "swap.b %1,%0; " - "swap.w %0,%0; " - "swap.b %0,%0" - : "=r" (swapped) - : "r" (value) ); - - return( swapped ); -} - -static inline unsigned int sh_swap_u16( - unsigned int value -) -{ - register unsigned int swapped ; - - asm volatile ( "swap.b %1,%0" : "=r" (swapped) : "r" (value) ); - - return( swapped ); -} - -#define CPU_swap_u32( value ) sh_swap_u32( value ) -#define CPU_swap_u16( value ) sh_swap_u16( value ) - -extern unsigned int sh_set_irq_priority( - unsigned int irq, - unsigned int prio ); - -#endif /* !ASM */ - -/* - * Bits on SH-4 registers. - * See SH-4 Programming manual for more details. - * - * Added by Alexandra Kossovsky <sasha@oktet.ru> - */ - -#if defined(__SH4__) -#define SH4_SR_MD 0x40000000 /* Priveleged mode */ -#define SH4_SR_RB 0x20000000 /* General register bank specifier */ -#define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */ -#define SH4_SR_FD 0x00008000 /* FPU disable bit */ -#define SH4_SR_M 0x00000200 /* For signed division: - divisor (module) is negative */ -#define SH4_SR_Q 0x00000100 /* For signed division: - dividend (and quotient) is negative */ -#define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */ -#define SH4_SR_IMASK_S 4 -#define SH4_SR_S 0x00000002 /* Saturation for MAC instruction: - if set, data in MACH/L register - is restricted to 48/32 bits - for MAC.W/L instructions */ -#define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */ -#define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */ - -/* FPSCR -- FPU Starus/Control Register */ -#define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */ -#define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */ -#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point - operations flag */ - /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */ -#define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */ -#define SH4_FPSCR_CAUSE 0x0003f000 /* FPU exeption cause field */ -#define SH4_FPSCR_CAUSE_S 12 -#define SH4_FPSCR_ENABLE 0x00000f80 /* FPU exeption enable field */ -#define SH4_FPSCR_ENABLE_s 7 -#define SH4_FPSCR_FLAG 0x0000007d /* FPU exeption flag field */ -#define SH4_FPSCR_FLAG_S 2 -#define SH4_FPSCR_RM 0x00000001 /* Rounding mode: - 1/0 -- round to zero/nearest */ -#define SH4_FPSCR_RESERV 0xffd00000 /* Reserved bits, read/write as 0 */ - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/sh/rtems/score/sh_io.h b/c/src/exec/score/cpu/sh/rtems/score/sh_io.h deleted file mode 100644 index 188e504385..0000000000 --- a/c/src/exec/score/cpu/sh/rtems/score/sh_io.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * These are some macros to access memory mapped devices - * on the SH7000-architecture. - * - * Inspired from the linux kernel's include/asm/io.h - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1996-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef _asm_io_h -#define _asm_io_h - -#define readb(addr) (*(volatile unsigned char *) (addr)) -#define readw(addr) (*(volatile unsigned short *) (addr)) -#define readl(addr) (*(volatile unsigned int *) (addr)) -#define read8(addr) (*(volatile unsigned8 *) (addr)) -#define read16(addr) (*(volatile unsigned16 *) (addr)) -#define read32(addr) (*(volatile unsigned32 *) (addr)) - -#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) -#define write8(b,addr) ((*(volatile unsigned8 *) (addr)) = (b)) -#define write16(b,addr) ((*(volatile unsigned16 *) (addr)) = (b)) -#define write32(b,addr) ((*(volatile unsigned32 *) (addr)) = (b)) - -#define inb(addr) readb(addr) -#define outb(b,addr) writeb(b,addr) - -#endif diff --git a/c/src/exec/score/cpu/sh/rtems/score/types.h b/c/src/exec/score/cpu/sh/rtems/score/types.h deleted file mode 100644 index d0e7180788..0000000000 --- a/c/src/exec/score/cpu/sh/rtems/score/types.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_SH_TYPES_h -#define __CPU_SH_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned16 boolean; /* Boolean value, external */ - /* data bus has 16 bits */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void sh_isr; -typedef void ( *sh_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif - diff --git a/c/src/exec/score/cpu/sparc/.cvsignore b/c/src/exec/score/cpu/sparc/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/sparc/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/sparc/ChangeLog b/c/src/exec/score/cpu/sparc/ChangeLog deleted file mode 100644 index d672b28816..0000000000 --- a/c/src/exec/score/cpu/sparc/ChangeLog +++ /dev/null @@ -1,143 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.S: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-04-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * cpu.c: Remove call to sparc_init_tbr/NO_TABLE_MOVE. - * rtems/score/cpu.h: Remove NO_TABLE_MOVE conditional code. - - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/sparctypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * cpu.c: Replace NO_TABLE_MOVE-support by external function - (code moved to libcpu/sparc/tbr/tbr.c). - * cpu.h: Replace NO_TABLE_MOVE-support by external function - (code moved to libcpu/sparc/tbr/tbr.h). - * sparc.h: Add sparc_init_tbr (implemented in libcpu/sparc/tbr/tbr.c). - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-31 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Reflect 2002-01-23 changes. - -2001-01-30 Joel Sherrill <joel@OARcorp.com> - - * Makefile.am: Corrected so .h files from rtems/score/ are installed. - -2002-01-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-27 Jiri Gaisler <jiri@gaisler.com> - - * cpu_asm.S: Small patch to fix a bug in the rtems sparc port. The - bug has been there all the time, but only hits the leon bsp since the - leon cpu has a 5-stage pipeline (erc32 has 4 stages). - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - * cpu_asm.S: Modify to properly dereference _ISR_Vector_table - now that it is dynamically allocated. - -2000-12-06 Joel Sherrill <joel@OARcorp.com> - - * cpu.c: Added include of <rtems/rtems/cache.h> to eliminate warning. - -2000-11-21 Jiri Gaisler <jgais@ws.estec.esa.nl> - - * cpu_asm.S: Fix for CPUs with FPU revision B or C. - -2000-11-14 Jiri Gaisler <jgais@ws.estec.esa.nl> - - * cpu.c, rtems/cpu/sparc.h: Make floating point optional based - on gcc arguments. Do not initialize FP context if there is - no FPU. Flush instruction cache after installing RTEMS trap handler. - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/sparc/Makefile.am b/c/src/exec/score/cpu/sparc/Makefile.am deleted file mode 100644 index 68153cba62..0000000000 --- a/c/src/exec/score/cpu/sparc/Makefile.am +++ /dev/null @@ -1,54 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS= asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/sparc.h \ - rtems/score/cpu.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/sparc/README b/c/src/exec/score/cpu/sparc/README deleted file mode 100644 index c4c2200075..0000000000 --- a/c/src/exec/score/cpu/sparc/README +++ /dev/null @@ -1,110 +0,0 @@ -# -# $Id$ -# - -This file discusses SPARC specific issues which are important to -this port. The primary topics in this file are: - - + Global Register Usage - + Stack Frame - + EF bit in the PSR - - -Global Register Usage -===================== - -This information on register usage is based heavily on a comment in the -file gcc-2.7.0/config/sparc/sparc.h in the the gcc 2.7.0 source. - - + g0 is hardwired to 0 - + On non-v9 systems: - - g1 is free to use as temporary. - - g2-g4 are reserved for applications. Gcc normally uses them as - temporaries, but this can be disabled via the -mno-app-regs option. - - g5 through g7 are reserved for the operating system. - + On v9 systems: - - g1 and g5 are free to use as temporaries. - - g2-g4 are reserved for applications (the compiler will not normally use - them, but they can be used as temporaries with -mapp-regs). - - g6-g7 are reserved for the operating system. - - NOTE: As of gcc 2.7.0 register g1 was used in the following scenarios: - - + as a temporary by the 64 bit sethi pattern - + when restoring call-preserved registers in large stack frames - -RTEMS places no constraints on the usage of the global registers. Although -gcc assumes that either g5-g7 (non-V9) or g6-g7 (V9) are reserved for the -operating system, RTEMS does not assume any special use for them. - - - -Stack Frame -=========== - -The stack grows downward (i.e. to lower addresses) on the SPARC architecture. - -The following is the organization of the stack frame: - - - - | ............... | - fp | | - +-------------------------------+ - | | - | Local registers, temporaries, | - | and saved floats | x bytes - | | - sp + x +-------------------------------+ - | | - | outgoing parameters past | - | the sixth one | x bytes - | | - sp + 92 +-------------------------------+ * - | | * - | area for callee to save | * - | register arguments | * 24 bytes - | | * - sp + 68 +-------------------------------+ * - | | * - | structure return pointer | * 4 bytes - | | * - sp + 64 +-------------------------------+ * - | | * - | local register set | * 32 bytes - | | * - sp + 32 +-------------------------------+ * - | | * - | input register set | * 32 bytes - | | * - sp +-------------------------------+ * - - -* = minimal stack frame - -x = optional components - -EF bit in the PSR -================= - -The EF (enable floating point unit) in the PSR is utilized in this port to -prevent non-floating point tasks from performing floating point -operations. This bit is maintained as part of the integer context. -However, the floating point context is switched BEFORE the integer -context. Thus the EF bit in place at the time of the FP switch may -indicate that FP operations are disabled. This occurs on certain task -switches, when the EF bit will be 0 for the outgoing task and thus a fault -will be generated on the first FP operation of the FP context save. - -The remedy for this is to enable FP access as the first step in both the -save and restore of the FP context area. This bit will be subsequently -reloaded by the integer context switch. - -Two of the scenarios which demonstrate this problem are outlined below: - -1. When the first FP task is switched to. The system tasks are not FP and -thus would be unable to restore the FP context of the incoming task. - -2. On a deferred FP context switch. In this case, the system might switch -from FP Task A to non-FP Task B and then to FP Task C. In this scenario, -the floating point state must technically be saved by a non-FP task. diff --git a/c/src/exec/score/cpu/sparc/asm.h b/c/src/exec/score/cpu/sparc/asm.h deleted file mode 100644 index c89f19e050..0000000000 --- a/c/src/exec/score/cpu/sparc/asm.h +++ /dev/null @@ -1,123 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. - * - * $Id$ - */ - -#ifndef __SPARC_ASM_h -#define __SPARC_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif - -#include <rtems/score/cpuopts.h> -#include <rtems/score/cpu.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */ -/* XXX The following ifdef magic fixes the problem but results in a warning */ -/* XXX when compiling assembly code. */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -/* - * Entry for traps which jump to a programmer-specified trap handler. - */ - -#define TRAP(_vector, _handler) \ - mov %psr, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - mov _vector, %l3 - -/* - * Used for the reset trap to avoid a supervisor instruction - */ - -#define RTRAP(_vector, _handler) \ - mov %g0, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - mov _vector, %l3 - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/sparc/configure.ac b/c/src/exec/score/cpu/sparc/configure.ac deleted file mode 100644 index bfd62c0c70..0000000000 --- a/c/src/exec/score/cpu/sparc/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-sparc],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/sparc/cpu.c b/c/src/exec/score/cpu/sparc/cpu.c deleted file mode 100644 index 7fb8d58bc1..0000000000 --- a/c/src/exec/score/cpu/sparc/cpu.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * SPARC Dependent Source - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/rtems/cache.h> - -/* - * This initializes the set of opcodes placed in each trap - * table entry. The routine which installs a handler is responsible - * for filling in the fields for the _handler address and the _vector - * trap type. - * - * The constants following this structure are masks for the fields which - * must be filled in when the handler is installed. - */ - -const CPU_Trap_table_entry _CPU_Trap_slot_template = { - 0xa1480000, /* mov %psr, %l0 */ - 0x29000000, /* sethi %hi(_handler), %l4 */ - 0x81c52000, /* jmp %l4 + %lo(_handler) */ - 0xa6102000 /* mov _vector, %l3 */ -}; - -/*PAGE - * - * _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * Input Parameters: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - * - * Output Parameters: NONE - * - * NOTE: There is no need to save the pointer to the thread dispatch routine. - * The SPARC's assembly code can reference it directly with no problems. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - void *pointer; - -#if (SPARC_HAS_FPU == 1) - - /* - * This seems to be the most appropriate way to obtain an initial - * FP context on the SPARC. The NULL fp context is copied it to - * the task's FP context during Context_Initialize. - */ - - pointer = &_CPU_Null_fp_context; - _CPU_Context_save_fp( &pointer ); -#endif - - /* - * Grab our own copy of the user's CPU table. - */ - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * Input Parameters: NONE - * - * Output Parameters: - * returns the current interrupt level (PIL field of the PSR) - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 level; - - sparc_get_interrupt_level( level ); - - return level; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * This routine installs the specified handler as a "raw" non-executive - * supported trap handler (a.k.a. interrupt service routine). - * - * Input Parameters: - * vector - trap table entry number plus synchronous - * vs. asynchronous information - * new_handler - address of the handler to be installed - * old_handler - pointer to an address of the handler previously installed - * - * Output Parameters: NONE - * *new_handler - address of the handler previously installed - * - * NOTE: - * - * On the SPARC, there are really only 256 vectors. However, the executive - * has no easy, fast, reliable way to determine which traps are synchronous - * and which are asynchronous. By default, synchronous traps return to the - * instruction which caused the interrupt. So if you install a software - * trap handler as an executive interrupt handler (which is desirable since - * RTEMS takes care of window and register issues), then the executive needs - * to know that the return address is to the trap rather than the instruction - * following the trap. - * - * So vectors 0 through 255 are treated as regular asynchronous traps which - * provide the "correct" return address. Vectors 256 through 512 are assumed - * by the executive to be synchronous and to require that the return address - * be fudged. - * - * If you use this mechanism to install a trap handler which must reexecute - * the instruction which caused the trap, then it should be installed as - * an asynchronous trap. This will avoid the executive changing the return - * address. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - unsigned32 real_vector; - CPU_Trap_table_entry *tbr; - CPU_Trap_table_entry *slot; - unsigned32 u32_tbr; - unsigned32 u32_handler; - - /* - * Get the "real" trap number for this vector ignoring the synchronous - * versus asynchronous indicator included with our vector numbers. - */ - - real_vector = SPARC_REAL_TRAP_NUMBER( vector ); - - /* - * Get the current base address of the trap table and calculate a pointer - * to the slot we are interested in. - */ - - sparc_get_tbr( u32_tbr ); - - u32_tbr &= 0xfffff000; - - tbr = (CPU_Trap_table_entry *) u32_tbr; - - slot = &tbr[ real_vector ]; - - /* - * Get the address of the old_handler from the trap table. - * - * NOTE: The old_handler returned will be bogus if it does not follow - * the RTEMS model. - */ - -#define HIGH_BITS_MASK 0xFFFFFC00 -#define HIGH_BITS_SHIFT 10 -#define LOW_BITS_MASK 0x000003FF - - if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) { - u32_handler = - ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) | - (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK); - *old_handler = (proc_ptr) u32_handler; - } else - *old_handler = 0; - - /* - * Copy the template to the slot and then fix it. - */ - - *slot = _CPU_Trap_slot_template; - - u32_handler = (unsigned32) new_handler; - - slot->mov_vector_l3 |= vector; - slot->sethi_of_handler_to_l4 |= - (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT; - slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK); - - /* need to flush icache after this !!! */ - - rtems_cache_invalidate_entire_instruction(); - -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * new_handler - replacement ISR for this vector number - * old_handler - pointer to former ISR for this vector number - * - * Output parameters: - * *old_handler - former ISR for this vector number - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - unsigned32 real_vector; - proc_ptr ignored; - - /* - * Get the "real" trap number for this vector ignoring the synchronous - * versus asynchronous indicator included with our vector numbers. - */ - - real_vector = SPARC_REAL_TRAP_NUMBER( vector ); - - /* - * Return the previous ISR handler. - */ - - *old_handler = _ISR_Vector_table[ real_vector ]; - - /* - * Install the wrapper so this ISR can be invoked properly. - */ - - _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ real_vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Context_Initialize - * - * This kernel routine initializes the basic non-FP context area associated - * with each thread. - * - * Input parameters: - * the_context - pointer to the context area - * stack_base - address of memory for the SPARC - * size - size in bytes of the stack area - * new_level - interrupt level for this context area - * entry_point - the starting execution point for this this context - * is_fp - TRUE if this context is associated with an FP thread - * - * Output parameters: NONE - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - unsigned32 *stack_base, - unsigned32 size, - unsigned32 new_level, - void *entry_point, - boolean is_fp -) -{ - unsigned32 stack_high; /* highest "stack aligned" address */ - unsigned32 the_size; - unsigned32 tmp_psr; - - /* - * On CPUs with stacks which grow down (i.e. SPARC), we build the stack - * based on the stack_high address. - */ - - stack_high = ((unsigned32)(stack_base) + size); - stack_high &= ~(CPU_STACK_ALIGNMENT - 1); - - the_size = size & ~(CPU_STACK_ALIGNMENT - 1); - - /* - * See the README in this directory for a diagram of the stack. - */ - - the_context->o7 = ((unsigned32) entry_point) - 8; - the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE; - the_context->i6_fp = stack_high; - - /* - * Build the PSR for the task. Most everything can be 0 and the - * CWP is corrected during the context switch. - * - * The EF bit determines if the floating point unit is available. - * The FPU is ONLY enabled if the context is associated with an FP task - * and this SPARC model has an FPU. - */ - - sparc_get_psr( tmp_psr ); - tmp_psr &= ~SPARC_PSR_PIL_MASK; - tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; - tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ - -#if (SPARC_HAS_FPU == 1) - /* - * If this bit is not set, then a task gets a fault when it accesses - * a floating point register. This is a nice way to detect floating - * point tasks which are not currently declared as such. - */ - - if ( is_fp ) - tmp_psr |= SPARC_PSR_EF_MASK; -#endif - the_context->psr = tmp_psr; -} diff --git a/c/src/exec/score/cpu/sparc/cpu_asm.S b/c/src/exec/score/cpu/sparc/cpu_asm.S deleted file mode 100644 index b5ef4ebf69..0000000000 --- a/c/src/exec/score/cpu/sparc/cpu_asm.S +++ /dev/null @@ -1,795 +0,0 @@ -/* cpu_asm.s - * - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Ported to ERC32 implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - * - * $Id$ - */ - -#include <asm.h> - -#if (SPARC_HAS_FPU == 1) - -/* - * void _CPU_Context_save_fp( - * void **fp_context_ptr - * ) - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * NOTE: See the README in this directory for information on the - * management of the "EF" bit in the PSR. - */ - - .align 4 - PUBLIC(_CPU_Context_save_fp) -SYM(_CPU_Context_save_fp): - save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp - - /* - * The following enables the floating point unit. - */ - - mov %psr, %l0 - sethi %hi(SPARC_PSR_EF_MASK), %l1 - or %l1, %lo(SPARC_PSR_EF_MASK), %l1 - or %l0, %l1, %l0 - mov %l0, %psr ! **** ENABLE FLOAT ACCESS **** - nop; nop; nop; ! Need three nops before EF is - ld [%i0], %l0 ! active due to pipeline delay!!! - std %f0, [%l0 + FO_F1_OFFSET] - std %f2, [%l0 + F2_F3_OFFSET] - std %f4, [%l0 + F4_F5_OFFSET] - std %f6, [%l0 + F6_F7_OFFSET] - std %f8, [%l0 + F8_F9_OFFSET] - std %f10, [%l0 + F1O_F11_OFFSET] - std %f12, [%l0 + F12_F13_OFFSET] - std %f14, [%l0 + F14_F15_OFFSET] - std %f16, [%l0 + F16_F17_OFFSET] - std %f18, [%l0 + F18_F19_OFFSET] - std %f20, [%l0 + F2O_F21_OFFSET] - std %f22, [%l0 + F22_F23_OFFSET] - std %f24, [%l0 + F24_F25_OFFSET] - std %f26, [%l0 + F26_F27_OFFSET] - std %f28, [%l0 + F28_F29_OFFSET] - std %f30, [%l0 + F3O_F31_OFFSET] - st %fsr, [%l0 + FSR_OFFSET] - ret - restore - -/* - * void _CPU_Context_restore_fp( - * void **fp_context_ptr - * ) - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * NOTE: See the README in this directory for information on the - * management of the "EF" bit in the PSR. - */ - - .align 4 - PUBLIC(_CPU_Context_restore_fp) -SYM(_CPU_Context_restore_fp): - save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE , %sp - - /* - * The following enables the floating point unit. - */ - - mov %psr, %l0 - sethi %hi(SPARC_PSR_EF_MASK), %l1 - or %l1, %lo(SPARC_PSR_EF_MASK), %l1 - or %l0, %l1, %l0 - mov %l0, %psr ! **** ENABLE FLOAT ACCESS **** - nop; nop; nop; ! Need three nops before EF is - ld [%i0], %l0 ! active due to pipeline delay!!! - ldd [%l0 + FO_F1_OFFSET], %f0 - ldd [%l0 + F2_F3_OFFSET], %f2 - ldd [%l0 + F4_F5_OFFSET], %f4 - ldd [%l0 + F6_F7_OFFSET], %f6 - ldd [%l0 + F8_F9_OFFSET], %f8 - ldd [%l0 + F1O_F11_OFFSET], %f10 - ldd [%l0 + F12_F13_OFFSET], %f12 - ldd [%l0 + F14_F15_OFFSET], %f14 - ldd [%l0 + F16_F17_OFFSET], %f16 - ldd [%l0 + F18_F19_OFFSET], %f18 - ldd [%l0 + F2O_F21_OFFSET], %f20 - ldd [%l0 + F22_F23_OFFSET], %f22 - ldd [%l0 + F24_F25_OFFSET], %f24 - ldd [%l0 + F26_F27_OFFSET], %f26 - ldd [%l0 + F28_F29_OFFSET], %f28 - ldd [%l0 + F3O_F31_OFFSET], %f30 - ld [%l0 + FSR_OFFSET], %fsr - ret - restore - -#endif /* SPARC_HAS_FPU */ - -/* - * void _CPU_Context_switch( - * Context_Control *run, - * Context_Control *heir - * ) - * - * This routine performs a normal non-FP context switch. - */ - - .align 4 - PUBLIC(_CPU_Context_switch) -SYM(_CPU_Context_switch): - ! skip g0 - st %g1, [%o0 + G1_OFFSET] ! save the global registers - std %g2, [%o0 + G2_OFFSET] - std %g4, [%o0 + G4_OFFSET] - std %g6, [%o0 + G6_OFFSET] - - std %l0, [%o0 + L0_OFFSET] ! save the local registers - std %l2, [%o0 + L2_OFFSET] - std %l4, [%o0 + L4_OFFSET] - std %l6, [%o0 + L6_OFFSET] - - std %i0, [%o0 + I0_OFFSET] ! save the input registers - std %i2, [%o0 + I2_OFFSET] - std %i4, [%o0 + I4_OFFSET] - std %i6, [%o0 + I6_FP_OFFSET] - - std %o0, [%o0 + O0_OFFSET] ! save the output registers - std %o2, [%o0 + O2_OFFSET] - std %o4, [%o0 + O4_OFFSET] - std %o6, [%o0 + O6_SP_OFFSET] - - rd %psr, %o2 - st %o2, [%o0 + PSR_OFFSET] ! save status register - - /* - * This is entered from _CPU_Context_restore with: - * o1 = context to restore - * o2 = psr - */ - - PUBLIC(_CPU_Context_restore_heir) -SYM(_CPU_Context_restore_heir): - /* - * Flush all windows with valid contents except the current one. - * In examining the set register windows, one may logically divide - * the windows into sets (some of which may be empty) based on their - * current status: - * - * + current (i.e. in use), - * + used (i.e. a restore would not trap) - * + invalid (i.e. 1 in corresponding bit in WIM) - * + unused - * - * Either the used or unused set of windows may be empty. - * - * NOTE: We assume only one bit is set in the WIM at a time. - * - * Given a CWP of 5 and a WIM of 0x1, the registers are divided - * into sets as follows: - * - * + 0 - invalid - * + 1-4 - unused - * + 5 - current - * + 6-7 - used - * - * In this case, we only would save the used windows -- 6 and 7. - * - * Traps are disabled for the same logical period as in a - * flush all windows trap handler. - * - * Register Usage while saving the windows: - * g1 = current PSR - * g2 = current wim - * g3 = CWP - * g4 = wim scratch - * g5 = scratch - */ - - ld [%o1 + PSR_OFFSET], %g1 ! g1 = saved psr - - and %o2, SPARC_PSR_CWP_MASK, %g3 ! g3 = CWP - ! g1 = psr w/o cwp - andn %g1, SPARC_PSR_ET_MASK | SPARC_PSR_CWP_MASK, %g1 - or %g1, %g3, %g1 ! g1 = heirs psr - mov %g1, %psr ! restore status register and - ! **** DISABLE TRAPS **** - mov %wim, %g2 ! g2 = wim - mov 1, %g4 - sll %g4, %g3, %g4 ! g4 = WIM mask for CW invalid - -save_frame_loop: - sll %g4, 1, %g5 ! rotate the "wim" left 1 - srl %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4 - or %g4, %g5, %g4 ! g4 = wim if we do one restore - - /* - * If a restore would not underflow, then continue. - */ - - andcc %g4, %g2, %g0 ! Any windows to flush? - bnz done_flushing ! No, then continue - nop - - restore ! back one window - - /* - * Now save the window just as if we overflowed to it. - */ - - std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET] - std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET] - std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET] - std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET] - - std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET] - std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET] - std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET] - std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET] - - ba save_frame_loop - nop - -done_flushing: - - add %g3, 1, %g3 ! calculate desired WIM - and %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3 - mov 1, %g4 - sll %g4, %g3, %g4 ! g4 = new WIM - mov %g4, %wim - - or %g1, SPARC_PSR_ET_MASK, %g1 - mov %g1, %psr ! **** ENABLE TRAPS **** - ! and restore CWP - nop - nop - nop - - ! skip g0 - ld [%o1 + G1_OFFSET], %g1 ! restore the global registers - ldd [%o1 + G2_OFFSET], %g2 - ldd [%o1 + G4_OFFSET], %g4 - ldd [%o1 + G6_OFFSET], %g6 - - ldd [%o1 + L0_OFFSET], %l0 ! restore the local registers - ldd [%o1 + L2_OFFSET], %l2 - ldd [%o1 + L4_OFFSET], %l4 - ldd [%o1 + L6_OFFSET], %l6 - - ldd [%o1 + I0_OFFSET], %i0 ! restore the output registers - ldd [%o1 + I2_OFFSET], %i2 - ldd [%o1 + I4_OFFSET], %i4 - ldd [%o1 + I6_FP_OFFSET], %i6 - - ldd [%o1 + O2_OFFSET], %o2 ! restore the output registers - ldd [%o1 + O4_OFFSET], %o4 - ldd [%o1 + O6_SP_OFFSET], %o6 - ! do o0/o1 last to avoid destroying heir context pointer - ldd [%o1 + O0_OFFSET], %o0 ! overwrite heir pointer - - jmp %o7 + 8 ! return - nop ! delay slot - -/* - * void _CPU_Context_restore( - * Context_Control *new_context - * ) - * - * This routine is generally used only to perform restart self. - * - * NOTE: It is unnecessary to reload some registers. - */ - - .align 4 - PUBLIC(_CPU_Context_restore) -SYM(_CPU_Context_restore): - save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp - rd %psr, %o2 - ba SYM(_CPU_Context_restore_heir) - mov %i0, %o1 ! in the delay slot - -/* - * void _ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * We enter this handler from the 4 instructions in the trap table with - * the following registers assumed to be set as shown: - * - * l0 = PSR - * l1 = PC - * l2 = nPC - * l3 = trap type - * - * NOTE: By an executive defined convention, trap type is between 0 and 255 if - * it is an asynchonous trap and 256 and 511 if it is synchronous. - */ - - .align 4 - PUBLIC(_ISR_Handler) -SYM(_ISR_Handler): - /* - * Fix the return address for synchronous traps. - */ - - andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0 - ! Is this a synchronous trap? - be,a win_ovflow ! No, then skip the adjustment - nop ! DELAY - mov %l1, %l6 ! save trapped pc for debug info - mov %l2, %l1 ! do not return to the instruction - add %l2, 4, %l2 ! indicated - -win_ovflow: - /* - * Save the globals this block uses. - * - * These registers are not restored from the locals. Their contents - * are saved directly from the locals into the ISF below. - */ - - mov %g4, %l4 ! save the globals this block uses - mov %g5, %l5 - - /* - * When at a "window overflow" trap, (wim == (1 << cwp)). - * If we get here like that, then process a window overflow. - */ - - rd %wim, %g4 - srl %g4, %l0, %g5 ! g5 = win >> cwp ; shift count and CWP - ! are LS 5 bits ; how convenient :) - cmp %g5, 1 ! Is this an invalid window? - bne dont_do_the_window ! No, then skip all this stuff - ! we are using the delay slot - - /* - * The following is same as a 1 position right rotate of WIM - */ - - srl %g4, 1, %g5 ! g5 = WIM >> 1 - sll %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4 - ! g4 = WIM << (Number Windows - 1) - or %g4, %g5, %g4 ! g4 = (WIM >> 1) | - ! (WIM << (Number Windows - 1)) - - /* - * At this point: - * - * g4 = the new WIM - * g5 is free - */ - - /* - * Since we are tinkering with the register windows, we need to - * make sure that all the required information is in global registers. - */ - - save ! Save into the window - wr %g4, 0, %wim ! WIM = new WIM - nop ! delay slots - nop - nop - - /* - * Now save the window just as if we overflowed to it. - */ - - std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET] - std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET] - std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET] - std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET] - - std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET] - std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET] - std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET] - std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET] - - restore - nop - -dont_do_the_window: - /* - * Global registers %g4 and %g5 are saved directly from %l4 and - * %l5 directly into the ISF below. - */ - -save_isf: - - /* - * Save the state of the interrupted task -- especially the global - * registers -- in the Interrupt Stack Frame. Note that the ISF - * includes a regular minimum stack frame which will be used if - * needed by register window overflow and underflow handlers. - * - * REGISTERS SAME AS AT _ISR_Handler - */ - - sub %fp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp - ! make space for ISF - - std %l0, [%sp + ISF_PSR_OFFSET] ! save psr, PC - st %l2, [%sp + ISF_NPC_OFFSET] ! save nPC - st %g1, [%sp + ISF_G1_OFFSET] ! save g1 - std %g2, [%sp + ISF_G2_OFFSET] ! save g2, g3 - std %l4, [%sp + ISF_G4_OFFSET] ! save g4, g5 -- see above - std %g6, [%sp + ISF_G6_OFFSET] ! save g6, g7 - - std %i0, [%sp + ISF_I0_OFFSET] ! save i0, i1 - std %i2, [%sp + ISF_I2_OFFSET] ! save i2, i3 - std %i4, [%sp + ISF_I4_OFFSET] ! save i4, i5 - std %i6, [%sp + ISF_I6_FP_OFFSET] ! save i6/fp, i7 - - rd %y, %g1 - st %g1, [%sp + ISF_Y_OFFSET] ! save y - st %l6, [%sp + ISF_TPC_OFFSET] ! save real trapped pc - - mov %sp, %o1 ! 2nd arg to ISR Handler - - /* - * Increment ISR nest level and Thread dispatch disable level. - * - * Register usage for this section: - * - * l4 = _Thread_Dispatch_disable_level pointer - * l5 = _ISR_Nest_level pointer - * l6 = _Thread_Dispatch_disable_level value - * l7 = _ISR_Nest_level value - * - * NOTE: It is assumed that l4 - l7 will be preserved until the ISR - * nest and thread dispatch disable levels are unnested. - */ - - sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4 - ld [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6 - sethi %hi(SYM(_ISR_Nest_level)), %l5 - ld [%l5 + %lo(SYM(_ISR_Nest_level))], %l7 - - add %l6, 1, %l6 - st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))] - - add %l7, 1, %l7 - st %l7, [%l5 + %lo(SYM(_ISR_Nest_level))] - - /* - * If ISR nest level was zero (now 1), then switch stack. - */ - - mov %sp, %fp - subcc %l7, 1, %l7 ! outermost interrupt handler? - bnz dont_switch_stacks ! No, then do not switch stacks - - sethi %hi(SYM(_CPU_Interrupt_stack_high)), %g4 - ld [%g4 + %lo(SYM(_CPU_Interrupt_stack_high))], %sp - -dont_switch_stacks: - /* - * Make sure we have a place on the stack for the window overflow - * trap handler to write into. At this point it is safe to - * enable traps again. - */ - - sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp - - /* - * Check if we have an external interrupt (trap 0x11 - 0x1f). If so, - * set the PIL in the %psr to mask off interrupts with lower priority. - * The original %psr in %l0 is not modified since it will be restored - * when the interrupt handler returns. - */ - - mov %l0, %g5 - and %l3, 0x0ff, %g4 - -/* This is a fix for ERC32 with FPU rev.B or rev.C */ - -#if defined(FPU_REVB) - - - subcc %g4, 0x08, %g0 - be fpu_revb - subcc %g4, 0x11, %g0 - bl dont_fix_pil - subcc %g4, 0x1f, %g0 - bg dont_fix_pil - sll %g4, 8, %g4 - and %g4, SPARC_PSR_PIL_MASK, %g4 - andn %l0, SPARC_PSR_PIL_MASK, %g5 - or %g4, %g5, %g5 - srl %l0, 12, %g4 - andcc %g4, 1, %g0 - be dont_fix_pil - nop - ba,a enable_irq - - -fpu_revb: - srl %l0, 12, %g4 ! check if EF is set in %psr - andcc %g4, 1, %g0 - be dont_fix_pil ! if FPU disabled than continue as normal - and %l3, 0xff, %g4 - subcc %g4, 0x08, %g0 - bne enable_irq ! if not a FPU exception then do two fmovs - set __sparc_fq, %g4 - st %fsr, [%g4] ! if FQ is not empty and FQ[1] = fmovs - ld [%g4], %g4 ! than this is bug 3.14 - srl %g4, 13, %g4 - andcc %g4, 1, %g0 - be dont_fix_pil - set __sparc_fq, %g4 - std %fq, [%g4] - ld [%g4+4], %g4 - set 0x81a00020, %g5 - subcc %g4, %g5, %g0 - bne,a dont_fix_pil2 - wr %l0, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** - ba,a simple_return - -enable_irq: - or %g5, SPARC_PSR_PIL_MASK, %g4 - wr %g4, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** - nop; nop; nop - fmovs %f0, %f0 - ba dont_fix_pil - fmovs %f0, %f0 - - .data - .global __sparc_fq - .align 8 -__sparc_fq: - .word 0,0 - - .text -/* end of ERC32 FPU rev.B/C fix */ - -#else - - subcc %g4, 0x11, %g0 - bl dont_fix_pil - subcc %g4, 0x1f, %g0 - bg dont_fix_pil - sll %g4, 8, %g4 - and %g4, SPARC_PSR_PIL_MASK, %g4 - andn %l0, SPARC_PSR_PIL_MASK, %g5 - or %g4, %g5, %g5 -#endif - -dont_fix_pil: - wr %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** -dont_fix_pil2: - - /* - * Vector to user's handler. - * - * NOTE: TBR may no longer have vector number in it since - * we just enabled traps. It is definitely in l3. - */ - - sethi %hi(SYM(_ISR_Vector_table)), %g4 - ld [%g4+%lo(SYM(_ISR_Vector_table))], %g4 - and %l3, 0xFF, %g5 ! remove synchronous trap indicator - sll %g5, 2, %g5 ! g5 = offset into table - ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ] - - - ! o1 = 2nd arg = address of the ISF - ! WAS LOADED WHEN ISF WAS SAVED!!! - mov %l3, %o0 ! o0 = 1st arg = vector number - call %g4, 0 - nop ! delay slot - - /* - * Redisable traps so we can finish up the interrupt processing. - * This is a VERY conservative place to do this. - * - * NOTE: %l0 has the PSR which was in place when we took the trap. - */ - - mov %l0, %psr ! **** DISABLE TRAPS **** - - /* - * Decrement ISR nest level and Thread dispatch disable level. - * - * Register usage for this section: - * - * l4 = _Thread_Dispatch_disable_level pointer - * l5 = _ISR_Nest_level pointer - * l6 = _Thread_Dispatch_disable_level value - * l7 = _ISR_Nest_level value - */ - - sub %l6, 1, %l6 - st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))] - - st %l7, [%l5 + %lo(SYM(_ISR_Nest_level))] - - /* - * If dispatching is disabled (includes nested interrupt case), - * then do a "simple" exit. - */ - - orcc %l6, %g0, %g0 ! Is dispatching disabled? - bnz simple_return ! Yes, then do a "simple" exit - nop ! delay slot - - /* - * If a context switch is necessary, then do fudge stack to - * return to the interrupt dispatcher. - */ - - sethi %hi(SYM(_Context_Switch_necessary)), %l4 - ld [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5 - - orcc %l5, %g0, %g0 ! Is thread switch necessary? - bnz SYM(_ISR_Dispatch) ! yes, then invoke the dispatcher - nop ! delay slot - - /* - * Finally, check to see if signals were sent to the currently - * executing task. If so, we need to invoke the interrupt dispatcher. - */ - - sethi %hi(SYM(_ISR_Signals_to_thread_executing)), %l6 - ld [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7 - - orcc %l7, %g0, %g0 ! Were signals sent to the currently - ! executing thread? - bz simple_return ! yes, then invoke the dispatcher - ! use the delay slot to clear the signals - ! to the currently executing task flag - st %g0, [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))] - - - /* - * Invoke interrupt dispatcher. - */ - - PUBLIC(_ISR_Dispatch) -SYM(_ISR_Dispatch): - - /* - * The following subtract should get us back on the interrupted - * tasks stack and add enough room to invoke the dispatcher. - * When we enable traps, we are mostly back in the context - * of the task and subsequent interrupts can operate normally. - */ - - sub %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp - - or %l0, SPARC_PSR_ET_MASK, %l7 ! l7 = PSR with ET=1 - mov %l7, %psr ! **** ENABLE TRAPS **** - nop - nop - nop - - call SYM(_Thread_Dispatch), 0 - nop - - /* - * The CWP in place at this point may be different from - * that which was in effect at the beginning of the ISR if we - * have been context switched between the beginning of this invocation - * of _ISR_Handler and this point. Thus the CWP and WIM should - * not be changed back to their values at ISR entry time. Any - * changes to the PSR must preserve the CWP. - */ - -simple_return: - ld [%fp + ISF_Y_OFFSET], %l5 ! restore y - wr %l5, 0, %y - - ldd [%fp + ISF_PSR_OFFSET], %l0 ! restore psr, PC - ld [%fp + ISF_NPC_OFFSET], %l2 ! restore nPC - rd %psr, %l3 - and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP - andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task - or %l3, %l0, %l0 ! install it later... - andn %l0, SPARC_PSR_ET_MASK, %l0 - - /* - * Restore tasks global and out registers - */ - - mov %fp, %g1 - - ! g1 is restored later - ldd [%fp + ISF_G2_OFFSET], %g2 ! restore g2, g3 - ldd [%fp + ISF_G4_OFFSET], %g4 ! restore g4, g5 - ldd [%fp + ISF_G6_OFFSET], %g6 ! restore g6, g7 - - ldd [%fp + ISF_I0_OFFSET], %i0 ! restore i0, i1 - ldd [%fp + ISF_I2_OFFSET], %i2 ! restore i2, i3 - ldd [%fp + ISF_I4_OFFSET], %i4 ! restore i4, i5 - ldd [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7 - - /* - * Registers: - * - * ALL global registers EXCEPT G1 and the input registers have - * already been restored and thuse off limits. - * - * The following is the contents of the local registers: - * - * l0 = original psr - * l1 = return address (i.e. PC) - * l2 = nPC - * l3 = CWP - */ - - /* - * if (CWP + 1) is an invalid window then we need to reload it. - * - * WARNING: Traps should now be disabled - */ - - mov %l0, %psr ! **** DISABLE TRAPS **** - nop - nop - nop - rd %wim, %l4 - add %l0, 1, %l6 ! l6 = cwp + 1 - and %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it - srl %l4, %l6, %l5 ! l5 = win >> cwp + 1 ; shift count - ! and CWP are conveniently LS 5 bits - cmp %l5, 1 ! Is tasks window invalid? - bne good_task_window - - /* - * The following code is the same as a 1 position left rotate of WIM. - */ - - sll %l4, 1, %l5 ! l5 = WIM << 1 - srl %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4 - ! l4 = WIM >> (Number Windows - 1) - or %l4, %l5, %l4 ! l4 = (WIM << 1) | - ! (WIM >> (Number Windows - 1)) - - /* - * Now restore the window just as if we underflowed to it. - */ - - wr %l4, 0, %wim ! WIM = new WIM - nop ! must delay after writing WIM - nop - nop - restore ! now into the tasks window - - ldd [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0 - ldd [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2 - ldd [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4 - ldd [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6 - ldd [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0 - ldd [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2 - ldd [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4 - ldd [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6 - ! reload of sp clobbers ISF - save ! Back to ISR dispatch window - -good_task_window: - - mov %l0, %psr ! **** DISABLE TRAPS **** - ! and restore condition codes. - ld [%g1 + ISF_G1_OFFSET], %g1 ! restore g1 - jmp %l1 ! transfer control and - rett %l2 ! go back to tasks window - -/* end of file */ diff --git a/c/src/exec/score/cpu/sparc/rtems/.cvsignore b/c/src/exec/score/cpu/sparc/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/sparc/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/sparc/rtems/score/.cvsignore b/c/src/exec/score/cpu/sparc/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/sparc/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/sparc/rtems/score/cpu.h b/c/src/exec/score/cpu/sparc/rtems/score/cpu.h deleted file mode 100644 index 3194c07f3b..0000000000 --- a/c/src/exec/score/cpu/sparc/rtems/score/cpu.h +++ /dev/null @@ -1,1000 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the port of - * the executive to the SPARC processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/sparc.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * This parameter could go either way on the SPARC. The interrupt flash - * code is relatively lengthy given the requirements for nops following - * writes to the psr. But if the clock speed were high enough, this would - * not represent a great deal of time. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does the executive manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * The SPARC does not have a dedicated HW interrupt stack and one has - * been implemented in SW. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * The SPARC does not have a dedicated HW interrupt stack. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Do we allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the FLOATING_POINT task attribute is supported. - * If FALSE, then the FLOATING_POINT task attribute is ignored. - */ - -#if ( SPARC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks FLOATING_POINT tasks implicitly? - * - * If TRUE, then the FLOATING_POINT task attribute is assumed. - * If FALSE, then the FLOATING_POINT task attribute is followed. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * The stack grows to lower addresses on the SPARC. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical data structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The SPARC does not appear to have particularly strict alignment - * requirements. This value was chosen to take advantages of caches. - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * The SPARC has 16 interrupt levels in the PIL field of the PSR. - */ - -#define CPU_MODES_INTERRUPT_MASK 0x0000000F - -/* - * This structure represents the organization of the minimum stack frame - * for the SPARC. More framing information is required in certain situaions - * such as when there are a large number of out parameters or when the callee - * must save floating point registers. - */ - -#ifndef ASM - -typedef struct { - unsigned32 l0; - unsigned32 l1; - unsigned32 l2; - unsigned32 l3; - unsigned32 l4; - unsigned32 l5; - unsigned32 l6; - unsigned32 l7; - unsigned32 i0; - unsigned32 i1; - unsigned32 i2; - unsigned32 i3; - unsigned32 i4; - unsigned32 i5; - unsigned32 i6_fp; - unsigned32 i7; - void *structure_return_address; - /* - * The following are for the callee to save the register arguments in - * should this be necessary. - */ - unsigned32 saved_arg0; - unsigned32 saved_arg1; - unsigned32 saved_arg2; - unsigned32 saved_arg3; - unsigned32 saved_arg4; - unsigned32 saved_arg5; - unsigned32 pad0; -} CPU_Minimum_stack_frame; - -#endif /* ASM */ - -#define CPU_STACK_FRAME_L0_OFFSET 0x00 -#define CPU_STACK_FRAME_L1_OFFSET 0x04 -#define CPU_STACK_FRAME_L2_OFFSET 0x08 -#define CPU_STACK_FRAME_L3_OFFSET 0x0c -#define CPU_STACK_FRAME_L4_OFFSET 0x10 -#define CPU_STACK_FRAME_L5_OFFSET 0x14 -#define CPU_STACK_FRAME_L6_OFFSET 0x18 -#define CPU_STACK_FRAME_L7_OFFSET 0x1c -#define CPU_STACK_FRAME_I0_OFFSET 0x20 -#define CPU_STACK_FRAME_I1_OFFSET 0x24 -#define CPU_STACK_FRAME_I2_OFFSET 0x28 -#define CPU_STACK_FRAME_I3_OFFSET 0x2c -#define CPU_STACK_FRAME_I4_OFFSET 0x30 -#define CPU_STACK_FRAME_I5_OFFSET 0x34 -#define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 -#define CPU_STACK_FRAME_I7_OFFSET 0x3c -#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 -#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 -#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 -#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c -#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 -#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 -#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 -#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c - -#define CPU_MINIMUM_STACK_FRAME_SIZE 0x60 - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On the SPARC, we are relatively conservative in that we save most - * of the CPU state in the context area. The ET (enable trap) bit and - * the CWP (current window pointer) fields of the PSR are considered - * system wide resources and are not maintained on a per-thread basis. - */ - -#ifndef ASM - -typedef struct { - /* - * Using a double g0_g1 will put everything in this structure on a - * double word boundary which allows us to use double word loads - * and stores safely in the context switch. - */ - double g0_g1; - unsigned32 g2; - unsigned32 g3; - unsigned32 g4; - unsigned32 g5; - unsigned32 g6; - unsigned32 g7; - - unsigned32 l0; - unsigned32 l1; - unsigned32 l2; - unsigned32 l3; - unsigned32 l4; - unsigned32 l5; - unsigned32 l6; - unsigned32 l7; - - unsigned32 i0; - unsigned32 i1; - unsigned32 i2; - unsigned32 i3; - unsigned32 i4; - unsigned32 i5; - unsigned32 i6_fp; - unsigned32 i7; - - unsigned32 o0; - unsigned32 o1; - unsigned32 o2; - unsigned32 o3; - unsigned32 o4; - unsigned32 o5; - unsigned32 o6_sp; - unsigned32 o7; - - unsigned32 psr; -} Context_Control; - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control for assembly routines. - */ - -#define G0_OFFSET 0x00 -#define G1_OFFSET 0x04 -#define G2_OFFSET 0x08 -#define G3_OFFSET 0x0C -#define G4_OFFSET 0x10 -#define G5_OFFSET 0x14 -#define G6_OFFSET 0x18 -#define G7_OFFSET 0x1C - -#define L0_OFFSET 0x20 -#define L1_OFFSET 0x24 -#define L2_OFFSET 0x28 -#define L3_OFFSET 0x2C -#define L4_OFFSET 0x30 -#define L5_OFFSET 0x34 -#define L6_OFFSET 0x38 -#define L7_OFFSET 0x3C - -#define I0_OFFSET 0x40 -#define I1_OFFSET 0x44 -#define I2_OFFSET 0x48 -#define I3_OFFSET 0x4C -#define I4_OFFSET 0x50 -#define I5_OFFSET 0x54 -#define I6_FP_OFFSET 0x58 -#define I7_OFFSET 0x5C - -#define O0_OFFSET 0x60 -#define O1_OFFSET 0x64 -#define O2_OFFSET 0x68 -#define O3_OFFSET 0x6C -#define O4_OFFSET 0x70 -#define O5_OFFSET 0x74 -#define O6_SP_OFFSET 0x78 -#define O7_OFFSET 0x7C - -#define PSR_OFFSET 0x80 - -#define CONTEXT_CONTROL_SIZE 0x84 - -/* - * The floating point context area. - */ - -#ifndef ASM - -typedef struct { - double f0_f1; - double f2_f3; - double f4_f5; - double f6_f7; - double f8_f9; - double f10_f11; - double f12_f13; - double f14_f15; - double f16_f17; - double f18_f19; - double f20_f21; - double f22_f23; - double f24_f25; - double f26_f27; - double f28_f29; - double f30_f31; - unsigned32 fsr; -} Context_Control_fp; - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control_fp for assembly routines. - */ - -#define FO_F1_OFFSET 0x00 -#define F2_F3_OFFSET 0x08 -#define F4_F5_OFFSET 0x10 -#define F6_F7_OFFSET 0x18 -#define F8_F9_OFFSET 0x20 -#define F1O_F11_OFFSET 0x28 -#define F12_F13_OFFSET 0x30 -#define F14_F15_OFFSET 0x38 -#define F16_F17_OFFSET 0x40 -#define F18_F19_OFFSET 0x48 -#define F2O_F21_OFFSET 0x50 -#define F22_F23_OFFSET 0x58 -#define F24_F25_OFFSET 0x60 -#define F26_F27_OFFSET 0x68 -#define F28_F29_OFFSET 0x70 -#define F3O_F31_OFFSET 0x78 -#define FSR_OFFSET 0x80 - -#define CONTEXT_CONTROL_FP_SIZE 0x84 - -#ifndef ASM - -/* - * Context saved on stack for an interrupt. - * - * NOTE: The PSR, PC, and NPC are only saved in this structure for the - * benefit of the user's handler. - */ - -typedef struct { - CPU_Minimum_stack_frame Stack_frame; - unsigned32 psr; - unsigned32 pc; - unsigned32 npc; - unsigned32 g1; - unsigned32 g2; - unsigned32 g3; - unsigned32 g4; - unsigned32 g5; - unsigned32 g6; - unsigned32 g7; - unsigned32 i0; - unsigned32 i1; - unsigned32 i2; - unsigned32 i3; - unsigned32 i4; - unsigned32 i5; - unsigned32 i6_fp; - unsigned32 i7; - unsigned32 y; - unsigned32 tpc; -} CPU_Interrupt_frame; - -#endif /* ASM */ - -/* - * Offsets of fields with CPU_Interrupt_frame for assembly routines. - */ - -#define ISF_STACK_FRAME_OFFSET 0x00 -#define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00 -#define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04 -#define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08 -#define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c -#define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10 -#define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14 -#define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18 -#define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c -#define ISF_G6_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x20 -#define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24 -#define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28 -#define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c -#define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30 -#define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34 -#define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38 -#define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c -#define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40 -#define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44 -#define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 -#define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c - -#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 -#ifndef ASM - -/* - * The following table contains the information required to configure - * the processor specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access SPARC specific additions to the CPU Table - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -/* - * This variable is contains the initialize context for the FP unit. - * It is filled in by _CPU_Initialize and copied into the task's FP - * context area during _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT; - -/* - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. Thus - * both must be present if either is. - * - * The SPARC supports a software based interrupt stack and these - * are required. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * The following type defines an entry in the SPARC's trap table. - * - * NOTE: The instructions chosen are RTEMS dependent although one is - * obligated to use two of the four instructions to perform a - * long jump. The other instructions load one register with the - * trap type (a.k.a. vector) and another with the psr. - */ - -typedef struct { - unsigned32 mov_psr_l0; /* mov %psr, %l0 */ - unsigned32 sethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */ - unsigned32 jmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */ - unsigned32 mov_vector_l3; /* mov _vector, %l3 */ -} CPU_Trap_table_entry; - -/* - * This is the set of opcodes for the instructions loaded into a trap - * table entry. The routine which installs a handler is responsible - * for filling in the fields for the _handler address and the _vector - * trap type. - * - * The constants following this structure are masks for the fields which - * must be filled in when the handler is installed. - */ - -extern const CPU_Trap_table_entry _CPU_Trap_slot_template; - -/* - * The size of the floating point context area. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by the executive. - * - * On the SPARC, there are really only 256 vectors. However, the executive - * has no easy, fast, reliable way to determine which traps are synchronous - * and which are asynchronous. By default, synchronous traps return to the - * instruction which caused the interrupt. So if you install a software - * trap handler as an executive interrupt handler (which is desirable since - * RTEMS takes care of window and register issues), then the executive needs - * to know that the return address is to the trap rather than the instruction - * following the trap. - * - * So vectors 0 through 255 are treated as regular asynchronous traps which - * provide the "correct" return address. Vectors 256 through 512 are assumed - * by the executive to be synchronous and to require that the return address - * be fudged. - * - * If you use this mechanism to install a trap handler which must reexecute - * the instruction which caused the trap, then it should be installed as - * an asynchronous trap. This will avoid the executive changing the return - * address. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 - -#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 -#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) -#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) - -#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all tests. This insures - * that a "reasonable" small application should not have any problems. - * - * This appears to be a fairly generous number for the SPARC since - * represents a call depth of about 20 routines based on the minimum - * stack frame. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * On the SPARC, this is required for double word loads and stores. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * The alignment restrictions for the SPARC are not that strict but this - * should unsure that the stack is always sufficiently alignment that the - * window overflow, underflow, and flush routines can use double word loads - * and stores. - */ - -#define CPU_STACK_ALIGNMENT 16 - -#ifndef ASM - -extern unsigned int sparc_disable_interrupts(); -extern void sparc_enable_interrupts(); - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for a critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level ) \ - (_level) = sparc_disable_interrupts() - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of a critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - sparc_enable_interrupts( _level ) -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level ) \ - sparc_flash_interrupts( _level ) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a straight fashion are undefined. - */ - -#define _CPU_ISR_Set_level( _newlevel ) \ - sparc_enable_interrupts( _newlevel << 8) - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * NOTE: Implemented as a subroutine for the SPARC port. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - unsigned32 *stack_base, - unsigned32 size, - unsigned32 new_level, - void *entry_point, - boolean is_fp -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. - * - * On the SPARC, this is is relatively painless but requires a small - * amount of wrapper code before using the regular restore code in - * of the context switch. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The FP context area for the SPARC is a simple structure and nothing - * special is required to find the "starting load point" - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * - * The SPARC allows us to use the simple initialization model - * in which an "initial" FP context was saved into _CPU_Null_fp_context - * at CPU initialization and it is simply copied into the destination - * context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } while (0) - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - do { \ - unsigned32 level; \ - \ - level = sparc_disable_interrupts(); \ - asm volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ - while (1); /* loop forever */ \ - } while (0) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - -#if ( SPARC_HAS_BITSCAN == 0 ) -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE -#else -#error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Bitfield handler macros */ - -/* Priority handler handler macros */ - -/* - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - -#if ( SPARC_HAS_BITSCAN == 1 ) -#error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs new_handler to be directly called from the trap - * table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) - -/* - * _CPU_Thread_Idle_body - * - * Some SPARC implementations have low power, sleep, or idle modes. This - * tries to take advantage of those models. - */ - -void _CPU_Thread_Idle_body( void ); - -#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* - * CPU_swap_u32 - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if you come across a better - * way for the SPARC PLEASE use it. The most common way to swap a 32-bit - * entity as shown below is not any more efficient on the SPARC. - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * It is not obvious how the SPARC can do significantly better than the - * generic code. gcc 2.7.0 only generates about 12 instructions for the - * following code at optimization level four (i.e. -O4). - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#endif ASM - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/sparc/rtems/score/sparc.h b/c/src/exec/score/cpu/sparc/rtems/score/sparc.h deleted file mode 100644 index e6d7690702..0000000000 --- a/c/src/exec/score/cpu/sparc/rtems/score/sparc.h +++ /dev/null @@ -1,266 +0,0 @@ -/* sparc.h - * - * This include file contains information pertaining to the SPARC - * processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef _INCLUDE_SPARC_h -#define _INCLUDE_SPARC_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "sparc" family. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - * - * Currently recognized feature flags: - * - * + SPARC_HAS_FPU - * 0 - no HW FPU - * 1 - has HW FPU (assumed to be compatible w/90C602) - * - * + SPARC_HAS_BITSCAN - * 0 - does not have scan instructions - * 1 - has scan instruction (not currently implemented) - * - * + SPARC_NUMBER_OF_REGISTER_WINDOWS - * 8 is the most common number supported by SPARC implementations. - * SPARC_PSR_CWP_MASK is derived from this value. - */ - -/* - * Some higher end SPARCs have a bitscan instructions. It would - * be nice to take advantage of them. Right now, there is no - * port to a CPU model with this feature and no (untested) code - * that is based on this feature flag. - */ - -#define SPARC_HAS_BITSCAN 0 - -/* - * This should be OK until a port to a higher end SPARC processor - * is made that has more than 8 register windows. If this cannot - * be determined based on multilib settings (v7/v8/v9), then the - * cpu_asm.S code that depends on this will have to move to libcpu. - */ - -#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8 - -/* - * This should be determined based on some soft float derived - * cpp predefine but gcc does not currently give us that information. - */ - - -#if defined(_SOFT_FLOAT) -#define SPARC_HAS_FPU 0 -#else -#define SPARC_HAS_FPU 1 -#endif - -#if SPARC_HAS_FPU -#define CPU_MODEL_NAME "w/FPU" -#else -#define CPU_MODEL_NAME "w/soft-float" -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "SPARC" - -/* - * Miscellaneous constants - */ - -/* - * PSR masks and starting bit positions - * - * NOTE: Reserved bits are ignored. - */ - -#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8) -#define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */ -#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16) -#define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */ -#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32) -#define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */ -#else -#error "Unsupported number of register windows for this cpu" -#endif - -#define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */ -#define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */ -#define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */ -#define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */ -#define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */ -#define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */ -#define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */ -#define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */ -#define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */ - -#define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */ -#define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */ -#define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */ -#define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */ -#define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */ -#define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */ -#define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */ -#define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */ -#define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */ -#define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */ - -#ifndef ASM - -/* - * Standard nop - */ - -#define nop() \ - do { \ - asm volatile ( "nop" ); \ - } while ( 0 ) - -/* - * Get and set the PSR - */ - -#define sparc_get_psr( _psr ) \ - do { \ - (_psr) = 0; \ - asm volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \ - } while ( 0 ) - -#define sparc_set_psr( _psr ) \ - do { \ - asm volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \ - nop(); \ - nop(); \ - nop(); \ - } while ( 0 ) - -/* - * Get and set the TBR - */ - -#define sparc_get_tbr( _tbr ) \ - do { \ - (_tbr) = 0; /* to avoid unitialized warnings */ \ - asm volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \ - } while ( 0 ) - -#define sparc_set_tbr( _tbr ) \ - do { \ - asm volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \ - } while ( 0 ) - -/* - * Get and set the WIM - */ - -#define sparc_get_wim( _wim ) \ - do { \ - asm volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \ - } while ( 0 ) - -#define sparc_set_wim( _wim ) \ - do { \ - asm volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \ - nop(); \ - nop(); \ - nop(); \ - } while ( 0 ) - -/* - * Get and set the Y - */ - -#define sparc_get_y( _y ) \ - do { \ - asm volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \ - } while ( 0 ) - -#define sparc_set_y( _y ) \ - do { \ - asm volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \ - } while ( 0 ) - -/* - * Manipulate the interrupt level in the psr - * - */ - -/* -#define sparc_disable_interrupts( _level ) \ - do { \ - register unsigned int _newlevel; \ - \ - sparc_get_psr( _level ); \ - (_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \ - sparc_set_psr( _newlevel ); \ - } while ( 0 ) - -#define sparc_enable_interrupts( _level ) \ - do { \ - unsigned int _tmp; \ - \ - sparc_get_psr( _tmp ); \ - _tmp &= ~SPARC_PSR_PIL_MASK; \ - _tmp |= (_level) & SPARC_PSR_PIL_MASK; \ - sparc_set_psr( _tmp ); \ - } while ( 0 ) -*/ - -#define sparc_flash_interrupts( _level ) \ - do { \ - register unsigned32 _ignored = 0; \ - \ - sparc_enable_interrupts( (_level) ); \ - sparc_disable_interrupts( _ignored ); \ - } while ( 0 ) - -/* -#define sparc_set_interrupt_level( _new_level ) \ - do { \ - register unsigned32 _new_psr_level = 0; \ - \ - sparc_get_psr( _new_psr_level ); \ - _new_psr_level &= ~SPARC_PSR_PIL_MASK; \ - _new_psr_level |= \ - (((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \ - sparc_set_psr( _new_psr_level ); \ - } while ( 0 ) -*/ - -#define sparc_get_interrupt_level( _level ) \ - do { \ - register unsigned32 _psr_level = 0; \ - \ - sparc_get_psr( _psr_level ); \ - (_level) = \ - (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \ - } while ( 0 ) - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_SPARC_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/sparc/rtems/score/types.h b/c/src/exec/score/cpu/sparc/rtems/score/types.h deleted file mode 100644 index 5e81acb4c7..0000000000 --- a/c/src/exec/score/cpu/sparc/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/* sparctypes.h - * - * This include file contains type definitions pertaining to the - * SPARC processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __SPARC_TYPES_h -#define __SPARC_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void sparc_isr; -typedef void ( *sparc_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/unix/.cvsignore b/c/src/exec/score/cpu/unix/.cvsignore deleted file mode 100644 index 62edb16be0..0000000000 --- a/c/src/exec/score/cpu/unix/.cvsignore +++ /dev/null @@ -1,15 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs -stamp-h.in diff --git a/c/src/exec/score/cpu/unix/ChangeLog b/c/src/exec/score/cpu/unix/ChangeLog deleted file mode 100644 index da6fb7c730..0000000000 --- a/c/src/exec/score/cpu/unix/ChangeLog +++ /dev/null @@ -1,134 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-26 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove references to RTEMS_BSP. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/unixtypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2001-03-28 Joel Sherrill <joel@OARcorp.com> - - * cpu.c: Define fix_syscall_errno() to nothing so MP links. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-02-13 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Fix the test to determine cpu context size. - -2001-02-05 Joel Sherrill <joel@OARcorp.com> - - * .cvsignore: Added stamp-h.in. - -2002-01-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Merge in rtems/Makefile.am and - rtems/score/Makefile.am. Remove gensize. Require automake-1.5. - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * rtems/score/.cvsignore: Add unixsize.h*. Add stamp-h*. - * configure.ac: Add AM_CONFIG_HEADER(rtems/score/unixsize.h). - * rtems/score/cpu.h: Replace CPU_CONTEXT_SIZE_IN_BYTES with - SIZEOF_CPU_CONTEXT. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-05-07 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/cpu.h: Remove #undef __STRICT_ANSI__. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-25 Joel Sherrill <joel@OARcorp.com> - - * cpu.c, rtems/score/cpu.h: Bug report from Peter Mueller - <peter.o.mueller@gmx.de> because of not correcting for the ISR - vector table now being allocated from the workspace. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use += to set up AM_CPPFLAGS. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use PROJECT_TOPdir in path to gensize. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/unix/Makefile.am b/c/src/exec/score/cpu/unix/Makefile.am deleted file mode 100644 index 3d100423aa..0000000000 --- a/c/src/exec/score/cpu/unix/Makefile.am +++ /dev/null @@ -1,50 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -AM_CPPFLAGS += -DCPU_SYNC_IO $(LIBC_DEFINES) - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/types.h \ - rtems/score/cpu.h \ - rtems/score/unix.h \ - rtems/score/unixsize.h -PREINSTALL_FILES = $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(rtems_cpu_rel_OBJECTS) $(REL) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/unix/configure.ac b/c/src/exec/score/cpu/unix/configure.ac deleted file mode 100644 index c9be4b92ed..0000000000 --- a/c/src/exec/score/cpu/unix/configure.ac +++ /dev/null @@ -1,50 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-unix],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu.c]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB -RTEMS_CHECK_MULTIPROCESSING - -# The only use of System V IPC is the UNIX port when multiprocessing. -AS_IF([test "$HAS_MP" = "yes"], - [RTEMS_CHECK_SYSV_UNIX]) - -## The code fragment below had been used in tools/cpu/unix/gensize.c. -## FIXME: -## * The pad very likely is not necessary. -AC_CHECK_SIZEOF([CPU_CONTEXT],[],[ -#include <stdio.h> -#include <setjmp.h> - -typedef struct { - jmp_buf regs; - int isr_level; - int pad[4]; /* just in case */ -} CPU_CONTEXT; -]) - -AM_CONFIG_HEADER(rtems/score/unixsize.h) - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/unix/cpu.c b/c/src/exec/score/cpu/unix/cpu.c deleted file mode 100644 index dc1b4a9e52..0000000000 --- a/c/src/exec/score/cpu/unix/cpu.c +++ /dev/null @@ -1,1137 +0,0 @@ -/* - * UNIX Simulator Dependent Source - * - * COPYRIGHT (c) 1994,95 by Division Incorporated - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/interr.h> - -#if defined(__linux__) -#define _XOPEN_SOURCE -#define MALLOC_0_RETURNS_NULL -#endif - -#include <sys/types.h> -#include <sys/times.h> -#include <stdio.h> -#include <stdlib.h> -#include <setjmp.h> -#include <signal.h> -#include <time.h> -#include <sys/time.h> -#include <errno.h> -#include <unistd.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <sys/ipc.h> -#include <sys/shm.h> -#include <sys/sem.h> -#endif -#include <string.h> /* memset */ - -#ifndef SA_RESTART -#define SA_RESTART 0 -#endif - -typedef struct { - jmp_buf regs; - int isr_level; -} Context_Control_overlay; - -void _CPU_Signal_initialize(void); -void _CPU_Stray_signal(int); -void _CPU_ISR_Handler(int); - -static sigset_t _CPU_Signal_mask; -static Context_Control_overlay _CPU_Context_Default_with_ISRs_enabled; -static Context_Control_overlay _CPU_Context_Default_with_ISRs_disabled; - -/* - * Sync IO support, an entry for each fd that can be set - */ - -void _CPU_Sync_io_Init(); - -static rtems_sync_io_handler _CPU_Sync_io_handlers[FD_SETSIZE]; -static int sync_io_nfds; -static fd_set sync_io_readfds; -static fd_set sync_io_writefds; -static fd_set sync_io_exceptfds; - -/* - * Which cpu are we? Used by libcpu and libbsp. - */ - -int cpu_number; - -/*PAGE - * - * _CPU_Initialize_vectors() - * - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * UNIX Specific Information: - * - * Complete initialization since the table is now allocated. - */ - -sigset_t posix_empty_mask; - -void _CPU_Initialize_vectors(void) -{ - unsigned32 i; - proc_ptr old_handler; - - /* - * Generate an empty mask to be used by disable_support - */ - - sigemptyset(&posix_empty_mask); - - /* - * Block all the signals except SIGTRAP for the debugger - * and fatal error signals. - */ - - (void) sigfillset(&_CPU_Signal_mask); - (void) sigdelset(&_CPU_Signal_mask, SIGTRAP); - (void) sigdelset(&_CPU_Signal_mask, SIGABRT); -#if !defined(__CYGWIN__) - (void) sigdelset(&_CPU_Signal_mask, SIGIOT); -#endif - (void) sigdelset(&_CPU_Signal_mask, SIGCONT); - (void) sigdelset(&_CPU_Signal_mask, SIGSEGV); - (void) sigdelset(&_CPU_Signal_mask, SIGBUS); - (void) sigdelset(&_CPU_Signal_mask, SIGFPE); - - _CPU_ISR_Enable(1); - - /* - * Set the handler for all signals to be signal_handler - * which will then vector out to the correct handler - * for whichever signal actually happened. Initially - * set the vectors to the stray signal handler. - */ - - for (i = 0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++) - (void)_CPU_ISR_install_vector(i, _CPU_Stray_signal, &old_handler); - - _CPU_Signal_initialize(); -} - -void _CPU_Signal_initialize( void ) -{ - struct sigaction act; - sigset_t mask; - - /* mark them all active except for TraceTrap and Abort */ - - mask = _CPU_Signal_mask; - sigprocmask(SIG_UNBLOCK, &mask, 0); - - act.sa_handler = _CPU_ISR_Handler; - act.sa_mask = mask; - act.sa_flags = SA_RESTART; - - sigaction(SIGHUP, &act, 0); - sigaction(SIGINT, &act, 0); - sigaction(SIGQUIT, &act, 0); - sigaction(SIGILL, &act, 0); -#ifdef SIGEMT - sigaction(SIGEMT, &act, 0); -#endif - sigaction(SIGFPE, &act, 0); - sigaction(SIGKILL, &act, 0); - sigaction(SIGBUS, &act, 0); - sigaction(SIGSEGV, &act, 0); -#ifdef SIGSYS - sigaction(SIGSYS, &act, 0); -#endif - sigaction(SIGPIPE, &act, 0); - sigaction(SIGALRM, &act, 0); - sigaction(SIGTERM, &act, 0); - sigaction(SIGUSR1, &act, 0); - sigaction(SIGUSR2, &act, 0); - sigaction(SIGCHLD, &act, 0); -#ifdef SIGCLD - sigaction(SIGCLD, &act, 0); -#endif -#ifdef SIGPWR - sigaction(SIGPWR, &act, 0); -#endif - sigaction(SIGVTALRM, &act, 0); - sigaction(SIGPROF, &act, 0); - sigaction(SIGIO, &act, 0); - sigaction(SIGWINCH, &act, 0); - sigaction(SIGSTOP, &act, 0); - sigaction(SIGTTIN, &act, 0); - sigaction(SIGTTOU, &act, 0); - sigaction(SIGURG, &act, 0); -#ifdef SIGLOST - sigaction(SIGLOST, &act, 0); -#endif -} - -/*PAGE - * - * _CPU_Context_From_CPU_Init - */ - -void _CPU_Context_From_CPU_Init() -{ - -#if defined(__hppa__) && defined(RTEMS_UNIXLIB_SETJMP) - /* - * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp - * will handle the full 32 floating point registers. - */ - - { - extern unsigned32 _SYSTEM_ID; - - _SYSTEM_ID = 0x20c; - } -#endif - - /* - * get default values to use in _CPU_Context_Initialize() - */ - - if ( sizeof(Context_Control_overlay) > sizeof(Context_Control) ) - _CPU_Fatal_halt( 0xdeadf00d ); - - (void) memset( - &_CPU_Context_Default_with_ISRs_enabled, - 0, - sizeof(Context_Control_overlay) - ); - (void) memset( - &_CPU_Context_Default_with_ISRs_disabled, - 0, - sizeof(Context_Control_overlay) - ); - - _CPU_ISR_Set_level( 0 ); - _CPU_Context_switch( - (Context_Control *) &_CPU_Context_Default_with_ISRs_enabled, - (Context_Control *) &_CPU_Context_Default_with_ISRs_enabled - ); - - _CPU_ISR_Set_level( 1 ); - _CPU_Context_switch( - (Context_Control *) &_CPU_Context_Default_with_ISRs_disabled, - (Context_Control *) &_CPU_Context_Default_with_ISRs_disabled - ); -} - -/*PAGE - * - * _CPU_Sync_io_Init - */ - -void _CPU_Sync_io_Init() -{ - int fd; - - for (fd = 0; fd < FD_SETSIZE; fd++) - _CPU_Sync_io_handlers[fd] = NULL; - - sync_io_nfds = 0; - FD_ZERO(&sync_io_readfds); - FD_ZERO(&sync_io_writefds); - FD_ZERO(&sync_io_exceptfds); -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - sigset_t old_mask; - - sigemptyset( &old_mask ); - sigprocmask(SIG_BLOCK, 0, &old_mask); - - if (memcmp((void *)&posix_empty_mask, (void *)&old_mask, sizeof(sigset_t))) - return 1; - - return 0; -} - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - /* - * If something happened where the public Context_Control is not - * at least as large as the private Context_Control_overlay, then - * we are in trouble. - */ - - if ( sizeof(Context_Control_overlay) > sizeof(Context_Control) ) - _CPU_Fatal_error(0x100 + 1); - - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; - - /* - * XXX; If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* XXX: FP context initialization support */ - - _CPU_Table = *cpu_table; - - _CPU_Sync_io_Init(); - - _CPU_Context_From_CPU_Init(); - -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - _CPU_Fatal_halt( 0xdeaddead ); -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _CPU_ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * Stop until we get a signal which is the logically the same thing - * entering low-power or sleep mode on a real processor and waiting for - * an interrupt. This significantly reduces the consumption of host - * CPU cycles which is again similar to low power mode. - */ - -void _CPU_Thread_Idle_body( void ) -{ -#if CPU_SYNC_IO - extern void _Thread_Dispatch(void); - int fd; -#endif - - while (1) { -#ifdef RTEMS_DEBUG - /* interrupts had better be enabled at this point! */ - if (_CPU_ISR_Get_level() != 0) - abort(); -#endif - - /* - * Block on a select statement, the CPU interface added allow the - * user to add new descriptors which are to be blocked on - */ - -#if CPU_SYNC_IO - if (sync_io_nfds) { - int result; - fd_set readfds, writefds, exceptfds; - - readfds = sync_io_readfds; - writefds = sync_io_writefds; - exceptfds = sync_io_exceptfds; - result = select(sync_io_nfds, - &readfds, - &writefds, - &exceptfds, - NULL); - - if (result < 0) { - if (errno != EINTR) - _CPU_Fatal_error(0x200); /* FIXME : what number should go here !! */ - _Thread_Dispatch(); - continue; - } - - for (fd = 0; fd < sync_io_nfds; fd++) { - boolean read = FD_ISSET(fd, &readfds); - boolean write = FD_ISSET(fd, &writefds); - boolean except = FD_ISSET(fd, &exceptfds); - - if (_CPU_Sync_io_handlers[fd] && (read || write || except)) - _CPU_Sync_io_handlers[fd](fd, read, write, except); - } - - _Thread_Dispatch(); - } else - pause(); -#else - pause(); -#endif - - } - -} - -/*PAGE - * - * _CPU_Context_Initialize - */ - -void _CPU_Context_Initialize( - Context_Control *_the_context, - unsigned32 *_stack_base, - unsigned32 _size, - unsigned32 _new_level, - void *_entry_point, - boolean _is_fp -) -{ - unsigned32 *addr; - unsigned32 jmp_addr; - unsigned32 _stack_low; /* lowest "stack aligned" address */ - unsigned32 _stack_high; /* highest "stack aligned" address */ - unsigned32 _the_size; - - jmp_addr = (unsigned32) _entry_point; - - /* - * On CPUs with stacks which grow down, we build the stack - * based on the _stack_high address. On CPUs with stacks which - * grow up, we build the stack based on the _stack_low address. - */ - - _stack_low = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT - 1; - _stack_low &= ~(CPU_STACK_ALIGNMENT - 1); - - _stack_high = (unsigned32)(_stack_base) + _size; - _stack_high &= ~(CPU_STACK_ALIGNMENT - 1); - - if (_stack_high > _stack_low) - _the_size = _stack_high - _stack_low; - else - _the_size = _stack_low - _stack_high; - - /* - * Slam our jmp_buf template into the context we are creating - */ - - if ( _new_level == 0 ) - *(Context_Control_overlay *)_the_context = - _CPU_Context_Default_with_ISRs_enabled; - else - *(Context_Control_overlay *)_the_context = - _CPU_Context_Default_with_ISRs_disabled; - - addr = (unsigned32 *)_the_context; - -#if defined(__hppa__) - *(addr + RP_OFF) = jmp_addr; - *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE); - - /* - * See if we are using shared libraries by checking - * bit 30 in 24 off of newp. If bit 30 is set then - * we are using shared libraries and the jump address - * points to the pointer, so we put that into rp instead. - */ - - if (jmp_addr & 0x40000000) { - jmp_addr &= 0xfffffffc; - *(addr + RP_OFF) = *(unsigned32 *)jmp_addr; - } -#elif defined(__sparc__) - - /* - * See /usr/include/sys/stack.h in Solaris 2.3 for a nice - * diagram of the stack. - */ - - asm ("ta 0x03"); /* flush registers */ - - *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET; - *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE); - *(addr + FP_OFF) = (unsigned32)(_stack_high); - -#elif defined(__i386__) - - /* - * This information was gathered by disassembling setjmp(). - */ - - { - unsigned32 stack_ptr; - - stack_ptr = _stack_high - CPU_FRAME_SIZE; - - *(addr + EBX_OFF) = 0xFEEDFEED; - *(addr + ESI_OFF) = 0xDEADDEAD; - *(addr + EDI_OFF) = 0xDEAFDEAF; - *(addr + EBP_OFF) = stack_ptr; - *(addr + ESP_OFF) = stack_ptr; - *(addr + RET_OFF) = jmp_addr; - - addr = (unsigned32 *) stack_ptr; - - addr[ 0 ] = jmp_addr; - addr[ 1 ] = (unsigned32) stack_ptr; - addr[ 2 ] = (unsigned32) stack_ptr; - } - -#else -#error "UNKNOWN CPU!!!" -#endif - -} - -/*PAGE - * - * _CPU_Context_restore - */ - -void _CPU_Context_restore( - Context_Control *next -) -{ - Context_Control_overlay *nextp = (Context_Control_overlay *)next; - - _CPU_ISR_Enable(nextp->isr_level); - longjmp( nextp->regs, 0 ); -} - -/*PAGE - * - * _CPU_Context_switch - */ - -static void do_jump( - Context_Control_overlay *currentp, - Context_Control_overlay *nextp -); - -void _CPU_Context_switch( - Context_Control *current, - Context_Control *next -) -{ - Context_Control_overlay *currentp = (Context_Control_overlay *)current; - Context_Control_overlay *nextp = (Context_Control_overlay *)next; -#if 0 - int status; -#endif - - currentp->isr_level = _CPU_ISR_Disable_support(); - - do_jump( currentp, nextp ); - -#if 0 - if (sigsetjmp(currentp->regs, 1) == 0) { /* Save the current context */ - siglongjmp(nextp->regs, 0); /* Switch to the new context */ - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - status - ); - } -#endif - -#ifdef RTEMS_DEBUG - if (_CPU_ISR_Get_level() == 0) - abort(); -#endif - - _CPU_ISR_Enable(currentp->isr_level); -} - -static void do_jump( - Context_Control_overlay *currentp, - Context_Control_overlay *nextp -) -{ - int status; - - if (setjmp(currentp->regs) == 0) { /* Save the current context */ - longjmp(nextp->regs, 0); /* Switch to the new context */ - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - status - ); - } -} - -/*PAGE - * - * _CPU_Save_float_context - */ - -void _CPU_Save_float_context( - Context_Control_fp *fp_context -) -{ -} - -/*PAGE - * - * _CPU_Restore_float_context - */ - -void _CPU_Restore_float_context( - Context_Control_fp *fp_context -) -{ -} - -/*PAGE - * - * _CPU_ISR_Disable_support - */ - -unsigned32 _CPU_ISR_Disable_support(void) -{ - int status; - sigset_t old_mask; - - sigemptyset( &old_mask ); - status = sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask); - if ( status ) - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - status - ); - - if (memcmp((void *)&posix_empty_mask, (void *)&old_mask, sizeof(sigset_t))) - return 1; - - return 0; -} - -/*PAGE - * - * _CPU_ISR_Enable - */ - -void _CPU_ISR_Enable( - unsigned32 level -) -{ - int status; - - if (level == 0) - status = sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0); - else - status = sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0); - - if ( status ) - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - status - ); -} - -/*PAGE - * - * _CPU_ISR_Handler - * - * External interrupt handler. - * This is installed as a UNIX signal handler. - * It vectors out to specific user interrupt handlers. - */ - -void _CPU_ISR_Handler(int vector) -{ - extern void _Thread_Dispatch(void); - extern unsigned32 _Thread_Dispatch_disable_level; - extern boolean _Context_Switch_necessary; - - if (_ISR_Nest_level++ == 0) { - /* switch to interrupt stack */ - } - - _Thread_Dispatch_disable_level++; - - if (_ISR_Vector_table[vector]) { - _ISR_Vector_table[vector](vector); - } else { - _CPU_Stray_signal(vector); - } - - if (_ISR_Nest_level-- == 0) { - /* switch back to original stack */ - } - - _Thread_Dispatch_disable_level--; - - if (_Thread_Dispatch_disable_level == 0 && - (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) { - _ISR_Signals_to_thread_executing = FALSE; - _CPU_ISR_Enable(0); - _Thread_Dispatch(); - } -} - -/*PAGE - * - * _CPU_Stray_signal - */ - -void _CPU_Stray_signal(int sig_num) -{ - char buffer[ 4 ]; - - /* - * print "stray" msg about ones which that might mean something - * Avoid using the stdio section of the library. - * The following is generally safe. - */ - - switch (sig_num) - { -#ifdef SIGCLD - case SIGCLD: - break; -#endif - default: - { - /* - * We avoid using the stdio section of the library. - * The following is generally safe - */ - - int digit; - int number = sig_num; - int len = 0; - - digit = number / 100; - number %= 100; - if (digit) buffer[len++] = '0' + digit; - - digit = number / 10; - number %= 10; - if (digit || len) buffer[len++] = '0' + digit; - - digit = number; - buffer[len++] = '0' + digit; - - buffer[ len++ ] = '\n'; - - write( 2, "Stray signal ", 13 ); - write( 2, buffer, len ); - - } - } - - /* - * If it was a "fatal" signal, then exit here - * If app code has installed a hander for one of these, then - * we won't call _CPU_Stray_signal, so this is ok. - */ - - switch (sig_num) { - case SIGINT: - case SIGHUP: - case SIGQUIT: - case SIGILL: -#ifdef SIGEMT - case SIGEMT: -#endif - case SIGKILL: - case SIGBUS: - case SIGSEGV: - case SIGTERM: -#if !defined(__CYGWIN__) - case SIGIOT: -#endif - _CPU_Fatal_error(0x100 + sig_num); - } -} - -/*PAGE - * - * _CPU_Fatal_error - */ - -void _CPU_Fatal_error(unsigned32 error) -{ - setitimer(ITIMER_REAL, 0, 0); - - if ( error ) { -#ifdef RTEMS_DEBUG - abort(); -#endif - if (getenv("RTEMS_DEBUG")) - abort(); - } - - _exit(error); -} - -/* - * Special Purpose Routines to hide the use of UNIX system calls. - */ - -int _CPU_Set_sync_io_handler( - int fd, - boolean read, - boolean write, - boolean except, - rtems_sync_io_handler handler -) -{ - if ((fd < FD_SETSIZE) && (_CPU_Sync_io_handlers[fd] == NULL)) { - if (read) - FD_SET(fd, &sync_io_readfds); - else - FD_CLR(fd, &sync_io_readfds); - if (write) - FD_SET(fd, &sync_io_writefds); - else - FD_CLR(fd, &sync_io_writefds); - if (except) - FD_SET(fd, &sync_io_exceptfds); - else - FD_CLR(fd, &sync_io_exceptfds); - _CPU_Sync_io_handlers[fd] = handler; - if ((fd + 1) > sync_io_nfds) - sync_io_nfds = fd + 1; - return 0; - } - return -1; -} - -int _CPU_Clear_sync_io_handler( - int fd -) -{ - if ((fd < FD_SETSIZE) && _CPU_Sync_io_handlers[fd]) { - FD_CLR(fd, &sync_io_readfds); - FD_CLR(fd, &sync_io_writefds); - FD_CLR(fd, &sync_io_exceptfds); - _CPU_Sync_io_handlers[fd] = NULL; - sync_io_nfds = 0; - for (fd = 0; fd < FD_SETSIZE; fd++) - if (FD_ISSET(fd, &sync_io_readfds) || - FD_ISSET(fd, &sync_io_writefds) || - FD_ISSET(fd, &sync_io_exceptfds)) - sync_io_nfds = fd + 1; - return 0; - } - return -1; -} - -int _CPU_Get_clock_vector( void ) -{ - return SIGALRM; -} - -void _CPU_Start_clock( - int microseconds -) -{ - struct itimerval new; - - new.it_value.tv_sec = 0; - new.it_value.tv_usec = microseconds; - new.it_interval.tv_sec = 0; - new.it_interval.tv_usec = microseconds; - - setitimer(ITIMER_REAL, &new, 0); -} - -void _CPU_Stop_clock( void ) -{ - struct itimerval new; - struct sigaction act; - - /* - * Set the SIGALRM signal to ignore any last - * signals that might come in while we are - * disarming the timer and removing the interrupt - * vector. - */ - - (void) memset(&act, 0, sizeof(act)); - act.sa_handler = SIG_IGN; - - sigaction(SIGALRM, &act, 0); - - (void) memset(&new, 0, sizeof(new)); - setitimer(ITIMER_REAL, &new, 0); -} - -#if 0 -extern void fix_syscall_errno( void ); -#endif -#define fix_syscall_errno() - -#if defined(RTEMS_MULTIPROCESSING) -int _CPU_SHM_Semid; - -void _CPU_SHM_Init( - unsigned32 maximum_nodes, - boolean is_master_node, - void **shm_address, - unsigned32 *shm_length -) -{ - int i; - int shmid; - char *shm_addr; - key_t shm_key; - key_t sem_key; - int status = 0; /* to avoid unitialized warnings */ - int shm_size; - - if (getenv("RTEMS_SHM_KEY")) - shm_key = strtol(getenv("RTEMS_SHM_KEY"), 0, 0); - else -#ifdef RTEMS_SHM_KEY - shm_key = RTEMS_SHM_KEY; -#else - shm_key = 0xa000; -#endif - - if (getenv("RTEMS_SHM_SIZE")) - shm_size = strtol(getenv("RTEMS_SHM_SIZE"), 0, 0); - else -#ifdef RTEMS_SHM_SIZE - shm_size = RTEMS_SHM_SIZE; -#else - shm_size = 64 * 1024; -#endif - - if (getenv("RTEMS_SHM_SEMAPHORE_KEY")) - sem_key = strtol(getenv("RTEMS_SHM_SEMAPHORE_KEY"), 0, 0); - else -#ifdef RTEMS_SHM_SEMAPHORE_KEY - sem_key = RTEMS_SHM_SEMAPHORE_KEY; -#else - sem_key = 0xa001; -#endif - - shmid = shmget(shm_key, shm_size, IPC_CREAT | 0660); - if ( shmid == -1 ) { - fix_syscall_errno(); /* in case of newlib */ - perror( "shmget" ); - _CPU_Fatal_halt( 0xdead0001 ); - } - - shm_addr = shmat(shmid, (char *)0, SHM_RND); - if ( shm_addr == (void *)-1 ) { - fix_syscall_errno(); /* in case of newlib */ - perror( "shmat" ); - _CPU_Fatal_halt( 0xdead0002 ); - } - - _CPU_SHM_Semid = semget(sem_key, maximum_nodes + 1, IPC_CREAT | 0660); - if ( _CPU_SHM_Semid == -1 ) { - fix_syscall_errno(); /* in case of newlib */ - perror( "semget" ); - _CPU_Fatal_halt( 0xdead0003 ); - } - - if ( is_master_node ) { - for ( i=0 ; i <= maximum_nodes ; i++ ) { -#if !HAS_UNION_SEMUN - union semun { - int val; - struct semid_ds *buf; - unsigned short int *array; -#if defined(__linux__) - struct seminfo *__buf; -#endif - } ; -#endif - union semun help ; - help.val = 1; - status = semctl( _CPU_SHM_Semid, i, SETVAL, help ); - - fix_syscall_errno(); /* in case of newlib */ - if ( status == -1 ) { - _CPU_Fatal_halt( 0xdead0004 ); - } - } - } - - *shm_address = shm_addr; - *shm_length = shm_size; - -} -#endif - -int _CPU_Get_pid( void ) -{ - return getpid(); -} - -#if defined(RTEMS_MULTIPROCESSING) -/* - * Define this to use signals for MPCI shared memory driver. - * If undefined, the shared memory driver will poll from the - * clock interrupt. - * Ref: ../shmsupp/getcfg.c - * - * BEWARE:: many UN*X kernels and debuggers become severely confused when - * debugging programs which use signals. The problem is *much* - * worse when using multiple signals, since ptrace(2) tends to - * drop all signals except 1 in the case of multiples. - * On hpux9, this problem was so bad, we couldn't use interrupts - * with the shared memory driver if we ever hoped to debug - * RTEMS programs. - * Maybe systems that use /proc don't have this problem... - */ - - -int _CPU_SHM_Get_vector( void ) -{ -#ifdef CPU_USE_SHM_INTERRUPTS - return SIGUSR1; -#else - return 0; -#endif -} - -void _CPU_SHM_Send_interrupt( - int pid, - int vector -) -{ - kill((pid_t) pid, vector); -} - -void _CPU_SHM_Lock( - int semaphore -) -{ - struct sembuf sb; - - sb.sem_num = semaphore; - sb.sem_op = -1; - sb.sem_flg = 0; - - while (1) { - int status = -1; - - status = semop(_CPU_SHM_Semid, &sb, 1); - if ( status >= 0 ) - break; - if ( status == -1 ) { - fix_syscall_errno(); /* in case of newlib */ - if (errno == EINTR) - continue; - perror("shm lock"); - _CPU_Fatal_halt( 0xdead0005 ); - } - } - -} - -void _CPU_SHM_Unlock( - int semaphore -) -{ - struct sembuf sb; - int status; - - sb.sem_num = semaphore; - sb.sem_op = 1; - sb.sem_flg = 0; - - while (1) { - status = semop(_CPU_SHM_Semid, &sb, 1); - if ( status >= 0 ) - break; - - if ( status == -1 ) { - fix_syscall_errno(); /* in case of newlib */ - if (errno == EINTR) - continue; - perror("shm unlock"); - _CPU_Fatal_halt( 0xdead0006 ); - } - } - -} -#endif diff --git a/c/src/exec/score/cpu/unix/rtems/.cvsignore b/c/src/exec/score/cpu/unix/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/unix/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/unix/rtems/score/.cvsignore b/c/src/exec/score/cpu/unix/rtems/score/.cvsignore deleted file mode 100644 index 7a3170081d..0000000000 --- a/c/src/exec/score/cpu/unix/rtems/score/.cvsignore +++ /dev/null @@ -1,4 +0,0 @@ -Makefile -Makefile.in -unixsize.h* -stamp-h* diff --git a/c/src/exec/score/cpu/unix/rtems/score/cpu.h b/c/src/exec/score/cpu/unix/rtems/score/cpu.h deleted file mode 100644 index 644fbb4b86..0000000000 --- a/c/src/exec/score/cpu/unix/rtems/score/cpu.h +++ /dev/null @@ -1,1120 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the HP - * PA-RISC processor (Level 1.1). - * - * COPYRIGHT (c) 1994 by Division Incorporated - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/unix.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -#include <rtems/score/unixsize.h> - -#if defined(solaris2) -#undef _POSIX_C_SOURCE -#define _POSIX_C_SOURCE 3 -#endif - -#if defined(linux) -#define MALLOC_0_RETURNS_NULL -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#if defined(__hppa__) -#define CPU_STACK_GROWS_UP TRUE -#elif defined(__sparc__) || defined(__i386__) -#define CPU_STACK_GROWS_UP FALSE -#else -#error "unknown CPU!!" -#endif - - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#ifdef __GNUC__ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) -#else -#define CPU_STRUCTURE_ALIGNMENT -#endif - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#if defined(__hppa__) || defined(__sparc__) -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE -#elif defined(__i386__) -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE -#else -#error "Unknown CPU!!!" -#endif - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_NAME "UNIX" - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -#if defined(__hppa__) -/* - * Word indices within a jmp_buf structure - */ - -#ifdef RTEMS_NEWLIB_SETJMP -#define RP_OFF 6 -#define SP_OFF 2 -#define R3_OFF 10 -#define R4_OFF 11 -#define R5_OFF 12 -#define R6_OFF 13 -#define R7_OFF 14 -#define R8_OFF 15 -#define R9_OFF 16 -#define R10_OFF 17 -#define R11_OFF 18 -#define R12_OFF 19 -#define R13_OFF 20 -#define R14_OFF 21 -#define R15_OFF 22 -#define R16_OFF 23 -#define R17_OFF 24 -#define R18_OFF 25 -#define DP_OFF 26 -#endif - -#ifdef RTEMS_UNIXLIB_SETJMP -#define RP_OFF 0 -#define SP_OFF 1 -#define R3_OFF 4 -#define R4_OFF 5 -#define R5_OFF 6 -#define R6_OFF 7 -#define R7_OFF 8 -#define R8_OFF 9 -#define R9_OFF 10 -#define R10_OFF 11 -#define R11_OFF 12 -#define R12_OFF 13 -#define R13_OFF 14 -#define R14_OFF 15 -#define R15_OFF 16 -#define R16_OFF 17 -#define R17_OFF 18 -#define R18_OFF 19 -#define DP_OFF 20 -#endif -#endif - -#if defined(__i386__) - -#ifdef RTEMS_NEWLIB -#error "Newlib not installed" -#endif - -/* - * For i386 targets - */ - -#ifdef RTEMS_UNIXLIB -#if defined(__FreeBSD__) -#define RET_OFF 0 -#define EBX_OFF 1 -#define EBP_OFF 2 -#define ESP_OFF 3 -#define ESI_OFF 4 -#define EDI_OFF 5 -#elif defined(__CYGWIN__) -#define EAX_OFF 0 -#define EBX_OFF 1 -#define ECX_OFF 2 -#define EDX_OFF 3 -#define ESI_OFF 4 -#define EDI_OFF 5 -#define EBP_OFF 6 -#define ESP_OFF 7 -#define RET_OFF 8 -#else -/* Linux */ -#define EBX_OFF 0 -#define ESI_OFF 1 -#define EDI_OFF 2 -#define EBP_OFF 3 -#define ESP_OFF 4 -#define RET_OFF 5 -#endif -#endif - -#endif - -#if defined(__sparc__) - -/* - * Word indices within a jmp_buf structure - */ - -#ifdef RTEMS_NEWLIB -#define ADDR_ADJ_OFFSET -8 -#define SP_OFF 0 -#define RP_OFF 1 -#define FP_OFF 2 -#endif - -#ifdef RTEMS_UNIXLIB -#define ADDR_ADJ_OFFSET 0 -#define G0_OFF 0 -#define SP_OFF 1 -#define RP_OFF 2 -#define FP_OFF 3 -#define I7_OFF 4 -#endif - -#endif - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -/* - * This is really just the area for the following fields. - * - * jmp_buf regs; - * unsigned32 isr_level; - * - * Doing it this way avoids conflicts between the native stuff and the - * RTEMS stuff. - * - * NOTE: - * hpux9 setjmp is optimized for the case where the setjmp buffer - * is 8 byte aligned. In a RISC world, this seems likely to enable - * 8 byte copies, especially for the float registers. - * So we always align them on 8 byte boundaries. - */ - -#ifdef __GNUC__ -#define CONTEXT_STRUCTURE_ALIGNMENT __attribute__ ((aligned (8))) -#else -#define CONTEXT_STRUCTURE_ALIGNMENT -#endif - -typedef struct { - char Area[ SIZEOF_CPU_CONTEXT ] CONTEXT_STRUCTURE_ALIGNMENT; -} Context_Control; - -typedef struct { -} Context_Control_fp; - -typedef struct { -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the UNIX Simulator specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of required fields */ -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access UNIX specific additions to the CPU Table - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * The size of a frame on the stack - */ - -#if defined(__hppa__) -#define CPU_FRAME_SIZE (32 * 4) -#elif defined(__sparc__) -#define CPU_FRAME_SIZE (112) /* based on disassembled test code */ -#elif defined(__i386__) -#define CPU_FRAME_SIZE (24) /* return address, sp, and bp pushed plus fudge */ -#else -#error "Unknown CPU!!!" -#endif - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (16 * 1024) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT 64 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -void _CPU_Initialize_vectors(void); - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -extern unsigned32 _CPU_ISR_Disable_support(void); - -#define _CPU_ISR_Disable( _level ) \ - do { \ - (_level) = _CPU_ISR_Disable_support(); \ - } while ( 0 ) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -void _CPU_ISR_Enable(unsigned32 level); - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level ) \ - do { \ - register unsigned32 _ignored = 0; \ - _CPU_ISR_Enable( (_level) ); \ - _CPU_ISR_Disable( _ignored ); \ - } while ( 0 ) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ - -#define _CPU_ISR_Set_level( new_level ) \ - { \ - if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \ - else _CPU_ISR_Enable( 1 ); \ - } - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } - -#define _CPU_Context_save_fp( _fp_context ) \ - _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context)) - -#define _CPU_Context_restore_fp( _fp_context ) \ - _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context)) - -extern void _CPU_Context_Initialize( - Context_Control *_the_context, - unsigned32 *_stack_base, - unsigned32 _size, - unsigned32 _new_level, - void *_entry_point, - boolean _is_fp -); - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - _CPU_Fatal_error( _error ) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -/* - * The UNIX port uses the generic C algorithm for bitfield scan to avoid - * dependencies on either a native bitscan instruction or an ffs() in the - * C library. - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/* end of Bitfield handler macros */ - -/* Priority handler handler macros */ - -/* - * The UNIX port uses the generic C algorithm for bitfield scan to avoid - * dependencies on either a native bitscan instruction or an ffs() in the - * C library. - */ - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Save_float_context - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Save_float_context( - Context_Control_fp *fp_context_ptr -); - -/* - * _CPU_Restore_float_context - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Restore_float_context( - Context_Control_fp *fp_context_ptr -); - - -void _CPU_ISR_Set_signal_level( - unsigned32 level -); - -void _CPU_Fatal_error( - unsigned32 _error -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -/* - * Special Purpose Routines to hide the use of UNIX system calls. - */ - - -/* - * Pointer to a sync io Handler - */ - -typedef void ( *rtems_sync_io_handler )( - int fd, - boolean read, - boolean wrtie, - boolean except -); - -/* returns -1 if fd to large, 0 is successful */ -int _CPU_Set_sync_io_handler( - int fd, - boolean read, - boolean write, - boolean except, - rtems_sync_io_handler handler -); - -/* returns -1 if fd to large, o if successful */ -int _CPU_Clear_sync_io_handler( - int fd -); - -int _CPU_Get_clock_vector( void ); - -void _CPU_Start_clock( - int microseconds -); - -void _CPU_Stop_clock( void ); - -#if defined(RTEMS_MULTIPROCESSING) - -void _CPU_SHM_Init( - unsigned32 maximum_nodes, - boolean is_master_node, - void **shm_address, - unsigned32 *shm_length -); - -int _CPU_Get_pid( void ); - -int _CPU_SHM_Get_vector( void ); - -void _CPU_SHM_Send_interrupt( - int pid, - int vector -); - -void _CPU_SHM_Lock( - int semaphore -); - -void _CPU_SHM_Unlock( - int semaphore -); -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/unix/rtems/score/types.h b/c/src/exec/score/cpu/unix/rtems/score/types.h deleted file mode 100644 index f423564ebc..0000000000 --- a/c/src/exec/score/cpu/unix/rtems/score/types.h +++ /dev/null @@ -1,71 +0,0 @@ -/* unixtypes.h - * - * This include file contains type definitions which are appropriate - * for a typical modern UNIX box using GNU C for the RTEMS simulator. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __UNIX_TYPES_h -#define __UNIX_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * some C++ compilers (eg: HP's) don't do 'signed' or 'volatile' - */ -#if defined(__cplusplus) && !defined(__GNUC__) -#define signed -#define volatile -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ - -/* - * some C++ compilers (eg: HP's) don't do 'long long' - */ -#if defined(__GNUC__) -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ -typedef signed long long signed64; /* 64 bit signed integer */ -#endif - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void unix_isr; - -typedef unix_isr ( *unix_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/unix/rtems/score/unix.h b/c/src/exec/score/cpu/unix/rtems/score/unix.h deleted file mode 100644 index e8a0c7bdd6..0000000000 --- a/c/src/exec/score/cpu/unix/rtems/score/unix.h +++ /dev/null @@ -1,72 +0,0 @@ -/* unix.h - * - * This include file contains the definitions required by RTEMS - * which are typical for a modern UNIX computer using GCC. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __UNIX_h -#define __UNIX_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "unix" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" - -#elif defined(hpux) - -#define CPU_MODEL_NAME "HP-UX" - -#elif defined(solaris2) - -#define CPU_MODEL_NAME "Solaris" - -#elif defined(__linux__) || defined(linux) - -#define CPU_MODEL_NAME "Linux" - -#elif defined(__CYGWIN__) - -#define CPU_MODEL_NAME "Cygwin" - -#elif defined(__FreeBSD__) - -#define CPU_MODEL_NAME "FreeBSD" - -#else - -#error "Unsupported CPU Model" - -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ - diff --git a/c/src/exec/score/include/.cvsignore b/c/src/exec/score/include/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/include/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/include/Makefile.am b/c/src/exec/score/include/Makefile.am deleted file mode 100644 index 8dc4904834..0000000000 --- a/c/src/exec/score/include/Makefile.am +++ /dev/null @@ -1,65 +0,0 @@ -## -## $Id$ -## - - -$(PROJECT_INCLUDE)/%: % - $(INSTALL_DATA) $< $@ - -include_rtemsdir = $(includedir)/rtems - -$(PROJECT_INCLUDE)/rtems: - @$(mkinstalldirs) $@ - -include_rtems_HEADERS = rtems/debug.h rtems/system.h rtems/seterr.h - -PREINSTALL_FILES = $(PROJECT_INCLUDE)/rtems \ - $(include_rtems_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score - -$(PROJECT_INCLUDE)/rtems/score: - @$(mkinstalldirs) $@ - -# We only build multiprocessing related files if HAS_MP was defined -MP_H_FILES = rtems/score/mpci.h rtems/score/mppkt.h rtems/score/objectmp.h \ - rtems/score/threadmp.h - -# H_FILES that get installed in the rtems/score subdirectoy -STD_H_FILES = rtems/score/address.h rtems/score/apiext.h \ - rtems/score/apimutex.h \ - rtems/score/bitfield.h rtems/score/chain.h rtems/score/context.h \ - rtems/score/copyrt.h rtems/score/coremsg.h rtems/score/coremutex.h \ - rtems/score/coresem.h rtems/score/heap.h rtems/score/interr.h \ - rtems/score/isr.h rtems/score/object.h rtems/score/priority.h \ - rtems/score/stack.h rtems/score/states.h rtems/score/sysstate.h \ - rtems/score/thread.h rtems/score/threadq.h rtems/score/tod.h \ - rtems/score/tqdata.h rtems/score/userext.h rtems/score/watchdog.h \ - rtems/score/wkspace.h - -if HAS_MP -include_rtems_score_HEADERS = $(STD_H_FILES) $(MP_H_FILES) rtems/score/cpuopts.h -else -include_rtems_score_HEADERS = $(STD_H_FILES) rtems/score/cpuopts.h -endif - -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%=$(PROJECT_INCLUDE)/%) - -# make the cpu dependent options file -# FIXME: We are exporting a config-header here, which is a bad idea in -# general -rtems/score/cpuopts.h: rtems/score/cpuopts-tmp.h - @echo "/* target cpu dependent options file */" >$@ - @echo "/* automatically generated -- DO NOT EDIT!! */" >>$@ - @echo >>$@ - @echo "#ifndef __CPU_OPTIONS_h" >>$@ - @echo "#define __CPU_OPTIONS_h" >>$@ - @echo >>$@ - @cat rtems/score/cpuopts-tmp.h | sed -e '/.*PACKAGE.*/d' >>$@ - @echo >>$@ - @echo "#endif" >>$@ - -all-local: $(PREINSTALL_FILES) - -include $(top_srcdir)/automake/local.am diff --git a/c/src/exec/score/include/rtems/.cvsignore b/c/src/exec/score/include/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/include/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/include/rtems/debug.h b/c/src/exec/score/include/rtems/debug.h deleted file mode 100644 index 1b142be59f..0000000000 --- a/c/src/exec/score/include/rtems/debug.h +++ /dev/null @@ -1,97 +0,0 @@ -/* debug.h - * - * This include file contains the information pertaining to the debug - * support within RTEMS. It is currently cast in the form of a - * Manager since it is externally accessible. - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_DEBUG_h -#define __RTEMS_DEBUG_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The following type is used to manage the debug mask. - */ - -typedef unsigned32 rtems_debug_control; - -/* - * These constants represent various classes of debugging. - */ - -#define RTEMS_DEBUG_ALL_MASK 0xffffffff -#define RTEMS_DEBUG_REGION 0x00000001 - -/* - * This variable contains the current debug level. - */ - -SCORE_EXTERN rtems_debug_control _Debug_Level; - -/* - * _Debug_Manager_initialization - * - * DESCRIPTION: - * - * This routine performs the initialization necessary for this manager. - */ - -void _Debug_Manager_initialization( void ); - -/* - * rtems_debug_enable - * - * DESCRIPTION: - * - * This routine enables the specified types of debug checks. - */ - -void rtems_debug_enable ( - rtems_debug_control to_be_enabled -); - -/* - * rtems_debug_disable - * - * DESCRIPTION: - * - * This routine disables the specified types of debug checks. - */ - -void rtems_debug_disable ( - rtems_debug_control to_be_disabled -); - -/* - * - * _Debug_Is_enabled - * - * DESCRIPTION: - * - * This routine returns TRUE if the requested debug level is - * enabled, and FALSE otherwise. - */ - -boolean _Debug_Is_enabled( - rtems_debug_control level -); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/.cvsignore b/c/src/exec/score/include/rtems/score/.cvsignore deleted file mode 100644 index 64ac014acb..0000000000 --- a/c/src/exec/score/include/rtems/score/.cvsignore +++ /dev/null @@ -1,8 +0,0 @@ -Makefile -Makefile.in -stamp-h -stamp-h.in -cpuopts.h -cpuopts.h.in -cpuopts-tmp.h -cpuopts-tmp.h.in diff --git a/c/src/exec/score/include/rtems/score/address.h b/c/src/exec/score/include/rtems/score/address.h deleted file mode 100644 index edb04729dc..0000000000 --- a/c/src/exec/score/include/rtems/score/address.h +++ /dev/null @@ -1,30 +0,0 @@ -/* address.h - * - * This include file contains the information required to manipulate - * physical addresses. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_ADDRESSES_h -#define __RTEMS_ADDRESSES_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/address.inl> - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/apiext.h b/c/src/exec/score/include/rtems/score/apiext.h deleted file mode 100644 index 1622f504da..0000000000 --- a/c/src/exec/score/include/rtems/score/apiext.h +++ /dev/null @@ -1,101 +0,0 @@ -/* apiext.h - * - * This is the API Extensions Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -#ifndef __API_EXTENSIONS_h -#define __API_EXTENSIONS_h - -#include <rtems/score/chain.h> -#include <rtems/score/thread.h> - -/* - * The control structure which defines the points at which an API - * can add an extension to the system initialization thread. - */ - -typedef void (*API_extensions_Predriver_hook)(void); -typedef void (*API_extensions_Postdriver_hook)(void); -typedef void (*API_extensions_Postswitch_hook)( - Thread_Control * - ); - - -typedef struct { - Chain_Node Node; - API_extensions_Predriver_hook predriver_hook; - API_extensions_Postdriver_hook postdriver_hook; - API_extensions_Postswitch_hook postswitch_hook; -} API_extensions_Control; - -/* - * This is the list of API extensions to the system initialization. - */ - -SCORE_EXTERN Chain_Control _API_extensions_List; - -/* - * _API_extensions_Initialization - * - * DESCRIPTION: - * - * This routine initializes the API extension handler. - * - */ - -void _API_extensions_Initialization( void ); - -/* - * _API_extensions_Add - * - * DESCRIPTION: - * - * XXX - */ - -void _API_extensions_Add( - API_extensions_Control *the_extension -); - -/* - * _API_extensions_Run_predriver - * - * DESCRIPTION: - * - * XXX - */ - -void _API_extensions_Run_predriver( void ); - -/* - * _API_extensions_Run_postdriver - * - * DESCRIPTION: - * - * XXX - */ - -void _API_extensions_Run_postdriver( void ); - -/* - * _API_extensions_Run_postswitch - * - * DESCRIPTION: - * - * XXX - */ - -void _API_extensions_Run_postswitch( void ); - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/apimutex.h b/c/src/exec/score/include/rtems/score/apimutex.h deleted file mode 100644 index 517032761f..0000000000 --- a/c/src/exec/score/include/rtems/score/apimutex.h +++ /dev/null @@ -1,154 +0,0 @@ -/* apimutex.h - * - * This include file contains all the constants and structures associated - * with the API Mutex Handler. This handler is used by API level - * routines to manage mutual exclusion. - * - * COPYRIGHT (c) 1989-2002. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __API_MUTEX_h -#define __API_MUTEX_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/coremutex.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> - -/* - * The following defines the control block used to manage each mutex. - */ - -typedef struct { - Objects_Control Object; - CORE_mutex_Control Mutex; -} API_Mutex_Control; - -/* - * The following defines the information control block used to manage - * this class of objects. - */ - -SCORE_EXTERN Objects_Information _API_Mutex_Information; - -/* - * _API_Mutex_Initialization - * - * DESCRIPTION: - * - * This routine performs the initialization necessary for this handler. - */ - -#if defined(RTEMS_MULTIPROCESSING) -#define _API_Mutex_Initialization( _maximum_mutexes ) \ - _Objects_Initialize_information( \ - &_API_Mutex_Information, \ - OBJECTS_INTERNAL_API, \ - OBJECTS_INTERNAL_MUTEXES, \ - _maximum_mutexes, \ - sizeof( API_Mutex_Control ), \ - FALSE, \ - 0, \ - FALSE, \ - NULL \ - ); -#else -#define _API_Mutex_Initialization( _maximum_mutexes ) \ - _Objects_Initialize_information( \ - &_API_Mutex_Information, \ - OBJECTS_INTERNAL_API, \ - OBJECTS_INTERNAL_MUTEXES, \ - _maximum_mutexes, \ - sizeof( API_Mutex_Control ), \ - FALSE, \ - 0 \ - ); -#endif - -/* - * _API_Mutex_Allocate - * - * DESCRIPTION: - * - * This routine allocates an api mutex from the inactive set. - */ - -#define _API_Mutex_Allocate( _the_mutex ) \ - do { \ - CORE_mutex_Attributes attr = \ - { CORE_MUTEX_NESTING_IS_ERROR, FALSE, \ - CORE_MUTEX_DISCIPLINES_PRIORITY_INHERIT, 0 }; \ - (_the_mutex) = (API_Mutex_Control *) \ - _Objects_Allocate( &_API_Mutex_Information ); \ - _CORE_mutex_Initialize( \ - &(_the_mutex)->Mutex, &attr, CORE_MUTEX_UNLOCKED ); \ - } while (0) - -/* - * _API_Mutex_Lock - * - * DESCRIPTION: - * - * This routine acquires the specified api mutex. - */ - -#define _API_Mutex_Lock( _the_mutex ) \ - do { \ - ISR_Level _level; \ - _ISR_Disable( _level ); \ - _CORE_mutex_Seize( \ - &(_the_mutex)->Mutex, (_the_mutex)->Object.id, TRUE, 0, (_level) ); \ - } while (0) - -/* - * _API_Mutex_Unlock - * - * DESCRIPTION: - * - * This routine releases the specified api mutex. - */ - -#define _API_Mutex_Unlock( _the_mutex ) \ - do { \ - _Thread_Disable_dispatch(); \ - _CORE_mutex_Surrender( \ - &(_the_mutex)->Mutex, (_the_mutex)->Object.id, NULL ); \ - _Thread_Enable_dispatch(); \ - } while (0); - -/*XXX when the APIs all use this for allocation and deallocation - *XXX protection, then they should be renamed and probably moved - */ - -SCORE_EXTERN API_Mutex_Control *_RTEMS_Allocator_Mutex; - -#define _RTEMS_Lock_allocator() \ - _API_Mutex_Lock( _RTEMS_Allocator_Mutex ) - -#define _RTEMS_Unlock_allocator() \ - _API_Mutex_Unlock( _RTEMS_Allocator_Mutex ) - -/* - * There are no inlines for this handler. - */ - -#ifndef __RTEMS_APPLICATION__ -/* #include <rtems/score/apimutex.inl> */ -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/bitfield.h b/c/src/exec/score/include/rtems/score/bitfield.h deleted file mode 100644 index 05c0daeb5b..0000000000 --- a/c/src/exec/score/include/rtems/score/bitfield.h +++ /dev/null @@ -1,97 +0,0 @@ -/* bitfield.h - * - * This include file contains all bit field manipulation routines. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_BITFIELD_h -#define __RTEMS_BITFIELD_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * _Bitfield_Find_first_bit - * - * DESCRIPTION: - * - * This routine returns the bit_number of the first bit set - * in the specified value. The correspondence between bit_number - * and actual bit position is processor dependent. The search for - * the first bit set may run from most to least significant bit - * or vice-versa. - * - * NOTE: - * - * This routine is used when the executing thread is removed - * from the ready state and, as a result, its performance has a - * significant impact on the performance of the executive as a whole. - */ - -#if ( CPU_USE_GENERIC_BITFIELD_DATA == TRUE ) - -#ifndef SCORE_INIT -extern const unsigned char __log2table[256]; -#else -const unsigned char __log2table[256] = { - 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; -#endif - -#endif - -#if ( CPU_USE_GENERIC_BITFIELD_CODE == FALSE ) - -#define _Bitfield_Find_first_bit( _value, _bit_number ) \ - _CPU_Bitfield_Find_first_bit( _value, _bit_number ) - -#else - -/* - * The following must be a macro because if a CPU specific version - * is used it will most likely use inline assembly. - */ - -#define _Bitfield_Find_first_bit( _value, _bit_number ) \ - { \ - register unsigned32 __value = (unsigned32) (_value); \ - register const unsigned char *__p = __log2table; \ - \ - if ( __value < 0x100 ) \ - (_bit_number) = __p[ __value ] + 8; \ - else \ - (_bit_number) = __p[ __value >> 8 ]; \ - } - -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/chain.h b/c/src/exec/score/include/rtems/score/chain.h deleted file mode 100644 index 469979c68e..0000000000 --- a/c/src/exec/score/include/rtems/score/chain.h +++ /dev/null @@ -1,167 +0,0 @@ -/* chain.h - * - * This include file contains all the constants and structures associated - * with the Doubly Linked Chain Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_CHAIN_h -#define __RTEMS_CHAIN_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/address.h> - -/* - * This is used to manage each element (node) which is placed - * on a chain. - * - * NOTE: Typically, a more complicated structure will use the - * chain package. The more complicated structure will - * include a chain node as the first element in its - * control structure. It will then call the chain package - * with a pointer to that node element. The node pointer - * and the higher level structure start at the same address - * so the user can cast the pointers back and forth. - * - */ - -typedef struct Chain_Node_struct Chain_Node; - -struct Chain_Node_struct { - Chain_Node *next; - Chain_Node *previous; -}; - -/* - * This is used to manage a chain. A chain consists of a doubly - * linked list of zero or more nodes. - * - * NOTE: This implementation does not require special checks for - * manipulating the first and last elements on the chain. - * To accomplish this the chain control structure is - * treated as two overlapping chain nodes. The permanent - * head of the chain overlays a node structure on the - * first and permanent_null fields. The permanent tail - * of the chain overlays a node structure on the - * permanent_null and last elements of the structure. - * - */ - -typedef struct { - Chain_Node *first; - Chain_Node *permanent_null; - Chain_Node *last; -} Chain_Control; - -/* - * _Chain_Initialize - * - * DESCRIPTION: - * - * This routine initializes the_chain structure to manage the - * contiguous array of number_nodes nodes which starts at - * starting_address. Each node is of node_size bytes. - * - */ - -void _Chain_Initialize( - Chain_Control *the_chain, - void *starting_address, - unsigned32 number_nodes, - unsigned32 node_size -); - -/* - * _Chain_Get_first_unprotected - */ - -#ifndef USE_INLINES -Chain_Node *_Chain_Get_first_unprotected( - Chain_Control *the_chain -); -#endif - -/* - * _Chain_Extract - * - * DESCRIPTION: - * - * This routine extracts the_node from the chain on which it resides. - * It disables interrupts to insure the atomicity of the - * extract operation. - * - */ - -void _Chain_Extract( - Chain_Node *the_node -); - -/* - * _Chain_Get - * - * DESCRIPTION: - * - * This function removes the first node from the_chain and returns - * a pointer to that node. If the_chain is empty, then NULL is returned. - * It disables interrupts to insure the atomicity of the - * get operation. - * - */ - -Chain_Node *_Chain_Get( - Chain_Control *the_chain -); - -/* - * _Chain_Insert - * - * DESCRIPTION: - * - * This routine inserts the_node on a chain immediately following - * after_node. It disables interrupts to insure the atomicity - * of the extract operation. - * - */ - -void _Chain_Insert( - Chain_Node *after_node, - Chain_Node *the_node -); - -/* - * _Chain_Append - * - * DESCRIPTION: - * - * This routine appends the_node onto the end of the_chain. - * It disables interrupts to insure the atomicity of the - * append operation. - * - */ - -void _Chain_Append( - Chain_Control *the_chain, - Chain_Node *the_node -); - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/chain.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/context.h b/c/src/exec/score/include/rtems/score/context.h deleted file mode 100644 index acfaeccef7..0000000000 --- a/c/src/exec/score/include/rtems/score/context.h +++ /dev/null @@ -1,133 +0,0 @@ -/* context.h - * - * This include file contains all information about a context. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_CONTEXT_h -#define __RTEMS_CONTEXT_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/cpu.h> - -/* - * The following constant defines the number of bytes required - * to store a full floating point context. - */ - -#define CONTEXT_FP_SIZE CPU_CONTEXT_FP_SIZE - -/* - * The following variable is set to TRUE when a reschedule operation - * has determined that the processor should be taken away from the - * currently executing thread and given to the heir thread. - */ - -SCORE_EXTERN volatile boolean _Context_Switch_necessary; - -/* - * _Context_Initialize - * - * DESCRIPTION: - * - * This routine initializes THE_CONTEXT such that the stack - * pointer, interrupt level, and entry point are correct for the - * thread's initial state. - */ - -#define \ - _Context_Initialize( _the_context, _stack, _size, _isr, _entry, _is_fp ) \ - _CPU_Context_Initialize( _the_context, _stack, _size, _isr, _entry, _is_fp ) - -/* - * _Context_Switch - * - * DESCRIPTION: - * - * This routine saves the current context into the EXECUTING - * context record and restores the context specified by HEIR. - */ - -#define _Context_Switch( _executing, _heir ) \ - _CPU_Context_switch( _executing, _heir ) - -/* - * _Context_Restart_self - * - * DESCRIPTION: - * - * This routine restarts the calling thread by restoring its initial - * stack pointer and returning to the thread's entry point. - */ - -#define _Context_Restart_self( _the_context ) \ - _CPU_Context_Restart_self( _the_context ) - -/* - * _Context_Fp_start - * - * DESCRIPTION: - * - * This function returns the starting address of the floating - * point context save area. It is assumed that the are reserved - * for the floating point save area is large enough. - */ - -#define _Context_Fp_start( _base, _offset ) \ - _CPU_Context_Fp_start( (_base), (_offset) ) - -/* - * _Context_Initialize_fp - * - * DESCRIPTION: - * - * This routine initializes the floating point context save - * area to contain an initial known state. - */ - -#define _Context_Initialize_fp( _fp_area ) \ - _CPU_Context_Initialize_fp( _fp_area ) - -/* - * _Context_Restore_fp - * - * DESCRIPTION: - * - * This routine restores the floating point context contained - * in the FP_CONTEXT area. It is assumed that the current - * floating point context has been saved by a previous invocation - * of SAVE_FP. - */ - -#define _Context_Restore_fp( _fp ) \ - _CPU_Context_restore_fp( _fp ) - -/* - * _Context_Save_fp - * - * DESCRIPTION: - * - * This routine saves the current floating point context - * in the FP_CONTEXT area. - */ - -#define _Context_Save_fp( _fp ) \ - _CPU_Context_save_fp( _fp ) - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/copyrt.h b/c/src/exec/score/include/rtems/score/copyrt.h deleted file mode 100644 index d7e1c3c474..0000000000 --- a/c/src/exec/score/include/rtems/score/copyrt.h +++ /dev/null @@ -1,40 +0,0 @@ -/* copyrt.h - * - * This include file contains the copyright notice for RTEMS - * which is included in every binary copy of the executive. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_COPYRIGHT_h -#define __RTEMS_COPYRIGHT_h - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef SCORE_INIT - -const char _Copyright_Notice[] = -"COPYRIGHT (c) 1989-1999.\n\ -On-Line Applications Research Corporation (OAR).\n"; - -#else - -extern const char _Copyright_Notice[]; - -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/coremsg.h b/c/src/exec/score/include/rtems/score/coremsg.h deleted file mode 100644 index c90ad2fcf0..0000000000 --- a/c/src/exec/score/include/rtems/score/coremsg.h +++ /dev/null @@ -1,300 +0,0 @@ -/* coremsg.h - * - * This include file contains all the constants and structures associated - * with the Message queue Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_CORE_MESSAGE_QUEUE_h -#define __RTEMS_CORE_MESSAGE_QUEUE_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <limits.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/priority.h> -#include <rtems/score/watchdog.h> - -/* - * The following type defines the callout which the API provides - * to support global/multiprocessor operations on message_queues. - */ - -typedef void ( *CORE_message_queue_API_mp_support_callout )( - Thread_Control *, - Objects_Id - ); - -/* - * The following defines the data types needed to manipulate - * the contents of message buffers. - * - * NOTE: The buffer field is normally longer than a single unsigned32. - * but since messages are variable length we just make a ptr to 1. - */ - -typedef struct { - unsigned32 size; - unsigned32 buffer[1]; -} CORE_message_queue_Buffer; - -/* - * The following records define the organization of a message - * buffer. - */ - -typedef struct { - Chain_Node Node; - int priority; - CORE_message_queue_Buffer Contents; -} CORE_message_queue_Buffer_control; - -/* - * Blocking disciplines for a message_queue. - */ - -typedef enum { - CORE_MESSAGE_QUEUE_DISCIPLINES_FIFO, - CORE_MESSAGE_QUEUE_DISCIPLINES_PRIORITY -} CORE_message_queue_Disciplines; - -/* - * The following enumerated type details the modes in which a message - * may be submitted to a message queue. The message may be posted - * in a send or urgent fashion. - * - * NOTE: All other values are message priorities. Numerically smaller - * priorities indicate higher priority messages. - * - */ - -#define CORE_MESSAGE_QUEUE_SEND_REQUEST INT_MAX -#define CORE_MESSAGE_QUEUE_URGENT_REQUEST INT_MIN - -typedef int CORE_message_queue_Submit_types; - -/* - * Core Message queue handler return statuses. - */ - -typedef enum { - CORE_MESSAGE_QUEUE_STATUS_SUCCESSFUL, - CORE_MESSAGE_QUEUE_STATUS_INVALID_SIZE, - CORE_MESSAGE_QUEUE_STATUS_TOO_MANY, - CORE_MESSAGE_QUEUE_STATUS_UNSATISFIED, - CORE_MESSAGE_QUEUE_STATUS_UNSATISFIED_NOWAIT, - CORE_MESSAGE_QUEUE_STATUS_WAS_DELETED, - CORE_MESSAGE_QUEUE_STATUS_TIMEOUT, - CORE_MESSAGE_QUEUE_STATUS_UNSATISFIED_WAIT -} CORE_message_queue_Status; - -/* - * The following defines the control block used to manage the - * attributes of each message queue. - */ - -typedef struct { - CORE_message_queue_Disciplines discipline; -} CORE_message_queue_Attributes; - -/* - * The following defines the type for a Notification handler. A notification - * handler is invoked when the message queue makes a 0->1 transition on - * pending messages. - */ - -typedef void (*CORE_message_queue_Notify_Handler)( void * ); - -/* - * The following defines the control block used to manage each - * counting message_queue. - */ - -typedef struct { - Thread_queue_Control Wait_queue; - CORE_message_queue_Attributes Attributes; - unsigned32 maximum_pending_messages; - unsigned32 number_of_pending_messages; - unsigned32 maximum_message_size; - Chain_Control Pending_messages; - CORE_message_queue_Buffer *message_buffers; - CORE_message_queue_Notify_Handler notify_handler; - void *notify_argument; - Chain_Control Inactive_messages; -} CORE_message_queue_Control; - -/* - * _CORE_message_queue_Initialize - * - * DESCRIPTION: - * - * This routine initializes the message_queue based on the parameters passed. - */ - -boolean _CORE_message_queue_Initialize( - CORE_message_queue_Control *the_message_queue, - CORE_message_queue_Attributes *the_message_queue_attributes, - unsigned32 maximum_pending_messages, - unsigned32 maximum_message_size -); - -/* - * _CORE_message_queue_Close - * - * DESCRIPTION: - * - * This function closes a message by returning all allocated space and - * flushing the message_queue's task wait queue. - */ - -void _CORE_message_queue_Close( - CORE_message_queue_Control *the_message_queue, - Thread_queue_Flush_callout remote_extract_callout, - unsigned32 status -); - -/* - * _CORE_message_queue_Flush - * - * DESCRIPTION: - * - * This function flushes the message_queue's pending message queue. The - * number of messages flushed from the queue is returned. - * - */ - -unsigned32 _CORE_message_queue_Flush( - CORE_message_queue_Control *the_message_queue -); - -/* - * _CORE_message_queue_Flush_support - * - * DESCRIPTION: - * - * This routine flushes all outstanding messages and returns - * them to the inactive message chain. - */ - -unsigned32 _CORE_message_queue_Flush_support( - CORE_message_queue_Control *the_message_queue -); - -/* - * _CORE_message_queue_Flush_waiting_threads - * - * DESCRIPTION: - * - * This function flushes the threads which are blocked on this - * message_queue's pending message queue. They are unblocked whether - * blocked sending or receiving. - */ - -void _CORE_message_queue_Flush_waiting_threads( - CORE_message_queue_Control *the_message_queue -); - -/* - * _CORE_message_queue_Broadcast - * - * DESCRIPTION: - * - * This function sends a message for every thread waiting on the queue and - * returns the number of threads made ready by the message. - * - */ - -CORE_message_queue_Status _CORE_message_queue_Broadcast( - CORE_message_queue_Control *the_message_queue, - void *buffer, - unsigned32 size, - Objects_Id id, - CORE_message_queue_API_mp_support_callout api_message_queue_mp_support, - unsigned32 *count -); - -/* - * _CORE_message_queue_Submit - * - * DESCRIPTION: - * - * This routine implements the send and urgent message functions. It - * processes a message that is to be submitted to the designated - * message queue. The message will either be processed as a - * send message which it will be inserted at the rear of the queue - * or it will be processed as an urgent message which will be inserted - * at the front of the queue. - * - */ - -CORE_message_queue_Status _CORE_message_queue_Submit( - CORE_message_queue_Control *the_message_queue, - void *buffer, - unsigned32 size, - Objects_Id id, - CORE_message_queue_API_mp_support_callout api_message_queue_mp_support, - CORE_message_queue_Submit_types submit_type, - boolean wait, - Watchdog_Interval timeout -); - -/* - * _CORE_message_queue_Seize - * - * DESCRIPTION: - * - * This kernel routine dequeues a message, copies the message buffer to - * a given destination buffer, and frees the message buffer to the - * inactive message pool. The thread will be blocked if wait is TRUE, - * otherwise an error will be given to the thread if no messages are available. - * - * NOTE: Returns message priority via return are in TCB. - */ - -void _CORE_message_queue_Seize( - CORE_message_queue_Control *the_message_queue, - Objects_Id id, - void *buffer, - unsigned32 *size, - boolean wait, - Watchdog_Interval timeout -); - -/* - * _CORE_message_queue_Insert_message - * - * DESCRIPTION: - * - * This kernel routine inserts the specified message into the - * message queue. It is assumed that the message has been filled - * in before this routine is called. - */ - -void _CORE_message_queue_Insert_message( - CORE_message_queue_Control *the_message_queue, - CORE_message_queue_Buffer_control *the_message, - CORE_message_queue_Submit_types submit_type -); - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/coremsg.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ - diff --git a/c/src/exec/score/include/rtems/score/coremutex.h b/c/src/exec/score/include/rtems/score/coremutex.h deleted file mode 100644 index 2eac6d489a..0000000000 --- a/c/src/exec/score/include/rtems/score/coremutex.h +++ /dev/null @@ -1,225 +0,0 @@ -/* mutex.h - * - * This include file contains all the constants and structures associated - * with the Mutex Handler. A mutex is an enhanced version of the standard - * Dijkstra binary semaphore used to provide synchronization and mutual - * exclusion capabilities. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_CORE_MUTEX_h -#define __RTEMS_CORE_MUTEX_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/priority.h> -#include <rtems/score/watchdog.h> - -/* - * The following type defines the callout which the API provides - * to support global/multiprocessor operations on mutexes. - */ - -typedef void ( *CORE_mutex_API_mp_support_callout )( - Thread_Control *, - Objects_Id - ); - -/* - * Blocking disciplines for a mutex. - */ - -typedef enum { - CORE_MUTEX_DISCIPLINES_FIFO, - CORE_MUTEX_DISCIPLINES_PRIORITY, - CORE_MUTEX_DISCIPLINES_PRIORITY_INHERIT, - CORE_MUTEX_DISCIPLINES_PRIORITY_CEILING -} CORE_mutex_Disciplines; - -/* - * Mutex handler return statuses. - */ - -typedef enum { - CORE_MUTEX_STATUS_SUCCESSFUL, - CORE_MUTEX_STATUS_UNSATISFIED_NOWAIT, - CORE_MUTEX_STATUS_NESTING_NOT_ALLOWED, - CORE_MUTEX_STATUS_NOT_OWNER_OF_RESOURCE, - CORE_MUTEX_WAS_DELETED, - CORE_MUTEX_TIMEOUT, - CORE_MUTEX_STATUS_CEILING_VIOLATED -} CORE_mutex_Status; - -/* - * Mutex lock nesting behavior - * - * CORE_MUTEX_NESTING_ACQUIRES: - * This sequence has no blocking or errors: - * lock(m) - * lock(m) - * unlock(m) - * unlock(m) - * - * CORE_MUTEX_NESTING_IS_ERROR - * This sequence returns an error at the indicated point: - * lock(m) - * lock(m) - already locked error - * unlock(m) - * - * CORE_MUTEX_NESTING_BLOCKS - * This sequence performs as indicated: - * lock(m) - * lock(m) - deadlocks or timeouts - * unlock(m) - releases - */ - -typedef enum { - CORE_MUTEX_NESTING_ACQUIRES, - CORE_MUTEX_NESTING_IS_ERROR, - CORE_MUTEX_NESTING_BLOCKS -} CORE_mutex_Nesting_behaviors; - -/* - * Locked and unlocked values - */ - -#define CORE_MUTEX_UNLOCKED 1 -#define CORE_MUTEX_LOCKED 0 - -/* - * The following defines the control block used to manage the - * attributes of each mutex. - */ - -typedef struct { - CORE_mutex_Nesting_behaviors lock_nesting_behavior; - boolean only_owner_release; - CORE_mutex_Disciplines discipline; - Priority_Control priority_ceiling; -} CORE_mutex_Attributes; - -/* - * The following defines the control block used to manage each mutex. - */ - -typedef struct { - Thread_queue_Control Wait_queue; - CORE_mutex_Attributes Attributes; - unsigned32 lock; - unsigned32 nest_count; - unsigned32 blocked_count; - Thread_Control *holder; - Objects_Id holder_id; -} CORE_mutex_Control; - -/* - * _CORE_mutex_Initialize - * - * DESCRIPTION: - * - * This routine initializes the mutex based on the parameters passed. - */ - -void _CORE_mutex_Initialize( - CORE_mutex_Control *the_mutex, - CORE_mutex_Attributes *the_mutex_attributes, - unsigned32 initial_lock -); - -/* - * _CORE_mutex_Seize - * - * DESCRIPTION: - * - * This routine attempts to receive a unit from the_mutex. - * If a unit is available or if the wait flag is FALSE, then the routine - * returns. Otherwise, the calling task is blocked until a unit becomes - * available. - * - * NOTE: For performance reasons, this routine is implemented as - * a macro that uses two support routines. - */ - -#ifndef __RTEMS_APPLICATION__ -RTEMS_INLINE_ROUTINE int _CORE_mutex_Seize_interrupt_trylock( - CORE_mutex_Control *the_mutex, - ISR_Level *level_p -); - -void _CORE_mutex_Seize_interrupt_blocking( - CORE_mutex_Control *the_mutex, - Watchdog_Interval timeout -); - -#define _CORE_mutex_Seize( \ - _the_mutex, _id, _wait, _timeout, _level ) \ - do { \ - if ( _CORE_mutex_Seize_interrupt_trylock( _the_mutex, &_level ) ) { \ - if ( !_wait ) { \ - _ISR_Enable( _level ); \ - _Thread_Executing->Wait.return_code = \ - CORE_MUTEX_STATUS_UNSATISFIED_NOWAIT; \ - } else { \ - _Thread_queue_Enter_critical_section( &(_the_mutex)->Wait_queue ); \ - _Thread_Executing->Wait.queue = &(_the_mutex)->Wait_queue; \ - _Thread_Executing->Wait.id = _id; \ - _Thread_Disable_dispatch(); \ - _ISR_Enable( _level ); \ - _CORE_mutex_Seize_interrupt_blocking( _the_mutex, _timeout ); \ - } \ - } \ - } while (0) - -/* - * _CORE_mutex_Surrender - * - * DESCRIPTION: - * - * This routine frees a unit to the mutex. If a task was blocked waiting for - * a unit from this mutex, then that task will be readied and the unit - * given to that task. Otherwise, the unit will be returned to the mutex. - */ - -CORE_mutex_Status _CORE_mutex_Surrender( - CORE_mutex_Control *the_mutex, - Objects_Id id, - CORE_mutex_API_mp_support_callout api_mutex_mp_support -); - -/* - * _CORE_mutex_Flush - * - * DESCRIPTION: - * - * This routine assists in the deletion of a mutex by flushing the associated - * wait queue. - */ - -void _CORE_mutex_Flush( - CORE_mutex_Control *the_mutex, - Thread_queue_Flush_callout remote_extract_callout, - unsigned32 status -); - -#include <rtems/score/coremutex.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ - diff --git a/c/src/exec/score/include/rtems/score/coresem.h b/c/src/exec/score/include/rtems/score/coresem.h deleted file mode 100644 index 9d4c4c4c50..0000000000 --- a/c/src/exec/score/include/rtems/score/coresem.h +++ /dev/null @@ -1,155 +0,0 @@ -/* core_sem.h - * - * This include file contains all the constants and structures associated - * with the Counting Semaphore Handler. A counting semaphore is the - * standard Dijkstra binary semaphore used to provide synchronization - * and mutual exclusion capabilities. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_CORE_COUNTING_SEMAPHORE_h -#define __RTEMS_CORE_COUNTING_SEMAPHORE_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/priority.h> -#include <rtems/score/watchdog.h> - -/* - * The following type defines the callout which the API provides - * to support global/multiprocessor operations on semaphores. - */ - -typedef void ( *CORE_semaphore_API_mp_support_callout )( - Thread_Control *, - Objects_Id - ); - -/* - * Blocking disciplines for a semaphore. - */ - -typedef enum { - CORE_SEMAPHORE_DISCIPLINES_FIFO, - CORE_SEMAPHORE_DISCIPLINES_PRIORITY -} CORE_semaphore_Disciplines; - -/* - * Core Semaphore handler return statuses. - */ - -typedef enum { - CORE_SEMAPHORE_STATUS_SUCCESSFUL, - CORE_SEMAPHORE_STATUS_UNSATISFIED_NOWAIT, - CORE_SEMAPHORE_WAS_DELETED, - CORE_SEMAPHORE_TIMEOUT, - CORE_SEMAPHORE_MAXIMUM_COUNT_EXCEEDED -} CORE_semaphore_Status; - -/* - * The following defines the control block used to manage the - * attributes of each semaphore. - */ - -typedef struct { - unsigned32 maximum_count; - CORE_semaphore_Disciplines discipline; -} CORE_semaphore_Attributes; - -/* - * The following defines the control block used to manage each - * counting semaphore. - */ - -typedef struct { - Thread_queue_Control Wait_queue; - CORE_semaphore_Attributes Attributes; - unsigned32 count; -} CORE_semaphore_Control; - -/* - * _CORE_semaphore_Initialize - * - * DESCRIPTION: - * - * This routine initializes the semaphore based on the parameters passed. - */ - -void _CORE_semaphore_Initialize( - CORE_semaphore_Control *the_semaphore, - CORE_semaphore_Attributes *the_semaphore_attributes, - unsigned32 initial_value -); - -/* - * _CORE_semaphore_Seize - * - * DESCRIPTION: - * - * This routine attempts to receive a unit from the_semaphore. - * If a unit is available or if the wait flag is FALSE, then the routine - * returns. Otherwise, the calling task is blocked until a unit becomes - * available. - */ - -void _CORE_semaphore_Seize( - CORE_semaphore_Control *the_semaphore, - Objects_Id id, - boolean wait, - Watchdog_Interval timeout -); - -/* - * _CORE_semaphore_Surrender - * - * DESCRIPTION: - * - * This routine frees a unit to the semaphore. If a task was blocked waiting - * for a unit from this semaphore, then that task will be readied and the unit - * given to that task. Otherwise, the unit will be returned to the semaphore. - */ - -CORE_semaphore_Status _CORE_semaphore_Surrender( - CORE_semaphore_Control *the_semaphore, - Objects_Id id, - CORE_semaphore_API_mp_support_callout api_semaphore_mp_support -); - -/* - * _CORE_semaphore_Flush - * - * DESCRIPTION: - * - * This routine assists in the deletion of a semaphore by flushing the - * associated wait queue. - */ - -void _CORE_semaphore_Flush( - CORE_semaphore_Control *the_semaphore, - Thread_queue_Flush_callout remote_extract_callout, - unsigned32 status -); - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/coresem.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ - diff --git a/c/src/exec/score/include/rtems/score/heap.h b/c/src/exec/score/include/rtems/score/heap.h deleted file mode 100644 index 10e8cd260f..0000000000 --- a/c/src/exec/score/include/rtems/score/heap.h +++ /dev/null @@ -1,269 +0,0 @@ -/* heap.h - * - * This include file contains the information pertaining to the Heap - * Handler. A heap is a doubly linked list of variable size - * blocks which are allocated using the first fit method. Garbage - * collection is performed each time a block is returned to the heap by - * coalescing neighbor blocks. Control information for both allocated - * and unallocated blocks is contained in the heap space. A heap header - * contains control information for the heap. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_HEAP_h -#define __RTEMS_HEAP_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Status codes for heap_extend - */ - -typedef enum { - HEAP_EXTEND_SUCCESSFUL, - HEAP_EXTEND_ERROR, - HEAP_EXTEND_NOT_IMPLEMENTED -} Heap_Extend_status; - -/* - * Status codes for _Heap_Get_information - */ - -typedef enum { - HEAP_GET_INFORMATION_SUCCESSFUL = 0, - HEAP_GET_INFORMATION_SYSTEM_STATE_ERROR, - HEAP_GET_INFORMATION_BLOCK_ERROR -} Heap_Get_information_status; - -/* - * Information block returned by _Heap_Get_information - */ - -typedef struct { - unsigned32 free_blocks; - unsigned32 free_size; - unsigned32 used_blocks; - unsigned32 used_size; -} Heap_Information_block; - -/* - * Constants used in the size/used field of each heap block to - * indicate when a block is free or in use. - */ - -#define HEAP_BLOCK_USED 1 /* indicates block is in use */ -#define HEAP_BLOCK_FREE 0 /* indicates block is free */ - -/* - * The size/used field value for the dummy front and back flags. - */ - -#define HEAP_DUMMY_FLAG (0 + HEAP_BLOCK_USED) - -/* - * The following constants reflect various requirements of the - * heap data structures which impact the management of a heap. - * - * NOTE: Because free block overhead is greater than used block - * overhead AND a portion of the allocated space is from - * the extra free block overhead, the absolute lower bound - * of the minimum fragment size is equal to the size of - * the free block overhead. - */ - -#define HEAP_OVERHEAD \ - (sizeof( unsigned32 ) * 2) /* size dummy first and last blocks */ -#define HEAP_BLOCK_USED_OVERHEAD \ - (sizeof( void * ) * 2) /* num bytes overhead in used block */ -#define HEAP_MINIMUM_SIZE \ - (HEAP_OVERHEAD + sizeof (Heap_Block)) - /* min number of bytes the user may */ - /* specify for the heap size */ - -/* - * The following defines the data structure used to manage - * individual blocks in a heap. When the block is allocated, the - * next and previous fields are not used by the Heap Handler - * and thus the address returned for the block starts at - * the address of the next field. - * - * NOTE: The next and previous pointers are only valid when the - * block is free. Caution must be exercised to insure that - * allocated blocks are large enough to contain them and - * that they are not accidentally overwritten when the - * block is actually allocated. - */ - -typedef struct Heap_Block_struct Heap_Block; - -struct Heap_Block_struct { - unsigned32 back_flag; /* size and status of prev block */ - unsigned32 front_flag; /* size and status of block */ - Heap_Block *next; /* pointer to next block */ - Heap_Block *previous; /* pointer to previous block */ -}; - -/* - * The following defines the control block used to manage each heap. - * - * NOTE: - * - * This structure is layed out such that it can be used a a dummy - * first and last block on the free block chain. The extra padding - * insures the dummy last block is the correct size. - * - * The first Heap_Block starts at first while the second starts at - * final. This is effectively the same trick as is used in the Chain - * Handler. - */ - -typedef struct { - Heap_Block *start; /* first valid block address in heap */ - Heap_Block *final; /* last valid block address in heap */ - - Heap_Block *first; /* pointer to first block in heap */ - Heap_Block *permanent_null; /* always NULL pointer */ - Heap_Block *last; /* pointer to last block in heap */ - unsigned32 page_size; /* allocation unit */ - unsigned32 reserved; -} Heap_Control; - -/* - * _Heap_Initialize - * - * DESCRIPTION: - * - * This routine initializes the_heap record to manage the - * contiguous heap of size bytes which starts at starting_address. - * Blocks of memory are allocated from the heap in multiples of - * page_size byte units. - */ - -unsigned32 _Heap_Initialize( - Heap_Control *the_heap, - void *starting_address, - unsigned32 size, - unsigned32 page_size -); - -/* - * _Heap_Extend - * - * DESCRIPTION: - * - * This routine grows the_heap memory area using the size bytes which - * begin at starting_address. - */ - -Heap_Extend_status _Heap_Extend( - Heap_Control *the_heap, - void *starting_address, - unsigned32 size, - unsigned32 *amount_extended -); - -/* - * _Heap_Allocate - * - * DESCRIPTION: - * - * DESCRIPTION: - * - * This function attempts to allocate a block of size bytes from - * the_heap. If insufficient memory is free in the_heap to allocate - * a block of the requested size, then NULL is returned. - */ - -void *_Heap_Allocate( - Heap_Control *the_heap, - unsigned32 size -); - -/* - * _Heap_Size_of_user_area - * - * DESCRIPTION: - * - * This kernel routine sets size to the size of the given heap block. - * It returns TRUE if the starting_address is in the heap, and FALSE - * otherwise. - */ - -boolean _Heap_Size_of_user_area( - Heap_Control *the_heap, - void *starting_address, - unsigned32 *size -); - -/* - * _Heap_Free - * - * DESCRIPTION: - * - * This routine returns the block of memory which begins - * at starting_address to the_heap. Any coalescing which is - * possible with the freeing of this routine is performed. - */ - -boolean _Heap_Free( - Heap_Control *the_heap, - void *start_address -); - -/* - * _Heap_Walk - * - * DESCRIPTION: - * - * This routine walks the heap to verify its integrity. - */ - -void _Heap_Walk( - Heap_Control *the_heap, - int source, - boolean do_dump -); - -/*PAGE - * - * _Heap_Get_information - * - * This kernel routine walks the heap and tots up the free and allocated - * sizes. Derived from _Heap_Walk. - * - * Input parameters: - * the_heap - pointer to heap header - * the_info - pointer to information block - * - * Output parameters: - * *the_info - status information - * return 0=success, otherwise heap is corrupt. - */ - - -Heap_Get_information_status _Heap_Get_information( - Heap_Control *the_heap, - Heap_Information_block *the_info -); - - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/heap.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/interr.h b/c/src/exec/score/include/rtems/score/interr.h deleted file mode 100644 index 293957ec2b..0000000000 --- a/c/src/exec/score/include/rtems/score/interr.h +++ /dev/null @@ -1,96 +0,0 @@ -/* interr.h - * - * This include file contains constants and prototypes related - * to the Internal Error Handler. - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_INTERNAL_ERROR_h -#define __RTEMS_INTERNAL_ERROR_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This type lists the possible sources from which an error - * can be reported. - */ - -typedef enum { - INTERNAL_ERROR_CORE, - INTERNAL_ERROR_RTEMS_API, - INTERNAL_ERROR_POSIX_API, - INTERNAL_ERROR_ITRON_API -} Internal_errors_Source; - -/* - * A list of errors which are generated internally by the executive core. - */ - -typedef enum { - INTERNAL_ERROR_NO_CONFIGURATION_TABLE, - INTERNAL_ERROR_NO_CPU_TABLE, - INTERNAL_ERROR_INVALID_WORKSPACE_ADDRESS, - INTERNAL_ERROR_TOO_LITTLE_WORKSPACE, - INTERNAL_ERROR_WORKSPACE_ALLOCATION, - INTERNAL_ERROR_INTERRUPT_STACK_TOO_SMALL, - INTERNAL_ERROR_THREAD_EXITTED, - INTERNAL_ERROR_INCONSISTENT_MP_INFORMATION, - INTERNAL_ERROR_INVALID_NODE, - INTERNAL_ERROR_NO_MPCI, - INTERNAL_ERROR_BAD_PACKET, - INTERNAL_ERROR_OUT_OF_PACKETS, - INTERNAL_ERROR_OUT_OF_GLOBAL_OBJECTS, - INTERNAL_ERROR_OUT_OF_PROXIES, - INTERNAL_ERROR_INVALID_GLOBAL_ID, - INTERNAL_ERROR_BAD_STACK_HOOK, - INTERNAL_ERROR_BAD_ATTRIBUTES -} Internal_errors_Core_list; - -/* - * This type holds the fatal error information. - */ - -typedef struct { - Internal_errors_Source the_source; - boolean is_internal; - unsigned32 the_error; -} Internal_errors_Information; - -/* - * When a fatal error occurs, the error information is stored here. - */ - -SCORE_EXTERN Internal_errors_Information Internal_errors_What_happened; - -/* - * _Internal_error_Occurred - * - * DESCRIPTION: - * - * This routine is invoked when the application or the executive itself - * determines that a fatal error has occurred. - */ - -void volatile _Internal_error_Occurred( - Internal_errors_Source the_source, - boolean is_internal, - unsigned32 the_error -); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/isr.h b/c/src/exec/score/include/rtems/score/isr.h deleted file mode 100644 index 276e9dada5..0000000000 --- a/c/src/exec/score/include/rtems/score/isr.h +++ /dev/null @@ -1,248 +0,0 @@ -/* isr.h - * - * This include file contains all the constants and structures associated - * with the management of processor interrupt levels. This handler - * supports interrupt critical sections, vectoring of user interrupt - * handlers, nesting of interrupts, and manipulating interrupt levels. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __ISR_h -#define __ISR_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The following type defines the control block used to manage - * the interrupt level portion of the status register. - */ - -typedef unsigned32 ISR_Level; - -/* - * The following type defines the type used to manage the vectors. - */ - -typedef unsigned32 ISR_Vector_number; - -/* - * Return type for ISR Handler - */ - -typedef void ISR_Handler; - -/* - * Pointer to an ISR Handler - */ - -#if (CPU_ISR_PASSES_FRAME_POINTER == 1) -typedef ISR_Handler ( *ISR_Handler_entry )( - ISR_Vector_number, - CPU_Interrupt_frame * - ); -#else -typedef ISR_Handler ( *ISR_Handler_entry )( - ISR_Vector_number - ); -#endif -/* - * This constant promotes out the number of vectors truly supported by - * the current CPU being used. This is usually the number of distinct vectors - * the cpu can vector. - */ - -#define ISR_NUMBER_OF_VECTORS CPU_INTERRUPT_NUMBER_OF_VECTORS - -/* - * This constant promotes out the highest valid interrupt vector number. - */ - -#define ISR_INTERRUPT_MAXIMUM_VECTOR_NUMBER CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER - -/* - * The following is TRUE if signals have been sent to the currently - * executing thread by an ISR handler. - */ - -SCORE_EXTERN boolean _ISR_Signals_to_thread_executing; - -/* - * The following contains the interrupt service routine nest level. - * When this variable is zero, a thread is executing. - */ - -SCORE_EXTERN volatile unsigned32 _ISR_Nest_level; - -/* - * The following declares the Vector Table. Application - * interrupt service routines are vectored by the ISR Handler via this table. - */ - -SCORE_EXTERN ISR_Handler_entry *_ISR_Vector_table; - -/* - * _ISR_Handler_initialization - * - * DESCRIPTION: - * - * This routine performs the initialization necessary for this handler. - */ - -void _ISR_Handler_initialization ( void ); - -/* - * _ISR_Disable - * - * DESCRIPTION: - * - * This routine disables all interrupts so that a critical section - * of code can be executing without being interrupted. Upon return, - * the argument _level will contain the previous interrupt mask level. - */ - -#define _ISR_Disable( _level ) \ - _CPU_ISR_Disable( _level ) - -/* - * _ISR_Enable - * - * DESCRIPTION: - * - * This routine enables interrupts to the previous interrupt mask - * LEVEL. It is used at the end of a critical section of code to - * enable interrupts so they can be processed again. - */ - -#define _ISR_Enable( _level ) \ - _CPU_ISR_Enable( _level ) - -/* - * _ISR_Flash - * - * DESCRIPTION: - * - * This routine temporarily enables interrupts to the previous - * interrupt mask level and then disables all interrupts so that - * the caller can continue into the second part of a critical - * section. This routine is used to temporarily enable interrupts - * during a long critical section. It is used in long sections of - * critical code when a point is reached at which interrupts can - * be temporarily enabled. Deciding where to flash interrupts - * in a long critical section is often difficult and the point - * must be selected with care to insure that the critical section - * properly protects itself. - */ - -#define _ISR_Flash( _level ) \ - _CPU_ISR_Flash( _level ) - -/* - * _ISR_Install_vector - * - * DESCRIPTION: - * - * This routine installs new_handler as the interrupt service routine - * for the specified vector. The previous interrupt service routine is - * returned as old_handler. - */ - -#define _ISR_Install_vector( _vector, _new_handler, _old_handler ) \ - _CPU_ISR_install_vector( _vector, _new_handler, _old_handler ) - -/* - * _ISR_Get_level - * - * DESCRIPTION: - * - * This routine returns the current interrupt level. - */ - -#define _ISR_Get_level() \ - _CPU_ISR_Get_level() - -/* - * _ISR_Set_level - * - * DESCRIPTION: - * - * This routine sets the current interrupt level to that specified - * by new_level. The new interrupt level is effective when the - * routine exits. - */ - -#define _ISR_Set_level( _new_level ) \ - _CPU_ISR_Set_level( _new_level ) - -/* - * _ISR_Handler - * - * DESCRIPTION: - * - * This routine is the interrupt dispatcher. ALL interrupts - * are vectored to this routine so that minimal context can be saved - * and setup performed before the application's high-level language - * interrupt service routine is invoked. After the application's - * interrupt service routine returns control to this routine, it - * will determine if a thread dispatch is necessary. If so, it will - * insure that the necessary thread scheduling operations are - * performed when the outermost interrupt service routine exits. - * - * NOTE: Implemented in assembly language. - */ - -void _ISR_Handler( void ); - -/* - * _ISR_Dispatch - * - * DESCRIPTION: - * - * This routine provides a wrapper so that the routine - * _Thread_Dispatch can be invoked when a reschedule is necessary - * at the end of the outermost interrupt service routine. This - * wrapper is necessary to establish the processor context needed - * by _Thread_Dispatch and to save the processor context which is - * corrupted by _Thread_Dispatch. This context typically consists - * of registers which are not preserved across routine invocations. - * - * NOTE: Implemented in assembly language. - */ - -void _ISR_Dispatch( void ); - -/*PAGE - * - * _ISR_Is_in_progress - * - * DESCRIPTION: - * - * This function returns TRUE if the processor is currently servicing - * and interrupt and FALSE otherwise. A return value of TRUE indicates - * that the caller is an interrupt service routine, NOT a thread. The - */ - -#if (CPU_PROVIDES_ISR_IS_IN_PROGRESS == TRUE) -boolean _ISR_Is_in_progress( void ); -#else -#define _ISR_Is_in_progress() \ - (_ISR_Nest_level != 0) -#endif - -#include <rtems/score/isr.inl> - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/mpci.h b/c/src/exec/score/include/rtems/score/mpci.h deleted file mode 100644 index 0ca7f15c02..0000000000 --- a/c/src/exec/score/include/rtems/score/mpci.h +++ /dev/null @@ -1,411 +0,0 @@ -/* mpci.h - * - * This include file contains all the constants and structures associated - * with the MPCI layer. It provides mechanisms to utilize packets. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __MPCI_h -#define __MPCI_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/mppkt.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> -#include <rtems/score/watchdog.h> -#include <rtems/score/coresem.h> - -/* - * The following constants define the stack size requirements for - * the system threads. - */ - -#define MPCI_RECEIVE_SERVER_STACK_SIZE \ - ( STACK_MINIMUM_SIZE + \ - CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK + \ - _CPU_Table.extra_mpci_receive_server_stack \ - ) - -/* - * The following defines the node number used when a broadcast is desired. - */ - -#define MPCI_ALL_NODES 0 - -/* - * For packets associated with requests that don't already have a timeout, - * use the one specified by this MPCI driver. The value specified by - * the MPCI driver sets an upper limit on how long a remote request - * should take to complete. - */ - -#define MPCI_DEFAULT_TIMEOUT 0xFFFFFFFF - -/* - * The following records define the Multiprocessor Communications - * Interface (MPCI) Table. This table defines the user-provided - * MPCI which is a required part of a multiprocessor system. - * - * For non-blocking local operations that become remote operations, - * we need a timeout. This is a per-driver timeout: default_timeout - */ - -typedef void MPCI_Entry; - -typedef MPCI_Entry ( *MPCI_initialization_entry )( void ); - -typedef MPCI_Entry ( *MPCI_get_packet_entry )( - MP_packet_Prefix ** - ); - -typedef MPCI_Entry ( *MPCI_return_packet_entry )( - MP_packet_Prefix * - ); - -typedef MPCI_Entry ( *MPCI_send_entry )( - unsigned32, - MP_packet_Prefix * - ); - -typedef MPCI_Entry ( *MPCI_receive_entry )( - MP_packet_Prefix ** - ); - -typedef struct { - unsigned32 default_timeout; /* in ticks */ - unsigned32 maximum_packet_size; - MPCI_initialization_entry initialization; - MPCI_get_packet_entry get_packet; - MPCI_return_packet_entry return_packet; - MPCI_send_entry send_packet; - MPCI_receive_entry receive_packet; -} MPCI_Control; - -/* - * The following defines the type for packet processing routines - * invoked by the MPCI Receive server. - */ - -typedef void (*MPCI_Packet_processor)( MP_packet_Prefix * ); - -/* - * The following enumerated type defines the list of - * internal MP operations. - */ - -typedef enum { - MPCI_PACKETS_SYSTEM_VERIFY = 0 -} MPCI_Internal_Remote_operations; - -/* - * The following data structure defines the packet used to perform - * remote event operations. - */ - -typedef struct { - MP_packet_Prefix Prefix; - MPCI_Internal_Remote_operations operation; - unsigned32 maximum_nodes; - unsigned32 maximum_global_objects; -} MPCI_Internal_packet; - -/* - * This is the core semaphore which the MPCI Receive Server blocks on. - */ - -SCORE_EXTERN CORE_semaphore_Control _MPCI_Semaphore; -/* - * The following thread queue is used to maintain a list of tasks - * which currently have outstanding remote requests. - */ - -SCORE_EXTERN Thread_queue_Control _MPCI_Remote_blocked_threads; - -/* - * The following define the internal pointers to the user's - * configuration information. - */ - -SCORE_EXTERN MPCI_Control *_MPCI_table; - -/* - * The following points to the MPCI Receive Server. - */ - -SCORE_EXTERN Thread_Control *_MPCI_Receive_server_tcb; - -/* - * The following table contains the process packet routines provided - * by each object that supports MP operations. - */ - -SCORE_EXTERN MPCI_Packet_processor - _MPCI_Packet_processors[MP_PACKET_CLASSES_LAST+1]; - -/* - * _MPCI_Handler_initialization - * - * DESCRIPTION: - * - * This routine performs the initialization necessary for this handler. - */ - -void _MPCI_Handler_initialization( - MPCI_Control *users_mpci_table, - unsigned32 timeout_status -); - -/* - * _MPCI_Create_server - * - * DESCRIPTION: - * - * This routine creates the packet receive server used in MP systems. - */ - -void _MPCI_Create_server( void ); - -/* - * _MPCI_Initialization - * - * DESCRIPTION: - * - * This routine initializes the MPCI driver by - * invoking the user provided MPCI initialization callout. - */ - -void _MPCI_Initialization ( void ); - -/* - * _MPCI_Register_packet_processor - * - * DESCRIPTION: - * - * This routine registers the MPCI packet processor for the - * designated object class. - */ - -void _MPCI_Register_packet_processor( - MP_packet_Classes the_class, - MPCI_Packet_processor the_packet_processor - -); - -/* - * _MPCI_Get_packet - * - * DESCRIPTION: - * - * This function obtains a packet by invoking the user provided - * MPCI get packet callout. - */ - -MP_packet_Prefix *_MPCI_Get_packet ( void ); - -/* - * _MPCI_Return_packet - * - * DESCRIPTION: - * - * This routine returns a packet by invoking the user provided - * MPCI return packet callout. - */ - -void _MPCI_Return_packet ( - MP_packet_Prefix *the_packet -); - -/* - * _MPCI_Send_process_packet - * - * DESCRIPTION: - * - * This routine sends a process packet by invoking the user provided - * MPCI send callout. - */ - -void _MPCI_Send_process_packet ( - unsigned32 destination, - MP_packet_Prefix *the_packet -); - -/* - * _MPCI_Send_request_packet - * - * DESCRIPTION: - * - * This routine sends a request packet by invoking the user provided - * MPCI send callout. - */ - -unsigned32 _MPCI_Send_request_packet ( - unsigned32 destination, - MP_packet_Prefix *the_packet, - States_Control extra_state -); - -/* - * _MPCI_Send_response_packet - * - * DESCRIPTION: - * - * This routine sends a response packet by invoking the user provided - * MPCI send callout. - */ - -void _MPCI_Send_response_packet ( - unsigned32 destination, - MP_packet_Prefix *the_packet -); - -/* - * _MPCI_Receive_packet - * - * DESCRIPTION: - * - * This routine receives a packet by invoking the user provided - * MPCI receive callout. - */ - -MP_packet_Prefix *_MPCI_Receive_packet ( void ); - -/* - * _MPCI_Process_response - * - * DESCRIPTION: - * - * This routine obtains a packet by invoking the user provided - * MPCI get packet callout. - */ - -Thread_Control *_MPCI_Process_response ( - MP_packet_Prefix *the_packet -); - -/*PAGE - * - * _MPCI_Receive_server - * - */ - -Thread _MPCI_Receive_server( - unsigned32 ignored -); - -/*PAGE - * - * _MPCI_Announce - * - * DESCRIPTION: - * - * XXX - */ - -void _MPCI_Announce ( void ); - -/* - * _MPCI_Internal_packets_Send_process_packet - * - * DESCRIPTION: - * - * This routine performs a remote procedure call so that a - * process operation can be performed on another node. - */ - -void _MPCI_Internal_packets_Send_process_packet ( - MPCI_Internal_Remote_operations operation -); - -/* - * _MPCI_Internal_packets_Send_request_packet - * - * DESCRIPTION: - * - * This routine performs a remote procedure call so that a - * directive operation can be initiated on another node. - * - * This routine is not needed since there are no request - * packets to be sent by this manager. - */ - -/* - * _MPCI_Internal_packets_Send_response_packet - * - * DESCRIPTION: - * - * This routine performs a remote procedure call so that a - * directive can be performed on another node. - * - * This routine is not needed since there are no response - * packets to be sent by this manager. - */ - -/* - * - * _MPCI_Internal_packets_Process_packet - * - * DESCRIPTION: - * - * This routine performs the actions specific to this package for - * the request from another node. - */ - -void _MPCI_Internal_packets_Process_packet ( - MP_packet_Prefix *the_packet_prefix -); - -/* - * _MPCI_Internal_packets_Send_object_was_deleted - * - * DESCRIPTION: - * - * This routine is invoked indirectly by the thread queue - * when a proxy has been removed from the thread queue and - * the remote node must be informed of this. - * - * This routine is not needed since there are no objects - * deleted by this manager. - */ - -/* - * _MPCI_Internal_packets_Send_extract_proxy - * - * DESCRIPTION: - * - * This routine is invoked when a task is deleted and it - * has a proxy which must be removed from a thread queue and - * the remote node must be informed of this. - * - * This routine is not needed since there are no objects - * deleted by this manager. - */ - -/* - * _MPCI_Internal_packets_Get_packet - * - * DESCRIPTION: - * - * This routine is used to obtain a internal threads mp packet. - */ - - MPCI_Internal_packet *_MPCI_Internal_packets_Get_packet ( void ); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/mppkt.h b/c/src/exec/score/include/rtems/score/mppkt.h deleted file mode 100644 index 58d4785a3b..0000000000 --- a/c/src/exec/score/include/rtems/score/mppkt.h +++ /dev/null @@ -1,100 +0,0 @@ -/* mppkt.h - * - * This package is the specification for the Packet Handler. - * This handler defines the basic packet and provides - * mechanisms to utilize packets based on this prefix. - * Packets are the fundamental basis for messages passed between - * nodes in an MP system. - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __MP_PACKET_h -#define __MP_PACKET_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/watchdog.h> - -/* - * The following enumerated type defines the packet classes. - * - * NOTE: In general, each class corresponds to a manager - * which supports global operations. Each manager - * defines the set of supported operations. - */ - -typedef enum { - MP_PACKET_MPCI_INTERNAL = 0, - MP_PACKET_TASKS = 1, - MP_PACKET_MESSAGE_QUEUE = 2, - MP_PACKET_SEMAPHORE = 3, - MP_PACKET_PARTITION = 4, - MP_PACKET_REGION = 5, - MP_PACKET_EVENT = 6, - MP_PACKET_SIGNAL = 7 -} MP_packet_Classes; - -#define MP_PACKET_CLASSES_FIRST MP_PACKET_MPCI_INTERNAL -#define MP_PACKET_CLASSES_LAST MP_PACKET_SIGNAL - -/* - * The following record contains the prefix for every packet - * passed between nodes in an MP system. - * - * NOTE: This structure is padded to insure that anything - * following it is on a 16 byte boundary. This is - * the most stringent structure alignment rule - * encountered yet (i960CA). - */ - -typedef struct { - MP_packet_Classes the_class; - Objects_Id id; - Objects_Id source_tid; - Priority_Control source_priority; - unsigned32 return_code; - unsigned32 length; - unsigned32 to_convert; - Watchdog_Interval timeout; -} MP_packet_Prefix; - -/* - * An MPCI must support packets of at least this size. - */ - -#define MP_PACKET_MINIMUM_PACKET_SIZE 64 - -/* - * The following constant defines the number of unsigned32's - * in a packet which must be converted to native format in a - * heterogeneous system. In packets longer than - * MP_PACKET_MINIMUN_HETERO_CONVERSION unsigned32's, some of the "extra" data - * may a user message buffer which is not automatically endian swapped. - */ - -#define MP_PACKET_MINIMUN_HETERO_CONVERSION \ - ( sizeof( MP_packet_Prefix ) / sizeof( unsigned32 ) ) - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/mppkt.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/object.h b/c/src/exec/score/include/rtems/score/object.h deleted file mode 100644 index af2b6f763b..0000000000 --- a/c/src/exec/score/include/rtems/score/object.h +++ /dev/null @@ -1,548 +0,0 @@ -/* object.h - * - * This include file contains all the constants and structures associated - * with the Object Handler. This Handler provides mechanisms which - * can be used to initialize and manipulate all objects which have - * ids. - * - * COPYRIGHT (c) 1989-2002. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __OBJECTS_h -#define __OBJECTS_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> - -/* - * Mask to enable unlimited objects. This is used in the configuration - * table when specifying the number of configured objects. - */ - -#define OBJECTS_UNLIMITED_OBJECTS 0x80000000 - -/* - * The following type defines the control block used to manage - * object names. - */ - -typedef void * Objects_Name; - -/* - * Space for object names is allocated in multiples of this. - * - * NOTE: Must be a power of 2. Matches the name manipulation routines. - */ - -#define OBJECTS_NAME_ALIGNMENT sizeof( unsigned32 ) - -/* - * Functions which compare names are prototyped like this. - */ - -typedef boolean (*Objects_Name_comparators)( - void * /* name_1 */, - void * /* name_2 */, - unsigned32 /* length */ -); - -/* - * The following type defines the control block used to manage - * object IDs. The format is as follows (0=LSB): - * - * Bits 0 .. 15 = index (up to 65535 objects of a type) - * Bits 16 .. 23 = node (up to 255 nodes) - * Bits 24 .. 26 = API (up to 7 API classes) - * Bits 27 .. 31 = class (up to 31 object types per API) - */ - -typedef unsigned32 Objects_Id; - -#define OBJECTS_INDEX_START_BIT 0 -#define OBJECTS_NODE_START_BIT 16 -#define OBJECTS_API_START_BIT 24 -#define OBJECTS_CLASS_START_BIT 27 - -#define OBJECTS_INDEX_MASK 0x0000ffff -#define OBJECTS_NODE_MASK 0x00ff0000 -#define OBJECTS_API_MASK 0x07000000 -#define OBJECTS_CLASS_MASK 0xf8000000 - -#define OBJECTS_INDEX_VALID_BITS 0x0000ffff -#define OBJECTS_NODE_VALID_BITS 0x000000ff -#define OBJECTS_API_VALID_BITS 0x00000007 -#define OBJECTS_CLASS_VALID_BITS 0x0000001f - -/* - * This enumerated type is used in the class field of the object ID. - */ - -#define OBJECTS_NO_CLASS 0 - -typedef enum { - OBJECTS_NO_API = 0, - OBJECTS_INTERNAL_API = 1, - OBJECTS_CLASSIC_API = 2, - OBJECTS_POSIX_API = 3, - OBJECTS_ITRON_API = 4 -} Objects_APIs; - -#define OBJECTS_APIS_LAST OBJECTS_ITRON_API - -typedef enum { - OBJECTS_INTERNAL_NO_CLASS = 0, - OBJECTS_INTERNAL_THREADS = 1, - OBJECTS_INTERNAL_MUTEXES = 2 -} Objects_Internal_API; - -#define OBJECTS_INTERNAL_CLASSES_LAST OBJECTS_INTERNAL_MUTEXES - -typedef enum { - OBJECTS_CLASSIC_NO_CLASS = 0, - OBJECTS_RTEMS_TASKS = 1, - OBJECTS_RTEMS_TIMERS = 2, - OBJECTS_RTEMS_SEMAPHORES = 3, - OBJECTS_RTEMS_MESSAGE_QUEUES = 4, - OBJECTS_RTEMS_PARTITIONS = 5, - OBJECTS_RTEMS_REGIONS = 6, - OBJECTS_RTEMS_PORTS = 7, - OBJECTS_RTEMS_PERIODS = 8, - OBJECTS_RTEMS_EXTENSIONS = 9 -} Objects_Classic_API; - -#define OBJECTS_RTEMS_CLASSES_LAST OBJECTS_RTEMS_EXTENSIONS - -typedef enum { - OBJECTS_POSIX_NO_CLASS = 0, - OBJECTS_POSIX_THREADS = 1, - OBJECTS_POSIX_KEYS = 2, - OBJECTS_POSIX_INTERRUPTS = 3, - OBJECTS_POSIX_MESSAGE_QUEUE_FDS = 4, - OBJECTS_POSIX_MESSAGE_QUEUES = 5, - OBJECTS_POSIX_MUTEXES = 6, - OBJECTS_POSIX_SEMAPHORES = 7, - OBJECTS_POSIX_CONDITION_VARIABLES = 8 -} Objects_POSIX_API; - -#define OBJECTS_POSIX_CLASSES_LAST OBJECTS_POSIX_CONDITION_VARIABLES - -typedef enum { - OBJECTS_ITRON_NO_CLASS = 0, - OBJECTS_ITRON_TASKS = 1, - OBJECTS_ITRON_EVENTFLAGS = 2, - OBJECTS_ITRON_MAILBOXES = 3, - OBJECTS_ITRON_MESSAGE_BUFFERS = 4, - OBJECTS_ITRON_PORTS = 5, - OBJECTS_ITRON_SEMAPHORES = 6, - OBJECTS_ITRON_VARIABLE_MEMORY_POOLS = 7, - OBJECTS_ITRON_FIXED_MEMORY_POOLS = 8 -} Objects_ITRON_API; - -#define OBJECTS_ITRON_CLASSES_LAST OBJECTS_ITRON_FIXED_MEMORY_POOLS - -/* - * This enumerated type lists the locations which may be returned - * by _Objects_Get. These codes indicate the success of locating - * an object with the specified ID. - */ - -typedef enum { - OBJECTS_LOCAL = 0, /* object is local */ - OBJECTS_REMOTE = 1, /* object is remote */ - OBJECTS_ERROR = 2 /* id was invalid */ -} Objects_Locations; - -/* - * The following type defines the callout used when a local task - * is extracted from a remote thread queue (i.e. it's proxy must - * extracted from the remote queue). - */ - -typedef void ( *Objects_Thread_queue_Extract_callout )( void * ); - - -/* - * The following defines the Object Control Block used to manage - * each object local to this node. - */ - -typedef struct { - Chain_Node Node; - Objects_Id id; - Objects_Name name; -} Objects_Control; - -/* - * The following defines the structure for the information used to - * manage each class of objects. - */ - -typedef struct { - Objects_APIs the_api; /* API of this object */ - unsigned32 the_class; /* class of this object */ - Objects_Id minimum_id; /* minimum valid id of this type */ - Objects_Id maximum_id; /* maximum valid id of this type */ - unsigned32 maximum; /* maximum number of objects */ - boolean auto_extend; /* TRUE if unlimited objects */ - unsigned32 allocation_size; /* number of objects in a block */ - unsigned32 size; /* size of the objects */ - Objects_Control **local_table; - Objects_Name *name_table; - Chain_Control Inactive; /* chain of inactive ctl blocks */ - unsigned32 inactive; /* number of objects on the InActive list */ - unsigned32 *inactive_per_block; /* used to release a block */ - void **object_blocks; /* the object memory to remove */ - boolean is_string; /* TRUE if names are strings */ - unsigned32 name_length; /* maximum length of names */ - Objects_Thread_queue_Extract_callout *extract; -#if defined(RTEMS_MULTIPROCESSING) - Chain_Control *global_table; /* pointer to global table */ -#endif -} Objects_Information; - -/* - * The following defines the data storage which contains the - * node number of the local node. - */ - -SCORE_EXTERN unsigned32 _Objects_Local_node; -SCORE_EXTERN unsigned32 _Objects_Maximum_nodes; - -/* - * The following is the list of information blocks per API for each object - * class. From the ID, we can go to one of these information blocks, - * and obtain a pointer to the appropriate object control block. - */ - -SCORE_EXTERN Objects_Information - **_Objects_Information_table[OBJECTS_APIS_LAST + 1]; - -/* - * The following defines the constant which may be used - * with _Objects_Get to manipulate the calling task. - * - */ - -#define OBJECTS_ID_OF_SELF ((Objects_Id) 0) - -/* - * The following define the constants which may be used in name searches. - */ - -#define OBJECTS_SEARCH_ALL_NODES 0 -#define OBJECTS_SEARCH_OTHER_NODES 0x7FFFFFFE -#define OBJECTS_SEARCH_LOCAL_NODE 0x7FFFFFFF -#define OBJECTS_WHO_AM_I 0 - -/* - * Parameters and return id's for _Objects_Get_next - */ - -#define OBJECTS_ID_INITIAL_INDEX (0) -#define OBJECTS_ID_FINAL_INDEX (0xffff) - -#define OBJECTS_ID_INITIAL(_api, _class, _node) \ - _Objects_Build_id( (_api), (_class), (_node), OBJECTS_ID_INITIAL_INDEX ) - -#define OBJECTS_ID_FINAL ((Objects_Id)~0) - -/* - * _Objects_Handler_initialization - * - * DESCRIPTION: - * - * This function performs the initialization necessary for this handler. - * - */ - -void _Objects_Handler_initialization( - unsigned32 node, - unsigned32 maximum_nodes, - unsigned32 maximum_global_objects -); - -/* - * _Objects_Extend_information - * - * DESCRIPTION: - * - * This function extends an object class information record. - */ - -void _Objects_Extend_information( - Objects_Information *information -); - -/* - * _Objects_Shrink_information - * - * DESCRIPTION: - * - * This function shrink an object class information record. - */ - -void _Objects_Shrink_information( - Objects_Information *information -); - -/* - * _Objects_Initialize_information - * - * DESCRIPTION: - * - * This function initializes an object class information record. - * SUPPORTS_GLOBAL is TRUE if the object class supports global - * objects, and FALSE otherwise. Maximum indicates the number - * of objects required in this class and size indicates the size - * in bytes of each control block for this object class. The - * name length and string designator are also set. In addition, - * the class may be a task, therefore this information is also included. - */ - -void _Objects_Initialize_information ( - Objects_Information *information, - Objects_APIs the_api, - unsigned32 the_class, - unsigned32 maximum, - unsigned32 size, - boolean is_string, - unsigned32 maximum_name_length -#if defined(RTEMS_MULTIPROCESSING) - , - boolean supports_global, - Objects_Thread_queue_Extract_callout *extract -#endif -); - -/*PAGE - * - * _Objects_Allocate - * - * DESCRIPTION: - * - * This function allocates a object control block from - * the inactive chain of free object control blocks. - */ - -Objects_Control *_Objects_Allocate( - Objects_Information *information -); - -/* - * _Objects_Allocate_by_index - * - * DESCRIPTION: - * - * This function allocates the object control block - * specified by the index from the inactive chain of - * free object control blocks. - */ - -Objects_Control *_Objects_Allocate_by_index( - Objects_Information *information, - unsigned32 index, - unsigned32 sizeof_control -); - -/*PAGE - * - * _Objects_Free - * - * DESCRIPTION: - * - * This function frees a object control block to the - * inactive chain of free object control blocks. - */ - -void _Objects_Free( - Objects_Information *information, - Objects_Control *the_object -); - -/* - * _Objects_Clear_name - * - * DESCRIPTION: - * - * This method zeroes out the name. - */ - -void _Objects_Clear_name( - void *name, - unsigned32 length -); - -/* - * _Objects_Copy_name_string - * - * DESCRIPTION: - * - * This method copies a string style object name from source to destination. - */ - -void _Objects_Copy_name_string( - void *source, - void *destination -); - -/* - * _Objects_Copy_name_raw - * - * DESCRIPTION: - * - * This method copies a raw style object name from source to destination. - */ - -void _Objects_Copy_name_raw( - void *source, - void *destination, - unsigned32 length -); - -/* - * _Objects_Compare_name_string - * - * DESCRIPTION: - * - * This method compares two string style object names. - */ - -boolean _Objects_Compare_name_string( - void *name_1, - void *name_2, - unsigned32 length -); - -/* - * _Objects_Compare_name_raw - * - * DESCRIPTION: - * - * This method compares two raw style object names. - */ - -boolean _Objects_Compare_name_raw( - void *name_1, - void *name_2, - unsigned32 length -); -/* - * _Objects_Name_to_id - * - * DESCRIPTION: - * - * This function implements the common portion of the object - * identification directives. This directive returns the object - * id associated with name. If more than one object of this class - * is named name, then the object to which the id belongs is - * arbitrary. Node indicates the extent of the search for the - * id of the object named name. If the object class supports global - * objects, then the search can be limited to a particular node - * or allowed to encompass all nodes. - * - */ - -typedef enum { - OBJECTS_SUCCESSFUL, - OBJECTS_INVALID_NAME, - OBJECTS_INVALID_NODE -} Objects_Name_to_id_errors; - -#define OBJECTS_NAME_ERRORS_FIRST OBJECTS_SUCCESSFUL -#define OBJECTS_NAME_ERRORS_LAST OBJECTS_INVALID_NODE - -Objects_Name_to_id_errors _Objects_Name_to_id( - Objects_Information *information, - Objects_Name name, - unsigned32 node, - Objects_Id *id -); - -/* - * _Objects_Get - * - * DESCRIPTION: - * - * This function maps object ids to object control blocks. - * If id corresponds to a local object, then it returns - * the_object control pointer which maps to id and location - * is set to OBJECTS_LOCAL. If the object class supports global - * objects and the object id is global and resides on a remote - * node, then location is set to OBJECTS_REMOTE, and the_object - * is undefined. Otherwise, location is set to OBJECTS_ERROR - * and the_object is undefined. - * - * NOTE: _Objects_Get returns with dispatching disabled for - * local and remote objects. - * _Objects_Get_isr_disable returns with dispatching - * disabled for remote objects and interrupts for local - * objects. - */ - -Objects_Control *_Objects_Get ( - Objects_Information *information, - Objects_Id id, - Objects_Locations *location -); - -Objects_Control *_Objects_Get_isr_disable( - Objects_Information *information, - Objects_Id id, - Objects_Locations *location, - ISR_Level *level -); - -Objects_Control *_Objects_Get_by_index ( - Objects_Information *information, - Objects_Id id, - Objects_Locations *location -); - -Objects_Control *_Objects_Get_no_protection( - Objects_Information *information, - Objects_Id id, - Objects_Locations *location -); - -/* - * _Objects_Get_next - * - * DESCRIPTION: - * - * Like _Objects_Get, but is used to find "next" open object. - * - */ - -Objects_Control *_Objects_Get_next( - Objects_Information *information, - Objects_Id id, - Objects_Locations *location_p, - Objects_Id *next_id_p -); - -/* - * Pieces of object.inl are promoted out to the user - */ - -#include <rtems/score/object.inl> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/objectmp.h b/c/src/exec/score/include/rtems/score/objectmp.h deleted file mode 100644 index de227a128b..0000000000 --- a/c/src/exec/score/include/rtems/score/objectmp.h +++ /dev/null @@ -1,151 +0,0 @@ -/* objectmp.h - * - * This include file contains all the constants and structures associated - * with the manipulation of Global RTEMS Objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_OBJECTS_MP_h -#define __RTEMS_OBJECTS_MP_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This defines the Global Object Control Block used to manage - * objects resident on other nodes. - */ - -typedef struct { - Objects_Control Object; - unsigned32 name; /* XXX broken but works */ - /* XXX If any API is MP with variable length names .. BOOM!!!! */ -} Objects_MP_Control; - -/* - * _Objects_MP_Handler_initialization - * - * DESCRIPTION: - * - * This routine intializes the inactive global object chain - * based on the maximum number of global objects configured. - */ - -void _Objects_MP_Handler_initialization ( - unsigned32 node, - unsigned32 maximum_nodes, - unsigned32 maximum_global_objects -); - -/*PAGE - * - * _Objects_MP_Open - * - * DESCRIPTION: - * - * This routine place the specified global object in the - * specified information table. - */ - -void _Objects_MP_Open ( - Objects_Information *information, - Objects_MP_Control *the_global_object, - unsigned32 the_name, /* XXX -- wrong for variable */ - Objects_Id the_id -); - -/* - * _Objects_MP_Allocate_and_open - * - * DESCRIPTION: - * - * This routine allocates a global object control block - * and places it in the specified information table. If the - * allocation fails, then is_fatal_error determines the - * error processing actions taken. - */ - -boolean _Objects_MP_Allocate_and_open ( - Objects_Information *information, - unsigned32 the_name, /* XXX -- wrong for variable length */ - Objects_Id the_id, - boolean is_fatal_error -); - -/* - * _Objects_MP_Close - * - * DESCRIPTION: - * - * This routine removes a global object from the specified - * information table and deallocates the global object control block. - */ - -void _Objects_MP_Close ( - Objects_Information *information, - Objects_Id the_id -); - -/* - * _Objects_MP_Global_name_search - * - * DESCRIPTION: - * - * This routine looks for the object with the_name in the global - * object tables indicated by information. It returns the ID of the - * object with that name if one is found. - */ - -Objects_Name_to_id_errors _Objects_MP_Global_name_search ( - Objects_Information *information, - Objects_Name the_name, - unsigned32 nodes_to_search, - Objects_Id *the_id -); - -/* - * _Objects_MP_Is_remote - * - * DESCRIPTION: - * - * This function searches the Global Object Table managed - * by information for the object indicated by ID. If the object - * is found, then location is set to objects_remote, otherwise - * location is set to objects_error. In both cases, the_object - * is undefined. - */ - -void _Objects_MP_Is_remote ( - Objects_Information *information, - Objects_Id the_id, - Objects_Locations *location, - Objects_Control **the_object -); - -/* - * The following chain header is used to manage the set of - * inactive global object control blocks. - */ - -SCORE_EXTERN unsigned32 _Objects_MP_Maximum_global_objects; -SCORE_EXTERN Chain_Control _Objects_MP_Inactive_global_objects; - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/objectmp.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/priority.h b/c/src/exec/score/include/rtems/score/priority.h deleted file mode 100644 index 216673bac2..0000000000 --- a/c/src/exec/score/include/rtems/score/priority.h +++ /dev/null @@ -1,96 +0,0 @@ -/* priority.h - * - * This include file contains all thread priority manipulation routines. - * This Handler provides mechanisms which can be used to - * initialize and manipulate thread priorities. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __PRIORITY_h -#define __PRIORITY_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The following type defines the control block used to manage - * thread priorities. - * - * NOTE: Priority 0 is reserved for internal threads only. - */ - -typedef unsigned32 Priority_Control; - -#define PRIORITY_MINIMUM 0 /* highest thread priority */ -#define PRIORITY_MAXIMUM 255 /* lowest thread priority */ - -/* - * The following record defines the information associated with - * each thread to manage its interaction with the priority bit maps. - */ - -typedef struct { - Priority_Bit_map_control *minor; /* addr of minor bit map slot */ - Priority_Bit_map_control ready_major; /* priority bit map ready mask */ - Priority_Bit_map_control ready_minor; /* priority bit map ready mask */ - Priority_Bit_map_control block_major; /* priority bit map block mask */ - Priority_Bit_map_control block_minor; /* priority bit map block mask */ -} Priority_Information; - -/* - * The following data items are the priority bit map. - * Each of the sixteen bits used in the _Priority_Major_bit_map is - * associated with one of the sixteen entries in the _Priority_Bit_map. - * Each bit in the _Priority_Bit_map indicates whether or not there are - * threads ready at a particular priority. The mapping of - * individual priority levels to particular bits is processor - * dependent as is the value of each bit used to indicate that - * threads are ready at that priority. - */ - -SCORE_EXTERN volatile Priority_Bit_map_control _Priority_Major_bit_map; -SCORE_EXTERN Priority_Bit_map_control - _Priority_Bit_map[16] CPU_STRUCTURE_ALIGNMENT; - -/* - * The definition of the Priority_Bit_map_control type is CPU dependent. - * - */ - -/* - * Priority Bitfield Manipulation Routines - * - * NOTE: - * - * These may simply be pass throughs to CPU dependent routines. - */ - -#if ( CPU_USE_GENERIC_BITFIELD_CODE == FALSE ) - -#define _Priority_Mask( _bit_number ) \ - _CPU_Priority_Mask( _bit_number ) - -#define _Priority_Bits_index( _priority ) \ - _CPU_Priority_bits_index( _priority ) - -#endif - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/priority.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/stack.h b/c/src/exec/score/include/rtems/score/stack.h deleted file mode 100644 index d9997bb389..0000000000 --- a/c/src/exec/score/include/rtems/score/stack.h +++ /dev/null @@ -1,49 +0,0 @@ -/* stack.h - * - * This include file contains all information about the thread - * Stack Handler. This Handler provides mechanisms which can be used to - * initialize and utilize stacks. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __STACK_h -#define __STACK_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The following constant defines the minimum stack size which every - * thread must exceed. - */ - -#define STACK_MINIMUM_SIZE CPU_STACK_MINIMUM_SIZE - -/* - * The following defines the control block used to manage each stack. - */ - -typedef struct { - unsigned32 size; /* stack size */ - void *area; /* low memory addr of stack */ -} Stack_Control; - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/stack.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/states.h b/c/src/exec/score/include/rtems/score/states.h deleted file mode 100644 index b12571824f..0000000000 --- a/c/src/exec/score/include/rtems/score/states.h +++ /dev/null @@ -1,83 +0,0 @@ -/* states.h - * - * This include file contains thread execution state information. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_STATES_h -#define __RTEMS_STATES_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The following type defines the control block used to manage a - * thread's state. - */ - -typedef unsigned32 States_Control; - -/* - * The following constants define the individual states which may be - * be used to compose and manipulate a thread's state. - */ - -#define STATES_ALL_SET 0xfffff /* all states */ -#define STATES_READY 0x00000 /* ready to run */ -#define STATES_DORMANT 0x00001 /* created not started */ -#define STATES_SUSPENDED 0x00002 /* waiting for resume */ -#define STATES_TRANSIENT 0x00004 /* in transition */ -#define STATES_DELAYING 0x00008 /* wait for timeout */ -#define STATES_WAITING_FOR_TIME 0x00010 /* wait for TOD */ -#define STATES_WAITING_FOR_BUFFER 0x00020 -#define STATES_WAITING_FOR_SEGMENT 0x00040 -#define STATES_WAITING_FOR_MESSAGE 0x00080 -#define STATES_WAITING_FOR_EVENT 0x00100 -#define STATES_WAITING_FOR_SEMAPHORE 0x00200 -#define STATES_WAITING_FOR_MUTEX 0x00400 -#define STATES_WAITING_FOR_CONDITION_VARIABLE 0x00800 -#define STATES_WAITING_FOR_JOIN_AT_EXIT 0x01000 -#define STATES_WAITING_FOR_RPC_REPLY 0x02000 -#define STATES_WAITING_FOR_PERIOD 0x04000 -#define STATES_WAITING_FOR_SIGNAL 0x08000 -#define STATES_INTERRUPTIBLE_BY_SIGNAL 0x10000 - -#define STATES_LOCALLY_BLOCKED ( STATES_WAITING_FOR_BUFFER | \ - STATES_WAITING_FOR_SEGMENT | \ - STATES_WAITING_FOR_MESSAGE | \ - STATES_WAITING_FOR_SEMAPHORE | \ - STATES_WAITING_FOR_MUTEX | \ - STATES_WAITING_FOR_CONDITION_VARIABLE | \ - STATES_WAITING_FOR_JOIN_AT_EXIT | \ - STATES_WAITING_FOR_SIGNAL ) - -#define STATES_WAITING_ON_THREAD_QUEUE \ - ( STATES_LOCALLY_BLOCKED | \ - STATES_WAITING_FOR_RPC_REPLY ) - -#define STATES_BLOCKED ( STATES_DELAYING | \ - STATES_WAITING_FOR_TIME | \ - STATES_WAITING_FOR_PERIOD | \ - STATES_WAITING_FOR_EVENT | \ - STATES_WAITING_ON_THREAD_QUEUE | \ - STATES_INTERRUPTIBLE_BY_SIGNAL ) - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/states.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/sysstate.h b/c/src/exec/score/include/rtems/score/sysstate.h deleted file mode 100644 index 526494b79b..0000000000 --- a/c/src/exec/score/include/rtems/score/sysstate.h +++ /dev/null @@ -1,66 +0,0 @@ -/* sysstates.h - * - * This include file contains information regarding the system state. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_SYSTEM_STATE_h -#define __RTEMS_SYSTEM_STATE_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* types */ - -/* enumerated constants */ - -/* - * The following type defines the possible system states. - */ - -typedef enum { - SYSTEM_STATE_BEFORE_INITIALIZATION, /* start -> end of 1st init part */ - SYSTEM_STATE_BEFORE_MULTITASKING, /* end of 1st -> beginning of 2nd */ - SYSTEM_STATE_BEGIN_MULTITASKING, /* just before multitasking starts */ - SYSTEM_STATE_UP, /* normal operation */ - SYSTEM_STATE_SHUTDOWN, /* shutdown */ - SYSTEM_STATE_FAILED /* fatal error occurred */ -} System_state_Codes; - -#define SYSTEM_STATE_CODES_FIRST SYSTEM_STATE_BEFORE_INITIALIZATION -#define SYSTEM_STATE_CODES_LAST SYSTEM_STATE_FAILED - -/* - * The following variable indicates whether or not this is - * an multiprocessing system. - */ - -SCORE_EXTERN boolean _System_state_Is_multiprocessing; - -/* - * The following variable contains the current system state. - */ - -SCORE_EXTERN System_state_Codes _System_state_Current; - -/* - * Make it possible for the application to get the system state information. - */ - -#include <rtems/score/sysstate.inl> - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/thread.h b/c/src/exec/score/include/rtems/score/thread.h deleted file mode 100644 index 18d4774a5d..0000000000 --- a/c/src/exec/score/include/rtems/score/thread.h +++ /dev/null @@ -1,778 +0,0 @@ -/* thread.h - * - * This include file contains all constants and structures associated - * with the thread control block. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __THREAD_h -#define __THREAD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/context.h> -#include <rtems/score/cpu.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mppkt.h> -#endif -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/stack.h> -#include <rtems/score/states.h> -#include <rtems/score/tod.h> -#include <rtems/score/tqdata.h> -#include <rtems/score/watchdog.h> - -/* - * The following defines the "return type" of a thread. - * - * NOTE: This cannot always be right. Some APIs have void - * tasks/threads, others return pointers, others may - * return a numeric value. Hopefully a pointer is - * always at least as big as an unsigned32. :) - */ - -typedef void *Thread; - -/* - * The following defines the ways in which the entry point for a - * thread can be invoked. Basically, it can be passed any - * combination/permutation of a pointer and an unsigned32 value. - * - * NOTE: For now, we are ignoring the return type. - */ - -typedef enum { - THREAD_START_NUMERIC, - THREAD_START_POINTER, - THREAD_START_BOTH_POINTER_FIRST, - THREAD_START_BOTH_NUMERIC_FIRST -} Thread_Start_types; - -typedef Thread ( *Thread_Entry )(); /* basic type */ - -typedef Thread ( *Thread_Entry_numeric )( unsigned32 ); -typedef Thread ( *Thread_Entry_pointer )( void * ); -typedef Thread ( *Thread_Entry_both_pointer_first )( void *, unsigned32 ); -typedef Thread ( *Thread_Entry_both_numeric_first )( unsigned32, void * ); - -/* - * The following lists the algorithms used to manage the thread cpu budget. - * - * Reset Timeslice: At each context switch, reset the time quantum. - * Exhaust Timeslice: Only reset the quantum once it is consumed. - * Callout: Execute routine when budget is consumed. - */ - -typedef enum { - THREAD_CPU_BUDGET_ALGORITHM_NONE, - THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE, - THREAD_CPU_BUDGET_ALGORITHM_EXHAUST_TIMESLICE, - THREAD_CPU_BUDGET_ALGORITHM_CALLOUT -} Thread_CPU_budget_algorithms; - -typedef struct Thread_Control_struct Thread_Control; - -typedef void (*Thread_CPU_budget_algorithm_callout )( Thread_Control * ); - -/* - * Per task variable structure - */ - -struct rtems_task_variable_tt; - -struct rtems_task_variable_tt { - struct rtems_task_variable_tt *next; - void **ptr; - void *gval; - void *tval; - void (*dtor)(void *); -}; - -typedef struct rtems_task_variable_tt rtems_task_variable_t; - -/* - * The following structure contains the information which defines - * the starting state of a thread. - */ - -typedef struct { - Thread_Entry entry_point; /* starting thread address */ - Thread_Start_types prototype; /* how task is invoked */ - void *pointer_argument; /* pointer argument */ - unsigned32 numeric_argument; /* numeric argument */ - /* initial execution modes */ - boolean is_preemptible; - Thread_CPU_budget_algorithms budget_algorithm; - Thread_CPU_budget_algorithm_callout budget_callout; - unsigned32 isr_level; - Priority_Control initial_priority; /* initial priority */ - boolean core_allocated_stack; - Stack_Control Initial_stack; /* stack information */ -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) - void *fp_context; /* initial FP context area address */ -#endif - void *stack; /* initial stack area address */ -} Thread_Start_information; - -/* - * The following structure contains the information necessary to manage - * a thread which it is waiting for a resource. - */ - -#define THREAD_STATUS_PROXY_BLOCKING 0x1111111 - -typedef struct { - Objects_Id id; /* waiting on this object */ - unsigned32 count; /* "generic" fields to be used */ - void *return_argument; /* when blocking */ - void *return_argument_1; - unsigned32 option; - - /* - * NOTE: The following assumes that all API return codes can be - * treated as an unsigned32. - */ - unsigned32 return_code; /* status for thread awakened */ - - Chain_Control Block2n; /* 2 - n priority blocked chain */ - Thread_queue_Control *queue; /* pointer to thread queue */ -} Thread_Wait_information; - -/* - * The following defines the control block used to manage - * each thread proxy. - * - * NOTE: It is critical that proxies and threads have identical - * memory images for the shared part. - */ - -typedef struct { - Objects_Control Object; - States_Control current_state; - Priority_Control current_priority; - Priority_Control real_priority; - unsigned32 resource_count; - Thread_Wait_information Wait; - Watchdog_Control Timer; -#if defined(RTEMS_MULTIPROCESSING) - MP_packet_Prefix *receive_packet; -#endif - /****************** end of common block ********************/ - Chain_Node Active; -} Thread_Proxy_control; - - -/* - * The following record defines the control block used - * to manage each thread. - * - * NOTE: It is critical that proxies and threads have identical - * memory images for the shared part. - */ - -typedef enum { - THREAD_API_RTEMS, - THREAD_API_POSIX, - THREAD_API_ITRON -} Thread_APIs; - -#define THREAD_API_FIRST THREAD_API_RTEMS -#define THREAD_API_LAST THREAD_API_ITRON - -struct Thread_Control_struct { - Objects_Control Object; - States_Control current_state; - Priority_Control current_priority; - Priority_Control real_priority; - unsigned32 resource_count; - Thread_Wait_information Wait; - Watchdog_Control Timer; -#if defined(RTEMS_MULTIPROCESSING) - MP_packet_Prefix *receive_packet; -#endif - /****************** end of common block ********************/ - unsigned32 suspend_count; - boolean is_global; - boolean do_post_task_switch_extension; - - boolean is_preemptible; - void *rtems_ada_self; - unsigned32 cpu_time_budget; - Thread_CPU_budget_algorithms budget_algorithm; - Thread_CPU_budget_algorithm_callout budget_callout; - - unsigned32 ticks_executed; - Chain_Control *ready; - Priority_Information Priority_map; - Thread_Start_information Start; - Context_Control Registers; -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) - void *fp_context; -#endif - void *libc_reent; - void *API_Extensions[ THREAD_API_LAST + 1 ]; - void **extensions; - rtems_task_variable_t *task_variables; -}; - -/* - * Self for the GNU Ada Run-Time - */ - -SCORE_EXTERN void *rtems_ada_self; - -/* - * The following defines the information control block used to - * manage this class of objects. - */ - -SCORE_EXTERN Objects_Information _Thread_Internal_information; - -/* - * The following define the thread control pointers used to access - * and manipulate the idle thread. - */ - -SCORE_EXTERN Thread_Control *_Thread_Idle; - -/* - * The following context area contains the context of the "thread" - * which invoked the start multitasking routine. This context is - * restored as the last action of the stop multitasking routine. Thus - * control of the processor can be returned to the environment - * which initiated the system. - */ - -SCORE_EXTERN Context_Control _Thread_BSP_context; - -/* - * The following declares the dispatch critical section nesting - * counter which is used to prevent context switches at inopportune - * moments. - */ - -SCORE_EXTERN volatile unsigned32 _Thread_Dispatch_disable_level; - -/* - * If this is non-zero, then the post-task switch extension - * is run regardless of the state of the per thread flag. - */ - -SCORE_EXTERN unsigned32 _Thread_Do_post_task_switch_extension; - -/* - * The following holds how many user extensions are in the system. This - * is used to determine how many user extension data areas to allocate - * per thread. - */ - -SCORE_EXTERN unsigned32 _Thread_Maximum_extensions; - -/* - * The following is used to manage the length of a timeslice quantum. - */ - -SCORE_EXTERN unsigned32 _Thread_Ticks_per_timeslice; - -/* - * The following points to the array of FIFOs used to manage the - * set of ready threads. - */ - -SCORE_EXTERN Chain_Control *_Thread_Ready_chain; - -/* - * The following points to the thread which is currently executing. - * This thread is implicitly manipulated by numerous directives. - */ - -SCORE_EXTERN Thread_Control *_Thread_Executing; - -/* - * The following points to the highest priority ready thread - * in the system. Unless the current thread is not preemptibl, - * then this thread will be context switched to when the next - * dispatch occurs. - */ - -SCORE_EXTERN Thread_Control *_Thread_Heir; - -/* - * The following points to the thread whose floating point - * context is currently loaded. - */ - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) -SCORE_EXTERN Thread_Control *_Thread_Allocated_fp; -#endif - -/* - * The C library re-enter-rant global pointer. Some C library implementations - * such as newlib have a single global pointer that changed during a context - * switch. The pointer points to that global pointer. The Thread control block - * holds a pointer to the task specific data. - */ - -SCORE_EXTERN void **_Thread_libc_reent; - -/* - * _Thread_Handler_initialization - * - * DESCRIPTION: - * - * This routine performs the initialization necessary for this handler. - */ - -void _Thread_Handler_initialization ( - unsigned32 ticks_per_timeslice, - unsigned32 maximum_extensions, - unsigned32 maximum_proxies -); - -/* - * _Thread_Create_idle - * - * DESCRIPTION: - * - * This routine creates the idle thread. - * - * WARNING!! No thread should be created before this one. - */ - -void _Thread_Create_idle( void ); - -/* - * _Thread_Start_multitasking - * - * DESCRIPTION: - * - * This routine initiates multitasking. It is invoked only as - * part of initialization and its invocation is the last act of - * the non-multitasking part of the system initialization. - */ - -void _Thread_Start_multitasking( void ); - -/* - * _Thread_Dispatch - * - * DESCRIPTION: - * - * This routine is responsible for transferring control of the - * processor from the executing thread to the heir thread. As part - * of this process, it is responsible for the following actions: - * - * + saving the context of the executing thread - * + restoring the context of the heir thread - * + dispatching any signals for the resulting executing thread - */ - -void _Thread_Dispatch( void ); - -/* - * _Thread_Stack_Allocate - * - * DESCRIPTION: - * - * Allocate the requested stack space for the thread. - * return the actual size allocated after any adjustment - * or return zero if the allocation failed. - * Set the Start.stack field to the address of the stack - * - * NOTES: NONE - * - */ - -unsigned32 _Thread_Stack_Allocate( - Thread_Control *the_thread, - unsigned32 stack_size -); - -/* - * _Thread_Stack_Free - * - * DESCRIPTION: - * - * Deallocate the Thread's stack. - * NOTES: NONE - * - */ - -void _Thread_Stack_Free( - Thread_Control *the_thread -); - -/* - * _Thread_Initialize - * - * DESCRIPTION: - * - * This routine initializes the specified the thread. It allocates - * all memory associated with this thread. It completes by adding - * the thread to the local object table so operations on this - * thread id are allowed. - * - * NOTES: - * - * If stack_area is NULL, it is allocated from the workspace. - * - * If the stack is allocated from the workspace, then it is guaranteed to be - * of at least minimum size. - */ - -boolean _Thread_Initialize( - Objects_Information *information, - Thread_Control *the_thread, - void *stack_area, - unsigned32 stack_size, - boolean is_fp, - Priority_Control priority, - boolean is_preemptible, - Thread_CPU_budget_algorithms budget_algorithm, - Thread_CPU_budget_algorithm_callout budget_callout, - unsigned32 isr_level, - Objects_Name name -); - -/* - * _Thread_Start - * - * DESCRIPTION: - * - * This routine initializes the executable information for a thread - * and makes it ready to execute. After this routine executes, the - * thread competes with all other threads for CPU time. - */ - -boolean _Thread_Start( - Thread_Control *the_thread, - Thread_Start_types the_prototype, - void *entry_point, - void *pointer_argument, - unsigned32 numeric_argument -); - -/* - * _Thread_Restart - * - * DESCRIPTION: - * - * This support routine restarts the specified task in a way that the - * next time this thread executes, it will begin execution at its - * original starting point. - */ - -/* XXX multiple task arg profiles */ - -boolean _Thread_Restart( - Thread_Control *the_thread, - void *pointer_argument, - unsigned32 numeric_argument -); - -/* - * _Thread_Reset - * - * DESCRIPTION: - * - * This routine resets a thread to its initial state but does - * not restart it. - */ - -void _Thread_Reset( - Thread_Control *the_thread, - void *pointer_argument, - unsigned32 numeric_argument -); - -/* - * _Thread_Close - * - * DESCRIPTION: - * - * This routine frees all memory associated with the specified - * thread and removes it from the local object table so no further - * operations on this thread are allowed. - */ - -void _Thread_Close( - Objects_Information *information, - Thread_Control *the_thread -); - -/* - * _Thread_Ready - * - * DESCRIPTION: - * - * This routine removes any set states for the_thread. It performs - * any necessary scheduling operations including the selection of - * a new heir thread. - */ - -void _Thread_Ready( - Thread_Control *the_thread -); - -/* - * _Thread_Clear_state - * - * DESCRIPTION: - * - * This routine clears the indicated STATES for the_thread. It performs - * any necessary scheduling operations including the selection of - * a new heir thread. - */ - -void _Thread_Clear_state( - Thread_Control *the_thread, - States_Control state -); - -/* - * _Thread_Set_state - * - * DESCRIPTION: - * - * This routine sets the indicated states for the_thread. It performs - * any necessary scheduling operations including the selection of - * a new heir thread. - * - */ - -void _Thread_Set_state( - Thread_Control *the_thread, - States_Control state -); - -/* - * _Thread_Set_transient - * - * DESCRIPTION: - * - * This routine sets the TRANSIENT state for the_thread. It performs - * any necessary scheduling operations including the selection of - * a new heir thread. - */ - -void _Thread_Set_transient( - Thread_Control *the_thread -); - -/* - * _Thread_Reset_timeslice - * - * DESCRIPTION: - * - * This routine is invoked upon expiration of the currently - * executing thread's timeslice. If no other thread's are ready - * at the priority of the currently executing thread, then the - * executing thread's timeslice is reset. Otherwise, the - * currently executing thread is placed at the rear of the - * FIFO for this priority and a new heir is selected. - */ - -void _Thread_Reset_timeslice( void ); - -/* - * _Thread_Tickle_timeslice - * - * DESCRIPTION: - * - * This routine is invoked as part of processing each clock tick. - * It is responsible for determining if the current thread allows - * timeslicing and, if so, when its timeslice expires. - */ - -void _Thread_Tickle_timeslice( void ); - -/* - * _Thread_Yield_processor - * - * DESCRIPTION: - * - * This routine is invoked when a thread wishes to voluntarily - * transfer control of the processor to another thread of equal - * or greater priority. - */ - -void _Thread_Yield_processor( void ); - -/* - * _Thread_Rotate_Ready_Queue - * - * DESCRIPTION: - * - * This routine is invoked to rotate the ready queue for the - * given priority. It can be used to yeild the processor - * by rotating the executing threads ready queue. - */ - -void _Thread_Rotate_Ready_Queue( - Priority_Control priority -); - -/* - * _Thread_Load_environment - * - * DESCRIPTION: - * - * This routine initializes the context of the_thread to its - * appropriate starting state. - */ - -void _Thread_Load_environment( - Thread_Control *the_thread -); - -/* - * _Thread_Handler - * - * DESCRIPTION: - * - * This routine is the wrapper function for all threads. It is - * the starting point for all threads. The user provided thread - * entry point is invoked by this routine. Operations - * which must be performed immediately before and after the user's - * thread executes are found here. - */ - -void _Thread_Handler( void ); - -/* - * _Thread_Delay_ended - * - * DESCRIPTION: - * - * This routine is invoked when a thread must be unblocked at the - * end of a time based delay (i.e. wake after or wake when). - */ - -void _Thread_Delay_ended( - Objects_Id id, - void *ignored -); - -/* - * _Thread_Change_priority - * - * DESCRIPTION: - * - * This routine changes the current priority of the_thread to - * new_priority. It performs any necessary scheduling operations - * including the selection of a new heir thread. - */ - -void _Thread_Change_priority ( - Thread_Control *the_thread, - Priority_Control new_priority, - boolean prepend_it -); - -/* - * _Thread_Set_priority - * - * DESCRIPTION: - * - * This routine updates the priority related fields in the_thread - * control block to indicate the current priority is now new_priority. - */ - -void _Thread_Set_priority( - Thread_Control *the_thread, - Priority_Control new_priority -); - -/* - * _Thread_Suspend - * - * DESCRIPTION: - * - * This routine updates the related suspend fields in the_thread - * control block to indicate the current nested level. - */ - -void _Thread_Suspend( - Thread_Control *the_thread -); - -/* - * _Thread_Resume - * - * DESCRIPTION: - * - * This routine updates the related suspend fields in the_thread - * control block to indicate the current nested level. A force - * parameter of TRUE will force a resume and clear the suspend count. - */ - -void _Thread_Resume( - Thread_Control *the_thread, - boolean force -); - -/* - * _Thread_Evaluate_mode - * - * DESCRIPTION: - * - * This routine evaluates the current scheduling information for the - * system and determines if a context switch is required. This - * is usually called after changing an execution mode such as preemptability - * for a thread. - */ - -boolean _Thread_Evaluate_mode( void ); - -/* - * _Thread_Get - * - * NOTE: If we are not using static inlines, this must be a real - * subroutine call. - */ - -#ifndef USE_INLINES -Thread_Control *_Thread_Get ( - Objects_Id id, - Objects_Locations *location -); -#endif - -/* - * _Thread_Idle_body - * - * DESCRIPTION: - * - * This routine is the body of the system idle thread. - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == FALSE) -Thread _Thread_Idle_body( - unsigned32 ignored -); -#endif - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/thread.inl> -#endif -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/threadmp.h> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/threadmp.h b/c/src/exec/score/include/rtems/score/threadmp.h deleted file mode 100644 index 62a379d723..0000000000 --- a/c/src/exec/score/include/rtems/score/threadmp.h +++ /dev/null @@ -1,88 +0,0 @@ -/* threadmp.h - * - * This include file contains the specification for all routines - * and data specific to the multiprocessing portion of the thread package. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_THREAD_MP_h -#define __RTEMS_THREAD_MP_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * _Thread_MP_Handler_initialization - * - * DESCRIPTION: - * - * This routine initializes the multiprocessing portion of the Thread Handler. - */ - -void _Thread_MP_Handler_initialization ( - unsigned32 maximum_proxies -); - -/* - * _Thread_MP_Allocate_proxy - * - * DESCRIPTION: - * - * This allocates a proxy control block from - * the inactive chain of free proxy control blocks. - * - * NOTE: This function returns a thread control pointer - * because proxies are substitutes for remote threads. - */ - -Thread_Control *_Thread_MP_Allocate_proxy ( - States_Control the_state -); - -/* - * _Thread_MP_Find_proxy - * - * DESCRIPTION: - * - * This function removes the proxy control block for the specified - * id from the active chain of proxy control blocks. - */ - -Thread_Control *_Thread_MP_Find_proxy ( - Objects_Id the_id -); - -/* - * The following is used to determine when the multiprocessing receive - * thread is executing so that a proxy can be allocated instead of - * blocking the multiprocessing receive thread. - */ - -SCORE_EXTERN Thread_Control *_Thread_MP_Receive; - -/* - * The following chains are used to manage proxies. - */ - -SCORE_EXTERN Chain_Control _Thread_MP_Active_proxies; -SCORE_EXTERN Chain_Control _Thread_MP_Inactive_proxies; - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/threadmp.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/threadq.h b/c/src/exec/score/include/rtems/score/threadq.h deleted file mode 100644 index db275177c5..0000000000 --- a/c/src/exec/score/include/rtems/score/threadq.h +++ /dev/null @@ -1,300 +0,0 @@ -/* threadq.h - * - * This include file contains all the constants and structures associated - * with the manipulation of objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __THREAD_QUEUE_h -#define __THREAD_QUEUE_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/tqdata.h> - -#include <rtems/score/object.h> -#include <rtems/score/thread.h> -#include <rtems/score/watchdog.h> - -/* - * Constant for indefinite wait. - */ - -#define THREAD_QUEUE_WAIT_FOREVER WATCHDOG_NO_TIMEOUT - -/* - * The following type defines the callout used when a remote task - * is extracted from a local thread queue. - */ - -typedef void ( *Thread_queue_Flush_callout )( - Thread_Control * - ); - -/* - * The following type defines the callout used when a local task - * is extracted from a remote thread queue (i.e. it's proxy must - * extracted from the remote queue). - */ - -#if 0 -typedef void ( *Thread_queue_Extract_callout )( - Thread_Control * - ); - -SCORE_EXTERN Thread_queue_Extract_callout - _Thread_queue_Extract_table[ OBJECTS_CLASSES_LAST + 1 ]; -#endif - -/* - * _Thread_queue_Dequeue - * - * DESCRIPTION: - * - * This function returns a pointer to a thread waiting on - * the_thread_queue. The selection of this thread is based on - * the discipline of the_thread_queue. If no threads are waiting - * on the_thread_queue, then NULL is returned. - */ - -Thread_Control *_Thread_queue_Dequeue( - Thread_queue_Control *the_thread_queue -); - -/* - * _Thread_queue_Enqueue - * - * DESCRIPTION: - * - * This routine enqueues the currently executing thread on - * the_thread_queue with an optional timeout. - */ - -void _Thread_queue_Enqueue( - Thread_queue_Control *the_thread_queue, - Watchdog_Interval timeout -); - -/* - * _Thread_queue_Extract - * - * DESCRIPTION: - * - * This routine removes the_thread from the_thread_queue - * and cancels any timeouts associated with this blocking. - */ - -void _Thread_queue_Extract( - Thread_queue_Control *the_thread_queue, - Thread_Control *the_thread -); - -/* - * _Thread_queue_Extract_with_proxy - * - * DESCRIPTION: - * - * This routine extracts the_thread from the_thread_queue - * and ensures that if there is a proxy for this task on - * another node, it is also dealt with. - */ - -boolean _Thread_queue_Extract_with_proxy( - Thread_Control *the_thread -); - -/* - * _Thread_queue_First - * - * DESCRIPTION: - * - * This function returns a pointer to the "first" thread - * on the_thread_queue. The "first" thread is selected - * based on the discipline of the_thread_queue. - */ - -Thread_Control *_Thread_queue_First( - Thread_queue_Control *the_thread_queue -); - -/* - * _Thread_queue_Flush - * - * DESCRIPTION: - * - * This routine unblocks all threads blocked on the_thread_queue - * and cancels any associated timeouts. - */ - -void _Thread_queue_Flush( - Thread_queue_Control *the_thread_queue, - Thread_queue_Flush_callout remote_extract_callout, - unsigned32 status -); - -/* - * _Thread_queue_Initialize - * - * DESCRIPTION: - * - * This routine initializes the_thread_queue based on the - * discipline indicated in attribute_set. The state set on - * threads which block on the_thread_queue is state. - */ - -void _Thread_queue_Initialize( - Thread_queue_Control *the_thread_queue, - Thread_queue_Disciplines the_discipline, - States_Control state, - unsigned32 timeout_status -); - -/* - * _Thread_queue_Dequeue_priority - * - * DESCRIPTION: - * - * This function returns a pointer to the highest priority - * thread waiting on the_thread_queue. If no threads are waiting - * on the_thread_queue, then NULL is returned. - */ - -Thread_Control *_Thread_queue_Dequeue_priority( - Thread_queue_Control *the_thread_queue -); - -/* - * _Thread_queue_Enqueue_priority - * - * DESCRIPTION: - * - * This routine enqueues the currently executing thread on - * the_thread_queue with an optional timeout using the - * priority discipline. - */ - -void _Thread_queue_Enqueue_priority( - Thread_queue_Control *the_thread_queue, - Thread_Control *the_thread, - Watchdog_Interval timeout -); - -/* - * _Thread_queue_Extract_priority - * - * DESCRIPTION: - * - * This routine removes the_thread from the_thread_queue - * and cancels any timeouts associated with this blocking. - */ - -void _Thread_queue_Extract_priority( - Thread_queue_Control *the_thread_queue, - Thread_Control *the_thread -); - -/* - * _Thread_queue_First_priority - * - * DESCRIPTION: - * - * This function returns a pointer to the "first" thread - * on the_thread_queue. The "first" thread is the highest - * priority thread waiting on the_thread_queue. - */ - -Thread_Control *_Thread_queue_First_priority( - Thread_queue_Control *the_thread_queue -); - -/* - * _Thread_queue_Dequeue_FIFO - * - * DESCRIPTION: - * - * This function returns a pointer to the thread which has - * been waiting the longest on the_thread_queue. If no - * threads are waiting on the_thread_queue, then NULL is returned. - */ - -Thread_Control *_Thread_queue_Dequeue_fifo( - Thread_queue_Control *the_thread_queue -); - -/* - * _Thread_queue_Enqueue_FIFO - * - * DESCRIPTION: - * - * This routine enqueues the currently executing thread on - * the_thread_queue with an optional timeout using the - * FIFO discipline. - */ - -void _Thread_queue_Enqueue_fifo( - Thread_queue_Control *the_thread_queue, - Thread_Control *the_thread, - Watchdog_Interval timeout -); - -/* - * _Thread_queue_Extract_FIFO - * - * DESCRIPTION: - * - * This routine removes the_thread from the_thread_queue - * and cancels any timeouts associated with this blocking. - */ - -void _Thread_queue_Extract_fifo( - Thread_queue_Control *the_thread_queue, - Thread_Control *the_thread -); - -/* - * _Thread_queue_First_FIFO - * - * DESCRIPTION: - * - * This function returns a pointer to the "first" thread - * on the_thread_queue. The first thread is the thread - * which has been waiting longest on the_thread_queue. - */ - -Thread_Control *_Thread_queue_First_fifo( - Thread_queue_Control *the_thread_queue -); - -/* - * _Thread_queue_timeout - * - * DESCRIPTION: - * - * This routine is invoked when a task's request has not - * been satisfied after the timeout interval specified to - * enqueue. The task represented by ID will be unblocked and - * its status code will be set in it's control block to indicate - * that a timeout has occurred. - */ - -void _Thread_queue_Timeout ( - Objects_Id id, - void *ignored -); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/tod.h b/c/src/exec/score/include/rtems/score/tod.h deleted file mode 100644 index c745fdb1f6..0000000000 --- a/c/src/exec/score/include/rtems/score/tod.h +++ /dev/null @@ -1,276 +0,0 @@ -/* tod.h - * - * This include file contains all the constants and structures associated - * with the Time of Day Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __TIME_OF_DAY_h -#define __TIME_OF_DAY_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/object.h> -#include <rtems/score/watchdog.h> - -/* - * The following constants are related to the time of day. - */ - -#define TOD_SECONDS_PER_MINUTE 60 -#define TOD_MINUTES_PER_HOUR 60 -#define TOD_MONTHS_PER_YEAR 12 -#define TOD_DAYS_PER_YEAR 365 -#define TOD_HOURS_PER_DAY 24 -#define TOD_SECONDS_PER_DAY (TOD_SECONDS_PER_MINUTE * \ - TOD_MINUTES_PER_HOUR * \ - TOD_HOURS_PER_DAY) - -#define TOD_SECONDS_PER_NON_LEAP_YEAR (365 * TOD_SECONDS_PER_DAY) - -#define TOD_MILLISECONDS_PER_SECOND 1000 -#define TOD_MICROSECONDS_PER_SECOND 1000000 -#define TOD_NANOSECONDS_PER_SECOND 1000000000 -#define TOD_NANOSECONDS_PER_MICROSECOND 1000 - -/* - * The following constant define the earliest year to which an - * time of day can be initialized. This is considered the - * epoch. - */ - -#define TOD_BASE_YEAR 1988 - -/* - * The following record defines the time of control block. This - * control block is used to maintain the current time of day. - */ - -typedef struct { /* RTEID style time/date */ - unsigned32 year; /* year, A.D. */ - unsigned32 month; /* month, 1 -> 12 */ - unsigned32 day; /* day, 1 -> 31 */ - unsigned32 hour; /* hour, 0 -> 23 */ - unsigned32 minute; /* minute, 0 -> 59 */ - unsigned32 second; /* second, 0 -> 59 */ - unsigned32 ticks; /* elapsed ticks between secs */ -} TOD_Control; - -/* - * The following is TRUE if the application has set the current - * time of day, and FALSE otherwise. - */ - -SCORE_EXTERN boolean _TOD_Is_set; - -/* - * The following contains the current time of day. - */ - -SCORE_EXTERN TOD_Control _TOD_Current; - -/* - * The following contains the number of seconds from 00:00:00 - * January 1, TOD_BASE_YEAR until the current time of day. - */ - -SCORE_EXTERN Watchdog_Interval _TOD_Seconds_since_epoch; - -/* - * The following contains the number of microseconds per tick. - */ - -SCORE_EXTERN unsigned32 _TOD_Microseconds_per_tick; - -/* - * The following contains the number of clock ticks per second. - * - * NOTE: - * - * If one second is NOT evenly divisible by the number of microseconds - * per clock tick, this value will contain only the integer portion - * of the division. This means that the interval between clock ticks - * can be a source of error in the current time of day. - */ - -SCORE_EXTERN unsigned32 _TOD_Ticks_per_second; - -/* - * This is the control structure for the watchdog timer which - * fires to service the seconds chain. - */ - -SCORE_EXTERN Watchdog_Control _TOD_Seconds_watchdog; - -#ifdef SCORE_INIT - -/* - * The following array contains the number of days in all months. - * The first dimension should be 1 for leap years, and 0 otherwise. - * The second dimension should range from 1 to 12 for January to - * February, respectively. - */ - -const unsigned32 _TOD_Days_per_month[ 2 ][ 13 ] = { - { 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }, - { 0, 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 } -}; - -/* - * The following array contains the number of days in all months - * up to the month indicated by the index of the second dimension. - * The first dimension should be 1 for leap years, and 0 otherwise. - */ - -const unsigned16 _TOD_Days_to_date[2][13] = { - { 0, 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 }, - { 0, 0, 31, 60, 91, 121, 152, 182, 213, 244, 274, 305, 335 } -}; - -/* - * The following array contains the number of days in the years - * since the last leap year. The index should be 0 for leap - * years, and the number of years since the beginning of a leap - * year otherwise. - */ - -const unsigned16 _TOD_Days_since_last_leap_year[4] = { 0, 366, 731, 1096 }; - -#else - -extern const unsigned16 _TOD_Days_to_date[2][13]; /* Julian days */ -extern const unsigned16 _TOD_Days_since_last_leap_year[4]; -extern const unsigned32 _TOD_Days_per_month[2][13]; - -#endif - -/* - * _TOD_Handler_initialization - * - * DESCRIPTION: - * - * This routine performs the initialization necessary for this handler. - */ - -void _TOD_Handler_initialization( - unsigned32 microseconds_per_tick -); - -/* - * _TOD_Set - * - * DESCRIPTION: - * - * This routine sets the current time of day to THE_TOD and - * the equivalent SECONDS_SINCE_EPOCH. - */ - -void _TOD_Set( - TOD_Control *the_tod, - Watchdog_Interval seconds_since_epoch -); - -/* - * _TOD_Validate - * - * DESCRIPTION: - * - * This function returns TRUE if THE_TOD contains - * a valid time of day, and FALSE otherwise. - */ - -boolean _TOD_Validate( - TOD_Control *the_tod -); - -/* - * _TOD_To_seconds - * - * DESCRIPTION: - * - * This function returns the number seconds between the epoch and THE_TOD. - */ - -Watchdog_Interval _TOD_To_seconds( - TOD_Control *the_tod -); - -/* - * _TOD_Tickle - * - * DESCRIPTION: - * - * This routine is scheduled as a watchdog function and is invoked at - * each second boundary. It updates the current time of day to indicate - * that a second has passed and processes the seconds watchdog chain. - */ - -void _TOD_Tickle( - Objects_Id id, - void *ignored -); - -/* - * TOD_MILLISECONDS_TO_MICROSECONDS - * - * DESCRIPTION: - * - * This routine converts an interval expressed in milliseconds to microseconds. - * - * NOTE: - * - * This must be a macro so it can be used in "static" tables. - */ - -#define TOD_MILLISECONDS_TO_MICROSECONDS(_ms) ((_ms) * 1000) - -/* - * TOD_MICROSECONDS_TO_TICKS - * - * DESCRIPTION: - * - * This routine converts an interval expressed in microseconds to ticks. - * - * NOTE: - * - * This must be a macro so it can be used in "static" tables. - */ - -#define TOD_MICROSECONDS_TO_TICKS(_us) \ - ((_us) / _TOD_Microseconds_per_tick) - -/* - * TOD_MILLISECONDS_TO_TICKS - * - * DESCRIPTION: - * - * This routine converts an interval expressed in milliseconds to ticks. - * - * NOTE: - * - * This must be a macro so it can be used in "static" tables. - */ - -#define TOD_MILLISECONDS_TO_TICKS(_ms) \ - (TOD_MILLISECONDS_TO_MICROSECONDS(_ms) / _TOD_Microseconds_per_tick) - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/tod.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/tqdata.h b/c/src/exec/score/include/rtems/score/tqdata.h deleted file mode 100644 index 98b9e4d9d2..0000000000 --- a/c/src/exec/score/include/rtems/score/tqdata.h +++ /dev/null @@ -1,89 +0,0 @@ -/* tqdata.h - * - * This include file contains all the constants and structures - * needed to declare a thread queue. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __THREAD_QUEUE_DATA_h -#define __THREAD_QUEUE_DATA_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/chain.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> - -/* - * The following enumerated type details all of the disciplines - * supported by the Thread Queue Handler. - */ - -typedef enum { - THREAD_QUEUE_DISCIPLINE_FIFO, /* FIFO queue discipline */ - THREAD_QUEUE_DISCIPLINE_PRIORITY /* PRIORITY queue discipline */ -} Thread_queue_Disciplines; - -/* - * The following enumerated types indicate what happened while the thread - * queue was in the synchronization window. - */ - -typedef enum { - THREAD_QUEUE_SYNCHRONIZED, - THREAD_QUEUE_NOTHING_HAPPENED, - THREAD_QUEUE_TIMEOUT, - THREAD_QUEUE_SATISFIED -} Thread_queue_States; - -/* - * The following constants are used to manage the priority queues. - * - * There are four chains used to maintain a priority -- each chain - * manages a distinct set of task priorities. The number of chains - * is determined by TASK_QUEUE_DATA_NUMBER_OF_PRIORITY_HEADERS. - * The following set must be consistent. - * - * The set below configures 4 headers -- each contains 64 priorities. - * Header x manages priority range (x*64) through ((x*64)+63). If - * the priority is more than half way through the priority range it - * is in, then the search is performed from the rear of the chain. - * This halves the search time to find the insertion point. - */ - -#define TASK_QUEUE_DATA_NUMBER_OF_PRIORITY_HEADERS 4 -#define TASK_QUEUE_DATA_PRIORITIES_PER_HEADER 64 -#define TASK_QUEUE_DATA_REVERSE_SEARCH_MASK 0x20 - -typedef struct { - union { - Chain_Control Fifo; /* FIFO discipline list */ - Chain_Control Priority[TASK_QUEUE_DATA_NUMBER_OF_PRIORITY_HEADERS]; - /* priority discipline list */ - } Queues; - Thread_queue_States sync_state; /* alloc/dealloc critical section */ - Thread_queue_Disciplines discipline; /* queue discipline */ - States_Control state; /* state of threads on Thread_q */ - unsigned32 timeout_status; -} Thread_queue_Control; - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/tqdata.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/userext.h b/c/src/exec/score/include/rtems/score/userext.h deleted file mode 100644 index 40e31fbba5..0000000000 --- a/c/src/exec/score/include/rtems/score/userext.h +++ /dev/null @@ -1,230 +0,0 @@ -/* userext.h - * - * This include file contains all information about user extensions. This - * Handler provides mechanisms which can be used to initialize and manipulate - * all user extensions. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __USER_EXTENSIONS_h -#define __USER_EXTENSIONS_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/interr.h> -#include <rtems/score/chain.h> -#include <rtems/score/thread.h> - -/* - * The following records defines the User Extension Table. - * This table defines the application dependent routines which - * are invoked at critical points in the life of each thread and - * the system as a whole. - */ - -typedef void User_extensions_routine; - -typedef boolean ( *User_extensions_thread_create_extension )( - Thread_Control *, - Thread_Control * - ); - -typedef User_extensions_routine ( *User_extensions_thread_delete_extension )( - Thread_Control *, - Thread_Control * - ); - -typedef User_extensions_routine ( *User_extensions_thread_start_extension )( - Thread_Control *, - Thread_Control * - ); - -typedef User_extensions_routine ( *User_extensions_thread_restart_extension )( - Thread_Control *, - Thread_Control * - ); - -typedef User_extensions_routine ( *User_extensions_thread_switch_extension )( - Thread_Control *, - Thread_Control * - ); - -typedef User_extensions_routine ( - *User_extensions_thread_post_switch_extension )( - Thread_Control * - ); - -typedef User_extensions_routine ( *User_extensions_thread_begin_extension )( - Thread_Control * - ); - -typedef User_extensions_routine ( *User_extensions_thread_exitted_extension )( - Thread_Control * - ); - -typedef User_extensions_routine ( *User_extensions_fatal_extension )( - Internal_errors_Source /* the_source */, - boolean /* is_internal */, - unsigned32 /* the_error */ - ); - - -typedef struct { - User_extensions_thread_create_extension thread_create; - User_extensions_thread_start_extension thread_start; - User_extensions_thread_restart_extension thread_restart; - User_extensions_thread_delete_extension thread_delete; - User_extensions_thread_switch_extension thread_switch; - User_extensions_thread_begin_extension thread_begin; - User_extensions_thread_exitted_extension thread_exitted; - User_extensions_fatal_extension fatal; -} User_extensions_Table; - -/* - * The following is used to manage the list of switch handlers. - */ - -typedef struct { - Chain_Node Node; - User_extensions_thread_switch_extension thread_switch; -} User_extensions_Switch_control; - -/* - * The following is used to manage each user extension set. - * The switch control is part of the extensions control even - * if not used due to the extension not having a switch - * handler. - */ - -typedef struct { - Chain_Node Node; - User_extensions_Switch_control Switch; - User_extensions_Table Callouts; -} User_extensions_Control; - -/* - * The following is used to manage the list of active extensions. - */ - -SCORE_EXTERN Chain_Control _User_extensions_List; - -/* - * The following is used to manage a chain of user extension task - * switch nodes. - */ - -SCORE_EXTERN Chain_Control _User_extensions_Switches_list; - -/* - * _User_extensions_Thread_create - * - * DESCRIPTION: - * - * This routine is used to invoke the user extension for - * the thread creation operate. - */ - -boolean _User_extensions_Thread_create ( - Thread_Control *the_thread -); - -/* - * _User_extensions_Thread_delete - * - * DESCRIPTION: - * - * This routine is used to invoke the user extension for - * the thread deletion operation. - */ - -void _User_extensions_Thread_delete ( - Thread_Control *the_thread -); - -/* - * _User_extensions_Thread_start - * - * DESCRIPTION: - * - * This routine is used to invoke the user extension for - * the thread start operation. - */ - -void _User_extensions_Thread_start ( - Thread_Control *the_thread -); - -/* - * _User_extensions_Thread_restart - * - * DESCRIPTION: - * - * This routine is used to invoke the user extension for - * the thread restart operation. - */ - -void _User_extensions_Thread_restart ( - Thread_Control *the_thread -); - -/* - * _User_extensions_Thread_begin - * - * DESCRIPTION: - * - * This routine is used to invoke the user extension which - * is invoked when a thread begins. - */ - -void _User_extensions_Thread_begin ( - Thread_Control *executing -); - -/* - * _User_extensions_Thread_exitted - * - * DESCRIPTION: - * - * This routine is used to invoke the user extension which - * is invoked when a thread exits. - */ - -void _User_extensions_Thread_exitted ( - Thread_Control *executing -); - -/* - * _User_extensions_Fatal - * - * DESCRIPTION: - * - * This routine is used to invoke the user extension invoked - * when a fatal error occurs. - */ - -void _User_extensions_Fatal ( - Internal_errors_Source the_source, - boolean is_internal, - unsigned32 the_error -); - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/userext.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/watchdog.h b/c/src/exec/score/include/rtems/score/watchdog.h deleted file mode 100644 index f24c7a1a69..0000000000 --- a/c/src/exec/score/include/rtems/score/watchdog.h +++ /dev/null @@ -1,195 +0,0 @@ -/* watchdog.h - * - * This include file contains all the constants and structures associated - * with watchdog timers. This Handler provides mechanisms which can be - * used to initialize and manipulate watchdog timers. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __WATCHDOG_h -#define __WATCHDOG_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/object.h> - -/* - * The following type defines the control block used to manage - * intervals. - */ - -#define WATCHDOG_MAXIMUM_INTERVAL ((Watchdog_Interval) 0xffffffff) - -typedef unsigned32 Watchdog_Interval; - -/* - * The following types define a pointer to a watchdog service routine. - */ - -typedef void Watchdog_Service_routine; - -typedef Watchdog_Service_routine ( *Watchdog_Service_routine_entry )( - Objects_Id, - void * - ); - -/* - * Constant for indefinite wait. (actually an illegal interval) - */ - -#define WATCHDOG_NO_TIMEOUT 0 - -/* - * The following enumerated type lists the states in which a - * watchdog timer may be at any given time. - */ - -typedef enum { - WATCHDOG_INACTIVE, /* off all chains */ - WATCHDOG_BEING_INSERTED, /* off all chains, searching for insertion point */ - WATCHDOG_ACTIVE, /* on chain, allowed to fire */ - WATCHDOG_REMOVE_IT /* on chain, remove without firing if expires */ -} Watchdog_States; - -/* - * The following enumerated type details the manner in which - * a watchdog chain may be adjusted by the Watchdog_Adjust - * routine. The direction indicates a movement FORWARD - * or BACKWARD in time. - */ - -typedef enum { - WATCHDOG_FORWARD, /* adjust delta value forward */ - WATCHDOG_BACKWARD /* adjust delta value backward */ -} Watchdog_Adjust_directions; - -/* - * The following record defines the control block used - * to manage each watchdog timer. - */ - -typedef struct { - Chain_Node Node; - Watchdog_States state; - Watchdog_Interval initial; - Watchdog_Interval delta_interval; - Watchdog_Interval start_time; - Watchdog_Interval stop_time; - Watchdog_Service_routine_entry routine; - Objects_Id id; - void *user_data; -} Watchdog_Control; - -/* - * The following are used for synchronization purposes - * during an insert on a watchdog delta chain. - */ - -SCORE_EXTERN volatile unsigned32 _Watchdog_Sync_level; -SCORE_EXTERN volatile unsigned32 _Watchdog_Sync_count; - -/* - * The following contains the number of ticks since the - * system was booted. - */ - -SCORE_EXTERN Watchdog_Interval _Watchdog_Ticks_since_boot; - -/* - * The following defines the watchdog chains which are managed - * on ticks and second boundaries. - */ - -SCORE_EXTERN Chain_Control _Watchdog_Ticks_chain; -SCORE_EXTERN Chain_Control _Watchdog_Seconds_chain; - -/* - * _Watchdog_Handler_initialization - * - * DESCRIPTION: - * - * This routine initializes the watchdog handler. The watchdog - * synchronization flag is initialized and the watchdog chains are - * initialized and emptied. - */ - -void _Watchdog_Handler_initialization( void ); - -/* - * _Watchdog_Remove - * - * DESCRIPTION: - * - * This routine removes THE_WATCHDOG from the watchdog chain on which - * it resides and returns the state THE_WATCHDOG timer was in. - */ - -Watchdog_States _Watchdog_Remove ( - Watchdog_Control *the_watchdog -); - -/* - * _Watchdog_Adjust - * - * DESCRIPTION: - * - * This routine adjusts the HEADER watchdog chain in the forward - * or backward DIRECTION for UNITS ticks. - */ - -void _Watchdog_Adjust ( - Chain_Control *header, - Watchdog_Adjust_directions direction, - Watchdog_Interval units -); - -/* - * _Watchdog_Insert - * - * DESCRIPTION: - * - * This routine inserts THE_WATCHDOG into the HEADER watchdog chain - * for a time of UNITS. The INSERT_MODE indicates whether - * THE_WATCHDOG is to be activated automatically or later, explicitly - * by the caller. - * - */ - -void _Watchdog_Insert ( - Chain_Control *header, - Watchdog_Control *the_watchdog -); - -/* - * _Watchdog_Tickle - * - * DESCRIPTION: - * - * This routine is invoked at appropriate intervals to update - * the HEADER watchdog chain. - */ - -void _Watchdog_Tickle ( - Chain_Control *header -); - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/watchdog.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/score/wkspace.h b/c/src/exec/score/include/rtems/score/wkspace.h deleted file mode 100644 index 77d7142204..0000000000 --- a/c/src/exec/score/include/rtems/score/wkspace.h +++ /dev/null @@ -1,70 +0,0 @@ -/* wkspace.h - * - * This include file contains information related to the - * RAM Workspace. This Handler provides mechanisms which can be used to - * define, initialize and manipulate the workspace. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __WORKSPACE_h -#define __WORKSPACE_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/heap.h> -#include <rtems/score/interr.h> - -/* - * The following is used to manage the Workspace. - * - */ - -SCORE_EXTERN Heap_Control _Workspace_Area; /* executive heap header */ - -/* - * _Workspace_Handler_initialization - * - * DESCRIPTION: - * - * This routine performs the initialization necessary for this handler. - */ - -void _Workspace_Handler_initialization( - void *starting_address, - unsigned32 size -); - -/* - * _Workspace_Allocate_or_fatal_error - * - * DESCRIPTION: - * - * This routine returns the address of a block of memory of size - * bytes. If a block of the appropriate size cannot be allocated - * from the workspace, then the internal error handler is invoked. - */ - -void *_Workspace_Allocate_or_fatal_error( - unsigned32 size -); - -#ifndef __RTEMS_APPLICATION__ -#include <rtems/score/wkspace.inl> -#endif - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/seterr.h b/c/src/exec/score/include/rtems/seterr.h deleted file mode 100644 index 64bf4eb17f..0000000000 --- a/c/src/exec/score/include/rtems/seterr.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_SET_ERRNO_h -#define __RTEMS_SET_ERRNO_h - -#define rtems_set_errno_and_return_minus_one( _error ) \ - do { errno = (_error); return -1; } while(0) - -#define rtems_set_errno_and_return_minus_one_cast( _error, _cast ) \ - do { errno = (_error); return (_cast) -1; } while(0) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/include/rtems/system.h b/c/src/exec/score/include/rtems/system.h deleted file mode 100644 index 92b05c340c..0000000000 --- a/c/src/exec/score/include/rtems/system.h +++ /dev/null @@ -1,210 +0,0 @@ -/* system.h - * - * This include file contains information that is included in every - * function in the executive. This must be the first include file - * included in all internal RTEMS files. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __RTEMS_SYSTEM_h -#define __RTEMS_SYSTEM_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The cpu options include file defines all cpu dependent - * parameters for this build of RTEMS. It must be included - * first so the basic macro definitions are in place. - */ - -#include <rtems/score/cpuopts.h> - -/* - * The following ensures that all data is declared in the space - * of the initialization routine for either the Initialization Manager - * or the initialization file for the appropriate API. It is - * referenced as "external" in every other file. - */ - -#ifdef SCORE_INIT -#undef SCORE_EXTERN -#define SCORE_EXTERN -#else -#undef SCORE_EXTERN -#define SCORE_EXTERN extern -#endif - -#ifdef SAPI_INIT -#undef SAPI_EXTERN -#define SAPI_EXTERN -#else -#undef SAPI_EXTERN -#define SAPI_EXTERN extern -#endif - -#ifdef RTEMS_API_INIT -#undef RTEMS_EXTERN -#define RTEMS_EXTERN -#else -#undef RTEMS_EXTERN -#define RTEMS_EXTERN extern -#endif - -#ifdef POSIX_API_INIT -#undef POSIX_EXTERN -#define POSIX_EXTERN -#else -#undef POSIX_EXTERN -#define POSIX_EXTERN extern -#endif - -#ifdef ITRON_API_INIT -#undef ITRON_EXTERN -#define ITRON_EXTERN -#else -#undef ITRON_EXTERN -#define ITRON_EXTERN extern -#endif - -/* - * The following (in conjunction with compiler arguments) are used - * to choose between the use of static inline functions and macro - * functions. The static inline implementation allows better - * type checking with no cost in code size or execution speed. - */ - -#ifdef USE_INLINES -# ifdef __GNUC__ -# define RTEMS_INLINE_ROUTINE static __inline__ -# else -# define RTEMS_INLINE_ROUTINE static inline -# endif -#else -# define RTEMS_INLINE_ROUTINE -#endif - -/* - * The following are used by the POSIX implementation to catch bad paths. - */ - -#ifdef RTEMS_POSIX_API -int POSIX_MP_NOT_IMPLEMENTED( void ); -int POSIX_NOT_IMPLEMENTED( void ); -int POSIX_BOTTOM_REACHED( void ); -#endif - -/* - * Include a base set of files. - */ - -/* - * XXX: Eventually proc_ptr needs to disappear!!! - */ - -typedef void * proc_ptr; - -/* - * Define NULL - */ - -#ifndef NULL -#define NULL 0 /* NULL value */ -#endif - -/* - * Boolean constants - */ - -#if !defined( TRUE ) || (TRUE != 1) -#undef TRUE -#define TRUE (1) -#endif - -#if !defined( FALSE ) || (FALSE != 0) -#undef FALSE -#define FALSE (0) -#endif - -#include <rtems/score/cpu.h> /* processor specific information */ - -#define stringify( _x ) # _x - -#define RTEMS_offsetof(type, field) \ - ((unsigned32) &(((type *) 0)->field)) - -/* - * The following is the extern for the RTEMS version string. - * The contents of this string are CPU specific. - */ - -extern const char _RTEMS_version[]; /* RTEMS version string */ -extern const char _Copyright_Notice[]; /* RTEMS copyright string */ - -/* - * The following defines the CPU dependent information table. - */ - -SCORE_EXTERN rtems_cpu_table _CPU_Table; /* CPU dependent info */ - -/* - * Macros to access CPU Table fields required by ALL ports. - * - * NOTE: Similar macros to access port specific fields in in the - * appropriate cpu.h file. - */ - -#define rtems_cpu_configuration_get_table() \ - (&_CPU_Table) - -#define rtems_cpu_configuration_get_pretasking_hook() \ - (_CPU_Table.pretasking_hook) - -#define rtems_cpu_configuration_get_predriver_hook() \ - (_CPU_Table.predriver_hook) - -#define rtems_cpu_configuration_get_postdriver_hook() \ - (_CPU_Table.postdriver_hook) - -#define rtems_cpu_configuration_get_idle_task() \ - (_CPU_Table.idle_task) - -#define rtems_cpu_configuration_get_do_zero_of_workspace() \ - (_CPU_Table.do_zero_of_workspace) - -#define rtems_cpu_configuration_get_idle_task_stack_size() \ - (_CPU_Table.idle_task_stack_size) - -#define rtems_cpu_configuration_get_interrupt_stack_size() \ - (_CPU_Table.interrupt_stack_size) - -#define rtems_cpu_configuration_get_extra_mpci_receive_server_stack() \ - (_CPU_Table.extra_mpci_receive_server_stack) - -#define rtems_cpu_configuration_get_stack_allocate_hook() \ - (_CPU_Table.stack_allocate_hook) - -#define rtems_cpu_configuration_get_stack_free_hook() \ - (_CPU_Table.stack_free_hook) - -/* - * XXX weird RTEMS stuff that probably should be somewhere else. - */ - -#define RTEMS_MAXIMUM_NAME_LENGTH sizeof(rtems_name) - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/.cvsignore b/c/src/exec/score/inline/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/inline/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/inline/Makefile.am b/c/src/exec/score/inline/Makefile.am deleted file mode 100644 index 392c18d4b0..0000000000 --- a/c/src/exec/score/inline/Makefile.am +++ /dev/null @@ -1,43 +0,0 @@ -## -## $Id$ -## - - -$(PROJECT_INCLUDE)/%: % - $(INSTALL_DATA) $< $@ - -include_rtems_scoredir = $(includedir)/rtems/score - -$(PROJECT_INCLUDE)/rtems/score: - @$(mkinstalldirs) $@ - -## We only build multiprocessing related files if HAS_MP was defined -MP_I_FILES = rtems/score/mppkt.inl rtems/score/objectmp.inl rtems/score/threadmp.inl - -STD_I_FILES = rtems/score/address.inl rtems/score/chain.inl \ - rtems/score/coremsg.inl rtems/score/coremutex.inl rtems/score/coresem.inl \ - rtems/score/heap.inl rtems/score/isr.inl rtems/score/object.inl \ - rtems/score/priority.inl rtems/score/stack.inl rtems/score/states.inl \ - rtems/score/sysstate.inl rtems/score/thread.inl rtems/score/tod.inl \ - rtems/score/tqdata.inl rtems/score/userext.inl rtems/score/watchdog.inl \ - rtems/score/wkspace.inl - -if HAS_MP -I_FILES = $(STD_I_FILES) $(MP_I_FILES) -else -I_FILES = $(STD_I_FILES) -endif - -if INLINE -include_rtems_score_HEADERS = $(I_FILES) - -PREINSTALL_FILES = $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%=$(PROJECT_INCLUDE)/%) - -endif - -all-local: $(PREINSTALL_FILES) - -EXTRA_DIST = $(STD_I_FILES) $(MP_I_FILES) - -include $(top_srcdir)/automake/local.am diff --git a/c/src/exec/score/inline/rtems/.cvsignore b/c/src/exec/score/inline/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/inline/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/inline/rtems/score/.cvsignore b/c/src/exec/score/inline/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/inline/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/inline/rtems/score/address.inl b/c/src/exec/score/inline/rtems/score/address.inl deleted file mode 100644 index 54f11c3ca4..0000000000 --- a/c/src/exec/score/inline/rtems/score/address.inl +++ /dev/null @@ -1,125 +0,0 @@ -/* inline/address.inl - * - * This include file contains the bodies of the routines - * about addresses which are inlined. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __INLINE_ADDRESSES_inl -#define __INLINE_ADDRESSES_inl - -/*PAGE - * - * _Addresses_Add_offset - * - * DESCRIPTION: - * - * This function is used to add an offset to a base address. - * It returns the resulting address. This address is typically - * converted to an access type before being used further. - */ - -RTEMS_INLINE_ROUTINE void *_Addresses_Add_offset ( - void *base, - unsigned32 offset -) -{ - return (void *)((char *)base + offset); -} - -/*PAGE - * - * _Addresses_Subtract_offset - * - * DESCRIPTION: - * - * This function is used to subtract an offset from a base - * address. It returns the resulting address. This address is - * typically converted to an access type before being used further. - */ - -RTEMS_INLINE_ROUTINE void *_Addresses_Subtract_offset ( - void *base, - unsigned32 offset -) -{ - return (void *)((char *)base - offset); -} - -/*PAGE - * - * _Addresses_Subtract - * - * DESCRIPTION: - * - * This function is used to subtract two addresses. It returns the - * resulting offset. - * - * NOTE: The cast of an address to an unsigned32 makes this code - * dependent on an addresses being thirty two bits. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _Addresses_Subtract ( - void *left, - void *right -) -{ - return ((char *) left - (char *) right); -} - -/*PAGE - * - * _Addresses_Is_aligned - * - * DESCRIPTION: - * - * This function returns TRUE if the given address is correctly - * aligned for this processor and FALSE otherwise. Proper alignment - * is based on correctness and efficiency. - */ - -RTEMS_INLINE_ROUTINE boolean _Addresses_Is_aligned ( - void *address -) -{ -#if (CPU_ALIGNMENT == 0) - return TRUE; -#elif defined(RTEMS_CPU_HAS_16_BIT_ADDRESSES) - return ( ( (unsigned short)address % CPU_ALIGNMENT ) == 0 ); -#else - return ( ( (unsigned32)address % CPU_ALIGNMENT ) == 0 ); -#endif -} - -/*PAGE - * - * _Addresses_Is_in_range - * - * DESCRIPTION: - * - * This function returns TRUE if the given address is within the - * memory range specified and FALSE otherwise. base is the address - * of the first byte in the memory range and limit is the address - * of the last byte in the memory range. The base address is - * assumed to be lower than the limit address. - */ - -RTEMS_INLINE_ROUTINE boolean _Addresses_Is_in_range ( - void *address, - void *base, - void *limit -) -{ - return ( address >= base && address <= limit ); -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/chain.inl b/c/src/exec/score/inline/rtems/score/chain.inl deleted file mode 100644 index ca005fe0a9..0000000000 --- a/c/src/exec/score/inline/rtems/score/chain.inl +++ /dev/null @@ -1,389 +0,0 @@ -/* inline/chain.inl - * - * This include file contains the bodies of the routines which are - * associated with doubly linked chains and inlined. - * - * NOTE: The routines in this file are ordered from simple - * to complex. No other Chain Handler routine is referenced - * unless it has already been defined. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __INLINE_CHAIN_inl -#define __INLINE_CHAIN_inl - -/*PAGE - * - * _Chain_Are_nodes_equal - * - * DESCRIPTION: - * - * This function returns TRUE if LEFT and RIGHT are equal, - * and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Chain_Are_nodes_equal( - Chain_Node *left, - Chain_Node *right -) -{ - return left == right; -} - -/*PAGE - * - * _Chain_Is_null - * - * DESCRIPTION: - * - * This function returns TRUE if the_chain is NULL and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Chain_Is_null( - Chain_Control *the_chain -) -{ - return ( the_chain == NULL ); -} - -/*PAGE - * - * _Chain_Is_null_node - * - * DESCRIPTION: - * - * This function returns TRUE if the_node is NULL and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Chain_Is_null_node( - Chain_Node *the_node -) -{ - return ( the_node == NULL ); -} - -/*PAGE - * - * _Chain_Head - * - * DESCRIPTION: - * - * This function returns a pointer to the first node on the chain. - */ - -RTEMS_INLINE_ROUTINE Chain_Node *_Chain_Head( - Chain_Control *the_chain -) -{ - return (Chain_Node *) the_chain; -} - -/*PAGE - * - * _Chain_Tail - * - * DESCRIPTION: - * - * This function returns a pointer to the last node on the chain. - */ - -RTEMS_INLINE_ROUTINE Chain_Node *_Chain_Tail( - Chain_Control *the_chain -) -{ - return (Chain_Node *) &the_chain->permanent_null; -} - -/*PAGE - * - * _Chain_Is_empty - * - * DESCRIPTION: - * - * This function returns TRUE if there a no nodes on the_chain and - * FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Chain_Is_empty( - Chain_Control *the_chain -) -{ - return ( the_chain->first == _Chain_Tail( the_chain ) ); -} - -/*PAGE - * - * _Chain_Is_first - * - * DESCRIPTION: - * - * This function returns TRUE if the_node is the first node on a chain and - * FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Chain_Is_first( - Chain_Node *the_node -) -{ - return ( the_node->previous == NULL ); -} - -/*PAGE - * - * _Chain_Is_last - * - * DESCRIPTION: - * - * This function returns TRUE if the_node is the last node on a chain and - * FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Chain_Is_last( - Chain_Node *the_node -) -{ - return ( the_node->next == NULL ); -} - -/*PAGE - * - * _Chain_Has_only_one_node - * - * DESCRIPTION: - * - * This function returns TRUE if there is only one node on the_chain and - * FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Chain_Has_only_one_node( - Chain_Control *the_chain -) -{ - return ( the_chain->first == the_chain->last ); -} - -/*PAGE - * - * _Chain_Is_head - * - * DESCRIPTION: - * - * This function returns TRUE if the_node is the head of the_chain and - * FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Chain_Is_head( - Chain_Control *the_chain, - Chain_Node *the_node -) -{ - return ( the_node == _Chain_Head( the_chain ) ); -} - -/*PAGE - * - * _Chain_Is_tail - * - * DESCRIPTION: - * - * This function returns TRUE if the_node is the tail of the_chain and - * FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Chain_Is_tail( - Chain_Control *the_chain, - Chain_Node *the_node -) -{ - return ( the_node == _Chain_Tail( the_chain ) ); -} - -/*PAGE - * - * Chain_Initialize_empty - * - * DESCRIPTION: - * - * This routine initializes the specified chain to contain zero nodes. - */ - -RTEMS_INLINE_ROUTINE void _Chain_Initialize_empty( - Chain_Control *the_chain -) -{ - the_chain->first = _Chain_Tail( the_chain ); - the_chain->permanent_null = NULL; - the_chain->last = _Chain_Head( the_chain ); -} - -/*PAGE - * - * _Chain_Extract_unprotected - * - * DESCRIPTION: - * - * This routine extracts the_node from the chain on which it resides. - * It does NOT disable interrupts to insure the atomicity of the - * extract operation. - */ - -RTEMS_INLINE_ROUTINE void _Chain_Extract_unprotected( - Chain_Node *the_node -) -{ - Chain_Node *next; - Chain_Node *previous; - - next = the_node->next; - previous = the_node->previous; - next->previous = previous; - previous->next = next; -} - -/*PAGE - * - * _Chain_Get_first_unprotected - * - * DESCRIPTION: - * - * This function removes the first node from the_chain and returns - * a pointer to that node. It does NOT disable interrupts to insure - * the atomicity of the get operation. - */ - -RTEMS_INLINE_ROUTINE Chain_Node *_Chain_Get_first_unprotected( - Chain_Control *the_chain -) -{ - Chain_Node *return_node; - Chain_Node *new_first; - - return_node = the_chain->first; - new_first = return_node->next; - the_chain->first = new_first; - new_first->previous = _Chain_Head( the_chain ); - - return return_node; -} - -/*PAGE - * - * Chain_Get_unprotected - * - * DESCRIPTION: - * - * This function removes the first node from the_chain and returns - * a pointer to that node. If the_chain is empty, then NULL is returned. - * It does NOT disable interrupts to insure the atomicity of the - * get operation. - */ - -RTEMS_INLINE_ROUTINE Chain_Node *_Chain_Get_unprotected( - Chain_Control *the_chain -) -{ - if ( !_Chain_Is_empty( the_chain ) ) - return _Chain_Get_first_unprotected( the_chain ); - else - return NULL; -} - -/*PAGE - * - * _Chain_Insert_unprotected - * - * DESCRIPTION: - * - * This routine inserts the_node on a chain immediately following - * after_node. It does NOT disable interrupts to insure the atomicity - * of the extract operation. - */ - -RTEMS_INLINE_ROUTINE void _Chain_Insert_unprotected( - Chain_Node *after_node, - Chain_Node *the_node -) -{ - Chain_Node *before_node; - - the_node->previous = after_node; - before_node = after_node->next; - after_node->next = the_node; - the_node->next = before_node; - before_node->previous = the_node; -} - -/*PAGE - * - * _Chain_Append_unprotected - * - * DESCRIPTION: - * - * This routine appends the_node onto the end of the_chain. - * It does NOT disable interrupts to insure the atomicity of the - * append operation. - */ - -RTEMS_INLINE_ROUTINE void _Chain_Append_unprotected( - Chain_Control *the_chain, - Chain_Node *the_node -) -{ - Chain_Node *old_last_node; - - the_node->next = _Chain_Tail( the_chain ); - old_last_node = the_chain->last; - the_chain->last = the_node; - old_last_node->next = the_node; - the_node->previous = old_last_node; -} - -/*PAGE - * - * _Chain_Prepend_unprotected - * - * DESCRIPTION: - * - * This routine prepends the_node onto the front of the_chain. - * It does NOT disable interrupts to insure the atomicity of the - * prepend operation. - */ - -RTEMS_INLINE_ROUTINE void _Chain_Prepend_unprotected( - Chain_Control *the_chain, - Chain_Node *the_node -) -{ - _Chain_Insert_unprotected( _Chain_Head( the_chain ), the_node ); - -} - -/*PAGE - * - * _Chain_Prepend - * - * DESCRIPTION: - * - * This routine prepends the_node onto the front of the_chain. - * It disables interrupts to insure the atomicity of the - * prepend operation. - */ - -RTEMS_INLINE_ROUTINE void _Chain_Prepend( - Chain_Control *the_chain, - Chain_Node *the_node -) -{ - _Chain_Insert( _Chain_Head( the_chain ), the_node ); -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/coremsg.inl b/c/src/exec/score/inline/rtems/score/coremsg.inl deleted file mode 100644 index 2f6fe5e877..0000000000 --- a/c/src/exec/score/inline/rtems/score/coremsg.inl +++ /dev/null @@ -1,275 +0,0 @@ -/* coremsg.inl - * - * This include file contains the static inline implementation of all - * inlined routines in the Core Message Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CORE_MESSAGE_QUEUE_inl -#define __CORE_MESSAGE_QUEUE_inl - -#include <string.h> /* needed for memcpy */ - -/*PAGE - * - * _CORE_message_queue_Send - * - * DESCRIPTION: - * - * This routine sends a message to the end of the specified message queue. - */ - -RTEMS_INLINE_ROUTINE CORE_message_queue_Status _CORE_message_queue_Send( - CORE_message_queue_Control *the_message_queue, - void *buffer, - unsigned32 size, - Objects_Id id, - CORE_message_queue_API_mp_support_callout api_message_queue_mp_support, - boolean wait, - Watchdog_Interval timeout -) -{ - return _CORE_message_queue_Submit( - the_message_queue, - buffer, - size, - id, -#if defined(RTEMS_MULTIPROCESSING) - api_message_queue_mp_support, -#else - NULL, -#endif - CORE_MESSAGE_QUEUE_SEND_REQUEST, - wait, /* sender may block */ - timeout /* timeout interval */ - ); -} - -/*PAGE - * - * _CORE_message_queue_Urgent - * - * DESCRIPTION: - * - * This routine sends a message to the front of the specified message queue. - */ - -RTEMS_INLINE_ROUTINE CORE_message_queue_Status _CORE_message_queue_Urgent( - CORE_message_queue_Control *the_message_queue, - void *buffer, - unsigned32 size, - Objects_Id id, - CORE_message_queue_API_mp_support_callout api_message_queue_mp_support, - boolean wait, - Watchdog_Interval timeout -) -{ - return _CORE_message_queue_Submit( - the_message_queue, - buffer, - size, - id, -#if defined(RTEMS_MULTIPROCESSING) - api_message_queue_mp_support, -#else - NULL, -#endif - CORE_MESSAGE_QUEUE_URGENT_REQUEST, - wait, /* sender may block */ - timeout /* timeout interval */ - ); -} - -/*PAGE - * - * _CORE_message_queue_Copy_buffer - * - * DESCRIPTION: - * - * This routine copies the contents of the source message buffer - * to the destination message buffer. - */ - -RTEMS_INLINE_ROUTINE void _CORE_message_queue_Copy_buffer ( - void *source, - void *destination, - unsigned32 size -) -{ - memcpy(destination, source, size); -} - -/*PAGE - * - * _CORE_message_queue_Allocate_message_buffer - * - * DESCRIPTION: - * - * This function allocates a message buffer from the inactive - * message buffer chain. - */ - -RTEMS_INLINE_ROUTINE CORE_message_queue_Buffer_control * -_CORE_message_queue_Allocate_message_buffer ( - CORE_message_queue_Control *the_message_queue -) -{ - return (CORE_message_queue_Buffer_control *) - _Chain_Get( &the_message_queue->Inactive_messages ); -} - -/*PAGE - * - * _CORE_message_queue_Free_message_buffer - * - * DESCRIPTION: - * - * This routine frees a message buffer to the inactive - * message buffer chain. - */ - -RTEMS_INLINE_ROUTINE void _CORE_message_queue_Free_message_buffer ( - CORE_message_queue_Control *the_message_queue, - CORE_message_queue_Buffer_control *the_message -) -{ - _Chain_Append( &the_message_queue->Inactive_messages, &the_message->Node ); -} - -/*PAGE - * - * _CORE_message_queue_Get_pending_message - * - * DESCRIPTION: - * - * This function removes the first message from the_message_queue - * and returns a pointer to it. - */ - -RTEMS_INLINE_ROUTINE - CORE_message_queue_Buffer_control *_CORE_message_queue_Get_pending_message ( - CORE_message_queue_Control *the_message_queue -) -{ - return (CORE_message_queue_Buffer_control *) - _Chain_Get_unprotected( &the_message_queue->Pending_messages ); -} - -/*PAGE - * - * _CORE_message_queue_Is_priority - * - * DESCRIPTION: - * - * This function returns TRUE if the priority attribute is - * enabled in the attribute_set and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _CORE_message_queue_Is_priority( - CORE_message_queue_Attributes *the_attribute -) -{ - return (the_attribute->discipline == CORE_MESSAGE_QUEUE_DISCIPLINES_PRIORITY); -} - -/*PAGE - * - * _CORE_message_queue_Append - * - * DESCRIPTION: - * - * This routine places the_message at the rear of the outstanding - * messages on the_message_queue. - */ - -RTEMS_INLINE_ROUTINE void _CORE_message_queue_Append ( - CORE_message_queue_Control *the_message_queue, - CORE_message_queue_Buffer_control *the_message -) -{ - _Chain_Append( &the_message_queue->Pending_messages, &the_message->Node ); -} - -/*PAGE - * - * _CORE_message_queue_Prepend - * - * DESCRIPTION: - * - * This routine places the_message at the front of the outstanding - * messages on the_message_queue. - */ - -RTEMS_INLINE_ROUTINE void _CORE_message_queue_Prepend ( - CORE_message_queue_Control *the_message_queue, - CORE_message_queue_Buffer_control *the_message -) -{ - _Chain_Prepend( - &the_message_queue->Pending_messages, - &the_message->Node - ); -} - -/*PAGE - * - * _CORE_message_queue_Is_null - * - * DESCRIPTION: - * - * This function returns TRUE if the_message_queue is TRUE and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _CORE_message_queue_Is_null ( - CORE_message_queue_Control *the_message_queue -) -{ - return ( the_message_queue == NULL ); -} - -/*PAGE - * - * _CORE_message_queue_Is_notify_enabled - * - * DESCRIPTION: - * - * This function returns TRUE if notification is enabled on this message - * queue and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _CORE_message_queue_Is_notify_enabled ( - CORE_message_queue_Control *the_message_queue -) -{ - return (the_message_queue->notify_handler != NULL); -} - -/*PAGE - * - * _CORE_message_queue_Set_notify - * - * DESCRIPTION: - * - * This routine initializes the notification information for the_message_queue. - */ - -RTEMS_INLINE_ROUTINE void _CORE_message_queue_Set_notify ( - CORE_message_queue_Control *the_message_queue, - CORE_message_queue_Notify_Handler the_handler, - void *the_argument -) -{ - the_message_queue->notify_handler = the_handler; - the_message_queue->notify_argument = the_argument; -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/coremutex.inl b/c/src/exec/score/inline/rtems/score/coremutex.inl deleted file mode 100644 index b57b2ef2f4..0000000000 --- a/c/src/exec/score/inline/rtems/score/coremutex.inl +++ /dev/null @@ -1,196 +0,0 @@ -/* inline/coremutex.inl - * - * This include file contains all of the inlined routines associated - * with the CORE mutexes. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __INLINE_CORE_MUTEX_inl -#define __INLINE_CORE_MUTEX_inl - -/*PAGE - * - * _CORE_mutex_Is_locked - * - * DESCRIPTION: - * - * This routine returns TRUE if the mutex specified is locked and FALSE - * otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _CORE_mutex_Is_locked( - CORE_mutex_Control *the_mutex -) -{ - return the_mutex->lock == CORE_MUTEX_LOCKED; -} - -/*PAGE - * - * _CORE_mutex_Is_fifo - * - * DESCRIPTION: - * - * This routine returns TRUE if the mutex's wait discipline is FIFO and FALSE - * otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _CORE_mutex_Is_fifo( - CORE_mutex_Attributes *the_attribute -) -{ - return the_attribute->discipline == CORE_MUTEX_DISCIPLINES_FIFO; -} - -/*PAGE - * - * _CORE_mutex_Is_priority - * - * DESCRIPTION: - * - * This routine returns TRUE if the mutex's wait discipline is PRIORITY and - * FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _CORE_mutex_Is_priority( - CORE_mutex_Attributes *the_attribute -) -{ - return the_attribute->discipline == CORE_MUTEX_DISCIPLINES_PRIORITY; -} - -/*PAGE - * - * _CORE_mutex_Is_inherit_priority - * - * DESCRIPTION: - * - * This routine returns TRUE if the mutex's wait discipline is - * INHERIT_PRIORITY and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _CORE_mutex_Is_inherit_priority( - CORE_mutex_Attributes *the_attribute -) -{ - return the_attribute->discipline == CORE_MUTEX_DISCIPLINES_PRIORITY_INHERIT; -} - -/*PAGE - * - * _CORE_mutex_Is_priority_ceiling - * - * DESCRIPTION: - * - * This routine returns TRUE if the mutex's wait discipline is - * PRIORITY_CEILING and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _CORE_mutex_Is_priority_ceiling( - CORE_mutex_Attributes *the_attribute -) -{ - return the_attribute->discipline == CORE_MUTEX_DISCIPLINES_PRIORITY_CEILING; -} - -/*PAGE - * - * _CORE_mutex_Seize_interrupt_trylock - * - * DESCRIPTION: - * - * This routine returns 0 if "trylock" can resolve whether or not the - * mutex is immediately obtained or there was an error attempting to - * get it. It returns 1 to indicate that the caller cannot obtain - * the mutex and will have to block to do so. - * - * NOTE: There is no MACRO version of this routine. - * A body is in coremutexseize.c that is duplicated - * from the .inl by hand. - */ - -RTEMS_INLINE_ROUTINE int _CORE_mutex_Seize_interrupt_trylock( - CORE_mutex_Control *the_mutex, - ISR_Level *level_p -) -{ - Thread_Control *executing; - ISR_Level level = *level_p; - - /* disabled when you get here */ - - executing = _Thread_Executing; - executing->Wait.return_code = CORE_MUTEX_STATUS_SUCCESSFUL; - if ( !_CORE_mutex_Is_locked( the_mutex ) ) { - the_mutex->lock = CORE_MUTEX_LOCKED; - the_mutex->holder = executing; - the_mutex->holder_id = executing->Object.id; - the_mutex->nest_count = 1; - if ( _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) || - _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) - executing->resource_count++; - if ( !_CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) { - _ISR_Enable( level ); - return 0; - } - /* else must be CORE_MUTEX_DISCIPLINES_PRIORITY_CEILING */ - { - Priority_Control ceiling; - Priority_Control current; - - ceiling = the_mutex->Attributes.priority_ceiling; - current = executing->current_priority; - if ( current == ceiling ) { - _ISR_Enable( level ); - return 0; - } - if ( current > ceiling ) { - _Thread_Disable_dispatch(); - _ISR_Enable( level ); - _Thread_Change_priority( - the_mutex->holder, - the_mutex->Attributes.priority_ceiling, - FALSE - ); - _Thread_Enable_dispatch(); - return 0; - } - /* if ( current < ceiling ) */ { - executing->Wait.return_code = CORE_MUTEX_STATUS_CEILING_VIOLATED; - the_mutex->nest_count = 0; /* undo locking above */ - executing->resource_count--; /* undo locking above */ - _ISR_Enable( level ); - return 0; - } - } - return 0; - } - - if ( _Thread_Is_executing( the_mutex->holder ) ) { - switch ( the_mutex->Attributes.lock_nesting_behavior ) { - case CORE_MUTEX_NESTING_ACQUIRES: - the_mutex->nest_count++; - _ISR_Enable( level ); - return 0; - case CORE_MUTEX_NESTING_IS_ERROR: - executing->Wait.return_code = CORE_MUTEX_STATUS_NESTING_NOT_ALLOWED; - _ISR_Enable( level ); - return 0; - case CORE_MUTEX_NESTING_BLOCKS: - break; - } - } - - return 1; -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/coresem.inl b/c/src/exec/score/inline/rtems/score/coresem.inl deleted file mode 100644 index 2f5f8c7bff..0000000000 --- a/c/src/exec/score/inline/rtems/score/coresem.inl +++ /dev/null @@ -1,107 +0,0 @@ -/* inline/coresem.inl - * - * This include file contains all of the inlined routines associated - * with the CORE semaphore. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __INLINE_CORE_SEMAPHORE_inl -#define __INLINE_CORE_SEMAPHORE_inl - -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> - -/*PAGE - * - * _CORE_semaphore_Is_priority - * - * DESCRIPTION: - * - * This function returns TRUE if the priority attribute is - * enabled in the attribute_set and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _CORE_semaphore_Is_priority( - CORE_semaphore_Attributes *the_attribute -) -{ - return ( the_attribute->discipline == CORE_SEMAPHORE_DISCIPLINES_PRIORITY ); -} - -/*PAGE - * - * _CORE_semaphore_Get_count - * - * DESCRIPTION: - * - * This routine returns the current count associated with the semaphore. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _CORE_semaphore_Get_count( - CORE_semaphore_Control *the_semaphore -) -{ - return the_semaphore->count; -} - -/*PAGE - * - * _CORE_semaphore_Seize_isr_disable - * - * DESCRIPTION: - * - * This routine attempts to receive a unit from the_semaphore. - * If a unit is available or if the wait flag is FALSE, then the routine - * returns. Otherwise, the calling task is blocked until a unit becomes - * available. - * - * NOTE: There is currently no MACRO version of this routine. - */ - -RTEMS_INLINE_ROUTINE void _CORE_semaphore_Seize_isr_disable( - CORE_semaphore_Control *the_semaphore, - Objects_Id id, - boolean wait, - Watchdog_Interval timeout, - ISR_Level *level_p -) -{ - Thread_Control *executing; - ISR_Level level = *level_p; - - /* disabled when you get here */ - - executing = _Thread_Executing; - executing->Wait.return_code = CORE_SEMAPHORE_STATUS_SUCCESSFUL; - if ( the_semaphore->count != 0 ) { - the_semaphore->count -= 1; - _ISR_Enable( level ); - return; - } - - if ( !wait ) { - _ISR_Enable( level ); - executing->Wait.return_code = CORE_SEMAPHORE_STATUS_UNSATISFIED_NOWAIT; - return; - } - - _Thread_Disable_dispatch(); - _Thread_queue_Enter_critical_section( &the_semaphore->Wait_queue ); - executing->Wait.queue = &the_semaphore->Wait_queue; - executing->Wait.id = id; - _ISR_Enable( level ); - - _Thread_queue_Enqueue( &the_semaphore->Wait_queue, timeout ); - _Thread_Enable_dispatch(); -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/heap.inl b/c/src/exec/score/inline/rtems/score/heap.inl deleted file mode 100644 index 976ddfa0af..0000000000 --- a/c/src/exec/score/inline/rtems/score/heap.inl +++ /dev/null @@ -1,273 +0,0 @@ -/* heap.inl - * - * This file contains the static inline implementation of the inlined - * routines from the heap handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __HEAP_inl -#define __HEAP_inl - -#include <rtems/score/address.h> - -/*PAGE - * - * _Heap_Head - * - * DESCRIPTION: - * - * This function returns the head of the specified heap. - */ - -RTEMS_INLINE_ROUTINE Heap_Block *_Heap_Head ( - Heap_Control *the_heap -) -{ - return (Heap_Block *)&the_heap->start; -} - -/*PAGE - * - * _Heap_Tail - * - * DESCRIPTION: - * - * This function returns the tail of the specified heap. - */ - -RTEMS_INLINE_ROUTINE Heap_Block *_Heap_Tail ( - Heap_Control *the_heap -) -{ - return (Heap_Block *)&the_heap->final; -} - -/*PAGE - * - * _Heap_Previous_block - * - * DESCRIPTION: - * - * This function returns the address of the block which physically - * precedes the_block in memory. - */ - -RTEMS_INLINE_ROUTINE Heap_Block *_Heap_Previous_block ( - Heap_Block *the_block -) -{ - return (Heap_Block *) _Addresses_Subtract_offset( - (void *)the_block, - the_block->back_flag & ~ HEAP_BLOCK_USED - ); -} - -/*PAGE - * - * _Heap_Next_block - * - * DESCRIPTION: - * - * This function returns the address of the block which physically - * follows the_block in memory. - * - * NOTE: Next_block assumes that the block is free. - */ - -RTEMS_INLINE_ROUTINE Heap_Block *_Heap_Next_block ( - Heap_Block *the_block -) -{ - return (Heap_Block *) _Addresses_Add_offset( - (void *)the_block, - the_block->front_flag & ~ HEAP_BLOCK_USED - ); -} - -/*PAGE - * - * _Heap_Block_at - * - * DESCRIPTION: - * - * This function calculates and returns a block's location (address) - * in the heap based upon a base address and an offset. - */ - -RTEMS_INLINE_ROUTINE Heap_Block *_Heap_Block_at( - void *base, - unsigned32 offset -) -{ - return (Heap_Block *) _Addresses_Add_offset( (void *)base, offset ); -} - -/*PAGE - * - * _Heap_User_block_at - * - * DESCRIPTION: - * - * XXX - */ - -RTEMS_INLINE_ROUTINE Heap_Block *_Heap_User_block_at( - void *base -) -{ - unsigned32 offset; - - offset = *(((unsigned32 *) base) - 1); - return _Heap_Block_at( base, -offset + -HEAP_BLOCK_USED_OVERHEAD); -} - -/*PAGE - * - * _Heap_Is_previous_block_free - * - * DESCRIPTION: - * - * This function returns TRUE if the previous block of the_block - * is free, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Heap_Is_previous_block_free ( - Heap_Block *the_block -) -{ - return !(the_block->back_flag & HEAP_BLOCK_USED); -} - -/*PAGE - * - * _Heap_Is_block_free - * - * DESCRIPTION: - * - * This function returns TRUE if the block is free, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Heap_Is_block_free ( - Heap_Block *the_block -) -{ - return !(the_block->front_flag & HEAP_BLOCK_USED); -} - -/*PAGE - * - * _Heap_Is_block_used - * - * DESCRIPTION: - * - * This function returns TRUE if the block is currently allocated, - * and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Heap_Is_block_used ( - Heap_Block *the_block -) -{ - return (the_block->front_flag & HEAP_BLOCK_USED); -} - -/*PAGE - * - * _Heap_Block_size - * - * DESCRIPTION: - * - * This function returns the size of the_block in bytes. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _Heap_Block_size ( - Heap_Block *the_block -) -{ - return (the_block->front_flag & ~HEAP_BLOCK_USED); -} - -/*PAGE - * - * _Heap_Start_of_user_area - * - * DESCRIPTION: - * - * This function returns the starting address of the portion of the block - * which the user may access. - */ - -RTEMS_INLINE_ROUTINE void *_Heap_Start_of_user_area ( - Heap_Block *the_block -) -{ - return (void *) &the_block->next; -} - -/*PAGE - * - * _Heap_Is_block_in - * - * DESCRIPTION: - * - * This function returns TRUE if the_block is within the memory area - * managed by the_heap, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Heap_Is_block_in ( - Heap_Control *the_heap, - Heap_Block *the_block -) -{ - return _Addresses_Is_in_range( the_block, the_heap->start, the_heap->final ); -} - -/*PAGE - * - * _Heap_Is_page_size_valid - * - * DESCRIPTION: - * - * This function validates a specified heap page size. If the page size - * is 0 or if lies outside a page size alignment boundary it is invalid - * and FALSE is returned. Otherwise, the page size is valid and TRUE is - * returned. - */ - -RTEMS_INLINE_ROUTINE boolean _Heap_Is_page_size_valid( - unsigned32 page_size -) -{ - return ((page_size != 0) && - ((page_size % CPU_HEAP_ALIGNMENT) == 0)); -} - -/*PAGE - * - * _Heap_Build_flag - * - * DESCRIPTION: - * - * This function returns the block flag composed of size and in_use_flag. - * The flag returned is suitable for use as a back or front flag in a - * heap block. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _Heap_Build_flag ( - unsigned32 size, - unsigned32 in_use_flag -) -{ - return size | in_use_flag; -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/isr.inl b/c/src/exec/score/inline/rtems/score/isr.inl deleted file mode 100644 index 61ff05952a..0000000000 --- a/c/src/exec/score/inline/rtems/score/isr.inl +++ /dev/null @@ -1,55 +0,0 @@ -/* isr.inl - * - * This include file contains the static implementation of all - * inlined routines in the Interrupt Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __ISR_inl -#define __ISR_inl - -/*PAGE - * - * _ISR_Is_vector_number_valid - * - * DESCRIPTION: - * - * This function returns TRUE if the vector is a valid vector number - * for this processor and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _ISR_Is_vector_number_valid ( - unsigned32 vector -) -{ - return ( vector <= CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER ); -} - -/*PAGE - * - * _ISR_Is_valid_user_handler - * - * - * DESCRIPTION: - * - * This function returns TRUE if handler is the entry point of a valid - * use interrupt service routine and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _ISR_Is_valid_user_handler ( - void *handler -) -{ - return ( handler != NULL); -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/mppkt.inl b/c/src/exec/score/inline/rtems/score/mppkt.inl deleted file mode 100644 index 3838a96812..0000000000 --- a/c/src/exec/score/inline/rtems/score/mppkt.inl +++ /dev/null @@ -1,57 +0,0 @@ -/* inline/mppkt.inl - * - * This package is the implementation of the Packet Handler - * routines which are inlined. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __INLINE_MP_PACKET_inl -#define __INLINE_MP_PACKET_inl - -/*PAGE - * - * _Mp_packet_Is_valid_packet_class - * - * DESCRIPTION: - * - * This function returns TRUE if the the_packet_class is valid, - * and FALSE otherwise. - * - * NOTE: Check for lower bounds (MP_PACKET_CLASSES_FIRST ) is unnecessary - * because this enum starts at lower bound of zero. - */ - -RTEMS_INLINE_ROUTINE boolean _Mp_packet_Is_valid_packet_class ( - MP_packet_Classes the_packet_class -) -{ - return ( the_packet_class <= MP_PACKET_CLASSES_LAST ); -} - -/*PAGE - * - * _Mp_packet_Is_null - * - * DESCRIPTION: - * - * This function returns TRUE if the the_packet_class is null, - * and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Mp_packet_Is_null ( - MP_packet_Prefix *the_packet -) -{ - return the_packet == NULL; -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/object.inl b/c/src/exec/score/inline/rtems/score/object.inl deleted file mode 100644 index c09c09bc00..0000000000 --- a/c/src/exec/score/inline/rtems/score/object.inl +++ /dev/null @@ -1,315 +0,0 @@ -/* object.inl - * - * This include file contains the static inline implementation of all - * of the inlined routines in the Object Handler. - * - * COPYRIGHT (c) 1989-2002. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __OBJECTS_inl -#define __OBJECTS_inl - -/*PAGE - * - * _Objects_Build_id - * - * DESCRIPTION: - * - * This function builds an object's id from the processor node and index - * values specified. - */ - -RTEMS_INLINE_ROUTINE Objects_Id _Objects_Build_id( - Objects_APIs the_api, - unsigned32 the_class, - unsigned32 node, - unsigned32 index -) -{ - return (( (Objects_Id) the_api ) << OBJECTS_API_START_BIT) | - (( (Objects_Id) the_class ) << OBJECTS_CLASS_START_BIT) | - (( (Objects_Id) node ) << OBJECTS_NODE_START_BIT) | - (( (Objects_Id) index ) << OBJECTS_INDEX_START_BIT); -} - -/*PAGE - * - * _Objects_Get_API - * - * DESCRIPTION: - * - * This function returns the API portion of the ID. - */ - -RTEMS_INLINE_ROUTINE Objects_APIs _Objects_Get_API( - Objects_Id id -) -{ - return (Objects_APIs) ((id >> OBJECTS_API_START_BIT) & OBJECTS_API_VALID_BITS); -} - -/*PAGE - * - * _Objects_Get_class - * - * DESCRIPTION: - * - * This function returns the class portion of the ID. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _Objects_Get_class( - Objects_Id id -) -{ - return (unsigned32) - ((id >> OBJECTS_CLASS_START_BIT) & OBJECTS_CLASS_VALID_BITS); -} - -/*PAGE - * - * _Objects_Get_node - * - * DESCRIPTION: - * - * This function returns the node portion of the ID. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _Objects_Get_node( - Objects_Id id -) -{ - return (id >> OBJECTS_NODE_START_BIT) & OBJECTS_NODE_VALID_BITS; -} - -/*PAGE - * - * _Objects_Get_index - * - * DESCRIPTION: - * - * This function returns the index portion of the ID. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _Objects_Get_index( - Objects_Id id -) -{ - return (id >> OBJECTS_INDEX_START_BIT) & OBJECTS_INDEX_VALID_BITS; -} - -/*PAGE - * - * _Objects_Is_class_valid - * - * DESCRIPTION: - * - * This function returns TRUE if the class is valid. - */ - -RTEMS_INLINE_ROUTINE boolean _Objects_Is_class_valid( - unsigned32 the_class -) -{ - /* XXX how do we determine this now? */ - return TRUE; /* the_class && the_class <= OBJECTS_CLASSES_LAST; */ -} - -/*PAGE - * - * _Objects_Is_local_node - * - * DESCRIPTION: - * - * This function returns TRUE if the node is of the local object, and - * FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Objects_Is_local_node( - unsigned32 node -) -{ - return ( node == _Objects_Local_node ); -} - -/*PAGE - * - * _Objects_Is_local_id - * - * DESCRIPTION: - * - * This function returns TRUE if the id is of a local object, and - * FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Objects_Is_local_id( - Objects_Id id -) -{ - return _Objects_Is_local_node( _Objects_Get_node(id) ); -} - -/*PAGE - * - * _Objects_Are_ids_equal - * - * DESCRIPTION: - * - * This function returns TRUE if left and right are equal, - * and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Objects_Are_ids_equal( - Objects_Id left, - Objects_Id right -) -{ - return ( left == right ); -} - -/*PAGE - * - * _Objects_Get_local_object - * - * DESCRIPTION: - * - * This function returns a pointer to the local_table object - * referenced by the index. - */ - -RTEMS_INLINE_ROUTINE Objects_Control *_Objects_Get_local_object( - Objects_Information *information, - unsigned32 index -) -{ - if ( index > information->maximum ) - return NULL; - return information->local_table[ index ]; -} - -/*PAGE - * - * _Objects_Set_local_object - * - * DESCRIPTION: - * - * This function sets the pointer to the local_table object - * referenced by the index. - */ - -RTEMS_INLINE_ROUTINE void _Objects_Set_local_object( - Objects_Information *information, - unsigned32 index, - Objects_Control *the_object -) -{ - if ( index <= information->maximum ) - information->local_table[ index ] = the_object; -} - - -/*PAGE - * - * _Objects_Get_information - * - * DESCRIPTION: - * - * This function return the information structure given - * an id of an object. - */ - -RTEMS_INLINE_ROUTINE Objects_Information *_Objects_Get_information( - Objects_Id id -) -{ - Objects_APIs the_api; - unsigned32 the_class; - - - the_class = _Objects_Get_class( id ); - - if ( !_Objects_Is_class_valid( the_class ) ) - return NULL; - - the_api = _Objects_Get_API( id ); - return _Objects_Information_table[ the_api ][ the_class ]; -} - -/*PAGE - * - * _Objects_Open - * - * DESCRIPTION: - * - * This function places the_object control pointer and object name - * in the Local Pointer and Local Name Tables, respectively. - */ - -RTEMS_INLINE_ROUTINE void _Objects_Open( - Objects_Information *information, - Objects_Control *the_object, - Objects_Name name -) -{ - unsigned32 index; - - index = _Objects_Get_index( the_object->id ); - _Objects_Set_local_object( information, index, the_object ); - - if ( information->is_string ) - /* _Objects_Copy_name_string( name, the_object->name ); */ - the_object->name = name; - else - /* _Objects_Copy_name_raw( name, the_object->name, information->name_length ); */ - the_object->name = name; -} - -/*PAGE - * - * _Objects_Close - * - * DESCRIPTION: - * - * This function removes the_object control pointer and object name - * in the Local Pointer and Local Name Tables. - */ - -RTEMS_INLINE_ROUTINE void _Objects_Close( - Objects_Information *information, - Objects_Control *the_object -) -{ - unsigned32 index; - - index = _Objects_Get_index( the_object->id ); - _Objects_Set_local_object( information, index, NULL ); - /* _Objects_Clear_name( the_object->name, information->name_length ); */ - the_object->name = 0; -} - -/*PAGE - * - * _Objects_Namespace_remove - * - * DESCRIPTION: - * - * This function removes the_object from the namespace. - */ - -RTEMS_INLINE_ROUTINE void _Objects_Namespace_remove( - Objects_Information *information, - Objects_Control *the_object -) -{ - /* _Objects_Clear_name( the_object->name, information->name_length ); */ - the_object->name = 0; -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/objectmp.inl b/c/src/exec/score/inline/rtems/score/objectmp.inl deleted file mode 100644 index 7e840c9ca3..0000000000 --- a/c/src/exec/score/inline/rtems/score/objectmp.inl +++ /dev/null @@ -1,72 +0,0 @@ -/* inline/objectmp.inl - * - * This include file contains the bodies of all inlined routines - * which deal with global objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __INLINE_MP_OBJECTS_inl -#define __INLINE_MP_OBJECTS_inl - -/*PAGE - * - * _Objects_MP_Allocate_global_object - * - * DESCRIPTION: - * - * This function allocates a Global Object control block. - */ - -RTEMS_INLINE_ROUTINE Objects_MP_Control *_Objects_MP_Allocate_global_object ( - void -) -{ - return (Objects_MP_Control *) - _Chain_Get( &_Objects_MP_Inactive_global_objects ); -} - -/*PAGE - * - * _Objects_MP_Free_global_object - * - * DESCRIPTION: - * - * This routine deallocates a Global Object control block. - */ - -RTEMS_INLINE_ROUTINE void _Objects_MP_Free_global_object ( - Objects_MP_Control *the_object -) -{ - _Chain_Append( - &_Objects_MP_Inactive_global_objects, - &the_object->Object.Node - ); -} - -/*PAGE - * - * _Objects_MP_Is_null_global_object - * - * DESCRIPTION: - * - * This function returns whether the global object is NULL or not. - */ - -RTEMS_INLINE_ROUTINE boolean _Objects_MP_Is_null_global_object ( - Objects_MP_Control *the_object -) -{ - return( the_object == NULL ); -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/priority.inl b/c/src/exec/score/inline/rtems/score/priority.inl deleted file mode 100644 index 4928dba5ef..0000000000 --- a/c/src/exec/score/inline/rtems/score/priority.inl +++ /dev/null @@ -1,246 +0,0 @@ -/* priority.inl - * - * This file contains the static inline implementation of all inlined - * routines in the Priority Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __PRIORITY_inl -#define __PRIORITY_inl - -#include <rtems/score/bitfield.h> - -/*PAGE - * - * _Priority_Handler_initialization - * - * DESCRIPTION: - * - * This routine performs the initialization necessary for this handler. - */ - -RTEMS_INLINE_ROUTINE void _Priority_Handler_initialization( void ) -{ - unsigned32 index; - - _Priority_Major_bit_map = 0; - for ( index=0 ; index <16 ; index++ ) - _Priority_Bit_map[ index ] = 0; -} - -/*PAGE - * - * _Priority_Is_valid - * - * DESCRIPTION: - * - * This function returns TRUE if the_priority if valid for a - * user task, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Priority_Is_valid ( - Priority_Control the_priority -) -{ - /* - * Since PRIORITY_MINIMUM is 0 and priorities are stored unsigned, - * then checking for less than 0 is unnecessary. - */ - - return ( the_priority <= PRIORITY_MAXIMUM ); -} - -/*PAGE - * - * _Priority_Major - * - * DESCRIPTION: - * - * This function returns the major portion of the_priority. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _Priority_Major ( - Priority_Control the_priority -) -{ - return ( the_priority / 16 ); -} - -/*PAGE - * - * _Priority_Minor - * - * DESCRIPTION: - * - * This function returns the minor portion of the_priority. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _Priority_Minor ( - Priority_Control the_priority -) -{ - return ( the_priority % 16 ); -} - -#if ( CPU_USE_GENERIC_BITFIELD_CODE == TRUE ) - -/*PAGE - * - * _Priority_Mask - * - * DESCRIPTION: - * - * This function returns the mask associated with the major or minor - * number passed to it. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _Priority_Mask ( - unsigned32 bit_number -) -{ - return (0x8000 >> bit_number); -} - - -/*PAGE - * - * _Priority_Bits_index - * - * DESCRIPTION: - * - * This function translates the bit numbers returned by the bit scan - * of a priority bit field into something suitable for use as - * a major or minor component of a priority. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _Priority_Bits_index ( - unsigned32 bit_number -) -{ - return bit_number; -} - -#endif - -/*PAGE - * - * _Priority_Add_to_bit_map - * - * DESCRIPTION: - * - * This routine uses the_priority_map to update the priority - * bit maps to indicate that a thread has been readied. - */ - -RTEMS_INLINE_ROUTINE void _Priority_Add_to_bit_map ( - Priority_Information *the_priority_map -) -{ - *the_priority_map->minor |= the_priority_map->ready_minor; - _Priority_Major_bit_map |= the_priority_map->ready_major; -} - -/*PAGE - * - * _Priority_Remove_from_bit_map - * - * DESCRIPTION: - * - * This routine uses the_priority_map to update the priority - * bit maps to indicate that a thread has been removed from the - * ready state. - */ - -RTEMS_INLINE_ROUTINE void _Priority_Remove_from_bit_map ( - Priority_Information *the_priority_map -) -{ - *the_priority_map->minor &= the_priority_map->block_minor; - if ( *the_priority_map->minor == 0 ) - _Priority_Major_bit_map &= the_priority_map->block_major; -} - -/*PAGE - * - * _Priority_Get_highest - * - * DESCRIPTION: - * - * This function returns the priority of the highest priority - * ready thread. - */ - -RTEMS_INLINE_ROUTINE Priority_Control _Priority_Get_highest( void ) -{ - Priority_Bit_map_control minor; - Priority_Bit_map_control major; - - _Bitfield_Find_first_bit( _Priority_Major_bit_map, major ); - _Bitfield_Find_first_bit( _Priority_Bit_map[major], minor ); - - return (_Priority_Bits_index( major ) << 4) + - _Priority_Bits_index( minor ); -} - -/*PAGE - * - * _Priority_Initialize_information - * - * DESCRIPTION: - * - * This routine initializes the_priority_map so that it - * contains the information necessary to manage a thread - * at new_priority. - */ - -RTEMS_INLINE_ROUTINE void _Priority_Initialize_information( - Priority_Information *the_priority_map, - Priority_Control new_priority -) -{ - Priority_Bit_map_control major; - Priority_Bit_map_control minor; - Priority_Bit_map_control mask; - - major = _Priority_Major( new_priority ); - minor = _Priority_Minor( new_priority ); - - the_priority_map->minor = - &_Priority_Bit_map[ _Priority_Bits_index(major) ]; - - mask = _Priority_Mask( major ); - the_priority_map->ready_major = mask; - the_priority_map->block_major = ~mask; - - mask = _Priority_Mask( minor ); - the_priority_map->ready_minor = mask; - the_priority_map->block_minor = ~mask; -} - -/*PAGE - * - * _Priority_Is_group_empty - * - * DESCRIPTION: - * - * This function returns TRUE if the priority GROUP is empty, and - * FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Priority_Is_group_empty ( - Priority_Control the_priority -) -{ - return the_priority == 0; -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/stack.inl b/c/src/exec/score/inline/rtems/score/stack.inl deleted file mode 100644 index ea7f2f1c36..0000000000 --- a/c/src/exec/score/inline/rtems/score/stack.inl +++ /dev/null @@ -1,80 +0,0 @@ -/* stack.inl - * - * This file contains the static inline implementation of the inlined - * routines from the Stack Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __STACK_inl -#define __STACK_inl - -/*PAGE - * - * _Stack_Initialize - * - * DESCRIPTION: - * - * This routine initializes the_stack record to indicate that - * size bytes of memory starting at starting_address have been - * reserved for a stack. - */ - -RTEMS_INLINE_ROUTINE void _Stack_Initialize ( - Stack_Control *the_stack, - void *starting_address, - unsigned32 size -) -{ - the_stack->area = starting_address; - the_stack->size = size; -} - -/*PAGE - * - * _Stack_Is_enough - * - * DESCRIPTION: - * - * This function returns TRUE if size bytes is enough memory for - * a valid stack area on this processor, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Stack_Is_enough ( - unsigned32 size -) -{ - return ( size >= STACK_MINIMUM_SIZE ); -} - -/*PAGE - * - * _Stack_Adjust_size - * - * DESCRIPTION: - * - * This function increases the stack size to insure that the thread - * has the desired amount of stack space after the initial stack - * pointer is determined based on alignment restrictions. - * - * NOTE: - * - * The amount of adjustment for alignment is CPU dependent. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _Stack_Adjust_size ( - unsigned32 size -) -{ - return size + CPU_STACK_ALIGNMENT; -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/states.inl b/c/src/exec/score/inline/rtems/score/states.inl deleted file mode 100644 index 5d57648f23..0000000000 --- a/c/src/exec/score/inline/rtems/score/states.inl +++ /dev/null @@ -1,383 +0,0 @@ -/* states.inl - * - * This file contains the macro implementation of the inlined - * routines associated with thread state information. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __STATES_inl -#define __STATES_inl - -/*PAGE - * - * _States_Set - * - * DESCRIPTION: - * - * This function sets the given states_to_set into the current_state - * passed in. The result is returned to the user in current_state. - */ - -RTEMS_INLINE_ROUTINE States_Control _States_Set ( - States_Control states_to_set, - States_Control current_state -) -{ - return (current_state | states_to_set); -} - -/*PAGE - * - * _States_Clear - * - * DESCRIPTION: - * - * This function clears the given states_to_clear into the current_state - * passed in. The result is returned to the user in current_state. - */ - -RTEMS_INLINE_ROUTINE States_Control _States_Clear ( - States_Control states_to_clear, - States_Control current_state -) -{ - return (current_state & ~states_to_clear); -} - -/*PAGE - * - * _States_Is_ready - * - * DESCRIPTION: - * - * This function returns TRUE if the_states indicates that the - * state is READY, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_ready ( - States_Control the_states -) -{ - return (the_states == STATES_READY); -} - -/*PAGE - * - * _States_Is_only_dormant - * - * DESCRIPTION: - * - * This function returns TRUE if the DORMANT state is the ONLY state - * set in the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_only_dormant ( - States_Control the_states -) -{ - return (the_states == STATES_DORMANT); -} - -/*PAGE - * - * _States_Is_dormant - * - * DESCRIPTION: - * - * This function returns TRUE if the DORMANT state is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_dormant ( - States_Control the_states -) -{ - return (the_states & STATES_DORMANT); -} - -/*PAGE - * - * _States_Is_suspended - * - * DESCRIPTION: - * - * This function returns TRUE if the SUSPENDED state is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_suspended ( - States_Control the_states -) -{ - return (the_states & STATES_SUSPENDED); -} - -/*PAGE - * - * _States_Is_Transient - * - * DESCRIPTION: - * - * This function returns TRUE if the TRANSIENT state is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_transient ( - States_Control the_states -) -{ - return (the_states & STATES_TRANSIENT); -} - -/*PAGE - * - * _States_Is_delaying - * - * DESCRIPTION: - * - * This function returns TRUE if the DELAYING state is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_delaying ( - States_Control the_states -) -{ - return (the_states & STATES_DELAYING); -} - -/*PAGE - * - * _States_Is_waiting_for_buffer - * - * DESCRIPTION: - * - * This function returns TRUE if the WAITING_FOR_BUFFER state is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_waiting_for_buffer ( - States_Control the_states -) -{ - return (the_states & STATES_WAITING_FOR_BUFFER); -} - -/*PAGE - * - * _States_Is_waiting_for_segment - * - * DESCRIPTION: - * - * This function returns TRUE if the WAITING_FOR_SEGMENT state is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_waiting_for_segment ( - States_Control the_states -) -{ - return (the_states & STATES_WAITING_FOR_SEGMENT); -} - -/*PAGE - * - * _States_Is_waiting_for_message - * - * DESCRIPTION: - * - * This function returns TRUE if the WAITING_FOR_MESSAGE state is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_waiting_for_message ( - States_Control the_states -) -{ - return (the_states & STATES_WAITING_FOR_MESSAGE); -} - -/*PAGE - * - * _States_Is_waiting_for_event - * - * DESCRIPTION: - * - * This function returns TRUE if the WAITING_FOR_EVENT state is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_waiting_for_event ( - States_Control the_states -) -{ - return (the_states & STATES_WAITING_FOR_EVENT); -} - -/*PAGE - * - * _States_Is_waiting_for_mutex - * - * DESCRIPTION: - * - * This function returns TRUE if the WAITING_FOR_MUTEX state - * is set in the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_waiting_for_mutex ( - States_Control the_states -) -{ - return (the_states & STATES_WAITING_FOR_MUTEX); -} - -/*PAGE - * - * _States_Is_waiting_for_semaphore - * - * DESCRIPTION: - * - * This function returns TRUE if the WAITING_FOR_SEMAPHORE state - * is set in the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_waiting_for_semaphore ( - States_Control the_states -) -{ - return (the_states & STATES_WAITING_FOR_SEMAPHORE); -} - -/*PAGE - * - * _States_Is_waiting_for_time - * - * DESCRIPTION: - * - * This function returns TRUE if the WAITING_FOR_TIME state is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_waiting_for_time ( - States_Control the_states -) -{ - return (the_states & STATES_WAITING_FOR_TIME); -} - -/*PAGE - * - * _States_Is_waiting_for_rpc_reply - * - * DESCRIPTION: - * - * This function returns TRUE if the WAITING_FOR_TIME state is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_waiting_for_rpc_reply ( - States_Control the_states -) -{ - return (the_states & STATES_WAITING_FOR_RPC_REPLY); -} - -/*PAGE - * - * _States_Is_waiting_for_period - * - * DESCRIPTION: - * - * This function returns TRUE if the WAITING_FOR_PERIOD state is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_waiting_for_period ( - States_Control the_states -) -{ - return (the_states & STATES_WAITING_FOR_PERIOD); -} - -/*PAGE - * - * _States_Is_locally_blocked - * - * DESCRIPTION: - * - * This function returns TRUE if one of the states which indicates - * that a task is blocked waiting for a local resource is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_locally_blocked ( - States_Control the_states -) -{ - return (the_states & STATES_LOCALLY_BLOCKED); -} - -/*PAGE - * - * _States_Is_waiting_on_thread_queue - * - * DESCRIPTION: - * - * This function returns TRUE if one of the states which indicates - * that a task is blocked waiting for a local resource is set in - * the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_waiting_on_thread_queue ( - States_Control the_states -) -{ - return (the_states & STATES_WAITING_ON_THREAD_QUEUE); -} - -/*PAGE - * - * _States_Is_blocked - * - * DESCRIPTION: - * - * This function returns TRUE if one of the states which indicates - * that a task is blocked is set in the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Is_blocked ( - States_Control the_states -) -{ - return (the_states & STATES_BLOCKED); -} - -/*PAGE - * - * - * _States_Are_set - * - * DESCRIPTION: - * - * This function returns TRUE if any of the states in the mask - * are set in the_states, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _States_Are_set ( - States_Control the_states, - States_Control mask -) -{ - return ( (the_states & mask) != STATES_READY); -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/sysstate.inl b/c/src/exec/score/inline/rtems/score/sysstate.inl deleted file mode 100644 index 17976f3e3f..0000000000 --- a/c/src/exec/score/inline/rtems/score/sysstate.inl +++ /dev/null @@ -1,153 +0,0 @@ -/* sysstates.inl - * - * This file contains the inline implementation of routines regarding the - * system state. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __SYSTEM_STATE_inl -#define __SYSTEM_STATE_inl - -/*PAGE - * - * _System_state_Handler_initialization - * - * DESCRIPTION: - * - * This routine initializes the system state handler. - */ - -RTEMS_INLINE_ROUTINE void _System_state_Handler_initialization ( - boolean is_multiprocessing -) -{ - _System_state_Current = SYSTEM_STATE_BEFORE_INITIALIZATION; - _System_state_Is_multiprocessing = is_multiprocessing; -} - -/*PAGE - * - * _System_state_Set - * - * DESCRIPTION: - * - * This routine sets the current system state to that specified by - * the called. - */ - -RTEMS_INLINE_ROUTINE void _System_state_Set ( - System_state_Codes state -) -{ - _System_state_Current = state; -} - -/*PAGE - * - * _System_state_Get - * - * DESCRIPTION: - * - * This function returns the current system state. - */ - -RTEMS_INLINE_ROUTINE System_state_Codes _System_state_Get ( void ) -{ - return _System_state_Current; -} - -/*PAGE - * - * _System_state_Is_before_initialization - * - * DESCRIPTION: - * - * This function returns TRUE if the state is equal to the - * "before initialization" state, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _System_state_Is_before_initialization ( - System_state_Codes state -) -{ - return (state == SYSTEM_STATE_BEFORE_INITIALIZATION); -} - -/*PAGE - * - * _System_state_Is_before_multitasking - * - * DESCRIPTION: - * - * This function returns TRUE if the state is equal to the - * "before multitasking" state, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _System_state_Is_before_multitasking ( - System_state_Codes state -) -{ - return (state == SYSTEM_STATE_BEFORE_MULTITASKING); -} - -/*PAGE - * - * _System_state_Is_begin_multitasking - * - * DESCRIPTION: - * - * This function returns TRUE if the state is equal to the - * "begin multitasking" state, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _System_state_Is_begin_multitasking ( - System_state_Codes state -) -{ - return (state == SYSTEM_STATE_BEGIN_MULTITASKING); -} - -/*PAGE - * - * _System_state_Is_up - * - * DESCRIPTION: - * - * This function returns TRUE if the state is equal to the - * "up" state, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _System_state_Is_up ( - System_state_Codes state -) -{ - return (state == SYSTEM_STATE_UP); -} - -/*PAGE - * - * _System_state_Is_failed - * - * DESCRIPTION: - * - * This function returns TRUE if the state is equal to the - * "failed" state, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _System_state_Is_failed ( - System_state_Codes state -) -{ - return (state == SYSTEM_STATE_FAILED); -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/thread.inl b/c/src/exec/score/inline/rtems/score/thread.inl deleted file mode 100644 index 72d7a5dac5..0000000000 --- a/c/src/exec/score/inline/rtems/score/thread.inl +++ /dev/null @@ -1,427 +0,0 @@ -/* thread.inl - * - * This file contains the macro implementation of the inlined - * routines from the Thread handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __THREAD_inl -#define __THREAD_inl - -/*PAGE - * - * _Thread_Stop_multitasking - * - * DESCRIPTION: - * - * This routine halts multitasking and returns control to - * the "thread" (i.e. the BSP) which initially invoked the - * routine which initialized the system. - */ - -RTEMS_INLINE_ROUTINE void _Thread_Stop_multitasking( void ) -{ - _Context_Switch( &_Thread_Executing->Registers, &_Thread_BSP_context ); -} - -/*PAGE - * - * _Thread_Is_executing - * - * DESCRIPTION: - * - * This function returns TRUE if the_thread is the currently executing - * thread, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Thread_Is_executing ( - Thread_Control *the_thread -) -{ - return ( the_thread == _Thread_Executing ); -} - -/*PAGE - * - * _Thread_Is_heir - * - * DESCRIPTION: - * - * This function returns TRUE if the_thread is the heir - * thread, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Thread_Is_heir ( - Thread_Control *the_thread -) -{ - return ( the_thread == _Thread_Heir ); -} - -/*PAGE - * - * _Thread_Is_executing_also_the_heir - * - * DESCRIPTION: - * - * This function returns TRUE if the currently executing thread - * is also the heir thread, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Thread_Is_executing_also_the_heir( void ) -{ - return ( _Thread_Executing == _Thread_Heir ); -} - -/*PAGE - * - * _Thread_Unblock - * - * DESCRIPTION: - * - * This routine clears any blocking state for the_thread. It performs - * any necessary scheduling operations including the selection of - * a new heir thread. - */ - -RTEMS_INLINE_ROUTINE void _Thread_Unblock ( - Thread_Control *the_thread -) -{ - _Thread_Clear_state( the_thread, STATES_BLOCKED ); -} - -/*PAGE - * - * _Thread_Restart_self - * - * DESCRIPTION: - * - * This routine resets the current context of the calling thread - * to that of its initial state. - */ - -RTEMS_INLINE_ROUTINE void _Thread_Restart_self( void ) -{ -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) - if ( _Thread_Executing->fp_context != NULL ) - _Context_Restore_fp( &_Thread_Executing->fp_context ); -#endif - - _CPU_Context_Restart_self( &_Thread_Executing->Registers ); -} - -/*PAGE - * - * _Thread_Calculate_heir - * - * DESCRIPTION: - * - * This function returns a pointer to the highest priority - * ready thread. - */ - -RTEMS_INLINE_ROUTINE void _Thread_Calculate_heir( void ) -{ - _Thread_Heir = (Thread_Control *) - _Thread_Ready_chain[ _Priority_Get_highest() ].first; -} - -/*PAGE - * - * _Thread_Is_allocated_fp - * - * DESCRIPTION: - * - * This function returns TRUE if the floating point context of - * the_thread is currently loaded in the floating point unit, and - * FALSE otherwise. - */ - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) -RTEMS_INLINE_ROUTINE boolean _Thread_Is_allocated_fp ( - Thread_Control *the_thread -) -{ - return ( the_thread == _Thread_Allocated_fp ); -} -#endif - -/*PAGE - * - * _Thread_Deallocate_fp - * - * DESCRIPTION: - * - * This routine is invoked when the currently loaded floating - * point context is now longer associated with an active thread. - */ - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) -RTEMS_INLINE_ROUTINE void _Thread_Deallocate_fp( void ) -{ - _Thread_Allocated_fp = NULL; -} -#endif - -/*PAGE - * - * _Thread_Disable_dispatch - * - * DESCRIPTION: - * - * This routine prevents dispatching. - */ - -RTEMS_INLINE_ROUTINE void _Thread_Disable_dispatch( void ) -{ - _Thread_Dispatch_disable_level += 1; -} - -/*PAGE - * - * _Thread_Enable_dispatch - * - * DESCRIPTION: - * - * This routine allows dispatching to occur again. If this is - * the outer most dispatching critical section, then a dispatching - * operation will be performed and, if necessary, control of the - * processor will be transferred to the heir thread. - */ - -#if ( CPU_INLINE_ENABLE_DISPATCH == TRUE ) -RTEMS_INLINE_ROUTINE void _Thread_Enable_dispatch() -{ - if ( (--_Thread_Dispatch_disable_level) == 0 ) - _Thread_Dispatch(); -} -#endif - -#if ( CPU_INLINE_ENABLE_DISPATCH == FALSE ) -void _Thread_Enable_dispatch( void ); -#endif - -/*PAGE - * - * _Thread_Unnest_dispatch - * - * DESCRIPTION: - * - * This routine allows dispatching to occur again. However, - * no dispatching operation is performed even if this is the outer - * most dispatching critical section. - */ - -RTEMS_INLINE_ROUTINE void _Thread_Unnest_dispatch( void ) -{ - _Thread_Dispatch_disable_level -= 1; -} - -/*PAGE - * - * _Thread_Is_dispatching_enabled - * - * DESCRIPTION: - * - * This function returns TRUE if dispatching is disabled, and FALSE - * otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Thread_Is_dispatching_enabled( void ) -{ - return ( _Thread_Dispatch_disable_level == 0 ); -} - -/*PAGE - * - * _Thread_Is_context_switch_necessary - * - * DESCRIPTION: - * - * This function returns TRUE if dispatching is disabled, and FALSE - * otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Thread_Is_context_switch_necessary( void ) -{ - return ( _Context_Switch_necessary ); -} - -/*PAGE - * - * _Thread_Dispatch_initialization - * - * DESCRIPTION: - * - * This routine initializes the thread dispatching subsystem. - */ - -RTEMS_INLINE_ROUTINE void _Thread_Dispatch_initialization( void ) -{ - _Thread_Dispatch_disable_level = 1; -} - -/*PAGE - * - * _Thread_Is_null - * - * DESCRIPTION: - * - * This function returns TRUE if the_thread is NULL and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Thread_Is_null ( - Thread_Control *the_thread -) -{ - return ( the_thread == NULL ); -} - -/*PAGE - * - * _Thread_Get - * - * DESCRIPTION: - * - * This function maps thread IDs to thread control - * blocks. If ID corresponds to a local thread, then it - * returns the_thread control pointer which maps to ID - * and location is set to OBJECTS_LOCAL. If the thread ID is - * global and resides on a remote node, then location is set - * to OBJECTS_REMOTE, and the_thread is undefined. - * Otherwise, location is set to OBJECTS_ERROR and - * the_thread is undefined. - * - * NOTE: XXX... This routine may be able to be optimized. - */ - -RTEMS_INLINE_ROUTINE Thread_Control *_Thread_Get ( - Objects_Id id, - Objects_Locations *location -) -{ - unsigned32 the_api; - unsigned32 the_class; - Objects_Information *information; - Thread_Control *tp = (Thread_Control *) 0; - - if ( _Objects_Are_ids_equal( id, OBJECTS_ID_OF_SELF ) ) { - _Thread_Disable_dispatch(); - *location = OBJECTS_LOCAL; - tp = _Thread_Executing; - goto done; - } - - the_api = _Objects_Get_API( id ); - if ( the_api && the_api > OBJECTS_APIS_LAST ) { - *location = OBJECTS_ERROR; - goto done; - } - - the_class = _Objects_Get_class( id ); - if ( the_class != 1 ) { /* threads are always first class :) */ - *location = OBJECTS_ERROR; - goto done; - } - - information = _Objects_Information_table[ the_api ][ the_class ]; - - if ( !information ) { - *location = OBJECTS_ERROR; - goto done; - } - - tp = (Thread_Control *) _Objects_Get( information, id, location ); - -done: - return tp; -} - - -/* - * _Thread_Is_proxy_blocking - * - * DESCRIPTION: - * - * This function returns TRUE if the status code is equal to the - * status which indicates that a proxy is blocking, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Thread_Is_proxy_blocking ( - unsigned32 code -) -{ - return (code == THREAD_STATUS_PROXY_BLOCKING); -} - -/*PAGE - * - * _Thread_Internal_allocate - * - * DESCRIPTION: - * - * This routine allocates an internal thread. - */ - -RTEMS_INLINE_ROUTINE Thread_Control *_Thread_Internal_allocate( void ) -{ - return (Thread_Control *) _Objects_Allocate( &_Thread_Internal_information ); -} - -/*PAGE - * - * _Thread_Internal_free - * - * DESCRIPTION: - * - * This routine frees an internal thread. - */ - -RTEMS_INLINE_ROUTINE void _Thread_Internal_free ( - Thread_Control *the_task -) -{ - _Objects_Free( &_Thread_Internal_information, &the_task->Object ); -} - -/*PAGE - * - * _Thread_Get_libc_reent - * - * DESCRIPTION: - * - * This routine returns the C library re-enterant pointer. - */ - -RTEMS_INLINE_ROUTINE void **_Thread_Get_libc_reent( void ) -{ - return _Thread_libc_reent; -} - -/*PAGE - * - * _Thread_Set_libc_reent - * - * DESCRIPTION: - * - * This routine set the C library re-enterant pointer. - */ - -RTEMS_INLINE_ROUTINE void _Thread_Set_libc_reent ( - void **libc_reent -) -{ - _Thread_libc_reent = libc_reent; -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/threadmp.inl b/c/src/exec/score/inline/rtems/score/threadmp.inl deleted file mode 100644 index c095fd5072..0000000000 --- a/c/src/exec/score/inline/rtems/score/threadmp.inl +++ /dev/null @@ -1,60 +0,0 @@ -/* inline/threadmp.inl - * - * This include file contains the bodies of all inlined routines - * for the multiprocessing part of thread package. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __INLINE_MP_THREAD_inl -#define __INLINE_MP_THREAD_inl - -/*PAGE - * - * _Thread_MP_Is_receive - * - * DESCRIPTION: - * - * This function returns true if the thread in question is the - * multiprocessing receive thread. - */ - -RTEMS_INLINE_ROUTINE boolean _Thread_MP_Is_receive ( - Thread_Control *the_thread -) -{ - return the_thread == _Thread_MP_Receive; -} - -/*PAGE - * - * _Thread_MP_Free_proxy - * - * DESCRIPTION: - * - * This routine frees a proxy control block to the - * inactive chain of free proxy control blocks. - */ - -RTEMS_INLINE_ROUTINE void _Thread_MP_Free_proxy ( - Thread_Control *the_thread -) -{ - Thread_Proxy_control *the_proxy; - - the_proxy = (Thread_Proxy_control *) the_thread; - - _Chain_Extract( &the_proxy->Active ); - - _Chain_Append( &_Thread_MP_Inactive_proxies, &the_thread->Object.Node ); -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/tod.inl b/c/src/exec/score/inline/rtems/score/tod.inl deleted file mode 100644 index 2d429a8005..0000000000 --- a/c/src/exec/score/inline/rtems/score/tod.inl +++ /dev/null @@ -1,66 +0,0 @@ -/* tod.inl - * - * This file contains the static inline implementation of the inlined routines - * from the Time of Day Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __TIME_OF_DAY_inl -#define __TIME_OF_DAY_inl - -/*PAGE - * - * _TOD_Tickle_ticks - * - * DESCRIPTION: - * - * This routine increments the ticks field of the current time of - * day at each clock tick. - */ - -RTEMS_INLINE_ROUTINE void _TOD_Tickle_ticks( void ) -{ - _TOD_Current.ticks += 1; - _Watchdog_Ticks_since_boot += 1; -} - -/*PAGE - * - * _TOD_Deactivate - * - * DESCRIPTION: - * - * This routine deactivates updating of the current time of day. - */ - -RTEMS_INLINE_ROUTINE void _TOD_Deactivate( void ) -{ - _Watchdog_Remove( &_TOD_Seconds_watchdog ); -} - -/*PAGE - * - * _TOD_Activate - * - * DESCRIPTION: - * - * This routine activates updating of the current time of day. - */ - -RTEMS_INLINE_ROUTINE void _TOD_Activate( - Watchdog_Interval ticks -) -{ - _Watchdog_Insert_ticks( &_TOD_Seconds_watchdog, ticks ); -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/tqdata.inl b/c/src/exec/score/inline/rtems/score/tqdata.inl deleted file mode 100644 index 201abeb82f..0000000000 --- a/c/src/exec/score/inline/rtems/score/tqdata.inl +++ /dev/null @@ -1,72 +0,0 @@ -/* tqdata.inl - * - * This file contains the static inline implementation of the inlined - * routines needed to support the Thread Queue Data. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __THREAD_QUEUE_DATA_inl -#define __THREAD_QUEUE_DATA_inl - -/*PAGE - * - * _Thread_queue_Header_number - * - * DESCRIPTION: - * - * This function returns the index of the priority chain on which - * a thread of the_priority should be placed. - */ - -RTEMS_INLINE_ROUTINE unsigned32 _Thread_queue_Header_number ( - Priority_Control the_priority -) -{ - return (the_priority / TASK_QUEUE_DATA_PRIORITIES_PER_HEADER); -} - -/*PAGE - * - * _Thread_queue_Is_reverse_search - * - * DESCRIPTION: - * - * This function returns TRUE if the_priority indicates that the - * enqueue search should start at the front of this priority - * group chain, and FALSE if the search should start at the rear. - */ - -RTEMS_INLINE_ROUTINE boolean _Thread_queue_Is_reverse_search ( - Priority_Control the_priority -) -{ - return ( the_priority & TASK_QUEUE_DATA_REVERSE_SEARCH_MASK ); -} - -/*PAGE - * - * _Thread_queue_Enter_critical_section - * - * DESCRIPTION: - * - * This routine is invoked to indicate that the specified thread queue is - * entering a critical section. - */ - -RTEMS_INLINE_ROUTINE void _Thread_queue_Enter_critical_section ( - Thread_queue_Control *the_thread_queue -) -{ - the_thread_queue->sync_state = THREAD_QUEUE_NOTHING_HAPPENED; -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/userext.inl b/c/src/exec/score/inline/rtems/score/userext.inl deleted file mode 100644 index ef225bc8e0..0000000000 --- a/c/src/exec/score/inline/rtems/score/userext.inl +++ /dev/null @@ -1,169 +0,0 @@ -/* userext.inl - * - * This file contains the macro implementation of the inlined routines - * from the User Extension Handler - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __USER_EXTENSIONS_inl -#define __USER_EXTENSIONS_inl - -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _User_extensions_Add_set - * - * DESCRIPTION: - * - * This routine is used to add a user extension set to the active list. - * - * NOTE: Must be before _User_extensions_Handler_initialization to - * ensure proper inlining. - */ - -RTEMS_INLINE_ROUTINE void _User_extensions_Add_set ( - User_extensions_Control *the_extension, - User_extensions_Table *extension_table -) -{ - the_extension->Callouts = *extension_table; - - _Chain_Append( &_User_extensions_List, &the_extension->Node ); - - /* - * If a switch handler is present, append it to the switch chain. - */ - - if ( extension_table->thread_switch != NULL ) { - the_extension->Switch.thread_switch = extension_table->thread_switch; - _Chain_Append( &_User_extensions_Switches_list, &the_extension->Switch.Node ); - } -} - -/*PAGE - * - * _User_extensions_Handler_initialization - * - * DESCRIPTION: - * - * This routine performs the initialization necessary for this handler. - */ - -RTEMS_INLINE_ROUTINE void _User_extensions_Handler_initialization ( - unsigned32 number_of_extensions, - User_extensions_Table *initial_extensions -) -{ - User_extensions_Control *extension; - unsigned32 i; - - _Chain_Initialize_empty( &_User_extensions_List ); - _Chain_Initialize_empty( &_User_extensions_Switches_list ); - - if ( initial_extensions ) { - extension = - _Workspace_Allocate_or_fatal_error( - number_of_extensions * sizeof( User_extensions_Control ) - ); - - memset ( - extension, - 0, - number_of_extensions * sizeof( User_extensions_Control ) - ); - - for ( i = 0 ; i < number_of_extensions ; i++ ) { - _User_extensions_Add_set (extension, &initial_extensions[i]); - extension++; - } - } -} - -/*PAGE - * - * _User_extensions_Add_API_set - * - * DESCRIPTION: - * - * This routine is used to add an API extension set to the active list. - */ - -RTEMS_INLINE_ROUTINE void _User_extensions_Add_API_set ( - User_extensions_Control *the_extension -) -{ - _Chain_Append( &_User_extensions_List, &the_extension->Node ); - - /* - * If a switch handler is present, append it to the switch chain. - */ - - if ( the_extension->Callouts.thread_switch != NULL ) { - the_extension->Switch.thread_switch = the_extension->Callouts.thread_switch; - _Chain_Append( - &_User_extensions_Switches_list, &the_extension->Switch.Node ); - } -} - -/*PAGE - * - * _User_extensions_Remove_set - * - * DESCRIPTION: - * - * This routine is used to remove a user extension set from the active list. - */ - -RTEMS_INLINE_ROUTINE void _User_extensions_Remove_set ( - User_extensions_Control *the_extension -) -{ - _Chain_Extract( &the_extension->Node ); - - /* - * If a switch handler is present, remove it. - */ - - if ( the_extension->Callouts.thread_switch != NULL ) - _Chain_Extract( &the_extension->Switch.Node ); -} - -/*PAGE - * - * _User_extensions_Thread_switch - * - * DESCRIPTION: - * - * This routine is used to invoke the user extension which - * is invoked when a context switch occurs. - */ - -RTEMS_INLINE_ROUTINE void _User_extensions_Thread_switch ( - Thread_Control *executing, - Thread_Control *heir -) -{ - Chain_Node *the_node; - User_extensions_Switch_control *the_extension_switch; - - for ( the_node = _User_extensions_Switches_list.first ; - !_Chain_Is_tail( &_User_extensions_Switches_list, the_node ) ; - the_node = the_node->next ) { - - the_extension_switch = (User_extensions_Switch_control *) the_node; - - (*the_extension_switch->thread_switch)( executing, heir ); - } -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/watchdog.inl b/c/src/exec/score/inline/rtems/score/watchdog.inl deleted file mode 100644 index 5b87c00f17..0000000000 --- a/c/src/exec/score/inline/rtems/score/watchdog.inl +++ /dev/null @@ -1,323 +0,0 @@ -/* watchdog.inl - * - * This file contains the static inline implementation of all inlined - * routines in the Watchdog Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __WATCHDOG_inl -#define __WATCHDOG_inl - -/*PAGE - * - * _Watchdog_Initialize - * - * DESCRIPTION: - * - * This routine initializes the specified watchdog. The watchdog is - * made inactive, the watchdog id and handler routine are set to the - * specified values. - */ - -RTEMS_INLINE_ROUTINE void _Watchdog_Initialize( - Watchdog_Control *the_watchdog, - Watchdog_Service_routine_entry routine, - Objects_Id id, - void *user_data -) -{ - the_watchdog->state = WATCHDOG_INACTIVE; - the_watchdog->routine = routine; - the_watchdog->id = id; - the_watchdog->user_data = user_data; -} - -/*PAGE - * - * _Watchdog_Is_active - * - * DESCRIPTION: - * - * This routine returns TRUE if the watchdog timer is in the ACTIVE - * state, and FALSE otherwise. - */ - -RTEMS_INLINE_ROUTINE boolean _Watchdog_Is_active( - Watchdog_Control *the_watchdog -) -{ - - return ( the_watchdog->state == WATCHDOG_ACTIVE ); - -} - -/*PAGE - * - * _Watchdog_Activate - * - * DESCRIPTION: - * - * This routine activates THE_WATCHDOG timer which is already - * on a watchdog chain. - */ - -RTEMS_INLINE_ROUTINE void _Watchdog_Activate( - Watchdog_Control *the_watchdog -) -{ - - the_watchdog->state = WATCHDOG_ACTIVE; - -} - -/*PAGE - * - * _Watchdog_Deactivate - * - * DESCRIPTION: - * - * This routine deactivates THE_WATCHDOG timer which will remain - * on a watchdog chain. - */ - -RTEMS_INLINE_ROUTINE void _Watchdog_Deactivate( - Watchdog_Control *the_watchdog -) -{ - - the_watchdog->state = WATCHDOG_REMOVE_IT; - -} - -/*PAGE - * - * _Watchdog_Tickle_ticks - * - * DESCRIPTION: - * - * This routine is invoked at each clock tick to update the ticks - * watchdog chain. - */ - -RTEMS_INLINE_ROUTINE void _Watchdog_Tickle_ticks( void ) -{ - - _Watchdog_Tickle( &_Watchdog_Ticks_chain ); - -} - -/*PAGE - * - * _Watchdog_Tickle_seconds - * - * DESCRIPTION: - * - * This routine is invoked at each clock tick to update the seconds - * watchdog chain. - */ - -RTEMS_INLINE_ROUTINE void _Watchdog_Tickle_seconds( void ) -{ - - _Watchdog_Tickle( &_Watchdog_Seconds_chain ); - -} - -/*PAGE - * - * _Watchdog_Insert_ticks - * - * DESCRIPTION: - * - * This routine inserts THE_WATCHDOG into the ticks watchdog chain - * for a time of UNITS ticks. The INSERT_MODE indicates whether - * THE_WATCHDOG is to be activated automatically or later, explicitly - * by the caller. - */ - -RTEMS_INLINE_ROUTINE void _Watchdog_Insert_ticks( - Watchdog_Control *the_watchdog, - Watchdog_Interval units -) -{ - - the_watchdog->initial = units; - - _Watchdog_Insert( &_Watchdog_Ticks_chain, the_watchdog ); - -} - -/*PAGE - * - * _Watchdog_Insert_seconds - * - * DESCRIPTION: - * - * This routine inserts THE_WATCHDOG into the seconds watchdog chain - * for a time of UNITS seconds. The INSERT_MODE indicates whether - * THE_WATCHDOG is to be activated automatically or later, explicitly - * by the caller. - */ - -RTEMS_INLINE_ROUTINE void _Watchdog_Insert_seconds( - Watchdog_Control *the_watchdog, - Watchdog_Interval units -) -{ - - the_watchdog->initial = units; - - _Watchdog_Insert( &_Watchdog_Seconds_chain, the_watchdog ); - -} - -/*PAGE - * - * _Watchdog_Adjust_seconds - * - * DESCRIPTION: - * - * This routine adjusts the seconds watchdog chain in the forward - * or backward DIRECTION for UNITS seconds. This is invoked when the - * current time of day is changed. - */ - -RTEMS_INLINE_ROUTINE void _Watchdog_Adjust_seconds( - Watchdog_Adjust_directions direction, - Watchdog_Interval units -) -{ - - _Watchdog_Adjust( &_Watchdog_Seconds_chain, direction, units ); - -} - -/*PAGE - * - * _Watchdog_Adjust_ticks - * - * DESCRIPTION: - * - * This routine adjusts the ticks watchdog chain in the forward - * or backward DIRECTION for UNITS ticks. - */ - -RTEMS_INLINE_ROUTINE void _Watchdog_Adjust_ticks( - Watchdog_Adjust_directions direction, - Watchdog_Interval units -) -{ - - _Watchdog_Adjust( &_Watchdog_Ticks_chain, direction, units ); - -} - -/*PAGE - * - * _Watchdog_Reset - * - * DESCRIPTION: - * - * This routine resets THE_WATCHDOG timer to its state at INSERT - * time. This routine is valid only on interval watchdog timers - * and is used to make an interval watchdog timer fire "every" so - * many ticks. - */ - -RTEMS_INLINE_ROUTINE void _Watchdog_Reset( - Watchdog_Control *the_watchdog -) -{ - - (void) _Watchdog_Remove( the_watchdog ); - - _Watchdog_Insert( &_Watchdog_Ticks_chain, the_watchdog ); - -} - -/*PAGE - * - * _Watchdog_Next - * - * DESCRIPTION: - * - * This routine returns a pointer to the watchdog timer following - * THE_WATCHDOG on the watchdog chain. - */ - -RTEMS_INLINE_ROUTINE Watchdog_Control *_Watchdog_Next( - Watchdog_Control *the_watchdog -) -{ - - return ( (Watchdog_Control *) the_watchdog->Node.next ); - -} - -/*PAGE - * - * _Watchdog_Previous - * - * DESCRIPTION: - * - * This routine returns a pointer to the watchdog timer preceding - * THE_WATCHDOG on the watchdog chain. - */ - -RTEMS_INLINE_ROUTINE Watchdog_Control *_Watchdog_Previous( - Watchdog_Control *the_watchdog -) -{ - - return ( (Watchdog_Control *) the_watchdog->Node.previous ); - -} - -/*PAGE - * - * _Watchdog_First - * - * DESCRIPTION: - * - * This routine returns a pointer to the first watchdog timer - * on the watchdog chain HEADER. - */ - -RTEMS_INLINE_ROUTINE Watchdog_Control *_Watchdog_First( - Chain_Control *header -) -{ - - return ( (Watchdog_Control *) header->first ); - -} - -/*PAGE - * - * _Watchdog_Last - * - * DESCRIPTION: - * - * This routine returns a pointer to the last watchdog timer - * on the watchdog chain HEADER. - */ - -RTEMS_INLINE_ROUTINE Watchdog_Control *_Watchdog_Last( - Chain_Control *header -) -{ - - return ( (Watchdog_Control *) header->last ); - -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/inline/rtems/score/wkspace.inl b/c/src/exec/score/inline/rtems/score/wkspace.inl deleted file mode 100644 index 2a31514c32..0000000000 --- a/c/src/exec/score/inline/rtems/score/wkspace.inl +++ /dev/null @@ -1,56 +0,0 @@ -/* wkspace.inl - * - * This include file contains the bodies of the routines which contains - * information related to the RAM Workspace. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __WORKSPACE_inl -#define __WORKSPACE_inl - -/*PAGE - * - * _Workspace_Allocate - * - * DESCRIPTION: - * - * This routine returns the address of a block of memory of size - * bytes. If a block of the appropriate size cannot be allocated - * from the workspace, then NULL is returned. - */ - -RTEMS_INLINE_ROUTINE void *_Workspace_Allocate( - unsigned32 size -) -{ - return _Heap_Allocate( &_Workspace_Area, size ); -} - -/*PAGE - * - * _Workspace_Free - * - * DESCRIPTION: - * - * This function frees the specified block of memory. If the block - * belongs to the Workspace and can be successfully freed, then - * TRUE is returned. Otherwise FALSE is returned. - */ - -RTEMS_INLINE_ROUTINE boolean _Workspace_Free( - void *block -) -{ - return _Heap_Free( &_Workspace_Area, block ); -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/.cvsignore b/c/src/exec/score/macros/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/macros/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/macros/Makefile.am b/c/src/exec/score/macros/Makefile.am deleted file mode 100644 index 2cefac6a56..0000000000 --- a/c/src/exec/score/macros/Makefile.am +++ /dev/null @@ -1,43 +0,0 @@ -## -## $Id$ -## - - -$(PROJECT_INCLUDE)/%: % - $(INSTALL_DATA) $< $@ - -include_rtems_scoredir = $(includedir)/rtems/score - -$(PROJECT_INCLUDE)/rtems/score: - @$(mkinstalldirs) $@ - -## We only build multiprocessing related files if HAS_MP was defined -MP_I_FILES = rtems/score/mppkt.inl rtems/score/objectmp.inl rtems/score/threadmp.inl - -STD_I_FILES = rtems/score/address.inl rtems/score/chain.inl \ - rtems/score/coremsg.inl rtems/score/coremutex.inl rtems/score/coresem.inl \ - rtems/score/heap.inl rtems/score/isr.inl rtems/score/object.inl \ - rtems/score/priority.inl rtems/score/stack.inl rtems/score/states.inl \ - rtems/score/sysstate.inl rtems/score/thread.inl rtems/score/tod.inl \ - rtems/score/tqdata.inl rtems/score/userext.inl rtems/score/watchdog.inl \ - rtems/score/wkspace.inl - -if HAS_MP -I_FILES = $(STD_I_FILES) $(MP_I_FILES) -else -I_FILES = $(STD_I_FILES) -endif - -if MACROS -include_rtems_score_HEADERS = $(I_FILES) - -PREINSTALL_FILES = $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%=$(PROJECT_INCLUDE)/%) - -endif - -all-local: $(PREINSTALL_FILES) - -EXTRA_DIST = $(STD_I_FILES) $(MP_I_FILES) README - -include $(top_srcdir)/automake/local.am diff --git a/c/src/exec/score/macros/README b/c/src/exec/score/macros/README deleted file mode 100644 index b2f0c4d481..0000000000 --- a/c/src/exec/score/macros/README +++ /dev/null @@ -1,18 +0,0 @@ -# -# $Id$ -# - -The files in this directory are not considered the "primary" source -of inlined routines for RTEMS. The "inline" directory contains -the implementations of the inlined basis which are regularly -tested. In general, an effort is made to keep the contents of -this directory up to date but testing is only performed irregularly -and even then it is usually with a single target processor and BSP. - -The primary purpose of the code in this directory is to insure -that RTEMS can be compiled using a C compiler which does not support -static inline routines. - -These were last successfully tested on 2/1/95 on a prerelease version -of 3.2.0. The testing was done only on the Force CPU386 i386 target board. -No testing was done on version of the code in the final release. diff --git a/c/src/exec/score/macros/rtems/.cvsignore b/c/src/exec/score/macros/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/macros/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/macros/rtems/score/.cvsignore b/c/src/exec/score/macros/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/macros/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/macros/rtems/score/README b/c/src/exec/score/macros/rtems/score/README deleted file mode 100644 index b2f0c4d481..0000000000 --- a/c/src/exec/score/macros/rtems/score/README +++ /dev/null @@ -1,18 +0,0 @@ -# -# $Id$ -# - -The files in this directory are not considered the "primary" source -of inlined routines for RTEMS. The "inline" directory contains -the implementations of the inlined basis which are regularly -tested. In general, an effort is made to keep the contents of -this directory up to date but testing is only performed irregularly -and even then it is usually with a single target processor and BSP. - -The primary purpose of the code in this directory is to insure -that RTEMS can be compiled using a C compiler which does not support -static inline routines. - -These were last successfully tested on 2/1/95 on a prerelease version -of 3.2.0. The testing was done only on the Force CPU386 i386 target board. -No testing was done on version of the code in the final release. diff --git a/c/src/exec/score/macros/rtems/score/address.inl b/c/src/exec/score/macros/rtems/score/address.inl deleted file mode 100644 index 24f9dc12e5..0000000000 --- a/c/src/exec/score/macros/rtems/score/address.inl +++ /dev/null @@ -1,75 +0,0 @@ -/* macros/address.h - * - * This include file contains the bodies of the routines - * about addresses which are inlined. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __MACROS_ADDRESSES_h -#define __MACROS_ADDRESSES_h - -/*PAGE - * - * _Addresses_Add_offset - * - */ - -#define _Addresses_Add_offset( _base, _offset ) \ - ((void *)((char *)(_base) + (_offset))) - -/*PAGE - * - * _Addresses_Subtract_offset - * - */ - -#define _Addresses_Subtract_offset( _base, _offset ) \ - ((void *)((char *)(_base) - (_offset))) - -/*PAGE - * - * _Addresses_Subtract - * - * NOTE: The cast of an address to an unsigned32 makes this code - * dependent on an addresses being thirty two bits. - */ - -#define _Addresses_Subtract( _left, _right ) \ - ((void *)(_left) - (void *)(_right)) - -/*PAGE - * - * _Addresses_Is_aligned - * - */ - -#if (CPU_ALIGNMENT == 0) -#define _Addresses_Is_aligned( _address ) \ - (TRUE) -#elif defined(RTEMS_CPU_HAS_16_BIT_ADDRESSES) -#define _Addresses_Is_aligned( _address ) \ - ( ( (unsigned short)(_address) % CPU_ALIGNMENT ) == 0 ) -#else -#define _Addresses_Is_aligned( _address ) \ - ( ( (unsigned32)(_address) % CPU_ALIGNMENT ) == 0 ) -#endif - -/*PAGE - * - * _Addresses_Is_in_range - * - */ - -#define _Addresses_Is_in_range( _address, _base, _limit ) \ - ( (_address) >= (_base) && (_address) <= (_limit) ) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/chain.inl b/c/src/exec/score/macros/rtems/score/chain.inl deleted file mode 100644 index 0c9f998117..0000000000 --- a/c/src/exec/score/macros/rtems/score/chain.inl +++ /dev/null @@ -1,199 +0,0 @@ -/* macros/chain.h - * - * This include file contains the bodies of the routines which are - * associated with doubly linked chains and inlined. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __MACROS_CHAIN_h -#define __MACROS_CHAIN_h - -/*PAGE - * - * _Chain_Are_nodes_equal - */ - -#define _Chain_Are_nodes_equal( _left, _right ) \ - ( (_left) == (_right) ) - -/*PAGE - * - * _Chain_Is_null - */ - -#define _Chain_Is_null( _the_chain ) \ - ( (_the_chain) == NULL ) - -/*PAGE - * - * _Chain_Is_null_node - */ - -#define _Chain_Is_null_node( _the_node ) \ - ( (_the_node) == NULL ) - -/*PAGE - * - * _Chain_Head - */ - -#define _Chain_Head( _the_chain ) \ - ((Chain_Node *) (_the_chain)) - -/*PAGE - * - * _Chain_Tail - */ - -#define _Chain_Tail( _the_chain ) \ - ((Chain_Node *) &(_the_chain)->permanent_null) - -/*PAGE - * - * _Chain_Is_empty - */ - -#define _Chain_Is_empty( _the_chain ) \ - ( (_the_chain)->first == _Chain_Tail( (_the_chain) ) ) - -/*PAGE - * - * _Chain_Is_first - */ - -#define _Chain_Is_first( _the_node ) \ - ( (the_node)->previous == NULL ) - -/*PAGE - * - * _Chain_Is_last - */ - -#define _Chain_Is_last( _the_node ) \ - ( (_the_node)->next == NULL ) - -/*PAGE - * - * _Chain_Has_only_one_node - */ - -#define _Chain_Has_only_one_node( _the_chain ) \ - ( (_the_chain)->first == (_the_chain)->last ) - -/*PAGE - * - * _Chain_Is_head - */ - -#define _Chain_Is_head( _the_chain, _the_node ) \ - ( (_the_node) == _Chain_Head( (_the_chain) ) ) - -/*PAGE - * - * _Chain_Is_tail - */ - -#define _Chain_Is_tail( _the_chain, _the_node ) \ - ( (_the_node) == _Chain_Tail( (_the_chain) ) ) - -/*PAGE - * - * Chain_Initialize_empty - */ - -#define _Chain_Initialize_empty( _the_chain ) \ -{ \ - (_the_chain)->first = _Chain_Tail( (_the_chain) ); \ - (_the_chain)->permanent_null = NULL; \ - (_the_chain)->last = _Chain_Head( (_the_chain) ); \ -} - -/*PAGE - * - * _Chain_Extract_unprotected - */ - -#define _Chain_Extract_unprotected( _the_node ) \ -{ \ - Chain_Node *_next; \ - Chain_Node *_previous; \ - \ - _next = (_the_node)->next; \ - _previous = (_the_node)->previous; \ - _next->previous = _previous; \ - _previous->next = _next; \ -} - -/*PAGE - * - * _Chain_Get_unprotected - */ - -/*PAGE - * - * Chain_Get_unprotected - */ - -#define _Chain_Get_unprotected( _the_chain ) \ - (( !_Chain_Is_empty( (_the_chain) ) ) \ - ? _Chain_Get_first_unprotected( (_the_chain) ) \ - : NULL) - -/*PAGE - * - * _Chain_Insert_unprotected - */ - -#define _Chain_Insert_unprotected( _after_node, _the_node ) \ -do { \ - Chain_Node *_before_node; \ - \ - (_the_node)->previous = (_after_node); \ - _before_node = (_after_node)->next; \ - (_after_node)->next = (_the_node); \ - (_the_node)->next = _before_node; \ - _before_node->previous = (_the_node); \ -} while (0) - -/*PAGE - * - * _Chain_Append_unprotected - */ - -#define _Chain_Append_unprotected( _the_chain, _the_node ) \ -{ \ - Chain_Node *_old_last_node; \ - \ - (_the_node)->next = _Chain_Tail( (_the_chain) ); \ - _old_last_node = (_the_chain)->last; \ - (_the_chain)->last = (_the_node); \ - _old_last_node->next = (_the_node); \ - (_the_node)->previous = _old_last_node; \ -} - -/*PAGE - * - * _Chain_Prepend_unprotected - */ - -#define _Chain_Prepend_unprotected( _the_chain, _the_node ) \ - _Chain_Insert_unprotected( _Chain_Head( (_the_chain) ), (_the_node) ) - -/*PAGE - * - * _Chain_Prepend - */ - -#define _Chain_Prepend( _the_chain, _the_node ) \ - _Chain_Insert( _Chain_Head( (_the_chain) ), (_the_node) ) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/coremsg.inl b/c/src/exec/score/macros/rtems/score/coremsg.inl deleted file mode 100644 index c37c307287..0000000000 --- a/c/src/exec/score/macros/rtems/score/coremsg.inl +++ /dev/null @@ -1,144 +0,0 @@ -/* coremsg.inl - * - * This include file contains the macro implementation of all - * inlined routines in the Core Message Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CORE_MESSAGE_QUEUE_inl -#define __CORE_MESSAGE_QUEUE_inl - -/*PAGE - * - * _CORE_message_queue_Send - * - */ - -#define _CORE_message_queue_Send( _the_message_queue, _buffer, _size, \ - _id, _api_message_queue_mp_support, _wait, _timeout ) \ - _CORE_message_queue_Submit( (_the_message_queue), (_buffer), (_size), \ - (_id), (_api_message_queue_mp_support), \ - CORE_MESSAGE_QUEUE_SEND_REQUEST, (_wait), (_timeout) ) - -/*PAGE - * - * _CORE_message_queue_Urgent - * - */ - -#define _CORE_message_queue_Urgent( _the_message_queue, _buffer, _size, \ - _id, _api_message_queue_mp_support, _wait, _timeout ) \ - _CORE_message_queue_Submit( (_the_message_queue), (_buffer), (_size), \ - (_id), (_api_message_queue_mp_support), \ - CORE_MESSAGE_QUEUE_URGENT_REQUEST, (_wait), (_timeout) ) - -/*PAGE - * - * _CORE_message_queue_Copy_buffer - */ - -#define _CORE_message_queue_Copy_buffer( _source, _destination, _size ) \ - memcpy( _destination, _source, _size) - -/*PAGE - * - * _CORE_message_queue_Allocate_message_buffer - * - */ - -#define _CORE_message_queue_Allocate_message_buffer( _the_message_queue ) \ - (CORE_message_queue_Buffer_control *) \ - _Chain_Get( &(_the_message_queue)->Inactive_messages ) - -/*PAGE - * - * _CORE_message_queue_Free_message_buffer - * - */ - -#define _CORE_message_queue_Free_message_buffer( _the_message_queue, _the_message ) \ - _Chain_Append( \ - &(_the_message_queue)->Inactive_messages, \ - &(_the_message)->Node \ - ) - -/*PAGE - * - * _CORE_message_queue_Is_priority - * - */ - -#define _CORE_message_queue_Is_priority( _the_attribute ) \ - ((_the_attribute)->discipline == CORE_MESSAGE_QUEUE_DISCIPLINES_PRIORITY) - -/*PAGE - * - * _CORE_message_queue_Get_pending_message - * - */ - -#define _CORE_message_queue_Get_pending_message( _the_message_queue ) \ - (CORE_message_queue_Buffer_control *) \ - _Chain_Get_unprotected( &(_the_message_queue)->Pending_messages ) - -/*PAGE - * - * _CORE_message_queue_Append - * - */ - -#define _CORE_message_queue_Append( _the_message_queue, _the_message ) \ - _Chain_Append( &(_the_message_queue)->Pending_messages, \ - &(_the_message)->Node ) - -/*PAGE - * - * _CORE_message_queue_Prepend - * - */ - -#define _CORE_message_queue_Prepend( _the_message_queue, _the_message ) \ - _Chain_Prepend( &(_the_message_queue)->Pending_messages, \ - &(_the_message)->Node ) - -/*PAGE - * - * _CORE_message_queue_Is_null - * - */ - -#define _CORE_message_queue_Is_null( _the_message_queue ) \ - ( (_the_message_queue) == NULL ) - -/*PAGE - * - * _CORE_message_queue_Is_notify_enabled - * - */ - -#define _CORE_message_queue_Is_notify_enabled( _the_message_queue ) \ - ( (_the_message_queue)->notify_handler != NULL ) - -/*PAGE - * - * _CORE_message_queue_Set_notify - * - */ - -#define _CORE_message_queue_Set_notify( \ - _the_message_queue, _the_handler, _the_argument ) \ - do { \ - (_the_message_queue)->notify_handler = (_the_handler); \ - (_the_message_queue)->notify_argument = (_the_argument); \ - } while ( 0 ) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/coremutex.inl b/c/src/exec/score/macros/rtems/score/coremutex.inl deleted file mode 100644 index 90323374e5..0000000000 --- a/c/src/exec/score/macros/rtems/score/coremutex.inl +++ /dev/null @@ -1,81 +0,0 @@ -/* macros/coremutex.h - * - * This include file contains all of the inlined routines associated - * with core mutexes. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __MACROS_CORE_MUTEX_h -#define __MACROS_CORE_MUTEX_h - - -/*PAGE - * - * _CORE_mutex_Is_locked - * - */ - -#define _CORE_mutex_Is_locked( _the_mutex ) \ - ( (_the_mutex)->lock == CORE_MUTEX_LOCKED ) - -/*PAGE - * - * _CORE_mutex_Is_fifo - * - */ - -#define _CORE_mutex_Is_fifo( _the_attribute ) \ - ( (_the_attribute)->discipline == CORE_MUTEX_DISCIPLINES_FIFO ) - -/*PAGE - * - * _CORE_mutex_Is_priority - * - */ - -#define _CORE_mutex_Is_priority( _the_attribute ) \ - ( (_the_attribute)->discipline == CORE_MUTEX_DISCIPLINES_PRIORITY ) - -/*PAGE - * - * _CORE_mutex_Is_inherit_priority - * - */ - -#define _CORE_mutex_Is_inherit_priority( _the_attribute ) \ - ( (_the_attribute)->discipline == \ - CORE_MUTEX_DISCIPLINES_PRIORITY_INHERIT ) - -/*PAGE - * - * _CORE_mutex_Is_priority_ceiling - * - */ - -#define _CORE_mutex_Is_priority_ceiling( _the_attribute )\ - ( (_the_attribute)->discipline == CORE_MUTEX_DISCIPLINES_PRIORITY_CEILING ) - -/*PAGE - * - * _CORE_mutex_Seize_interrupt_trylock - * - * NOTE: This is not really a MACRO version of this routine. - * A body is in coremutexseize.c that is duplicated - * from the .inl by hand. - */ - -int _CORE_mutex_Seize_interrupt_trylock( - CORE_mutex_Control *the_mutex, - ISR_Level *level_p -); - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/coresem.inl b/c/src/exec/score/macros/rtems/score/coresem.inl deleted file mode 100644 index eebb34d3c2..0000000000 --- a/c/src/exec/score/macros/rtems/score/coresem.inl +++ /dev/null @@ -1,71 +0,0 @@ -/* macros/coresem.h - * - * This include file contains all of the inlined routines associated - * with core semaphores. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __MACROS_CORE_SEMAPHORE_h -#define __MACROS_CORE_SEMAPHORE_h - -/*PAGE - * - * _CORE_semaphore_Is_priority - * - */ - -#define _CORE_semaphore_Is_priority( _the_attribute ) \ - ( (_the_attribute)->discipline == CORE_SEMAPHORE_DISCIPLINES_PRIORITY ) - -/*PAGE - * - * _CORE_semaphore_Get_count - * - */ - -#define _CORE_semaphore_Get_count( _the_semaphore ) \ - ( (_the_semaphore)->count ) - -/*PAGE - * - * _CORE_semaphore_Seize_isr_disable - */ - -#define _CORE_semaphore_Seize_isr_disable( \ - _the_semaphore, _id, _wait, _timeout, _level_p) \ -{ \ - Thread_Control *executing; \ - ISR_Level level = *(_level_p); \ - \ - /* disabled when you get here */ \ - \ - executing = _Thread_Executing; \ - executing->Wait.return_code = CORE_SEMAPHORE_STATUS_SUCCESSFUL; \ - if ( (_the_semaphore)->count != 0 ) { \ - (_the_semaphore)->count -= 1; \ - _ISR_Enable( level ); \ - } else if ( !(_wait) ) { \ - _ISR_Enable( level ); \ - executing->Wait.return_code = CORE_SEMAPHORE_STATUS_UNSATISFIED_NOWAIT; \ - } else { \ - _Thread_Disable_dispatch(); \ - _Thread_queue_Enter_critical_section( &(_the_semaphore)->Wait_queue ); \ - executing->Wait.queue = &(_the_semaphore)->Wait_queue; \ - executing->Wait.id = (_id); \ - _ISR_Enable( level ); \ - \ - _Thread_queue_Enqueue( &(_the_semaphore)->Wait_queue, (_timeout) ); \ - _Thread_Enable_dispatch(); \ - } \ -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/heap.inl b/c/src/exec/score/macros/rtems/score/heap.inl deleted file mode 100644 index 6c2016be8d..0000000000 --- a/c/src/exec/score/macros/rtems/score/heap.inl +++ /dev/null @@ -1,149 +0,0 @@ -/* heap.inl - * - * This file contains the macro implementation of the inlined - * routines from the heap handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __HEAP_inl -#define __HEAP_inl - -#include <rtems/score/address.h> - -/*PAGE - * - * _Heap_Head - */ - -#define _Heap_Head( _the_heap ) \ - ((Heap_Block *)&(_the_heap)->start) - -/*PAGE - * - * _Heap_Tail - */ - -#define _Heap_Tail( _the_heap ) \ - ((Heap_Block *)&(_the_heap)->final) - -/*PAGE - * - * _Heap_Previous_block - */ - -#define _Heap_Previous_block( _the_block ) \ - ( (Heap_Block *) _Addresses_Subtract_offset( \ - (void *)(_the_block), \ - (_the_block)->back_flag & ~ HEAP_BLOCK_USED \ - ) \ - ) - -/*PAGE - * - * _Heap_Next_block - */ - -#define _Heap_Next_block( _the_block ) \ - ( (Heap_Block *) _Addresses_Add_offset( \ - (void *)(_the_block), \ - (_the_block)->front_flag & ~ HEAP_BLOCK_USED \ - ) \ - ) - -/*PAGE - * - * _Heap_Block_at - */ - -#define _Heap_Block_at( _base, _offset ) \ - ( (Heap_Block *) \ - _Addresses_Add_offset( (void *)(_base), (_offset) ) ) - -/*PAGE - * - * _Heap_User_block_at - * - */ - -#define _Heap_User_block_at( _base ) \ - _Heap_Block_at( \ - (_base), \ - -*(((unsigned32 *) (_base)) - 1) + -HEAP_BLOCK_USED_OVERHEAD \ - ) - -/*PAGE - * - * _Heap_Is_previous_block_free - */ - -#define _Heap_Is_previous_block_free( _the_block ) \ - ( !((_the_block)->back_flag & HEAP_BLOCK_USED) ) - -/*PAGE - * - * _Heap_Is_block_free - */ - -#define _Heap_Is_block_free( _the_block ) \ - ( !((_the_block)->front_flag & HEAP_BLOCK_USED) ) - -/*PAGE - * - * _Heap_Is_block_used - */ - -#define _Heap_Is_block_used( _the_block ) \ - ((_the_block)->front_flag & HEAP_BLOCK_USED) - -/*PAGE - * - * _Heap_Block_size - */ - -#define _Heap_Block_size( _the_block ) \ - ((_the_block)->front_flag & ~HEAP_BLOCK_USED) - -/*PAGE - * - * _Heap_Start_of_user_area - */ - -#define _Heap_Start_of_user_area( _the_block ) \ - ((void *) &(_the_block)->next) - -/*PAGE - * - * _Heap_Is_block_in - */ - -#define _Heap_Is_block_in( _the_heap, _the_block ) \ - ( ((_the_block) >= (_the_heap)->start) && \ - ((_the_block) <= (_the_heap)->final) ) - -/*PAGE - * - * _Heap_Is_page_size_valid - */ - -#define _Heap_Is_page_size_valid( _page_size ) \ - ( ((_page_size) != 0) && \ - (((_page_size) % CPU_HEAP_ALIGNMENT) == 0) ) - -/*PAGE - * - * _Heap_Build_flag - */ - -#define _Heap_Build_flag( _size, _in_use_flag ) \ - ( (_size) | (_in_use_flag)) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/isr.inl b/c/src/exec/score/macros/rtems/score/isr.inl deleted file mode 100644 index b75d6b002d..0000000000 --- a/c/src/exec/score/macros/rtems/score/isr.inl +++ /dev/null @@ -1,38 +0,0 @@ -/* isr.inl - * - * This include file contains the macro implementation of all - * inlined routines in the Interrupt Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __ISR_inl -#define __ISR_inl - -/*PAGE - * - * _ISR_Is_vector_number_valid - * - */ - -#define _ISR_Is_vector_number_valid( _vector ) \ - ( (_vector) <= CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER ) - -/*PAGE - * - * _ISR_Is_valid_user_handler - * - */ - -#define _ISR_Is_valid_user_handler( _handler ) \ - ((_handler) != NULL) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/mppkt.inl b/c/src/exec/score/macros/rtems/score/mppkt.inl deleted file mode 100644 index ca88f64907..0000000000 --- a/c/src/exec/score/macros/rtems/score/mppkt.inl +++ /dev/null @@ -1,40 +0,0 @@ -/* macros/mppkt.h - * - * This package is the implementation of the Packet Handler - * routines which are inlined. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __MACROS_MP_PACKET_h -#define __MACROS_MP_PACKET_h - -/*PAGE - * - * _Mp_packet_Is_valid_packet_class - * - * NOTE: Check for lower bounds (MP_PACKET_CLASSES_FIRST ) is unnecessary - * because this enum starts at lower bound of zero. - */ - -#define _Mp_packet_Is_valid_packet_class( _the_packet_class ) \ - ( (_the_packet_class) <= MP_PACKET_CLASSES_LAST ) - -/*PAGE - * - * _Mp_packet_Is_null - * - */ - -#define _Mp_packet_Is_null ( _the_packet ) \ - ( (_the_packet) == NULL ) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/object.inl b/c/src/exec/score/macros/rtems/score/object.inl deleted file mode 100644 index 10721497f2..0000000000 --- a/c/src/exec/score/macros/rtems/score/object.inl +++ /dev/null @@ -1,188 +0,0 @@ -/* object.inl - * - * This include file contains the macro implementation of all - * of the inlined routines in the Object Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __OBJECTS_inl -#define __OBJECTS_inl - -/*PAGE - * - * _Objects_Build_id - * - */ - -#define _Objects_Build_id( _the_api, _the_class, _node, _index ) \ - ( (( (Objects_Id) _the_api ) << OBJECTS_API_START_BIT) | \ - (( (Objects_Id) _the_class ) << OBJECTS_CLASS_START_BIT) | \ - (( (Objects_Id) _node ) << OBJECTS_NODE_START_BIT) | \ - (( (Objects_Id) _index ) << OBJECTS_INDEX_START_BIT) ) - -/*PAGE - * - * _Objects_Get_API - */ - -#define _Objects_Get_API( _id ) \ - (Objects_APIs) \ - (((_id) >> OBJECTS_API_START_BIT) & OBJECTS_API_VALID_BITS) - -/*PAGE - * - * _Objects_Get_class - */ - -#define _Objects_Get_class( _id ) \ - (unsigned32) \ - (((_id) >> OBJECTS_CLASS_START_BIT) & OBJECTS_CLASS_VALID_BITS) - -/*PAGE - * - * _Objects_Get_node - * - */ - -#define _Objects_Get_node( _id ) \ - (((_id) >> OBJECTS_NODE_START_BIT) & OBJECTS_NODE_VALID_BITS) - -/*PAGE - * - * _Objects_Get_index - * - */ - -#define _Objects_Get_index( _id ) \ - (((_id) >> OBJECTS_INDEX_START_BIT) & OBJECTS_INDEX_VALID_BITS) - -/*PAGE - * - * _Objects_Is_class_valid - * - */ - -#define _Objects_Is_class_valid( _the_class ) \ - ( (_the_class) /* XXX && (_the_class) <= OBJECTS_CLASSES_LAST */ ) - -/*PAGE - * - * _Objects_Is_local_node - * - */ - -#define _Objects_Is_local_node( _node ) \ - ( (_node) == _Objects_Local_node ) - -/*PAGE - * - * _Objects_Is_local_id - * - */ - -#define _Objects_Is_local_id( _id ) \ - _Objects_Is_local_node( _Objects_Get_node(_id) ) - -/*PAGE - * - * _Objects_Are_ids_equal - * - */ - -#define _Objects_Are_ids_equal( _left, _right ) \ - ( (_left) == (_right) ) - -/*PAGE - * - * _Objects_Get_local_object - * - */ - -#define _Objects_Get_local_object( _information, _index ) \ - ( ( (_index) > (_information)->maximum) ? NULL : \ - (_information)->local_table[ (_index) ] ) - -/*PAGE - * - * _Objects_Set_local_object - * - */ - -#define _Objects_Set_local_object( information, index, the_object ) \ - { \ - if ( index <= information->maximum) \ - information->local_table[ index ] = the_object; \ - } - - -/*PAGE - * - * _Objects_Get_information - * - */ - -#define _Objects_Get_information( id ) \ - ( \ - ( !_Objects_Is_class_valid( _Objects_Get_class( id ) ) ) ? \ - NULL : \ - _Objects_Information_table[ _Objects_Get_API( id ) ] \ - [ _Objects_Get_class( id ) ] \ - ) - -/*PAGE - * - * _Objects_Open - * - */ - -#define _Objects_Open( _information, _the_object, _name ) \ - do { \ - unsigned32 _index; \ - \ - _index = _Objects_Get_index( (_the_object)->id ); \ - (_information)->local_table[ _index ] = (_the_object); \ - \ - if ( (_information)->is_string ) \ - /* _Objects_Copy_name_string( (_name), (_the_object)->name ); */\ - (_the_object)->name = (_name); \ - else \ - /* _Objects_Copy_name_raw( \ - (_name), (_the_object)->name, (_information)->name_length ); */ \ - (_the_object)->name = (_name); \ - } while (0) - -/*PAGE - * - * _Objects_Close - * - */ - -#define _Objects_Close( _information, _the_object ) \ - do { \ - unsigned32 _index; \ - \ - _index = _Objects_Get_index( (_the_object)->id ); \ - (_information)->local_table[ _index ] = (Objects_Control *) NULL; \ - /* _Objects_Clear_name( (_the_object)->name, (_information)->name_length ); */ \ - (_the_object)->name = 0; \ - } while (0) - -/*PAGE - * - * _Objects_Namespace_remove - */ - -#define _Objects_Namespace_remove( _information, _the_object ) \ - (_the_object)->name = 0; \ - _Objects_Clear_name( (_the_object)->name, (_information)->name_length ) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/objectmp.inl b/c/src/exec/score/macros/rtems/score/objectmp.inl deleted file mode 100644 index ce5550018d..0000000000 --- a/c/src/exec/score/macros/rtems/score/objectmp.inl +++ /dev/null @@ -1,49 +0,0 @@ -/* macros/objectmp.inl - * - * This include file contains the bodies of all inlined routines - * which deal with global objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __MACROS_MP_OBJECTS_inl -#define __MACROS_MP_OBJECTS_inl - -/*PAGE - * - * _Objects_MP_Allocate_global_object - * - */ - -#define _Objects_MP_Allocate_global_object() \ - (Objects_MP_Control *) \ - _Chain_Get( &_Objects_MP_Inactive_global_objects ) - -/*PAGE - * _Objects_MP_Free_global_object - * - */ - -#define _Objects_MP_Free_global_object( _the_object ) \ - _Chain_Append( \ - &_Objects_MP_Inactive_global_objects, \ - &(_the_object)->Object.Node \ - ) - -/*PAGE - * _Objects_MP_Is_null_global_object - * - */ - -#define _Objects_MP_Is_null_global_object( _the_object ) \ - ( (_the_object) == NULL ) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/priority.inl b/c/src/exec/score/macros/rtems/score/priority.inl deleted file mode 100644 index f8598abb5c..0000000000 --- a/c/src/exec/score/macros/rtems/score/priority.inl +++ /dev/null @@ -1,169 +0,0 @@ -/* priority.inl - * - * This file contains the macro implementation of all inlined routines - * in the Priority Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __PRIORITY_inl -#define __PRIORITY_inl - -#include <rtems/score/bitfield.h> - -/*PAGE - * - * _Priority_Handler_initialization - * - */ - -#define _Priority_Handler_initialization() \ - { \ - unsigned32 index; \ - \ - _Priority_Major_bit_map = 0; \ - for ( index=0 ; index <16 ; index++ ) \ - _Priority_Bit_map[ index ] = 0; \ - } - -/*PAGE - * - * _Priority_Is_valid - * - */ - - /* - * Since PRIORITY_MINIMUM is 0 and priorities are stored unsigned, - * then checking for less than 0 is unnecessary. - */ - -#define _Priority_Is_valid( _the_priority ) \ - ( (_the_priority) <= PRIORITY_MAXIMUM ) - -/*PAGE - * - * _Priority_Major - * - */ - -#define _Priority_Major( _the_priority ) ( (_the_priority) / 16 ) - -/*PAGE - * - * _Priority_Minor - * - */ - -#define _Priority_Minor( _the_priority ) ( (_the_priority) % 16 ) - -#if ( CPU_USE_GENERIC_BITFIELD_CODE == TRUE ) - -/*PAGE - * - * _Priority_Mask - * - */ - -#define _Priority_Mask( _bit_number ) \ - (0x8000 >> _bit_number) - -/*PAGE - * - * _Priority_Bits_index - * - */ - -#define _Priority_Bits_index( _bit_number ) \ - (_bit_number) - -#endif - -/*PAGE - * - * _Priority_Add_to_bit_map - * - */ - -#define _Priority_Add_to_bit_map( _the_priority_map ) \ - { \ - *(_the_priority_map)->minor |= (_the_priority_map)->ready_minor; \ - _Priority_Major_bit_map |= (_the_priority_map)->ready_major; \ - } - -/*PAGE - * - * _Priority_Remove_from_bit_map - * - */ - -#define _Priority_Remove_from_bit_map( _the_priority_map ) \ - { \ - *(_the_priority_map)->minor &= (_the_priority_map)->block_minor; \ - if ( *(_the_priority_map)->minor == 0 ) \ - _Priority_Major_bit_map &= (_the_priority_map)->block_major; \ - } - -/*PAGE - * - * _Priority_Get_highest - * - */ - -#define _Priority_Get_highest( _high_priority ) \ - { \ - Priority_Bit_map_control minor; \ - Priority_Bit_map_control major; \ - \ - _Bitfield_Find_first_bit( _Priority_Major_bit_map, major ); \ - _Bitfield_Find_first_bit( _Priority_Bit_map[major], minor ); \ - \ - (_high_priority) = (_Priority_Bits_index( major ) * 16) + \ - _Priority_Bits_index( minor ); \ - } - -/*PAGE - * - * _Priority_Initialize_information - * - */ - -#define _Priority_Initialize_information( \ - _the_priority_map, _new_priority ) \ - { \ - Priority_Bit_map_control _major; \ - Priority_Bit_map_control _minor; \ - Priority_Bit_map_control _mask; \ - \ - _major = _Priority_Major( (_new_priority) ); \ - _minor = _Priority_Minor( (_new_priority) ); \ - \ - (_the_priority_map)->minor = \ - &_Priority_Bit_map[ _Priority_Bits_index(_major) ]; \ - \ - _mask = _Priority_Mask( _major ); \ - (_the_priority_map)->ready_major = _mask; \ - (_the_priority_map)->block_major = ~_mask; \ - \ - _mask = _Priority_Mask( _minor ); \ - (_the_priority_map)->ready_minor = _mask; \ - (_the_priority_map)->block_minor = ~_mask; \ - } - -/*PAGE - * - * _Priority_Is_group_empty - * - */ - -#define _Priority_Is_group_empty ( _the_priority ) \ - ( (_the_priority) == 0 ) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/stack.inl b/c/src/exec/score/macros/rtems/score/stack.inl deleted file mode 100644 index fc0c94a980..0000000000 --- a/c/src/exec/score/macros/rtems/score/stack.inl +++ /dev/null @@ -1,49 +0,0 @@ -/* stack.inl - * - * This file contains the macro implementation of the inlined - * routines from the Stack Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __STACK_inl -#define __STACK_inl - -/*PAGE - * - * _Stack_Initialize - * - */ - -#define _Stack_Initialize( _the_stack, _starting_address, _size ) \ - { \ - (_the_stack)->area = (_starting_address); \ - (_the_stack)->size = (_size); \ - } - -/*PAGE - * - * _Stack_Is_enough - * - */ - -#define _Stack_Is_enough( _size ) \ - ( (_size) >= STACK_MINIMUM_SIZE ) - -/*PAGE - * - * _Stack_Adjust_size - */ - -#define _Stack_Adjust_size( _size ) \ - ((_size) + CPU_STACK_ALIGNMENT) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/states.inl b/c/src/exec/score/macros/rtems/score/states.inl deleted file mode 100644 index 05a816f18d..0000000000 --- a/c/src/exec/score/macros/rtems/score/states.inl +++ /dev/null @@ -1,209 +0,0 @@ -/* states.inl - * - * This file contains the macro implementation of the inlined - * routines associated with thread state information. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __STATES_inl -#define __STATES_inl - -/*PAGE - * - * _States_Set - * - */ - -#define _States_Set( _states_to_set, _current_state ) \ - ((_current_state) | (_states_to_set)) - -/*PAGE - * - * _States_Clear - * - */ - -#define _States_Clear( _states_to_clear, _current_state ) \ - ((_current_state) & ~(_states_to_clear)) - -/*PAGE - * - * _States_Is_ready - * - */ - -#define _States_Is_ready( _the_states ) \ - ( (_the_states) == STATES_READY ) - -/*PAGE - * - * _States_Is_only_dormant - * - */ - -#define _States_Is_only_dormant( _the_states ) \ - ( (_the_states) == STATES_DORMANT ) - -/*PAGE - * - * _States_Is_dormant - * - */ - -#define _States_Is_dormant( _the_states ) \ - ( (_the_states) & STATES_DORMANT ) - -/*PAGE - * - * _States_Is_suspended - * - */ - -#define _States_Is_suspended( _the_states ) \ - ( (_the_states) & STATES_SUSPENDED ) - -/*PAGE - * - * _States_Is_Transient - * - */ - -#define _States_Is_transient( _the_states ) \ - ( (_the_states) & STATES_TRANSIENT ) - -/*PAGE - * - * _States_Is_delaying - * - */ - -#define _States_Is_delaying( _the_states ) \ - ( (_the_states) & STATES_DELAYING ) - -/*PAGE - * - * _States_Is_waiting_for_buffer - * - */ - -#define _States_Is_waiting_for_buffer( _the_states ) \ - ( (_the_states) & STATES_WAITING_FOR_BUFFER ) - -/*PAGE - * - * _States_Is_waiting_for_segment - * - */ - -#define _States_Is_waiting_for_segment( _the_states ) \ - ( (_the_states) & STATES_WAITING_FOR_SEGMENT ) - -/*PAGE - * - * _States_Is_waiting_for_message - * - */ - -#define _States_Is_waiting_for_message( _the_states ) \ - ( (_the_states) & STATES_WAITING_FOR_MESSAGE ) - -/*PAGE - * - * _States_Is_waiting_for_event - * - */ - -#define _States_Is_waiting_for_event( _the_states ) \ - ( (_the_states) & STATES_WAITING_FOR_EVENT ) - -/*PAGE - * - * _States_Is_waiting_for_mutex - * - */ - -#define _States_Is_waiting_for_mutex( _the_states ) \ - ( (_the_states) & STATES_WAITING_FOR_MUTEX ) - -/*PAGE - * - * _States_Is_waiting_for_semaphore - * - */ - -#define _States_Is_waiting_for_semaphore( _the_states ) \ - ( (_the_states) & STATES_WAITING_FOR_SEMAPHORE ) - -/*PAGE - * - * _States_Is_waiting_for_time - * - */ - -#define _States_Is_waiting_for_time( _the_states ) \ - ( (_the_states) & STATES_WAITING_FOR_TIME ) - -/*PAGE - * - * _States_Is_waiting_for_rpc_reply - * - */ - -#define _States_Is_waiting_for_rpc_reply( _the_states ) \ - ( (_the_states) & STATES_WAITING_FOR_RPC_REPLY ) - -/*PAGE - * - * _States_Is_waiting_for_period - * - */ - -#define _States_Is_waiting_for_period( _the_states ) \ - ( (_the_states) & STATES_WAITING_FOR_PERIOD ) - -/*PAGE - * - * _States_Is_locally_blocked - * - */ - -#define _States_Is_locally_blocked( _the_states ) \ - ( (_the_states) & STATES_LOCALLY_BLOCKED ) - -/*PAGE - * - * _States_Is_waiting_on_thread_queue - * - */ - -#define _States_Is_waiting_on_thread_queue( _the_states ) \ - ( (_the_states) & STATES_WAITING_ON_THREAD_QUEUE ) - -/*PAGE - * - * _States_Is_blocked - * - */ - -#define _States_Is_blocked( _the_states ) \ - ( (_the_states) & STATES_BLOCKED ) - -/*PAGE - * - * _States_Are_set - * - */ - -#define _States_Are_set( _the_states, _mask ) \ - ( ((_the_states) & (_mask)) != STATES_READY ) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/sysstate.inl b/c/src/exec/score/macros/rtems/score/sysstate.inl deleted file mode 100644 index ac4197e8c6..0000000000 --- a/c/src/exec/score/macros/rtems/score/sysstate.inl +++ /dev/null @@ -1,89 +0,0 @@ -/* sysstates.inl - * - * This file contains the macro implementation of routines regarding the - * system state. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __SYSTEM_STATE_inl -#define __SYSTEM_STATE_inl - -/*PAGE - * - * _System_state_Handler_initialization - */ - -#define _System_state_Handler_initialization( _is_multiprocessing ) \ - do { \ - _System_state_Current = SYSTEM_STATE_BEFORE_INITIALIZATION; \ - _System_state_Is_multiprocessing = (_is_multiprocessing); \ - } while ( 0 ) - -/*PAGE - * - * _System_state_Set - */ - -#define _System_state_Set( _state ) \ - do { \ - _System_state_Current = (_state); \ - } while ( 0 ) - -/*PAGE - * - * _System_state_Get - */ - -#define _System_state_Get() \ - (_System_state_Current) - -/*PAGE - * - * _System_state_Is_before_initialization - */ - -#define _System_state_Is_before_initialization( _state ) \ - ((_state) == SYSTEM_STATE_BEFORE_INITIALIZATION) - -/*PAGE - * - * _System_state_Is_before_multitasking - */ - -#define _System_state_Is_before_multitasking( _state ) \ - ((_state) == SYSTEM_STATE_BEFORE_MULTITASKING) - -/*PAGE - * - * _System_state_Is_begin_multitasking - */ - -#define _System_state_Is_begin_multitasking( _state ) \ - ((_state) == SYSTEM_STATE_BEGIN_MULTITASKING) - -/*PAGE - * - * _System_state_Is_up - */ - -#define _System_state_Is_up( _state ) \ - ((_state) == SYSTEM_STATE_UP) - -/*PAGE - * - * _System_state_Is_failed - */ - -#define _System_state_Is_failed( _state ) \ - ((_state) == SYSTEM_STATE_FAILED) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/thread.inl b/c/src/exec/score/macros/rtems/score/thread.inl deleted file mode 100644 index 6abb287d8b..0000000000 --- a/c/src/exec/score/macros/rtems/score/thread.inl +++ /dev/null @@ -1,234 +0,0 @@ -/* thread.inl - * - * This file contains the macro implementation of the inlined - * routines from the Thread handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __THREAD_inl -#define __THREAD_inl - -/*PAGE - * - * _Thread_Stop_multitasking - * - */ - -#define _Thread_Stop_multitasking() \ - _Context_Switch( &_Thread_Executing->Registers, &_Thread_BSP_context ); - -/*PAGE - * - * _Thread_Is_executing - * - */ - -#define _Thread_Is_executing( _the_thread ) \ - ( (_the_thread) == _Thread_Executing ) - -/*PAGE - * - * _Thread_Is_heir - * - */ - -#define _Thread_Is_heir( _the_thread ) \ - ( (_the_thread) == _Thread_Heir ) - -/*PAGE - * - * _Thread_Is_executing_also_the_heir - * - */ - -#define _Thread_Is_executing_also_the_heir() \ - ( _Thread_Executing == _Thread_Heir ) - -/*PAGE - * - * _Thread_Unblock - * - */ - -#define _Thread_Unblock( _the_thread ) \ - _Thread_Clear_state( (_the_thread), STATES_BLOCKED ); - -/*PAGE - * - * _Thread_Restart_self - * - */ - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) -#define _Thread_Restart_self() \ - { \ - if ( _Thread_Executing->fp_context != NULL ) \ - _Context_Restore_fp( &_Thread_Executing->fp_context ); \ - \ - _CPU_Context_Restart_self( &_Thread_Executing->Registers ); \ - } -#else -#define _Thread_Restart_self() \ - { \ - _CPU_Context_Restart_self( &_Thread_Executing->Registers ); \ - } -#endif - -/*PAGE - * - * _Thread_Calculate_heir - * - */ - -#define _Thread_Calculate_heir() \ - { \ - Priority_Control highest; \ - \ - _Priority_Get_highest( highest ); \ - \ - _Thread_Heir = (Thread_Control *) _Thread_Ready_chain[ highest ].first; \ - } - -/*PAGE - * - * _Thread_Is_allocated_fp - * - */ - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) -#define _Thread_Is_allocated_fp( _the_thread ) \ - ( (_the_thread) == _Thread_Allocated_fp ) -#endif - -/*PAGE - * - * _Thread_Deallocate_fp - * - */ - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) -#define _Thread_Deallocate_fp() \ - _Thread_Allocated_fp = NULL -#endif - -/*PAGE - * - * _Thread_Disable_dispatch - * - */ - -#define _Thread_Disable_dispatch() \ - _Thread_Dispatch_disable_level += 1 - -/*PAGE - * - * _Thread_Enable_dispatch - * - */ - -#if ( CPU_INLINE_ENABLE_DISPATCH == TRUE ) -#define _Thread_Enable_dispatch() \ - { if ( (--_Thread_Dispatch_disable_level) == 0 ) \ - _Thread_Dispatch(); \ - } -#endif - -#if ( CPU_INLINE_ENABLE_DISPATCH == FALSE ) -void _Thread_Enable_dispatch( void ); -#endif - -/*PAGE - * - * _Thread_Unnest_dispatch - * - */ - -#define _Thread_Unnest_dispatch() \ - _Thread_Dispatch_disable_level -= 1 - -/*PAGE - * - * _Thread_Is_dispatching_enabled - * - */ - -#define _Thread_Is_dispatching_enabled() \ - ( _Thread_Dispatch_disable_level == 0 ) - -/*PAGE - * - * _Thread_Is_context_switch_necessary - * - */ - -#define _Thread_Is_context_switch_necessary() \ - ( _Context_Switch_necessary == TRUE ) - -/*PAGE - * - * _Thread_Dispatch_initialization - * - */ - -#define _Thread_Dispatch_initialization() \ - _Thread_Dispatch_disable_level = 1 - -/*PAGE - * - * _Thread_Is_null - * - */ - -#define _Thread_Is_null( _the_thread ) \ - ( (_the_thread) == NULL ) - -/* - * _Thread_Is_proxy_blocking - * - */ - -#define _Thread_Is_proxy_blocking( _code ) \ - ( (_code) == THREAD_STATUS_PROXY_BLOCKING ) - -/* - * _Thread_Internal_allocate - * - */ - -#define _Thread_Internal_allocate() \ - ((Thread_Control *) _Objects_Allocate( &_Thread_Internal_information )) - -/* - * _Thread_Internal_free - * - */ - -#define _Thread_Internal_free( _the_task ) \ - _Objects_Free( &_Thread_Internal_information, &(_the_task)->Object ) - -/* - * _Thread_Get_libc_reent - */ - -#define _Thread_Get_libc_reent() \ - (_Thread_libc_reent) - -/* - * _Thread_Set_libc_reent - */ - -#define _Thread_Set_libc_reent(_libc_reent) \ - do { \ - _Thread_libc_reent = (_libc_reent); \ - } while (0) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/threadmp.inl b/c/src/exec/score/macros/rtems/score/threadmp.inl deleted file mode 100644 index 975403860d..0000000000 --- a/c/src/exec/score/macros/rtems/score/threadmp.inl +++ /dev/null @@ -1,49 +0,0 @@ -/* macros/threadmp.h - * - * This include file contains the bodies of all inlined routines - * for the multiprocessing part of thread package. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __MACROS_MP_THREAD_h -#define __MACROS_MP_THREAD_h - -/*PAGE - * - * _Thread_MP_Is_receive - * - */ - -#define _Thread_MP_Is_receive( _the_thread ) \ - ( (_the_thread) == _Thread_MP_Receive) - -/*PAGE - * - * _Thread_MP_Free_proxy - * - */ - -#define _Thread_MP_Free_proxy( _the_thread ) \ -{ \ - Thread_Proxy_control *_the_proxy; \ - \ - _the_proxy = (Thread_Proxy_control *) (_the_thread); \ - \ - _Chain_Extract( &_the_proxy->Active ); \ - \ - _Chain_Append( \ - &_Thread_MP_Inactive_proxies, \ - &(_the_thread)->Object.Node \ - ); \ -} - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/tod.inl b/c/src/exec/score/macros/rtems/score/tod.inl deleted file mode 100644 index 2fa91b127b..0000000000 --- a/c/src/exec/score/macros/rtems/score/tod.inl +++ /dev/null @@ -1,48 +0,0 @@ -/* tod.inl - * - * This file contains the macro implementation of the inlined routines - * from the Time of Day Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __TIME_OF_DAY_inl -#define __TIME_OF_DAY_inl - -/*PAGE - * - * _TOD_Tickle_ticks - * - */ - -#define _TOD_Tickle_ticks() \ - _TOD_Current.ticks++; \ - _Watchdog_Ticks_since_boot++ - -/*PAGE - * - * _TOD_Deactivate - * - */ - -#define _TOD_Deactivate() \ - _Watchdog_Remove( &_TOD_Seconds_watchdog ) - -/*PAGE - * - * _TOD_Activate - * - */ - -#define _TOD_Activate( _ticks ) \ - _Watchdog_Insert_ticks( &_TOD_Seconds_watchdog, (_ticks) ) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/tqdata.inl b/c/src/exec/score/macros/rtems/score/tqdata.inl deleted file mode 100644 index 96be35427b..0000000000 --- a/c/src/exec/score/macros/rtems/score/tqdata.inl +++ /dev/null @@ -1,49 +0,0 @@ -/* tqdata.inl - * - * This file contains the macro implementation of the inlined - * routines needed to support the Thread Queue Data. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __THREAD_QUEUE_DATA_inl -#define __THREAD_QUEUE_DATA_inl - -/*PAGE - * - * _Thread_queue_Header_number - * - */ - -#define _Thread_queue_Header_number( _the_priority ) \ - ((_the_priority) / TASK_QUEUE_DATA_PRIORITIES_PER_HEADER) - -/*PAGE - * - * _Thread_queue_Is_reverse_search - * - */ - -#define _Thread_queue_Is_reverse_search( _the_priority ) \ - ( (_the_priority) & TASK_QUEUE_DATA_REVERSE_SEARCH_MASK ) - -/*PAGE - * - * _Thread_queue_Enter_critical_section - * - */ - -#define _Thread_queue_Enter_critical_section( _the_thread_queue ) \ - do { \ - (_the_thread_queue)->sync_state = THREAD_QUEUE_NOTHING_HAPPENED; \ - } while ( 0 ) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/userext.inl b/c/src/exec/score/macros/rtems/score/userext.inl deleted file mode 100644 index 2c95e6a04e..0000000000 --- a/c/src/exec/score/macros/rtems/score/userext.inl +++ /dev/null @@ -1,132 +0,0 @@ -/* userext.inl - * - * This file contains the macro implementation of the inlined routines - * from the User Extension Handler - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __USER_EXTENSIONS_inl -#define __USER_EXTENSIONS_inl - -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _User_extensions_Add_set - * - * NOTE: Must be before _User_extensions_Handler_initialization to - * ensure proper inlining. - */ - -#define _User_extensions_Add_set( _the_extension, _extension_table ) \ - do { \ - (_the_extension)->Callouts = *(_extension_table); \ - \ - _Chain_Append( &_User_extensions_List, &(_the_extension)->Node ); \ - \ - if ( (_the_extension)->Callouts.thread_switch != NULL ) { \ - (_the_extension)->Switch.thread_switch = \ - (_the_extension)->Callouts.thread_switch; \ - _Chain_Append( \ - &_User_extensions_Switches_list, \ - &(_the_extension)->Switch.Node \ - ); \ - } \ - } while ( 0 ) - - -/*PAGE - * - * _User_extensions_Handler_initialization - * - */ - -#define _User_extensions_Handler_initialization( \ - _number_of_extensions, _initial_extensions \ -) \ - { \ - User_extensions_Control *extension; \ - unsigned32 i; \ - \ - _Chain_Initialize_empty( &_User_extensions_List ); \ - _Chain_Initialize_empty( &_User_extensions_Switches_list ); \ - \ - if ( (_initial_extensions) ) { \ - extension = _Workspace_Allocate_or_fatal_error( \ - sizeof(User_extensions_Control) * _number_of_extensions ); \ - \ - memset ( \ - extension, \ - 0, \ - _number_of_extensions * sizeof( User_extensions_Control ) \ - ); \ - \ - for ( i = 0 ; i < _number_of_extensions ; i++ ) { \ - _User_extensions_Add_set (extension, &_initial_extensions[i]); \ - extension++; \ - } \ - } \ - } - -/*PAGE - * - * _User_extensions_Add_API_set - */ - -#define _User_extensions_Add_API_set( _the_extension ) \ - do { \ - _Chain_Append( &_User_extensions_List, &(_the_extension)->Node ); \ - \ - if ( (_the_extension)->Callouts.thread_switch != NULL ) { \ - (_the_extension)->Switch.thread_switch = \ - (_the_extension)->Callouts.thread_switch; \ - _Chain_Append( \ - &_User_extensions_Switches_list, &(_the_extension)->Switch.Node ); \ - } \ - } while ( 0 ) - -/*PAGE - * - * _User_extensions_Remove_set - */ - -#define _User_extensions_Remove_set( _the_extension ) \ - do { \ - _Chain_Extract( &(_the_extension)->Node ); \ - \ - if ( (_the_extension)->Callouts.thread_switch != NULL ) { \ - _Chain_Extract( &(_the_extension)->Node ); \ - } \ - } while (0) - -/*PAGE - * - * _User_extensions_Thread_switch - * - */ - -#define _User_extensions_Thread_switch( _executing, _heir ) \ - do { \ - Chain_Node *the_node; \ - User_extensions_Switch_control *the_extension_switch; \ - \ - for ( the_node = _User_extensions_Switches_list.first ; \ - !_Chain_Is_tail( &_User_extensions_Switches_list, the_node ) ; \ - the_node = the_node->next ) { \ - \ - the_extension_switch = (User_extensions_Switch_control *) the_node; \ - \ - (*the_extension_switch->thread_switch)( _executing, _heir ); \ - } \ - } while (0) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/watchdog.inl b/c/src/exec/score/macros/rtems/score/watchdog.inl deleted file mode 100644 index 53a88eacad..0000000000 --- a/c/src/exec/score/macros/rtems/score/watchdog.inl +++ /dev/null @@ -1,171 +0,0 @@ -/* watchdog.inl - * - * This file contains the macro implementation of all inlined routines - * in the Watchdog Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __WATCHDOG_inl -#define __WATCHDOG_inl - -#include <rtems/score/object.h> - -/*PAGE - * - * _Watchdog_Initialize - * - */ - -#define _Watchdog_Initialize( _the_watchdog, _routine, _id, _user_data ) \ - { \ - (_the_watchdog)->state = WATCHDOG_INACTIVE; \ - (_the_watchdog)->routine = (_routine); \ - (_the_watchdog)->id = (_id); \ - (_the_watchdog)->user_data = (_user_data); \ - } - -/*PAGE - * - * _Watchdog_Is_active - * - */ - -#define _Watchdog_Is_active( _the_watchdog ) \ - ( (_the_watchdog)->state == WATCHDOG_ACTIVE ) - -/*PAGE - * - * _Watchdog_Activate - * - */ - -#define _Watchdog_Activate( _the_watchdog ) \ - (_the_watchdog)->state = WATCHDOG_ACTIVE - -/*PAGE - * - * _Watchdog_Deactivate - * - */ - -#define _Watchdog_Deactivate( _the_watchdog ) \ - (_the_watchdog)->state = WATCHDOG_REMOVE_IT - -/*PAGE - * - * _Watchdog_Tickle_ticks - * - */ - -#define _Watchdog_Tickle_ticks() \ - _Watchdog_Tickle( &_Watchdog_Ticks_chain ) - -/*PAGE - * - * _Watchdog_Tickle_seconds - * - */ - -#define _Watchdog_Tickle_seconds() \ - _Watchdog_Tickle( &_Watchdog_Seconds_chain ) - -/*PAGE - * - * _Watchdog_Insert_ticks - * - */ - -#define _Watchdog_Insert_ticks( _the_watchdog, _units ) \ - do { \ - (_the_watchdog)->initial = (_units); \ - _Watchdog_Insert( &_Watchdog_Ticks_chain, (_the_watchdog) ); \ - } while ( 0 ) - -/*PAGE - * - * _Watchdog_Insert_seconds - * - */ - -#define _Watchdog_Insert_seconds( _the_watchdog, _units ) \ - do { \ - (_the_watchdog)->initial = (_units); \ - _Watchdog_Insert( &_Watchdog_Seconds_chain, (_the_watchdog) ); \ - } while ( 0 ) - -/*PAGE - * - * _Watchdog_Adjust_seconds - * - */ - -#define _Watchdog_Adjust_seconds( _direction, _units ) \ - _Watchdog_Adjust( &_Watchdog_Seconds_chain, (_direction), (_units) ) - -/*PAGE - * - * _Watchdog_Adjust_ticks - * - */ - -#define _Watchdog_Adjust_ticks( _direction, _units ) \ - _Watchdog_Adjust( &_Watchdog_Ticks_chain, (_direction), (_units) ) - -/*PAGE - * - * _Watchdog_Reset - * - */ - -#define _Watchdog_Reset( _the_watchdog ) \ - { \ - (void) _Watchdog_Remove( (_the_watchdog) ); \ - _Watchdog_Insert( &_Watchdog_Ticks_chain, (_the_watchdog) ); \ - } - -/*PAGE - * - * _Watchdog_Next - * - */ - -#define _Watchdog_Next( _watchdog ) \ - ((Watchdog_Control *) (_watchdog)->Node.next) - -/*PAGE - * - * _Watchdog_Previous - * - */ - -#define _Watchdog_Previous( _watchdog ) \ - ((Watchdog_Control *) (_watchdog)->Node.previous) - -/*PAGE - * - * _Watchdog_First - * - */ - -#define _Watchdog_First( _header ) \ - ((Watchdog_Control *) (_header)->first) - -/*PAGE - * - * _Watchdog_Last - * - */ - -#define _Watchdog_Last( _header ) \ - ((Watchdog_Control *) (_header)->last) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/macros/rtems/score/wkspace.inl b/c/src/exec/score/macros/rtems/score/wkspace.inl deleted file mode 100644 index e327d27349..0000000000 --- a/c/src/exec/score/macros/rtems/score/wkspace.inl +++ /dev/null @@ -1,38 +0,0 @@ -/* wkspace.inl - * - * This file contains the macro implementation of the inlined routines - * from the RAM Workspace Handler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __WORKSPACE_inl -#define __WORKSPACE_inl - -/*PAGE - * - * _Workspace_Allocate - * - */ - -#define _Workspace_Allocate( _size ) \ - _Heap_Allocate( &_Workspace_Area, (_size) ) - -/*PAGE - * - * _Workspace_Free - * - */ - -#define _Workspace_Free( _block ) \ - _Heap_Free( &_Workspace_Area, (_block) ) - -#endif -/* end of include file */ diff --git a/c/src/exec/score/src/.cvsignore b/c/src/exec/score/src/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/src/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/src/Makefile.am b/c/src/exec/score/src/Makefile.am deleted file mode 100644 index 64d0d50a15..0000000000 --- a/c/src/exec/score/src/Makefile.am +++ /dev/null @@ -1,79 +0,0 @@ -## -## $Id$ -## - - -include $(top_srcdir)/automake/multilib.am -include $(top_srcdir)/automake/compile.am -include $(top_srcdir)/automake/lib.am - -# We only build multiprocessing related files if HAS_MP was defined -MP_C_FILES = mpci.c objectmp.c threadmp.c - -CORE_MESSAGE_QUEUE_C_FILES = coremsg.c coremsgbroadcast.c coremsgclose.c \ - coremsgflush.c coremsgflushwait.c coremsginsert.c coremsgflushsupp.c \ - coremsgseize.c coremsgsubmit.c - -CORE_MUTEX_C_FILES = coremutex.c coremutexflush.c coremutexseize.c \ - coremutexsurrender.c - -CORE_SEMAPHORE_C_FILES = coresem.c coresemflush.c coresemseize.c \ - coresemsurrender.c - -HEAP_C_FILES = heap.c heapallocate.c heapextend.c heapfree.c \ - heapsizeofuserarea.c heapwalk.c heapgetinfo.c - -OBJECT_C_FILES = object.c objectallocate.c objectallocatebyindex.c \ - objectclearname.c objectcomparenameraw.c objectcomparenamestring.c \ - objectcopynameraw.c objectcopynamestring.c objectextendinformation.c \ - objectfree.c objectget.c objectgetisr.c objectgetbyindex.c \ - objectgetnext.c objectinitializeinformation.c objectnametoid.c \ - objectshrinkinformation.c objectgetnoprotection.c - -THREAD_C_FILES = thread.c threadchangepriority.c threadclearstate.c \ - threadclose.c threadcreateidle.c threaddelayended.c threaddispatch.c \ - threadevaluatemode.c threadget.c threadhandler.c threadidlebody.c \ - threadinitialize.c threadloadenv.c threadready.c threadresettimeslice.c \ - threadreset.c threadrestart.c threadresume.c threadrotatequeue.c \ - threadsetpriority.c threadsetstate.c threadsettransient.c \ - threadstackallocate.c threadstackfree.c threadstart.c \ - threadstartmultitasking.c threadsuspend.c threadtickletimeslice.c \ - threadyieldprocessor.c - -THREADQ_C_FILES = threadq.c threadqdequeue.c threadqdequeuefifo.c \ - threadqdequeuepriority.c threadqenqueue.c threadqenqueuefifo.c \ - threadqenqueuepriority.c threadqextract.c threadqextractfifo.c \ - threadqextractpriority.c threadqextractwithproxy.c threadqfirst.c \ - threadqfirstfifo.c threadqfirstpriority.c threadqflush.c threadqtimeout.c - -TOD_C_FILES = coretod.c coretodset.c coretodtickle.c coretodtoseconds.c \ - coretodvalidate.c - -WATCHDOG_C_FILES = watchdog.c watchdogadjust.c watchdoginsert.c \ - watchdogremove.c watchdogtickle.c - -STD_C_FILES = apiext.c chain.c $(CORE_MESSAGE_QUEUE_C_FILES) \ - $(CORE_MUTEX_C_FILES) $(CORE_SEMAPHORE_C_FILES) $(HEAP_C_FILES) interr.c \ - isr.c $(OBJECT_C_FILES) $(THREAD_C_FILES) $(THREADQ_C_FILES) \ - $(TOD_C_FILES) userext.c $(WATCHDOG_C_FILES) wkspace.c - -if HAS_MP -C_FILES = $(STD_C_FILES) $(MP_C_FILES) -else -C_FILES = $(STD_C_FILES) -endif -C_O_FILES = $(C_FILES:%.c=${ARCH}/%.o) - -OBJS = $(C_O_FILES) - -# -# Add local stuff here using += -# - -AM_CPPFLAGS += -D__RTEMS_INSIDE__ - -all-local: ${ARCH} ${OBJS} - -EXTRA_DIST = $(STD_C_FILES) $(MP_C_FILES) Unlimited.txt - -include $(top_srcdir)/automake/local.am diff --git a/c/src/exec/score/src/Unlimited.txt b/c/src/exec/score/src/Unlimited.txt deleted file mode 100644 index 7340fc2dfe..0000000000 --- a/c/src/exec/score/src/Unlimited.txt +++ /dev/null @@ -1,387 +0,0 @@ -# -# $Id$ -# - -This document explains how the unlimited objects support works. This was -written by Chris Johns <ccj@acm.org> of Objective Design Systems as a -design document. This was submitted as part of the patch which added -this capability. - -Unlimited Local Node Objects -============================ - -1. Why ? - -This patch changes the way RTEMS allocates, frees, and manages the -'Objects_Control' structure. - -The 'Objects_Control' structure is at the root of all objects in -RTEMS. The RTEMS and POSIX API allows users to create tasks, message -queues, semaphores and other resources. These are all a type of -Object. The POSIX API allow similar operations. These also map to -Objects. - -Currently the number of objects that can be created is a static value -loaded into the Configuration table before starting the kernel. The -application cannot exceed these limits. Various means are used to tune -this value. During development the value is usually set large. This -saves having to change it everytime a developer adds a new -resource. With a large team of developers the configuration table file -can cycle through a large number of revisions. The wasted memory is -only recovered when memory runs short. The issue of the configuration -table parameters become more important the less memory you have. - -The Configuration table requires a calculation to occur at compile -time to set the size of the Workspace. The calculation is an -estimate. You need to specify an overhead value for memory that can -not be calculated. An example of memory that cannot be calculated is -stack sizes. This issue is not directly related to allowing unlimited -objects how-ever the need to calculate the memory usage for a system -in this manner is prone to error. - -I would like to see download support added to RTEMS. The kernel -configuration being set at boot time means a download application can -be limited. This can defeat one of the purposes of using downloaded -code, no need to change ROMs. In a system I worked on the cost to -change ROMS in a complete system was high and could take a week. This -change is the first phase of supporting downloaded applications. - -1.1 How do Objects work ? - -All applications interact with the super core (c/src/exec/score) via -an API. The central structure used in the super core is the -`object'. Two application interfaces exist. They are RTEMS and -POSIX. Both map to the super core using objects. - -An object in RTEMS is a resource which the user (through the API) -creates. The different types of objects are referred to as classes of -objects. An object is referenced by an id. This is of type `rtems_id' -and is a 32bit unsigned integer. The id is unique for each object no -matter what class. - -Objects are anchored by the `_Object_Information' structure. There is -one per type or class of object. A global table of pointers to each -information structure for a class of objects is held in -`Objects_Information_table'. - -Objects consist of 6 main structures. The `_Object_Information' is the -root structure. It contains pointers to the `local_table', -`name_table', `global_table', the Inactive chain, and the object -memory. It also contains the various variables which describe the -object. We are only concerned with the `local_table', `name_table', -Inactive chain, and the object memory to support unlimited objects. - -The `local_table' holds the pointers to open objects. A `local_table -entry which is null is free and the object will be sitting on the -Inactive chain. The index into the table is based on part of the -id. Given an id the you can find the index into the `local_table', and -therefore the object. The `local_table' has the entries for the -indexes below the minimum_id's index. The minimum_id is always set to -1 (the change allows another value to be selected if require). The -index of 0 is reserved and never used. This allows any actions using -an id of zero to fail or map to a special case. - -The `name_table' holds the names of the objects. Each entry in this -table is the maximum size the name of the object can be. The size of -names is not constrained by the object code (but is by the MP object -code, and the API and should be fixed). - -The `global_table' and code that uses it has not changed. I did not -look at the this code, and I am not farmilar with it. - -The Inactive chain stores objects which are free or not -allocated. This design saves searching for a free object when -allocating therefore providing a deterministic allocation scheme. When -the chain is empty a null is returned. - -The change documented below basically extends the `local_table' and -`name_table' structures at run-time. The memory used be these table -is not large compared to the memory for the objects, and so are never -reduced in size once extended. The object's memory grows and shrinks -depending of the user's usage. - -Currently, the user specifies the total number of objects in the -Configuration table. The change alters the function of the values in -the Configuration table. A flag can be masked on to the value which -selects the extending mode. If the user does not set the flag the -object code operates with an object ceiling. A small performance -overhead will be incurred as the allocate and free routines are now -not inlined and a check of the auto_extend flag is made. The remaining -value field of the Configuration table entry is total number of -objects that can be allocated when not in unlimited mode. - -If the user masks the flag on to a value on the Configuration table -auto-exdending mode is selected for that class of object. The value -becomes the allocation unit size. If there are no free objects the -object's tables are extended by the allocation unit number of -objects. The object table is shrunk when the user frees objects. The -table must have one free allocation block, and at least half the -allocation size of another block before the object memory of the free -allocation block is returned to the heap. This stops threshold -thrashing when objects around the allocation unit size and created and -destroyed. - -At least one allocation block size of objects is created and never -destroyed. - -The change to support unlimited objects has extended the object -information structure. - -The flag, `auto_extend' controls if the object can be automatically -extended. The user masks the flag RTEMS_UNLIMITED_FLAGS onto the -Configuration table number to select the auto-extend mode. This is -passed to the `_Objects_Initialize_information' function in the -parameter maximum. The flag is tested for and the auto_extend flag -updated to reflect the state of the flag before being stipped from the -maximum. - -The `allocation_size' is set to the parameter maxium in the function -`_Objects_Initialize_information' if `auto_extend' is true. Making the -allocation size small causes the memory to be allocated and freed more -often. This only effects the performance times for creating a resource -such as a task. It does how-ever give you fine grain memory -control. If the performance of creating resources is not a problem -make the size small. - -The size of the object is required to be stored. It is used when -extending the object information. - -A count of the object on the Inactive list is maintained. This is used -during freeing objects. If the count is above 1.5 times the -`allocation_size' an attempt is made to shrink the object -informtation. Shrinking might not always succeed as a single -allocation block might not be free. Random freeing of objects can -result in some fragmentation. Any further allocations will use the -free objects before extending the object's information tables. - -A table of inactive objects per block is maintained. This table, like -the `local_table' and `name_table' grows as more blocks are -allocated. A check is made of a blocks inactive count when an object -which is part of that block is freed. If the total inactive count -exceeds 1.5 times the allocation size, and the block's inactive count -is the allocation_size, the objects data block is returnd to the -workspace heap. - -The `objects_blocks' is a table of pointers. The object_block's pointers -point to the object's data block. The object's data block is a single -allocation of the name space and object space. This was two separate -allocations but is now one. The objects_block's table is use to -determine if a block is allocated, and the address of the memory block -to be returned to the workspace heap when the object informtation -space is shrunk. - -2.0 Detail Of the Auto-Extend Patch to rtems-4.0.0, Snapshot 19990302 - -o Configuration table support. - - Added a flag OBJECTS_UNLIMITED_OBJECTS to score/headers/object.h - header file. This is referenced in the file sapi/headers/config.h to - create the flag RTEMS_UNLIMITED_OBJECTS. A macro is provided to take - a resource count and apply the flag. The macro is called - `rtems_resource_unlimited'. The user uses this macro when building a - configuration table. It can be used with the condefs.h header file. - -o Object Information Structure - - The object information structure, Objects_Information, has been - extended with the follow fields : - - boolean auto_extend - - - When true the object's information tables can be extended untill - all memory is used. When false the current functionallity is - maintained. - - unsigned32 allocation_size - - - When auto_extend is true, it is the value in the Configuration - table and is the number of objects the object's information - tables are extended or shrunk. - - unsigned32 size - - - The size of the object. It is used to calculate the size of - memory required to be allocated when extending the table. - - unsigned32 inactive - - - The number of elements on the Inactive chain. - - unsigned32 *inactive_per_block - - - Pointer to a table of counts of the inactive objects from a - block on the Inactive chain. It is used to know which blocks are - all free and therefore can be returned to the heap. - - void **object_blocks - - - Pointer to a table of pointers to the object data. The table - holds the pointer used to return a block to the heap when - shrinking the object's information tables. - -o Changes to Existing Object Functions - - Two functions prototypes are added. They are : - - _Objects_Extend_information, - _Objects_Shrink_information - _Object_Allocate, and - _Object_Free - - The last were inlined, how-ever now they are not as they are too - complex to implement as macros now. - -o Object Inline and Macro Changes - - The functions : - - _Object_Allocate, and - _Object_Free - - are now not inlined. The function : - - _Objects_Get_local_object, and - _Objects_Set_local_object - - have been added. There was no provided interface to allow an API to - get/set an objects local pointer given an index. The POSIX code - should be updated to use this interface. - - The function : - - _Objects_Get_information - - has been moved to be an inline function. It is used in the get - object call which the API uses for every object reference. - -o Object Initialisation - - The function _Objects_Initialize_information has been changed to - initialisation of the information structure's fields then call the - new function _Objects_Extend_information. - - The first block of objects is always allocated and never - released. This means with the auto-extend flag set to true the user - still sees the same behaviour expected without this change. That is - the number objects specified in the Configuration table is the - number of object allocated during RTEMS initialisation. If not - enough memory is found during this initial extend a fatal error - occurs. The fatal error only occurs for this case of extending the - object's information tables. - -o Object Information Extend - - The _Object_Information_Extend is a new function. It takes some of - the code form the old _Object_Initialize_information function. The - function extends an object's information base. - - Extending the first time is a special case. The function assumes the - maximum index will be less than the minimum index. This means the - minimum index must be greater than 0 at initialisation. The other - special case made is coping the tables from the old location to the - new location. The first block case is trapped and tables are - initialised instead. Workspace allocation for the first block is - tested for an if the first block the allocate or fatal error call is - made. This traps an RTEMS initialise allocation error. - - The remainder of the code deals with all cases of extending the - object's information. - - The current block count is first determined, then a scan of the - object_block table is made to locate a free slot. Blocks can be - freed in any order. The index base for the block is also determined. - - If the index base is greater than the maximum index, the tables must - grow. To grow the tables, a new larger memory block is allocated and - the tables copied. The object's information structure is then - updated to point to the new tables. The tables are allocated in one - memory block from the work-space heap. The single block is then - broken down in the required tables. - - Once the tables are copied, and the new extended parts initialised - the table pointers in the object's information structure are - updated. This is protected by masking interrupts. - - The old table's memory block is returned to the heap. - - The names table and object is allocated. This again is a single - block which is divided. - - The objects are initialised onto a local Inactive chain. They are - then copied to the object's Inactive chain to complete the - initialisation. - -o Object Informtation Shrink - - The _Object_Shrink_information function is new. It is required to - scan all the blocks to see which one has no objects allocated. The - last object freed might not belong to a block which is completely - free. - - Once a block is located, the Inactive chain is interated down - looking for objects which belong to the block of object being - released. - - Once the Inactive chain scan is complete the names table and object - memory is returned to the work-space heap and the table references cleared. - - XXX - I am not sure if this should occur if better protection or - different code to provide better protection. - - The information tables do not change size. Once extended they never - shrink. - -o Object Allocation - - The _Objects_Allocate attempts to get an object from the Inactive - chain. If auto-extend mode is not enabled no further processing - occurs. The extra overhead for this implemetation is the function is - not inlined and check of a boolean occurs. It should effect the - timing figures. - - If auto-extend is enabled, a further check is made to see if the get - from the Inactive chain suceeded in getting an object. If it failed - a call is made to extend the object's information tables. - - The get from the Inactive chain is retried. The result of this is - returned to the user. A failure here is the users problem. - -o Object Free - - The _Objects_Free puts the object back onto the Inactive - chain. Again if auto-extend mode is not enabled no further - processing occurs and performance overhead will low. - - If auto-extend mode is enabled, a check is to see if the number of - Inactive objects is one and a half times the allocation size. If - there are that many free objects an attempt is made to shrink the - object's information. - -o Object Index and the Get Function - - The existing code allocates the number of object specified in the - configuration table, how-ever it makes the local_table have one more - element. This is the slot for an id of 0. The 0 slot is always a - NULL providing a simple check for a 0 id for object classes. - - The existing _Objects_Get code removes the minimum id, which I think - could only be 1 from the index, then adds one for the 0 slot. - - This change removes this index adjustment code in _Objects_Get. - - The extend information starts the index count when scanning for free - blocks at the minumun index. This means the base index for a block - will always be adjusted by the minimum index. The extend information - function only ever allocates the allocation size of - objects. Finially the object's local_table size is the maximum plus - the minumum index size. The maximum is really the maximum index. - - This means the values in the object's information structure and - tables do not need the index adjustments which existed before. - -o The Test - - A new sample test, unlimited is provided. It attempts to test this - change. - - diff --git a/c/src/exec/score/src/apiext.c b/c/src/exec/score/src/apiext.c deleted file mode 100644 index 5bb2ad658e..0000000000 --- a/c/src/exec/score/src/apiext.c +++ /dev/null @@ -1,104 +0,0 @@ -/* apiext.c - * - * XXX - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -#include <rtems/system.h> -#include <rtems/score/apiext.h> - -/*PAGE - * - * _API_extensions_Initialization - */ - -void _API_extensions_Initialization( void ) -{ - _Chain_Initialize_empty( &_API_extensions_List ); -} - -/*PAGE - * - * _API_extensions_Add - */ - -void _API_extensions_Add( - API_extensions_Control *the_extension -) -{ - _Chain_Append( &_API_extensions_List, &the_extension->Node ); -} - -/*PAGE - * - * _API_extensions_Run_predriver - */ - -void _API_extensions_Run_predriver( void ) -{ - Chain_Node *the_node; - API_extensions_Control *the_extension; - - for ( the_node = _API_extensions_List.first ; - !_Chain_Is_tail( &_API_extensions_List, the_node ) ; - the_node = the_node->next ) { - - the_extension = (API_extensions_Control *) the_node; - - if ( the_extension->predriver_hook ) - (*the_extension->predriver_hook)(); - } -} - -/*PAGE - * - * _API_extensions_Run_postdriver - */ - -void _API_extensions_Run_postdriver( void ) -{ - Chain_Node *the_node; - API_extensions_Control *the_extension; - - for ( the_node = _API_extensions_List.first ; - !_Chain_Is_tail( &_API_extensions_List, the_node ) ; - the_node = the_node->next ) { - - the_extension = (API_extensions_Control *) the_node; - - if ( the_extension->postdriver_hook ) - (*the_extension->postdriver_hook)(); - } -} - -/*PAGE - * - * _API_extensions_Run_postswitch - */ - -void _API_extensions_Run_postswitch( void ) -{ - Chain_Node *the_node; - API_extensions_Control *the_extension; - - for ( the_node = _API_extensions_List.first ; - !_Chain_Is_tail( &_API_extensions_List, the_node ) ; - the_node = the_node->next ) { - - the_extension = (API_extensions_Control *) the_node; - - if ( the_extension->postswitch_hook ) - (*the_extension->postswitch_hook)( _Thread_Executing ); - } -} - -/* end of file */ diff --git a/c/src/exec/score/src/chain.c b/c/src/exec/score/src/chain.c deleted file mode 100644 index 1819968c76..0000000000 --- a/c/src/exec/score/src/chain.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Chain Handler - * - * NOTE: - * - * The order of this file is to allow proper compilation due to the - * order of inlining required by the compiler. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Chain_Initialize - * - * This kernel routine initializes a doubly linked chain. - * - * Input parameters: - * the_chain - pointer to chain header - * starting_address - starting address of first node - * number_nodes - number of nodes in chain - * node_size - size of node in bytes - * - * Output parameters: NONE - */ - -void _Chain_Initialize( - Chain_Control *the_chain, - void *starting_address, - unsigned32 number_nodes, - unsigned32 node_size -) -{ - unsigned32 count; - Chain_Node *current; - Chain_Node *next; - - count = number_nodes; - current = _Chain_Head( the_chain ); - the_chain->permanent_null = NULL; - next = (Chain_Node *)starting_address; - while ( count-- ) { - current->next = next; - next->previous = current; - current = next; - next = (Chain_Node *) - _Addresses_Add_offset( (void *) next, node_size ); - } - current->next = _Chain_Tail( the_chain ); - the_chain->last = current; -} - -/*PAGE - * - * _Chain_Get_first_unprotected - */ - -#ifndef USE_INLINES -Chain_Node *_Chain_Get_first_unprotected( - Chain_Control *the_chain -) -{ - Chain_Node *return_node; - Chain_Node *new_first; - - return_node = the_chain->first; - new_first = return_node->next; - the_chain->first = new_first; - new_first->previous = _Chain_Head( the_chain ); - - return return_node; -} -#endif /* USE_INLINES */ - -/*PAGE - * - * _Chain_Get - * - * This kernel routine returns a pointer to a node taken from the - * given chain. - * - * Input parameters: - * the_chain - pointer to chain header - * - * Output parameters: - * return_node - pointer to node in chain allocated - * CHAIN_END - if no nodes available - * - * INTERRUPT LATENCY: - * only case - */ - -Chain_Node *_Chain_Get( - Chain_Control *the_chain -) -{ - ISR_Level level; - Chain_Node *return_node; - - return_node = NULL; - _ISR_Disable( level ); - if ( !_Chain_Is_empty( the_chain ) ) - return_node = _Chain_Get_first_unprotected( the_chain ); - _ISR_Enable( level ); - return return_node; -} - -/*PAGE - * - * _Chain_Append - * - * This kernel routine puts a node on the end of the specified chain. - * - * Input parameters: - * the_chain - pointer to chain header - * node - address of node to put at rear of chain - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * only case - */ - -void _Chain_Append( - Chain_Control *the_chain, - Chain_Node *node -) -{ - ISR_Level level; - - _ISR_Disable( level ); - _Chain_Append_unprotected( the_chain, node ); - _ISR_Enable( level ); -} - -/*PAGE - * - * _Chain_Extract - * - * This kernel routine deletes the given node from a chain. - * - * Input parameters: - * node - pointer to node in chain to be deleted - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * only case - */ - -void _Chain_Extract( - Chain_Node *node -) -{ - ISR_Level level; - - _ISR_Disable( level ); - _Chain_Extract_unprotected( node ); - _ISR_Enable( level ); -} - -/*PAGE - * - * _Chain_Insert - * - * This kernel routine inserts a given node after a specified node - * a requested chain. - * - * Input parameters: - * after_node - pointer to node in chain to be inserted after - * node - pointer to node to be inserted - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * only case - */ - -void _Chain_Insert( - Chain_Node *after_node, - Chain_Node *node -) -{ - ISR_Level level; - - _ISR_Disable( level ); - _Chain_Insert_unprotected( after_node, node ); - _ISR_Enable( level ); -} diff --git a/c/src/exec/score/src/coremsg.c b/c/src/exec/score/src/coremsg.c deleted file mode 100644 index 5ae58a2908..0000000000 --- a/c/src/exec/score/src/coremsg.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * CORE Message Queue Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Message Queue Handler. - * This core object provides task synchronization and communication functions - * via messages passed to queue objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/coremsg.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * _CORE_message_queue_Initialize - * - * This routine initializes a newly created message queue based on the - * specified data. - * - * Input parameters: - * the_message_queue - the message queue to initialize - * the_class - the API specific object class - * the_message_queue_attributes - the message queue's attributes - * maximum_pending_messages - maximum message and reserved buffer count - * maximum_message_size - maximum size of each message - * - * Output parameters: - * TRUE - if the message queue is initialized - * FALSE - if the message queue is NOT initialized - */ - -boolean _CORE_message_queue_Initialize( - CORE_message_queue_Control *the_message_queue, - CORE_message_queue_Attributes *the_message_queue_attributes, - unsigned32 maximum_pending_messages, - unsigned32 maximum_message_size -) -{ - unsigned32 message_buffering_required; - unsigned32 allocated_message_size; - - the_message_queue->maximum_pending_messages = maximum_pending_messages; - the_message_queue->number_of_pending_messages = 0; - the_message_queue->maximum_message_size = maximum_message_size; - _CORE_message_queue_Set_notify( the_message_queue, NULL, NULL ); - - /* - * round size up to multiple of a ptr for chain init - */ - - allocated_message_size = maximum_message_size; - if (allocated_message_size & (sizeof(unsigned32) - 1)) { - allocated_message_size += sizeof(unsigned32); - allocated_message_size &= ~(sizeof(unsigned32) - 1); - } - - message_buffering_required = maximum_pending_messages * - (allocated_message_size + sizeof(CORE_message_queue_Buffer_control)); - - the_message_queue->message_buffers = (CORE_message_queue_Buffer *) - _Workspace_Allocate( message_buffering_required ); - - if (the_message_queue->message_buffers == 0) - return FALSE; - - _Chain_Initialize ( - &the_message_queue->Inactive_messages, - the_message_queue->message_buffers, - maximum_pending_messages, - allocated_message_size + sizeof( CORE_message_queue_Buffer_control ) - ); - - _Chain_Initialize_empty( &the_message_queue->Pending_messages ); - - _Thread_queue_Initialize( - &the_message_queue->Wait_queue, - _CORE_message_queue_Is_priority( the_message_queue_attributes ) ? - THREAD_QUEUE_DISCIPLINE_PRIORITY : THREAD_QUEUE_DISCIPLINE_FIFO, - STATES_WAITING_FOR_MESSAGE, - CORE_MESSAGE_QUEUE_STATUS_TIMEOUT - ); - - return TRUE; -} diff --git a/c/src/exec/score/src/coremsgbroadcast.c b/c/src/exec/score/src/coremsgbroadcast.c deleted file mode 100644 index 18e148ab1c..0000000000 --- a/c/src/exec/score/src/coremsgbroadcast.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * CORE Message Queue Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Message Queue Handler. - * This core object provides task synchronization and communication functions - * via messages passed to queue objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/coremsg.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * _CORE_message_queue_Broadcast - * - * This function sends a message for every thread waiting on the queue and - * returns the number of threads made ready by the message. - * - * Input parameters: - * the_message_queue - message is submitted to this message queue - * buffer - pointer to message buffer - * size - size in bytes of message to send - * id - id of message queue - * api_message_queue_mp_support - api specific mp support callout - * count - area to store number of threads made ready - * - * Output parameters: - * count - number of threads made ready - * CORE_MESSAGE_QUEUE_SUCCESSFUL - if successful - * error code - if unsuccessful - */ - -CORE_message_queue_Status _CORE_message_queue_Broadcast( - CORE_message_queue_Control *the_message_queue, - void *buffer, - unsigned32 size, - Objects_Id id, - CORE_message_queue_API_mp_support_callout api_message_queue_mp_support, - unsigned32 *count -) -{ - Thread_Control *the_thread; - unsigned32 number_broadcasted; - Thread_Wait_information *waitp; - unsigned32 constrained_size; - - /* - * If there are pending messages, then there can't be threads - * waiting for us to send them a message. - * - * NOTE: This check is critical because threads can block on - * send and receive and this ensures that we are broadcasting - * the message to threads waiting to receive -- not to send. - */ - - if ( the_message_queue->number_of_pending_messages != 0 ) { - *count = 0; - return CORE_MESSAGE_QUEUE_STATUS_SUCCESSFUL; - } - - /* - * There must be no pending messages if there is a thread waiting to - * receive a message. - */ - - number_broadcasted = 0; - while ((the_thread = _Thread_queue_Dequeue(&the_message_queue->Wait_queue))) { - waitp = &the_thread->Wait; - number_broadcasted += 1; - - constrained_size = size; - if ( size > the_message_queue->maximum_message_size ) - constrained_size = the_message_queue->maximum_message_size; - - _CORE_message_queue_Copy_buffer( - buffer, - waitp->return_argument, - constrained_size - ); - - *(unsigned32 *)the_thread->Wait.return_argument_1 = size; - -#if defined(RTEMS_MULTIPROCESSING) - if ( !_Objects_Is_local_id( the_thread->Object.id ) ) - (*api_message_queue_mp_support) ( the_thread, id ); -#endif - - } - *count = number_broadcasted; - return CORE_MESSAGE_QUEUE_STATUS_SUCCESSFUL; -} - diff --git a/c/src/exec/score/src/coremsgclose.c b/c/src/exec/score/src/coremsgclose.c deleted file mode 100644 index 245c18524f..0000000000 --- a/c/src/exec/score/src/coremsgclose.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * CORE Message Queue Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Message Queue Handler. - * This core object provides task synchronization and communication functions - * via messages passed to queue objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/coremsg.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * _CORE_message_queue_Close - * - * This function closes a message by returning all allocated space and - * flushing the message_queue's task wait queue. - * - * Input parameters: - * the_message_queue - the message_queue to be flushed - * remote_extract_callout - function to invoke remotely - * status - status to pass to thread - * - * Output parameters: NONE - */ - -void _CORE_message_queue_Close( - CORE_message_queue_Control *the_message_queue, - Thread_queue_Flush_callout remote_extract_callout, - unsigned32 status -) -{ - - /* - * This will flush blocked threads whether they were blocked on - * a send or receive. - */ - - _Thread_queue_Flush( - &the_message_queue->Wait_queue, - remote_extract_callout, - status - ); - - /* - * This removes all messages from the pending message queue. Since - * we just flushed all waiting threads, we don't have to worry about - * the flush satisfying any blocked senders as a side-effect. - */ - - if ( the_message_queue->number_of_pending_messages != 0 ) - (void) _CORE_message_queue_Flush_support( the_message_queue ); - - (void) _Workspace_Free( the_message_queue->message_buffers ); - -} - diff --git a/c/src/exec/score/src/coremsgflush.c b/c/src/exec/score/src/coremsgflush.c deleted file mode 100644 index 957d00a59e..0000000000 --- a/c/src/exec/score/src/coremsgflush.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * CORE Message Queue Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Message Queue Handler. - * This core object provides task synchronization and communication functions - * via messages passed to queue objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/coremsg.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * _CORE_message_queue_Flush - * - * This function flushes the message_queue's pending message queue. The - * number of messages flushed from the queue is returned. - * - * Input parameters: - * the_message_queue - the message_queue to be flushed - * - * Output parameters: - * returns - the number of messages flushed from the queue - */ - -unsigned32 _CORE_message_queue_Flush( - CORE_message_queue_Control *the_message_queue -) -{ - if ( the_message_queue->number_of_pending_messages != 0 ) - return _CORE_message_queue_Flush_support( the_message_queue ); - else - return 0; -} - diff --git a/c/src/exec/score/src/coremsgflushsupp.c b/c/src/exec/score/src/coremsgflushsupp.c deleted file mode 100644 index 4bfd8f358b..0000000000 --- a/c/src/exec/score/src/coremsgflushsupp.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * CORE Message Queue Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Message Queue Handler. - * This core object provides task synchronization and communication functions - * via messages passed to queue objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/coremsg.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * _CORE_message_queue_Flush_support - * - * This message handler routine removes all messages from a message queue - * and returns them to the inactive message pool. The number of messages - * flushed from the queue is returned - * - * Input parameters: - * the_message_queue - pointer to message queue - * - * Output parameters: - * returns - number of messages placed on inactive chain - * - * INTERRUPT LATENCY: - * only case - */ - -unsigned32 _CORE_message_queue_Flush_support( - CORE_message_queue_Control *the_message_queue -) -{ - ISR_Level level; - Chain_Node *inactive_first; - Chain_Node *message_queue_first; - Chain_Node *message_queue_last; - unsigned32 count; - - /* - * Currently, RTEMS supports no API that has both flush and blocking - * sends. Thus, this routine assumes that there are no senders - * blocked waiting to send messages. In the event, that an API is - * added that can flush a message queue when threads are blocked - * waiting to send, there are two basic behaviors envisioned: - * - * (1) The thread queue of pending senders is a logical extension - * of the pending message queue. In this case, it should be - * flushed using the _Thread_queue_Flush() service with a status - * such as CORE_MESSAGE_QUEUE_SENDER_FLUSHED (which currently does - * not exist). This can be implemented without changing the "big-O" - * of the message flushing part of the routine. - * - * (2) Only the actual messages queued should be purged. In this case, - * the blocked sender threads must be allowed to send their messages. - * In this case, the implementation will be forced to individually - * dequeue the senders and queue their messages. This will force - * this routine to have "big O(n)" where n is the number of blocked - * senders. If there are more messages pending than senders blocked, - * then the existing flush code can be used to dispose of the remaining - * pending messages. - * - * For now, though, we are very happy to have a small routine with - * fixed execution time that only deals with pending messages. - */ - - _ISR_Disable( level ); - inactive_first = the_message_queue->Inactive_messages.first; - message_queue_first = the_message_queue->Pending_messages.first; - message_queue_last = the_message_queue->Pending_messages.last; - - the_message_queue->Inactive_messages.first = message_queue_first; - message_queue_last->next = inactive_first; - inactive_first->previous = message_queue_last; - message_queue_first->previous = - _Chain_Head( &the_message_queue->Inactive_messages ); - - _Chain_Initialize_empty( &the_message_queue->Pending_messages ); - - count = the_message_queue->number_of_pending_messages; - the_message_queue->number_of_pending_messages = 0; - _ISR_Enable( level ); - return count; -} - diff --git a/c/src/exec/score/src/coremsgflushwait.c b/c/src/exec/score/src/coremsgflushwait.c deleted file mode 100644 index bda8143ffd..0000000000 --- a/c/src/exec/score/src/coremsgflushwait.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * CORE Message Queue Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Message Queue Handler. - * This core object provides task synchronization and communication functions - * via messages passed to queue objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/coremsg.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * _CORE_message_queue_Flush_waiting_threads - * - * This function flushes the message_queue's task wait queue. The number - * of messages flushed from the queue is returned. - * - * Input parameters: - * the_message_queue - the message_queue to be flushed - * - * Output parameters: - * returns - the number of messages flushed from the queue - */ - -void _CORE_message_queue_Flush_waiting_threads( - CORE_message_queue_Control *the_message_queue -) -{ - /* XXX this is not supported for global message queues */ - - /* - * IF there are no pending messages, - * THEN threads may be blocked waiting to RECEIVE a message, - * - * IF the pending message queue is full - * THEN threads may be blocked waiting to SEND a message - * - * But in either case, we will return "unsatisfied nowait" - * to indicate that the blocking condition was not satisfied - * and that the blocking state was canceled. - */ - - _Thread_queue_Flush( - &the_message_queue->Wait_queue, - NULL, - CORE_MESSAGE_QUEUE_STATUS_UNSATISFIED_NOWAIT - ); -} - diff --git a/c/src/exec/score/src/coremsginsert.c b/c/src/exec/score/src/coremsginsert.c deleted file mode 100644 index f468334c97..0000000000 --- a/c/src/exec/score/src/coremsginsert.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * CORE Message Queue Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Message Queue Handler. - * This core object provides task synchronization and communication functions - * via messages passed to queue objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/coremsg.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * _CORE_message_queue_Insert_message - * - * This kernel routine inserts the specified message into the - * message queue. It is assumed that the message has been filled - * in before this routine is called. - * - * Input parameters: - * the_message_queue - pointer to message queue - * the_message - message to insert - * priority - insert indication - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * insert - */ - -void _CORE_message_queue_Insert_message( - CORE_message_queue_Control *the_message_queue, - CORE_message_queue_Buffer_control *the_message, - CORE_message_queue_Submit_types submit_type -) -{ - the_message_queue->number_of_pending_messages += 1; - - the_message->priority = submit_type; - - switch ( submit_type ) { - case CORE_MESSAGE_QUEUE_SEND_REQUEST: - _CORE_message_queue_Append( the_message_queue, the_message ); - break; - case CORE_MESSAGE_QUEUE_URGENT_REQUEST: - _CORE_message_queue_Prepend( the_message_queue, the_message ); - break; - default: - /* XXX interrupt critical section needs to be addressed */ - { - CORE_message_queue_Buffer_control *this_message; - Chain_Node *the_node; - Chain_Control *the_header; - - the_header = &the_message_queue->Pending_messages; - the_node = the_header->first; - while ( !_Chain_Is_tail( the_header, the_node ) ) { - - this_message = (CORE_message_queue_Buffer_control *) the_node; - - if ( this_message->priority <= the_message->priority ) { - the_node = the_node->next; - continue; - } - - break; - } - _Chain_Insert( the_node->previous, &the_message->Node ); - } - break; - } - - /* - * According to POSIX, does this happen before or after the message - * is actually enqueued. It is logical to think afterwards, because - * the message is actually in the queue at this point. - */ - - if ( the_message_queue->number_of_pending_messages == 1 && - the_message_queue->notify_handler ) - (*the_message_queue->notify_handler)( the_message_queue->notify_argument ); -} diff --git a/c/src/exec/score/src/coremsgseize.c b/c/src/exec/score/src/coremsgseize.c deleted file mode 100644 index 9e72f2f8a1..0000000000 --- a/c/src/exec/score/src/coremsgseize.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * CORE Message Queue Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Message Queue Handler. - * This core object provides task synchronization and communication functions - * via messages passed to queue objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/coremsg.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * _CORE_message_queue_Seize - * - * This kernel routine dequeues a message, copies the message buffer to - * a given destination buffer, and frees the message buffer to the - * inactive message pool. The thread will be blocked if wait is TRUE, - * otherwise an error will be given to the thread if no messages are available. - * - * Input parameters: - * the_message_queue - pointer to message queue - * id - id of object we are waitig on - * buffer - pointer to message buffer to be filled - * size - pointer to the size of buffer to be filled - * wait - TRUE if wait is allowed, FALSE otherwise - * timeout - time to wait for a message - * - * Output parameters: NONE - * - * NOTE: Dependent on BUFFER_LENGTH - * - * INTERRUPT LATENCY: - * available - * wait - */ - -void _CORE_message_queue_Seize( - CORE_message_queue_Control *the_message_queue, - Objects_Id id, - void *buffer, - unsigned32 *size, - boolean wait, - Watchdog_Interval timeout -) -{ - ISR_Level level; - CORE_message_queue_Buffer_control *the_message; - Thread_Control *executing; - Thread_Control *the_thread; - - executing = _Thread_Executing; - executing->Wait.return_code = CORE_MESSAGE_QUEUE_STATUS_SUCCESSFUL; - _ISR_Disable( level ); - if ( the_message_queue->number_of_pending_messages != 0 ) { - the_message_queue->number_of_pending_messages -= 1; - - the_message = _CORE_message_queue_Get_pending_message( the_message_queue ); - _ISR_Enable( level ); - - *size = the_message->Contents.size; - _Thread_Executing->Wait.count = the_message->priority; - _CORE_message_queue_Copy_buffer(the_message->Contents.buffer,buffer,*size); - - /* - * There could be a thread waiting to send a message. If there - * is not, then we can go ahead and free the buffer. - * - * NOTE: If we note that the queue was not full before this receive, - * then we can avoid this dequeue. - */ - - the_thread = _Thread_queue_Dequeue( &the_message_queue->Wait_queue ); - if ( !the_thread ) { - _CORE_message_queue_Free_message_buffer( the_message_queue, the_message ); - return; - } - - /* - * There was a thread waiting to send a message. This code - * puts the messages in the message queue on behalf of the - * waiting task. - */ - - the_message->priority = the_thread->Wait.count; - the_message->Contents.size = (unsigned32)the_thread->Wait.return_argument_1; - _CORE_message_queue_Copy_buffer( - the_thread->Wait.return_argument, - the_message->Contents.buffer, - the_message->Contents.size - ); - - _CORE_message_queue_Insert_message( - the_message_queue, - the_message, - the_message->priority - ); - return; - } - - if ( !wait ) { - _ISR_Enable( level ); - executing->Wait.return_code = CORE_MESSAGE_QUEUE_STATUS_UNSATISFIED_NOWAIT; - return; - } - - _Thread_queue_Enter_critical_section( &the_message_queue->Wait_queue ); - executing->Wait.queue = &the_message_queue->Wait_queue; - executing->Wait.id = id; - executing->Wait.return_argument = (void *)buffer; - executing->Wait.return_argument_1 = (void *)size; - /* Wait.count will be filled in with the message priority */ - _ISR_Enable( level ); - - _Thread_queue_Enqueue( &the_message_queue->Wait_queue, timeout ); -} - diff --git a/c/src/exec/score/src/coremsgsubmit.c b/c/src/exec/score/src/coremsgsubmit.c deleted file mode 100644 index eabcb79ddf..0000000000 --- a/c/src/exec/score/src/coremsgsubmit.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * CORE Message Queue Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Message Queue Handler. - * This core object provides task synchronization and communication functions - * via messages passed to queue objects. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/coremsg.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * _CORE_message_queue_Submit - * - * This routine implements the send and urgent message functions. It - * processes a message that is to be submitted to the designated - * message queue. The message will either be processed as a - * send message which it will be inserted at the rear of the queue - * or it will be processed as an urgent message which will be inserted - * at the front of the queue. - * - * Input parameters: - * the_message_queue - message is submitted to this message queue - * buffer - pointer to message buffer - * size - size in bytes of message to send - * id - id of message queue - * api_message_queue_mp_support - api specific mp support callout - * submit_type - send or urgent message - * - * Output parameters: - * CORE_MESSAGE_QUEUE_SUCCESSFUL - if successful - * error code - if unsuccessful - */ - -CORE_message_queue_Status _CORE_message_queue_Submit( - CORE_message_queue_Control *the_message_queue, - void *buffer, - unsigned32 size, - Objects_Id id, - CORE_message_queue_API_mp_support_callout api_message_queue_mp_support, - CORE_message_queue_Submit_types submit_type, - boolean wait, - Watchdog_Interval timeout -) -{ - ISR_Level level; - CORE_message_queue_Buffer_control *the_message; - Thread_Control *the_thread; - - if ( size > the_message_queue->maximum_message_size ) { - return CORE_MESSAGE_QUEUE_STATUS_INVALID_SIZE; - } - - /* - * Is there a thread currently waiting on this message queue? - */ - - if ( the_message_queue->number_of_pending_messages == 0 ) { - the_thread = _Thread_queue_Dequeue( &the_message_queue->Wait_queue ); - if ( the_thread ) { - _CORE_message_queue_Copy_buffer( - buffer, - the_thread->Wait.return_argument, - size - ); - *(unsigned32 *)the_thread->Wait.return_argument_1 = size; - the_thread->Wait.count = submit_type; - -#if defined(RTEMS_MULTIPROCESSING) - if ( !_Objects_Is_local_id( the_thread->Object.id ) ) - (*api_message_queue_mp_support) ( the_thread, id ); -#endif - return CORE_MESSAGE_QUEUE_STATUS_SUCCESSFUL; - } - } - - /* - * No one waiting on the message queue at this time, so attempt to - * queue the message up for a future receive. - */ - - if ( the_message_queue->number_of_pending_messages < - the_message_queue->maximum_pending_messages ) { - - the_message = - _CORE_message_queue_Allocate_message_buffer( the_message_queue ); - - /* - * NOTE: If the system is consistent, this error should never occur. - */ - - if ( !the_message ) { - return CORE_MESSAGE_QUEUE_STATUS_UNSATISFIED; - } - - _CORE_message_queue_Copy_buffer( - buffer, - the_message->Contents.buffer, - size - ); - the_message->Contents.size = size; - the_message->priority = submit_type; - - _CORE_message_queue_Insert_message( - the_message_queue, - the_message, - submit_type - ); - return CORE_MESSAGE_QUEUE_STATUS_SUCCESSFUL; - } - - /* - * No message buffers were available so we may need to return an - * overflow error or block the sender until the message is placed - * on the queue. - */ - - if ( !wait ) { - return CORE_MESSAGE_QUEUE_STATUS_TOO_MANY; - } - - /* - * Do NOT block on a send if the caller is in an ISR. It is - * deadly to block in an ISR. - */ - - if ( _ISR_Is_in_progress() ) { - return CORE_MESSAGE_QUEUE_STATUS_UNSATISFIED; - } - - /* - * WARNING!! executing should NOT be used prior to this point. - * Thus the unusual choice to open a new scope and declare - * it as a variable. Doing this emphasizes how dangerous it - * would be to use this variable prior to here. - */ - - { - Thread_Control *executing = _Thread_Executing; - - _ISR_Disable( level ); - _Thread_queue_Enter_critical_section( &the_message_queue->Wait_queue ); - executing->Wait.queue = &the_message_queue->Wait_queue; - executing->Wait.id = id; - executing->Wait.return_argument = (void *)buffer; - executing->Wait.return_argument_1 = (void *)size; - executing->Wait.count = submit_type; - _ISR_Enable( level ); - - _Thread_queue_Enqueue( &the_message_queue->Wait_queue, timeout ); - } - - return CORE_MESSAGE_QUEUE_STATUS_UNSATISFIED_WAIT; -} diff --git a/c/src/exec/score/src/coremutex.c b/c/src/exec/score/src/coremutex.c deleted file mode 100644 index e2ef275b75..0000000000 --- a/c/src/exec/score/src/coremutex.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Mutex Handler - * - * DESCRIPTION: - * - * This package is the implementation of the Mutex Handler. - * This handler provides synchronization and mutual exclusion capabilities. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/coremutex.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> - -/*PAGE - * - * _CORE_mutex_Initialize - * - * This routine initializes a mutex at create time and set the control - * structure according to the values passed. - * - * Input parameters: - * the_mutex - the mutex control block to initialize - * the_mutex_attributes - the mutex attributes specified at create time - * initial_lock - mutex initial lock or unlocked status - * - * Output parameters: NONE - */ - -void _CORE_mutex_Initialize( - CORE_mutex_Control *the_mutex, - CORE_mutex_Attributes *the_mutex_attributes, - unsigned32 initial_lock -) -{ - -/* Add this to the RTEMS environment later ????????? - rtems_assert( initial_lock == CORE_MUTEX_LOCKED || - initial_lock == CORE_MUTEX_UNLOCKED ); - */ - - the_mutex->Attributes = *the_mutex_attributes; - the_mutex->lock = initial_lock; - the_mutex->blocked_count = 0; - -#if 0 - if ( !the_mutex_attributes->only_owner_release && - the_mutex_attributes->nesting_allowed ) { - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_BAD_ATTRIBUTES - ); - } -#endif - - if ( initial_lock == CORE_MUTEX_LOCKED ) { - the_mutex->nest_count = 1; - the_mutex->holder = _Thread_Executing; - the_mutex->holder_id = _Thread_Executing->Object.id; - if ( _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) || - _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) - _Thread_Executing->resource_count++; - } else { - the_mutex->nest_count = 0; - the_mutex->holder = NULL; - the_mutex->holder_id = 0; - } - - _Thread_queue_Initialize( - &the_mutex->Wait_queue, - _CORE_mutex_Is_fifo( the_mutex_attributes ) ? - THREAD_QUEUE_DISCIPLINE_FIFO : THREAD_QUEUE_DISCIPLINE_PRIORITY, - STATES_WAITING_FOR_MUTEX, - CORE_MUTEX_TIMEOUT - ); -} - diff --git a/c/src/exec/score/src/coremutexflush.c b/c/src/exec/score/src/coremutexflush.c deleted file mode 100644 index ad4f3b6cc3..0000000000 --- a/c/src/exec/score/src/coremutexflush.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Mutex Handler - * - * DESCRIPTION: - * - * This package is the implementation of the Mutex Handler. - * This handler provides synchronization and mutual exclusion capabilities. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/coremutex.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> - -/*PAGE - * - * _CORE_mutex_Flush - * - * This function a flushes the mutex's task wait queue. - * - * Input parameters: - * the_mutex - the mutex to be flushed - * remote_extract_callout - function to invoke remotely - * status - status to pass to thread - * - * Output parameters: NONE - */ - -void _CORE_mutex_Flush( - CORE_mutex_Control *the_mutex, - Thread_queue_Flush_callout remote_extract_callout, - unsigned32 status -) -{ - _Thread_queue_Flush( - &the_mutex->Wait_queue, - remote_extract_callout, - status - ); -} diff --git a/c/src/exec/score/src/coremutexseize.c b/c/src/exec/score/src/coremutexseize.c deleted file mode 100644 index 2fb2fc27e9..0000000000 --- a/c/src/exec/score/src/coremutexseize.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Mutex Handler - * - * DESCRIPTION: - * - * This package is the implementation of the Mutex Handler. - * This handler provides synchronization and mutual exclusion capabilities. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/coremutex.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> - -/*PAGE - * - * _CORE_mutex_Seize (interrupt blocking support) - * - * This routine blocks the caller thread after an attempt attempts to obtain - * the specified mutex has failed. - * - * Input parameters: - * the_mutex - pointer to mutex control block - * timeout - number of ticks to wait (0 means forever) - */ - -void _CORE_mutex_Seize_interrupt_blocking( - CORE_mutex_Control *the_mutex, - Watchdog_Interval timeout -) -{ - Thread_Control *executing; - - executing = _Thread_Executing; - if ( _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) ) { - if ( the_mutex->holder->current_priority > executing->current_priority ) { - _Thread_Change_priority( - the_mutex->holder, - executing->current_priority, - FALSE - ); - } - } - - the_mutex->blocked_count++; - _Thread_queue_Enqueue( &the_mutex->Wait_queue, timeout ); - - if ( _Thread_Executing->Wait.return_code == CORE_MUTEX_STATUS_SUCCESSFUL ) { - /* - * if CORE_MUTEX_DISCIPLINES_PRIORITY_INHERIT then nothing to do - * because this task is already the highest priority. - */ - - if ( _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) { - if (the_mutex->Attributes.priority_ceiling < executing->current_priority){ - _Thread_Change_priority( - executing, - the_mutex->Attributes.priority_ceiling, - FALSE - ); - } - } - } - _Thread_Enable_dispatch(); -} - -#if !defined(USE_INLINES) -int _CORE_mutex_Seize_interrupt_trylock( - CORE_mutex_Control *the_mutex, - ISR_Level *level_p -) -{ - Thread_Control *executing; - ISR_Level level = *level_p; - - /* disabled when you get here */ - - executing = _Thread_Executing; - executing->Wait.return_code = CORE_MUTEX_STATUS_SUCCESSFUL; - if ( !_CORE_mutex_Is_locked( the_mutex ) ) { - the_mutex->lock = CORE_MUTEX_LOCKED; - the_mutex->holder = executing; - the_mutex->holder_id = executing->Object.id; - the_mutex->nest_count = 1; - if ( _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) || - _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) - executing->resource_count++; - - if ( !_CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) { - _ISR_Enable( level ); - return 0; - } - /* else must be CORE_MUTEX_DISCIPLINES_PRIORITY_CEILING */ - { - Priority_Control ceiling; - Priority_Control current; - - ceiling = the_mutex->Attributes.priority_ceiling; - current = executing->current_priority; - if ( current == ceiling ) { - _ISR_Enable( level ); - return 0; - } - if ( current > ceiling ) { - _Thread_Disable_dispatch(); - _ISR_Enable( level ); - _Thread_Change_priority( - the_mutex->holder, - the_mutex->Attributes.priority_ceiling, - FALSE - ); - _Thread_Enable_dispatch(); - return 0; - } - /* if ( current < ceiling ) */ { - executing->Wait.return_code = CORE_MUTEX_STATUS_CEILING_VIOLATED; - the_mutex->nest_count = 0; /* undo locking above */ - executing->resource_count--; /* undo locking above */ - _ISR_Enable( level ); - return 0; - } - } - return 0; - } - - if ( _Thread_Is_executing( the_mutex->holder ) ) { - switch ( the_mutex->Attributes.lock_nesting_behavior ) { - case CORE_MUTEX_NESTING_ACQUIRES: - the_mutex->nest_count++; - _ISR_Enable( level ); - return 0; - case CORE_MUTEX_NESTING_IS_ERROR: - executing->Wait.return_code = CORE_MUTEX_STATUS_NESTING_NOT_ALLOWED; - _ISR_Enable( level ); - return 0; - case CORE_MUTEX_NESTING_BLOCKS: - break; - } - } - - return 1; -} -#endif diff --git a/c/src/exec/score/src/coremutexsurrender.c b/c/src/exec/score/src/coremutexsurrender.c deleted file mode 100644 index bd9cc5bf65..0000000000 --- a/c/src/exec/score/src/coremutexsurrender.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Mutex Handler - * - * DESCRIPTION: - * - * This package is the implementation of the Mutex Handler. - * This handler provides synchronization and mutual exclusion capabilities. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/coremutex.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> - -/* - * _CORE_mutex_Surrender - * - * DESCRIPTION: - * - * This routine frees a unit to the mutex. If a task was blocked waiting for - * a unit from this mutex, then that task will be readied and the unit - * given to that task. Otherwise, the unit will be returned to the mutex. - * - * Input parameters: - * the_mutex - the mutex to be flushed - * id - id of parent mutex - * api_mutex_mp_support - api dependent MP support actions - * - * Output parameters: - * CORE_MUTEX_STATUS_SUCCESSFUL - if successful - * core error code - if unsuccessful - */ - -CORE_mutex_Status _CORE_mutex_Surrender( - CORE_mutex_Control *the_mutex, - Objects_Id id, - CORE_mutex_API_mp_support_callout api_mutex_mp_support -) -{ - Thread_Control *the_thread; - Thread_Control *holder; - - holder = the_mutex->holder; - - /* - * The following code allows a thread (or ISR) other than the thread - * which acquired the mutex to release that mutex. This is only - * allowed when the mutex in quetion is FIFO or simple Priority - * discipline. But Priority Ceiling or Priority Inheritance mutexes - * must be released by the thread which acquired them. - */ - - if ( the_mutex->Attributes.only_owner_release ) { - if ( !_Thread_Is_executing( holder ) ) - return CORE_MUTEX_STATUS_NOT_OWNER_OF_RESOURCE; - } - - /* XXX already unlocked -- not right status */ - - if ( !the_mutex->nest_count ) - return CORE_MUTEX_STATUS_SUCCESSFUL; - - the_mutex->nest_count--; - - if ( the_mutex->nest_count != 0 ) { - switch ( the_mutex->Attributes.lock_nesting_behavior ) { - case CORE_MUTEX_NESTING_ACQUIRES: - return CORE_MUTEX_STATUS_SUCCESSFUL; - case CORE_MUTEX_NESTING_IS_ERROR: - /* should never occur */ - return CORE_MUTEX_STATUS_NESTING_NOT_ALLOWED; - case CORE_MUTEX_NESTING_BLOCKS: - /* Currently no API exercises this behavior. */ - break; - } - } - - if ( _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) || - _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) - holder->resource_count--; - the_mutex->holder = NULL; - the_mutex->holder_id = 0; - - /* - * Whether or not someone is waiting for the mutex, an - * inherited priority must be lowered if this is the last - * mutex (i.e. resource) this task has. - */ - - if ( _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) || - _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) { - if ( holder->resource_count == 0 && - holder->real_priority != holder->current_priority ) { - _Thread_Change_priority( holder, holder->real_priority, TRUE ); - } - } - - if ( ( the_thread = _Thread_queue_Dequeue( &the_mutex->Wait_queue ) ) ) { - -#if defined(RTEMS_MULTIPROCESSING) - if ( !_Objects_Is_local_id( the_thread->Object.id ) ) { - - the_mutex->holder = NULL; - the_mutex->holder_id = the_thread->Object.id; - the_mutex->nest_count = 1; - - ( *api_mutex_mp_support)( the_thread, id ); - - } else -#endif - { - - the_mutex->holder = the_thread; - the_mutex->holder_id = the_thread->Object.id; - if ( _CORE_mutex_Is_inherit_priority( &the_mutex->Attributes ) || - _CORE_mutex_Is_priority_ceiling( &the_mutex->Attributes ) ) - the_thread->resource_count++; - the_mutex->nest_count = 1; - - /* - * No special action for priority inheritance or priority ceiling - * because the_thread is guaranteed to be the highest priority - * thread waiting for the mutex. - */ - } - } else - the_mutex->lock = CORE_MUTEX_UNLOCKED; - - return CORE_MUTEX_STATUS_SUCCESSFUL; -} - diff --git a/c/src/exec/score/src/coresem.c b/c/src/exec/score/src/coresem.c deleted file mode 100644 index 9dc878ca6c..0000000000 --- a/c/src/exec/score/src/coresem.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * CORE Semaphore Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Semaphore Handler. - * This core object utilizes standard Dijkstra counting semaphores to provide - * synchronization and mutual exclusion capabilities. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/coresem.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * CORE_semaphore_Initialize - * - * This function initialize a semaphore and sets the initial value based - * on the given count. - * - * Input parameters: - * the_semaphore - the semaphore control block to initialize - * the_semaphore_attributes - the attributes specified at create time - * initial_value - semaphore's initial value - * - * Output parameters: NONE - */ - -void _CORE_semaphore_Initialize( - CORE_semaphore_Control *the_semaphore, - CORE_semaphore_Attributes *the_semaphore_attributes, - unsigned32 initial_value -) -{ - - the_semaphore->Attributes = *the_semaphore_attributes; - the_semaphore->count = initial_value; - - _Thread_queue_Initialize( - &the_semaphore->Wait_queue, - _CORE_semaphore_Is_priority( the_semaphore_attributes ) ? - THREAD_QUEUE_DISCIPLINE_PRIORITY : THREAD_QUEUE_DISCIPLINE_FIFO, - STATES_WAITING_FOR_SEMAPHORE, - CORE_SEMAPHORE_TIMEOUT - ); -} diff --git a/c/src/exec/score/src/coresemflush.c b/c/src/exec/score/src/coresemflush.c deleted file mode 100644 index e30f768aab..0000000000 --- a/c/src/exec/score/src/coresemflush.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * CORE Semaphore Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Semaphore Handler. - * This core object utilizes standard Dijkstra counting semaphores to provide - * synchronization and mutual exclusion capabilities. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/coresem.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * _CORE_semaphore_Flush - * - * This function a flushes the semaphore's task wait queue. - * - * Input parameters: - * the_semaphore - the semaphore to be flushed - * remote_extract_callout - function to invoke remotely - * status - status to pass to thread - * - * Output parameters: NONE - */ - -void _CORE_semaphore_Flush( - CORE_semaphore_Control *the_semaphore, - Thread_queue_Flush_callout remote_extract_callout, - unsigned32 status -) -{ - - _Thread_queue_Flush( - &the_semaphore->Wait_queue, - remote_extract_callout, - status - ); - -} diff --git a/c/src/exec/score/src/coresemseize.c b/c/src/exec/score/src/coresemseize.c deleted file mode 100644 index 0f3c25aeac..0000000000 --- a/c/src/exec/score/src/coresemseize.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * CORE Semaphore Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Semaphore Handler. - * This core object utilizes standard Dijkstra counting semaphores to provide - * synchronization and mutual exclusion capabilities. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/coresem.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * _CORE_semaphore_Seize - * - * This routine attempts to allocate a core semaphore to the calling thread. - * - * Input parameters: - * the_semaphore - pointer to semaphore control block - * id - id of object to wait on - * wait - TRUE if wait is allowed, FALSE otherwise - * timeout - number of ticks to wait (0 means forever) - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * available - * wait - */ - -void _CORE_semaphore_Seize( - CORE_semaphore_Control *the_semaphore, - Objects_Id id, - boolean wait, - Watchdog_Interval timeout -) -{ - Thread_Control *executing; - ISR_Level level; - - executing = _Thread_Executing; - executing->Wait.return_code = CORE_SEMAPHORE_STATUS_SUCCESSFUL; - _ISR_Disable( level ); - if ( the_semaphore->count != 0 ) { - the_semaphore->count -= 1; - _ISR_Enable( level ); - return; - } - - if ( !wait ) { - _ISR_Enable( level ); - executing->Wait.return_code = CORE_SEMAPHORE_STATUS_UNSATISFIED_NOWAIT; - return; - } - - _Thread_queue_Enter_critical_section( &the_semaphore->Wait_queue ); - executing->Wait.queue = &the_semaphore->Wait_queue; - executing->Wait.id = id; - _ISR_Enable( level ); - - _Thread_queue_Enqueue( &the_semaphore->Wait_queue, timeout ); -} diff --git a/c/src/exec/score/src/coresemsurrender.c b/c/src/exec/score/src/coresemsurrender.c deleted file mode 100644 index 1a54a5c712..0000000000 --- a/c/src/exec/score/src/coresemsurrender.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * CORE Semaphore Handler - * - * DESCRIPTION: - * - * This package is the implementation of the CORE Semaphore Handler. - * This core object utilizes standard Dijkstra counting semaphores to provide - * synchronization and mutual exclusion capabilities. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/coresem.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#endif - -/*PAGE - * - * _CORE_semaphore_Surrender - * - * Input parameters: - * the_semaphore - the semaphore to be flushed - * id - id of parent semaphore - * api_semaphore_mp_support - api dependent MP support actions - * - * Output parameters: - * CORE_SEMAPHORE_STATUS_SUCCESSFUL - if successful - * core error code - if unsuccessful - * - * Output parameters: - */ - -CORE_semaphore_Status _CORE_semaphore_Surrender( - CORE_semaphore_Control *the_semaphore, - Objects_Id id, - CORE_semaphore_API_mp_support_callout api_semaphore_mp_support -) -{ - Thread_Control *the_thread; - ISR_Level level; - CORE_semaphore_Status status; - - status = CORE_SEMAPHORE_STATUS_SUCCESSFUL; - - if ( (the_thread = _Thread_queue_Dequeue(&the_semaphore->Wait_queue)) ) { - - if ( !_Objects_Is_local_id( the_thread->Object.id ) ) - (*api_semaphore_mp_support) ( the_thread, id ); - - } else { - _ISR_Disable( level ); - if ( the_semaphore->count <= the_semaphore->Attributes.maximum_count ) - the_semaphore->count += 1; - else - status = CORE_SEMAPHORE_MAXIMUM_COUNT_EXCEEDED; - _ISR_Enable( level ); - } - - return status; -} - diff --git a/c/src/exec/score/src/coretod.c b/c/src/exec/score/src/coretod.c deleted file mode 100644 index ef1091e1d2..0000000000 --- a/c/src/exec/score/src/coretod.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Time of Day (TOD) Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/object.h> -#include <rtems/score/thread.h> -#include <rtems/score/tod.h> -#include <rtems/score/watchdog.h> - -/*PAGE - * - * _TOD_Handler_initialization - * - * This routine initializes the time of day handler. - * - * Input parameters: - * microseconds_per_tick - microseconds between clock ticks - * - * Output parameters: NONE - */ - -void _TOD_Handler_initialization( - unsigned32 microseconds_per_tick -) -{ - _TOD_Microseconds_per_tick = microseconds_per_tick; - - _TOD_Seconds_since_epoch = 0; - - _TOD_Current.year = TOD_BASE_YEAR; - _TOD_Current.month = 1; - _TOD_Current.day = 1; - _TOD_Current.hour = 0; - _TOD_Current.minute = 0; - _TOD_Current.second = 0; - _TOD_Current.ticks = 0; - - if ( microseconds_per_tick == 0 ) - _TOD_Ticks_per_second = 0; - else - _TOD_Ticks_per_second = - TOD_MICROSECONDS_PER_SECOND / microseconds_per_tick; - - _Watchdog_Initialize( &_TOD_Seconds_watchdog, _TOD_Tickle, 0, NULL ); - - _TOD_Is_set = FALSE; - _TOD_Activate( _TOD_Ticks_per_second ); -} diff --git a/c/src/exec/score/src/coretodset.c b/c/src/exec/score/src/coretodset.c deleted file mode 100644 index ddb6f8ee43..0000000000 --- a/c/src/exec/score/src/coretodset.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Time of Day (TOD) Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/object.h> -#include <rtems/score/thread.h> -#include <rtems/score/tod.h> -#include <rtems/score/watchdog.h> - -/*PAGE - * - * _TOD_Set - * - * This rountine sets the current date and time with the specified - * new date and time structure. - * - * Input parameters: - * the_tod - pointer to the time and date structure - * seconds_since_epoch - seconds since system epoch - * - * Output parameters: NONE - */ - -void _TOD_Set( - TOD_Control *the_tod, - Watchdog_Interval seconds_since_epoch -) -{ - Watchdog_Interval ticks_until_next_second; - - _Thread_Disable_dispatch(); - _TOD_Deactivate(); - - if ( seconds_since_epoch < _TOD_Seconds_since_epoch ) - _Watchdog_Adjust_seconds( WATCHDOG_BACKWARD, - _TOD_Seconds_since_epoch - seconds_since_epoch ); - else - _Watchdog_Adjust_seconds( WATCHDOG_FORWARD, - seconds_since_epoch - _TOD_Seconds_since_epoch ); - - ticks_until_next_second = _TOD_Ticks_per_second; - if ( ticks_until_next_second > _TOD_Current.ticks ) - ticks_until_next_second -= _TOD_Current.ticks; - - _TOD_Current = *the_tod; - _TOD_Seconds_since_epoch = seconds_since_epoch; - _TOD_Is_set = TRUE; - _TOD_Activate( ticks_until_next_second ); - - _Thread_Enable_dispatch(); -} - diff --git a/c/src/exec/score/src/coretodtickle.c b/c/src/exec/score/src/coretodtickle.c deleted file mode 100644 index c28545f2b4..0000000000 --- a/c/src/exec/score/src/coretodtickle.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Time of Day (TOD) Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/object.h> -#include <rtems/score/thread.h> -#include <rtems/score/tod.h> -#include <rtems/score/watchdog.h> - -/*PAGE - * - * _TOD_Tickle - * - * This routine updates the calendar time and tickles the - * per second watchdog timer chain. - * - * Input parameters: - * ignored - this parameter is ignored - * - * Output parameters: NONE - * - * NOTE: This routine only works for leap-years through 2099. - */ - -void _TOD_Tickle( - Objects_Id id, - void *ignored -) -{ - unsigned32 leap; - - _TOD_Current.ticks = 0; - ++_TOD_Seconds_since_epoch; - if ( ++_TOD_Current.second >= TOD_SECONDS_PER_MINUTE ) { - _TOD_Current.second = 0; - if ( ++_TOD_Current.minute >= TOD_MINUTES_PER_HOUR ) { - _TOD_Current.minute = 0; - if ( ++_TOD_Current.hour >= TOD_HOURS_PER_DAY ) { - _TOD_Current.hour = 0; - if ( _TOD_Current.year & 0x3 ) leap = 0; - else leap = 1; - if ( ++_TOD_Current.day > - _TOD_Days_per_month[ leap ][ _TOD_Current.month ]) { - _TOD_Current.day = 1; - if ( ++_TOD_Current.month > TOD_MONTHS_PER_YEAR ) { - _TOD_Current.month = 1; - _TOD_Current.year++; - } - } - } - } - } - - _Watchdog_Tickle_seconds(); - _Watchdog_Insert_ticks( &_TOD_Seconds_watchdog, _TOD_Ticks_per_second ); -} diff --git a/c/src/exec/score/src/coretodtoseconds.c b/c/src/exec/score/src/coretodtoseconds.c deleted file mode 100644 index 16e9d24a1e..0000000000 --- a/c/src/exec/score/src/coretodtoseconds.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Time of Day (TOD) Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/object.h> -#include <rtems/score/thread.h> -#include <rtems/score/tod.h> -#include <rtems/score/watchdog.h> - -/*PAGE - * - * _TOD_To_seconds - * - * This routine returns the seconds from the epoch until the - * current date and time. - * - * Input parameters: - * the_tod - pointer to the time and date structure - * - * Output parameters: - * returns - seconds since epoch until the_tod - */ - -unsigned32 _TOD_To_seconds( - TOD_Control *the_tod -) -{ - unsigned32 time; - unsigned32 year_mod_4; - - time = the_tod->day - 1; - year_mod_4 = the_tod->year & 3; - - if ( year_mod_4 == 0 ) - time += _TOD_Days_to_date[ 1 ][ the_tod->month ]; - else - time += _TOD_Days_to_date[ 0 ][ the_tod->month ]; - - time += ( (the_tod->year - TOD_BASE_YEAR) / 4 ) * - ( (TOD_DAYS_PER_YEAR * 4) + 1); - - time += _TOD_Days_since_last_leap_year[ year_mod_4 ]; - - time *= TOD_SECONDS_PER_DAY; - - time += ((the_tod->hour * TOD_MINUTES_PER_HOUR) + the_tod->minute) - * TOD_SECONDS_PER_MINUTE; - - time += the_tod->second; - - return( time ); -} - diff --git a/c/src/exec/score/src/coretodvalidate.c b/c/src/exec/score/src/coretodvalidate.c deleted file mode 100644 index 18f377e500..0000000000 --- a/c/src/exec/score/src/coretodvalidate.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Time of Day (TOD) Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/object.h> -#include <rtems/score/thread.h> -#include <rtems/score/tod.h> -#include <rtems/score/watchdog.h> - -/*PAGE - * - * _TOD_Validate - * - * This kernel routine checks the validity of a date and time structure. - * - * Input parameters: - * the_tod - pointer to a time and date structure - * - * Output parameters: - * TRUE - if the date, time, and tick are valid - * FALSE - if the the_tod is invalid - * - * NOTE: This routine only works for leap-years through 2099. - */ - -boolean _TOD_Validate( - TOD_Control *the_tod -) -{ - unsigned32 days_in_month; - - if ((the_tod->ticks >= _TOD_Ticks_per_second) || - (the_tod->second >= TOD_SECONDS_PER_MINUTE) || - (the_tod->minute >= TOD_MINUTES_PER_HOUR) || - (the_tod->hour >= TOD_HOURS_PER_DAY) || - (the_tod->month == 0) || - (the_tod->month > TOD_MONTHS_PER_YEAR) || - (the_tod->year < TOD_BASE_YEAR) || - (the_tod->day == 0) ) - return FALSE; - - if ( (the_tod->year % 4) == 0 ) - days_in_month = _TOD_Days_per_month[ 1 ][ the_tod->month ]; - else - days_in_month = _TOD_Days_per_month[ 0 ][ the_tod->month ]; - - if ( the_tod->day > days_in_month ) - return FALSE; - - return TRUE; -} - diff --git a/c/src/exec/score/src/heap.c b/c/src/exec/score/src/heap.c deleted file mode 100644 index 9ad4ca51ee..0000000000 --- a/c/src/exec/score/src/heap.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Heap Handler - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -#include <rtems/system.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/heap.h> - -/*PAGE - * - * _Heap_Initialize - * - * This kernel routine initializes a heap. - * - * Input parameters: - * the_heap - pointer to heap header - * starting_address - starting address of heap - * size - size of heap - * page_size - allocatable unit of memory - * - * Output parameters: - * returns - maximum memory available if RTEMS_SUCCESSFUL - * 0 - otherwise - * - * This is what a heap looks like in memory immediately - * after initialization: - * - * +--------------------------------+ - * 0 | size = 0 | status = used | a.k.a. dummy back flag - * +--------------------------------+ - * 4 | size = size-8 | status = free | a.k.a. front flag - * +--------------------------------+ - * 8 | next = PERM HEAP_TAIL | - * +--------------------------------+ - * 12 | previous = PERM HEAP_HEAD | - * +--------------------------------+ - * | | - * | memory available | - * | for allocation | - * | | - * +--------------------------------+ - * size - 8 | size = size-8 | status = free | a.k.a. back flag - * +--------------------------------+ - * size - 4 | size = 0 | status = used | a.k.a. dummy front flag - * +--------------------------------+ - */ - -unsigned32 _Heap_Initialize( - Heap_Control *the_heap, - void *starting_address, - unsigned32 size, - unsigned32 page_size -) -{ - Heap_Block *the_block; - unsigned32 the_size; - - if ( !_Heap_Is_page_size_valid( page_size ) || - (size < HEAP_MINIMUM_SIZE) ) - return 0; - - the_heap->page_size = page_size; - the_size = size - HEAP_OVERHEAD; - - the_block = (Heap_Block *) starting_address; - the_block->back_flag = HEAP_DUMMY_FLAG; - the_block->front_flag = the_size; - the_block->next = _Heap_Tail( the_heap ); - the_block->previous = _Heap_Head( the_heap ); - - the_heap->start = the_block; - the_heap->first = the_block; - the_heap->permanent_null = NULL; - the_heap->last = the_block; - - the_block = _Heap_Next_block( the_block ); - the_block->back_flag = the_size; - the_block->front_flag = HEAP_DUMMY_FLAG; - the_heap->final = the_block; - - return ( the_size - HEAP_BLOCK_USED_OVERHEAD ); -} - diff --git a/c/src/exec/score/src/heapallocate.c b/c/src/exec/score/src/heapallocate.c deleted file mode 100644 index 3699a6b080..0000000000 --- a/c/src/exec/score/src/heapallocate.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Heap Handler - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -#include <rtems/system.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/heap.h> - -/*PAGE - * - * _Heap_Allocate - * - * This kernel routine allocates the requested size of memory - * from the specified heap. - * - * Input parameters: - * the_heap - pointer to heap header. - * size - size in bytes of the memory block to allocate. - * - * Output parameters: - * returns - starting address of memory block allocated - */ - -void *_Heap_Allocate( - Heap_Control *the_heap, - unsigned32 size -) -{ - unsigned32 excess; - unsigned32 the_size; - Heap_Block *the_block; - Heap_Block *next_block; - Heap_Block *temporary_block; - void *ptr; - unsigned32 offset; - - /* - * Catch the case of a user allocating close to the limit of the - * unsigned32. - */ - - if ( size >= (-1 - HEAP_BLOCK_USED_OVERHEAD) ) - return( NULL ); - - excess = size % the_heap->page_size; - the_size = size + the_heap->page_size + HEAP_BLOCK_USED_OVERHEAD; - - if ( excess ) - the_size += the_heap->page_size - excess; - - if ( the_size < sizeof( Heap_Block ) ) - the_size = sizeof( Heap_Block ); - - for ( the_block = the_heap->first; - ; - the_block = the_block->next ) { - if ( the_block == _Heap_Tail( the_heap ) ) - return( NULL ); - if ( the_block->front_flag >= the_size ) - break; - } - - if ( (the_block->front_flag - the_size) > - (the_heap->page_size + HEAP_BLOCK_USED_OVERHEAD) ) { - the_block->front_flag -= the_size; - next_block = _Heap_Next_block( the_block ); - next_block->back_flag = the_block->front_flag; - - temporary_block = _Heap_Block_at( next_block, the_size ); - temporary_block->back_flag = - next_block->front_flag = _Heap_Build_flag( the_size, - HEAP_BLOCK_USED ); - ptr = _Heap_Start_of_user_area( next_block ); - } else { - next_block = _Heap_Next_block( the_block ); - next_block->back_flag = _Heap_Build_flag( the_block->front_flag, - HEAP_BLOCK_USED ); - the_block->front_flag = next_block->back_flag; - the_block->next->previous = the_block->previous; - the_block->previous->next = the_block->next; - ptr = _Heap_Start_of_user_area( the_block ); - } - - /* - * round ptr up to a multiple of page size - * Have to save the bump amount in the buffer so that free can figure it out - */ - - offset = the_heap->page_size - (((unsigned32) ptr) & (the_heap->page_size - 1)); - ptr = _Addresses_Add_offset( ptr, offset ); - *(((unsigned32 *) ptr) - 1) = offset; - -#ifdef RTEMS_DEBUG - { - unsigned32 ptr_u32; - ptr_u32 = (unsigned32) ptr; - if (ptr_u32 & (the_heap->page_size - 1)) - abort(); - } -#endif - - return ptr; -} - diff --git a/c/src/exec/score/src/heapextend.c b/c/src/exec/score/src/heapextend.c deleted file mode 100644 index 3b928301ae..0000000000 --- a/c/src/exec/score/src/heapextend.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Heap Handler - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -#include <rtems/system.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/heap.h> - -/*PAGE - * - * _Heap_Extend - * - * This routine grows the_heap memory area using the size bytes which - * begin at starting_address. - * - * Input parameters: - * the_heap - pointer to heap header. - * starting_address - pointer to the memory area. - * size - size in bytes of the memory block to allocate. - * - * Output parameters: - * *amount_extended - amount of memory added to the_heap - */ - -Heap_Extend_status _Heap_Extend( - Heap_Control *the_heap, - void *starting_address, - unsigned32 size, - unsigned32 *amount_extended -) -{ - Heap_Block *the_block; - unsigned32 *p; - - /* - * The overhead was taken from the original heap memory. - */ - - Heap_Block *old_final; - Heap_Block *new_final; - - /* - * There are five possibilities for the location of starting - * address: - * - * 1. non-contiguous lower address (NOT SUPPORTED) - * 2. contiguous lower address (NOT SUPPORTED) - * 3. in the heap (ERROR) - * 4. contiguous higher address (SUPPORTED) - * 5. non-contiguous higher address (NOT SUPPORTED) - * - * As noted, this code only supports (4). - */ - - if ( starting_address >= (void *) the_heap->start && /* case 3 */ - starting_address <= (void *) the_heap->final - ) - return HEAP_EXTEND_ERROR; - - if ( starting_address < (void *) the_heap->start ) { /* cases 1 and 2 */ - - return HEAP_EXTEND_NOT_IMPLEMENTED; /* cases 1 and 2 */ - - } else { /* cases 4 and 5 */ - - the_block = (Heap_Block *) - _Addresses_Subtract_offset( starting_address, HEAP_OVERHEAD ); - if ( the_block != the_heap->final ) - return HEAP_EXTEND_NOT_IMPLEMENTED; /* case 5 */ - } - - /* - * Currently only case 4 should make it to this point. - * The basic trick is to make the extend area look like a used - * block and free it. - */ - - *amount_extended = size; - - old_final = the_heap->final; - new_final = _Addresses_Add_offset( old_final, size ); - /* SAME AS: _Addresses_Add_offset( starting_address, size-HEAP_OVERHEAD ); */ - - the_heap->final = new_final; - - old_final->front_flag = - new_final->back_flag = _Heap_Build_flag( size, HEAP_BLOCK_USED ); - new_final->front_flag = HEAP_DUMMY_FLAG; - - /* - * Must pass in address of "user" area - * So add in the offset field. - */ - - p = (unsigned32 *) &old_final->next; - *p = sizeof(unsigned32); - p++; - _Heap_Free( the_heap, p ); - - return HEAP_EXTEND_SUCCESSFUL; -} - diff --git a/c/src/exec/score/src/heapfree.c b/c/src/exec/score/src/heapfree.c deleted file mode 100644 index 1571e1ea2b..0000000000 --- a/c/src/exec/score/src/heapfree.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Heap Handler - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -#include <rtems/system.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/heap.h> - -/*PAGE - * - * _Heap_Free - * - * This kernel routine returns the memory designated by the - * given heap and given starting address to the memory pool. - * - * Input parameters: - * the_heap - pointer to heap header - * starting_address - starting address of the memory block to free. - * - * Output parameters: - * TRUE - if starting_address is valid heap address - * FALSE - if starting_address is invalid heap address - */ - -boolean _Heap_Free( - Heap_Control *the_heap, - void *starting_address -) -{ - Heap_Block *the_block; - Heap_Block *next_block; - Heap_Block *new_next_block; - Heap_Block *previous_block; - Heap_Block *temporary_block; - unsigned32 the_size; - - the_block = _Heap_User_block_at( starting_address ); - - if ( !_Heap_Is_block_in( the_heap, the_block ) || - _Heap_Is_block_free( the_block ) ) { - return( FALSE ); - } - - the_size = _Heap_Block_size( the_block ); - next_block = _Heap_Block_at( the_block, the_size ); - - if ( !_Heap_Is_block_in( the_heap, next_block ) || - (the_block->front_flag != next_block->back_flag) ) { - return( FALSE ); - } - - if ( _Heap_Is_previous_block_free( the_block ) ) { - previous_block = _Heap_Previous_block( the_block ); - - if ( !_Heap_Is_block_in( the_heap, previous_block ) ) { - return( FALSE ); - } - - if ( _Heap_Is_block_free( next_block ) ) { /* coalesce both */ - previous_block->front_flag += next_block->front_flag + the_size; - temporary_block = _Heap_Next_block( previous_block ); - temporary_block->back_flag = previous_block->front_flag; - next_block->next->previous = next_block->previous; - next_block->previous->next = next_block->next; - } - else { /* coalesce prev */ - previous_block->front_flag = - next_block->back_flag = previous_block->front_flag + the_size; - } - } - else if ( _Heap_Is_block_free( next_block ) ) { /* coalesce next */ - the_block->front_flag = the_size + next_block->front_flag; - new_next_block = _Heap_Next_block( the_block ); - new_next_block->back_flag = the_block->front_flag; - the_block->next = next_block->next; - the_block->previous = next_block->previous; - next_block->previous->next = the_block; - next_block->next->previous = the_block; - - if (the_heap->first == next_block) - the_heap->first = the_block; - } - else { /* no coalesce */ - next_block->back_flag = - the_block->front_flag = the_size; - the_block->previous = _Heap_Head( the_heap ); - the_block->next = the_heap->first; - the_heap->first = the_block; - the_block->next->previous = the_block; - } - - return( TRUE ); -} - diff --git a/c/src/exec/score/src/heapgetinfo.c b/c/src/exec/score/src/heapgetinfo.c deleted file mode 100644 index a55348c3c8..0000000000 --- a/c/src/exec/score/src/heapgetinfo.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Heap Handler - * - * COPYRIGHT (c) 1989-2000. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - - -#include <rtems/system.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/heap.h> - -/*PAGE - * - * _Heap_Get_information - * - * This kernel routine walks the heap and tots up the free and allocated - * sizes. Derived from _Heap_Walk. - * - * Input parameters: - * the_heap - pointer to heap header - * - * Output parameters: - * free_sz - Pointer for free amount return - * used_sz - Pointer for used amount return - * return 0=success, otherwise heap is corrupt. - */ - - -Heap_Get_information_status _Heap_Get_information( - Heap_Control *the_heap, - Heap_Information_block *the_info -) -{ - Heap_Block *the_block = 0; /* avoid warnings */ - Heap_Block *next_block = 0; /* avoid warnings */ - int notdone = 1; - - - the_info->free_blocks = 0; - the_info->free_size = 0; - the_info->used_blocks = 0; - the_info->used_size = 0; - - /* - * We don't want to allow walking the heap until we have - * transferred control to the user task so we watch the - * system state. - */ - - if ( !_System_state_Is_up( _System_state_Get() ) ) - return HEAP_GET_INFORMATION_SYSTEM_STATE_ERROR; - - the_block = the_heap->start; - - /* - * Handle the 1st block - */ - - if ( the_block->back_flag != HEAP_DUMMY_FLAG ) { - return HEAP_GET_INFORMATION_BLOCK_ERROR; - } - - while (notdone) { - - /* - * Accumulate size - */ - - if ( _Heap_Is_block_free(the_block) ) { - the_info->free_blocks++; - the_info->free_size += _Heap_Block_size(the_block); - } else { - the_info->used_blocks++; - the_info->used_size += _Heap_Block_size(the_block); - } - - /* - * Handle the last block - */ - - if ( the_block->front_flag != HEAP_DUMMY_FLAG ) { - next_block = _Heap_Next_block(the_block); - if ( the_block->front_flag != next_block->back_flag ) { - return HEAP_GET_INFORMATION_BLOCK_ERROR; - } - } - - if ( the_block->front_flag == HEAP_DUMMY_FLAG ) - notdone = 0; - else - the_block = next_block; - } /* while(notdone) */ - - return HEAP_GET_INFORMATION_SUCCESSFUL; -} diff --git a/c/src/exec/score/src/heapsizeofuserarea.c b/c/src/exec/score/src/heapsizeofuserarea.c deleted file mode 100644 index 243d1844e6..0000000000 --- a/c/src/exec/score/src/heapsizeofuserarea.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Heap Handler - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -#include <rtems/system.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/heap.h> - -/*PAGE - * - * _Heap_Size_of_user_area - * - * This kernel routine returns the size of the memory area - * given heap block. - * - * Input parameters: - * the_heap - pointer to heap header - * starting_address - starting address of the memory block to free. - * size - pointer to size of area - * - * Output parameters: - * size - size of area filled in - * TRUE - if starting_address is valid heap address - * FALSE - if starting_address is invalid heap address - */ - -boolean _Heap_Size_of_user_area( - Heap_Control *the_heap, - void *starting_address, - unsigned32 *size -) -{ - Heap_Block *the_block; - Heap_Block *next_block; - unsigned32 the_size; - - the_block = _Heap_User_block_at( starting_address ); - - if ( !_Heap_Is_block_in( the_heap, the_block ) || - _Heap_Is_block_free( the_block ) ) - return( FALSE ); - - the_size = _Heap_Block_size( the_block ); - next_block = _Heap_Block_at( the_block, the_size ); - - if ( !_Heap_Is_block_in( the_heap, next_block ) || - (the_block->front_flag != next_block->back_flag) ) - return( FALSE ); - - *size = the_size; - return( TRUE ); -} - diff --git a/c/src/exec/score/src/heapwalk.c b/c/src/exec/score/src/heapwalk.c deleted file mode 100644 index 3cd9c356ae..0000000000 --- a/c/src/exec/score/src/heapwalk.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Heap Handler - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -#include <rtems/system.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/heap.h> - -/*PAGE - * - * _Heap_Walk - * - * This kernel routine walks the heap and verifies its correctness. - * - * Input parameters: - * the_heap - pointer to heap header - * source - a numeric indicator of the invoker of this routine - * do_dump - when TRUE print the information - * - * Output parameters: NONE - */ - -#ifndef RTEMS_DEBUG - -void _Heap_Walk( - Heap_Control *the_heap, - int source, - boolean do_dump -) -{ -} - -#else - -#include <stdio.h> -#include <unistd.h> - -void _Heap_Walk( - Heap_Control *the_heap, - int source, - boolean do_dump -) -{ - Heap_Block *the_block = 0; /* avoid warnings */ - Heap_Block *next_block = 0; /* avoid warnings */ - int notdone = 1; - int error = 0; - int passes = 0; - - /* - * We don't want to allow walking the heap until we have - * transferred control to the user task so we watch the - * system state. - */ - - if ( !_System_state_Is_up( _System_state_Get() ) ) - return; - - the_block = the_heap->start; - - if (do_dump == TRUE) { - printf("\nPASS: %d start @ 0x%p final 0x%p, first 0x%p last 0x%p\n", - source, the_heap->start, the_heap->final, - the_heap->first, the_heap->last - ); - } - - /* - * Handle the 1st block - */ - - if (the_block->back_flag != HEAP_DUMMY_FLAG) { - printf("PASS: %d Back flag of 1st block isn't HEAP_DUMMY_FLAG\n", source); - error = 1; - } - - while (notdone) { - passes++; - if (error && (passes > 10)) - abort(); - - if (do_dump == TRUE) { - printf("PASS: %d Block @ 0x%p Back %d, Front %d", - source, the_block, - the_block->back_flag, the_block->front_flag); - if ( _Heap_Is_block_free(the_block) ) { - printf( " Prev 0x%p, Next 0x%p\n", - the_block->previous, the_block->next); - } else { - printf("\n"); - } - } - - /* - * Handle the last block - */ - - if ( the_block->front_flag != HEAP_DUMMY_FLAG ) { - next_block = _Heap_Next_block(the_block); - if ( the_block->front_flag != next_block->back_flag ) { - error = 1; - printf("PASS: %d Front and back flags don't match\n", source); - printf(" Current Block (%p): Back - %d, Front - %d", - the_block, the_block->back_flag, the_block->front_flag); - if (do_dump == TRUE) { - if (_Heap_Is_block_free(the_block)) { - printf(" Prev 0x%p, Next 0x%p\n", - the_block->previous, the_block->next); - } else { - printf("\n"); - } - } else { - printf("\n"); - } - printf(" Next Block (%p): Back - %d, Front - %d", - next_block, next_block->back_flag, next_block->front_flag); - if (do_dump == TRUE) { - if (_Heap_Is_block_free(next_block)) { - printf(" Prev 0x%p, Next 0x%p\n", - the_block->previous, the_block->next); - } else { - printf("\n"); - } - } else { - printf("\n"); - } - } - } - - if (the_block->front_flag == HEAP_DUMMY_FLAG) - notdone = 0; - else - the_block = next_block; - } - - if (error) - abort(); -} -#endif diff --git a/c/src/exec/score/src/interr.c b/c/src/exec/score/src/interr.c deleted file mode 100644 index e2a4d078bb..0000000000 --- a/c/src/exec/score/src/interr.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Internal Error Handler - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/interr.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/userext.h> - -/*PAGE - * - * _Internal_error_Occurred - * - * This routine will invoke the fatal error handler supplied by the user - * followed by the the default one provided by the executive. The default - * error handler assumes no hardware is present to help inform the user - * of the problem. Halt stores the error code in a known register, - * disables interrupts, and halts the CPU. If the CPU does not have a - * halt instruction, it will loop to itself. - * - * Input parameters: - * the_source - what subsystem the error originated in - * is_internal - if the error was internally generated - * the_error - fatal error status code - * - * Output parameters: - * As much information as possible is stored in a CPU dependent fashion. - * See the CPU dependent code for more information. - * - * NOTE: The the_error is not necessarily a directive status code. - */ - -void volatile _Internal_error_Occurred( - Internal_errors_Source the_source, - boolean is_internal, - unsigned32 the_error -) -{ - - Internal_errors_What_happened.the_source = the_source; - Internal_errors_What_happened.is_internal = is_internal; - Internal_errors_What_happened.the_error = the_error; - - _User_extensions_Fatal( the_source, is_internal, the_error ); - - _System_state_Set( SYSTEM_STATE_FAILED ); - - _CPU_Fatal_halt( the_error ); - - /* will not return from this routine */ -} diff --git a/c/src/exec/score/src/isr.c b/c/src/exec/score/src/isr.c deleted file mode 100644 index ac9be65e63..0000000000 --- a/c/src/exec/score/src/isr.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * ISR Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/stack.h> -#include <rtems/score/interr.h> -#include <rtems/score/wkspace.h> - -/* _ISR_Handler_initialization - * - * This routine initializes the ISR handler. - * - * Input parameters: NONE - * - * Output parameters: NONE - */ - -void _ISR_Handler_initialization( void ) -{ - _ISR_Signals_to_thread_executing = FALSE; - - _ISR_Nest_level = 0; - - _ISR_Vector_table = _Workspace_Allocate_or_fatal_error( - sizeof(ISR_Handler_entry) * ISR_NUMBER_OF_VECTORS - ); - - _CPU_Initialize_vectors(); - -#if ( CPU_ALLOCATE_INTERRUPT_STACK == TRUE ) - - if ( _CPU_Table.interrupt_stack_size < STACK_MINIMUM_SIZE ) - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_INTERRUPT_STACK_TOO_SMALL - ); - - _CPU_Interrupt_stack_low = - _Workspace_Allocate_or_fatal_error( _CPU_Table.interrupt_stack_size ); - - _CPU_Interrupt_stack_high = _Addresses_Add_offset( - _CPU_Interrupt_stack_low, - _CPU_Table.interrupt_stack_size - ); - -#endif - -#if ( CPU_HAS_HARDWARE_INTERRUPT_STACK == TRUE ) - _CPU_Install_interrupt_stack(); -#endif - -} diff --git a/c/src/exec/score/src/mpci.c b/c/src/exec/score/src/mpci.c deleted file mode 100644 index 547b690178..0000000000 --- a/c/src/exec/score/src/mpci.c +++ /dev/null @@ -1,522 +0,0 @@ -/* - * Multiprocessing Communications Interface (MPCI) Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/cpu.h> -#include <rtems/score/interr.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/mpci.h> -#include <rtems/score/mppkt.h> -#endif -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> -#include <rtems/score/watchdog.h> -#include <rtems/score/sysstate.h> - -#include <rtems/score/coresem.h> - -/*PAGE - * - * _MPCI_Handler_initialization - * - * This subprogram performs the initialization necessary for this handler. - */ - -void _MPCI_Handler_initialization( - MPCI_Control *users_mpci_table, - unsigned32 timeout_status -) -{ - CORE_semaphore_Attributes attributes; - - if ( _System_state_Is_multiprocessing && !users_mpci_table ) - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_NO_MPCI - ); - - _MPCI_table = users_mpci_table; - - if ( !_System_state_Is_multiprocessing ) - return; - - /* - * Register the MP Process Packet routine. - */ - - _MPCI_Register_packet_processor( - MP_PACKET_MPCI_INTERNAL, - _MPCI_Internal_packets_Process_packet - ); - - /* - * Create the counting semaphore used by the MPCI Receive Server. - */ - - attributes.discipline = CORE_SEMAPHORE_DISCIPLINES_FIFO; - - _CORE_semaphore_Initialize( - &_MPCI_Semaphore, - &attributes, /* the_semaphore_attributes */ - 0 /* initial_value */ - ); - - _Thread_queue_Initialize( - &_MPCI_Remote_blocked_threads, - THREAD_QUEUE_DISCIPLINE_FIFO, - STATES_WAITING_FOR_RPC_REPLY, - timeout_status - ); -} - -/*PAGE - * - * _MPCI_Create_server - * - * This subprogram creates the MPCI receive server. - */ - -char *_MPCI_Internal_name = "MPCI"; - -void _MPCI_Create_server( void ) -{ - - if ( !_System_state_Is_multiprocessing ) - return; - - /* - * Initialize the MPCI Receive Server - */ - - _MPCI_Receive_server_tcb = _Thread_Internal_allocate(); - - _Thread_Initialize( - &_Thread_Internal_information, - _MPCI_Receive_server_tcb, - NULL, /* allocate the stack */ - MPCI_RECEIVE_SERVER_STACK_SIZE, - CPU_ALL_TASKS_ARE_FP, - PRIORITY_MINIMUM, - FALSE, /* no preempt */ - THREAD_CPU_BUDGET_ALGORITHM_NONE, - NULL, /* no budget algorithm callout */ - 0, /* all interrupts enabled */ - _MPCI_Internal_name - ); - - _Thread_Start( - _MPCI_Receive_server_tcb, - THREAD_START_NUMERIC, - (void *) _MPCI_Receive_server, - NULL, - 0 - ); -} - -/*PAGE - * - * _MPCI_Initialization - * - * This subprogram initializes the MPCI driver by - * invoking the user provided MPCI initialization callout. - */ - -void _MPCI_Initialization ( void ) -{ - (*_MPCI_table->initialization)(); -} - -/*PAGE - * - * _MPCI_Register_packet_processor - * - * This routine registers the MPCI packet processor for the - * designated object class. - */ - -void _MPCI_Register_packet_processor( - MP_packet_Classes the_class, - MPCI_Packet_processor the_packet_processor - -) -{ - _MPCI_Packet_processors[ the_class ] = the_packet_processor; -} - -/*PAGE - * - * _MPCI_Get_packet - * - * This subprogram obtains a packet by invoking the user provided - * MPCI get packet callout. - */ - -MP_packet_Prefix *_MPCI_Get_packet ( void ) -{ - MP_packet_Prefix *the_packet; - - (*_MPCI_table->get_packet)( &the_packet ); - - if ( the_packet == NULL ) - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_OUT_OF_PACKETS - ); - - /* - * Put in a default timeout that will be used for - * all packets that do not otherwise have a timeout. - */ - - the_packet->timeout = MPCI_DEFAULT_TIMEOUT; - - return the_packet; -} - -/*PAGE - * - * _MPCI_Return_packet - * - * This subprogram returns a packet by invoking the user provided - * MPCI return packet callout. - */ - -void _MPCI_Return_packet ( - MP_packet_Prefix *the_packet -) -{ - (*_MPCI_table->return_packet)( the_packet ); -} - -/*PAGE - * - * _MPCI_Send_process_packet - * - * This subprogram sends a process packet by invoking the user provided - * MPCI send callout. - */ - -void _MPCI_Send_process_packet ( - unsigned32 destination, - MP_packet_Prefix *the_packet -) -{ - the_packet->source_tid = _Thread_Executing->Object.id; - the_packet->to_convert = - ( the_packet->to_convert - sizeof(MP_packet_Prefix) ) / - sizeof(unsigned32); - - (*_MPCI_table->send_packet)( destination, the_packet ); -} - -/*PAGE - * - * _MPCI_Send_request_packet - * - * This subprogram sends a request packet by invoking the user provided - * MPCI send callout. - */ - -unsigned32 _MPCI_Send_request_packet ( - unsigned32 destination, - MP_packet_Prefix *the_packet, - States_Control extra_state -) -{ - the_packet->source_tid = _Thread_Executing->Object.id; - the_packet->source_priority = _Thread_Executing->current_priority; - the_packet->to_convert = - ( the_packet->to_convert - sizeof(MP_packet_Prefix) ) / - sizeof(unsigned32); - - _Thread_Executing->Wait.id = the_packet->id; - - _Thread_Executing->Wait.queue = &_MPCI_Remote_blocked_threads; - - _Thread_Disable_dispatch(); - - (*_MPCI_table->send_packet)( destination, the_packet ); - - _Thread_queue_Enter_critical_section( &_MPCI_Remote_blocked_threads ); - - /* - * See if we need a default timeout - */ - - if (the_packet->timeout == MPCI_DEFAULT_TIMEOUT) - the_packet->timeout = _MPCI_table->default_timeout; - - _Thread_queue_Enqueue( &_MPCI_Remote_blocked_threads, the_packet->timeout ); - - _Thread_Executing->current_state = - _States_Set( extra_state, _Thread_Executing->current_state ); - - _Thread_Enable_dispatch(); - - return _Thread_Executing->Wait.return_code; -} - -/*PAGE - * - * _MPCI_Send_response_packet - * - * This subprogram sends a response packet by invoking the user provided - * MPCI send callout. - */ - -void _MPCI_Send_response_packet ( - unsigned32 destination, - MP_packet_Prefix *the_packet -) -{ - the_packet->source_tid = _Thread_Executing->Object.id; - - (*_MPCI_table->send_packet)( destination, the_packet ); -} - -/*PAGE - * - * _MPCI_Receive_packet - * - * This subprogram receives a packet by invoking the user provided - * MPCI receive callout. - */ - -MP_packet_Prefix *_MPCI_Receive_packet ( void ) -{ - MP_packet_Prefix *the_packet; - - (*_MPCI_table->receive_packet)( &the_packet ); - - return the_packet; -} - -/*PAGE - * - * _MPCI_Process_response - * - * This subprogram obtains a packet by invoking the user provided - * MPCI get packet callout. - */ - -Thread_Control *_MPCI_Process_response ( - MP_packet_Prefix *the_packet -) -{ - Thread_Control *the_thread; - Objects_Locations location; - - the_thread = _Thread_Get( the_packet->id, &location ); - switch ( location ) { - case OBJECTS_ERROR: - case OBJECTS_REMOTE: - the_thread = NULL; /* IMPOSSIBLE */ - break; - case OBJECTS_LOCAL: - _Thread_queue_Extract( &_MPCI_Remote_blocked_threads, the_thread ); - the_thread->Wait.return_code = the_packet->return_code; - _Thread_Unnest_dispatch(); - break; - } - - return the_thread; -} - -/*PAGE - * - * _MPCI_Receive_server - * - */ - -Thread _MPCI_Receive_server( - unsigned32 ignored -) -{ - - MP_packet_Prefix *the_packet; - MPCI_Packet_processor the_function; - Thread_Control *executing; - - executing = _Thread_Executing; - - for ( ; ; ) { - - executing->receive_packet = NULL; - - _Thread_Disable_dispatch(); - _CORE_semaphore_Seize( &_MPCI_Semaphore, 0, TRUE, WATCHDOG_NO_TIMEOUT ); - _Thread_Enable_dispatch(); - - for ( ; ; ) { - the_packet = _MPCI_Receive_packet(); - - if ( !the_packet ) - break; - - executing->receive_packet = the_packet; - - if ( !_Mp_packet_Is_valid_packet_class ( the_packet->the_class ) ) - break; - - the_function = _MPCI_Packet_processors[ the_packet->the_class ]; - - if ( !the_function ) - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_BAD_PACKET - ); - - (*the_function)( the_packet ); - } - } -} - -/*PAGE - * - * _MPCI_Announce - * - */ - -void _MPCI_Announce ( void ) -{ - _Thread_Disable_dispatch(); - (void) _CORE_semaphore_Surrender( &_MPCI_Semaphore, 0, 0 ); - _Thread_Enable_dispatch(); -} - -/*PAGE - * - * _MPCI_Internal_packets_Send_process_packet - * - */ - -void _MPCI_Internal_packets_Send_process_packet ( - MPCI_Internal_Remote_operations operation -) -{ - MPCI_Internal_packet *the_packet; - - switch ( operation ) { - - case MPCI_PACKETS_SYSTEM_VERIFY: - - the_packet = _MPCI_Internal_packets_Get_packet(); - the_packet->Prefix.the_class = MP_PACKET_MPCI_INTERNAL; - the_packet->Prefix.length = sizeof ( MPCI_Internal_packet ); - the_packet->Prefix.to_convert = sizeof ( MPCI_Internal_packet ); - the_packet->operation = operation; - - the_packet->maximum_nodes = _Objects_Maximum_nodes; - - the_packet->maximum_global_objects = _Objects_MP_Maximum_global_objects; - - _MPCI_Send_process_packet( MPCI_ALL_NODES, &the_packet->Prefix ); - break; - } -} - -/*PAGE - * - * _MPCI_Internal_packets_Send_request_packet - * - * This subprogram is not needed since there are no request - * packets to be sent by this manager. - * - */ - -/*PAGE - * - * _MPCI_Internal_packets_Send_response_packet - * - * This subprogram is not needed since there are no response - * packets to be sent by this manager. - * - */ - -/*PAGE - * - * - * _MPCI_Internal_packets_Process_packet - * - */ - -void _MPCI_Internal_packets_Process_packet ( - MP_packet_Prefix *the_packet_prefix -) -{ - MPCI_Internal_packet *the_packet; - unsigned32 maximum_nodes; - unsigned32 maximum_global_objects; - - the_packet = (MPCI_Internal_packet *) the_packet_prefix; - - switch ( the_packet->operation ) { - - case MPCI_PACKETS_SYSTEM_VERIFY: - - maximum_nodes = the_packet->maximum_nodes; - maximum_global_objects = the_packet->maximum_global_objects; - if ( maximum_nodes != _Objects_Maximum_nodes || - maximum_global_objects != _Objects_MP_Maximum_global_objects ) { - - _MPCI_Return_packet( the_packet_prefix ); - - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_INCONSISTENT_MP_INFORMATION - ); - } - - _MPCI_Return_packet( the_packet_prefix ); - - break; - } -} - -/*PAGE - * - * _MPCI_Internal_packets_Send_object_was_deleted - * - * This subprogram is not needed since there are no objects - * deleted by this manager. - * - */ - -/*PAGE - * - * _MPCI_Internal_packets_Send_extract_proxy - * - * This subprogram is not needed since there are no objects - * deleted by this manager. - * - */ - -/*PAGE - * - * _MPCI_Internal_packets_Get_packet - * - */ - -MPCI_Internal_packet *_MPCI_Internal_packets_Get_packet ( void ) -{ - return ( (MPCI_Internal_packet *) _MPCI_Get_packet() ); -} - -/* end of file */ diff --git a/c/src/exec/score/src/object.c b/c/src/exec/score/src/object.c deleted file mode 100644 index 5d3ffb5916..0000000000 --- a/c/src/exec/score/src/object.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Handler_initialization - * - * This routine initializes the object handler. - * - * Input parameters: - * node - local node - * maximum_nodes - number of nodes in the system - * maximum_global_objects - number of configured global objects - * - * Output parameters: NONE - */ - -void _Objects_Handler_initialization( - unsigned32 node, - unsigned32 maximum_nodes, - unsigned32 maximum_global_objects -) -{ - if ( node < 1 || node > maximum_nodes ) - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_INVALID_NODE - ); - - _Objects_Local_node = node; - _Objects_Maximum_nodes = maximum_nodes; - -#if defined(RTEMS_MULTIPROCESSING) - _Objects_MP_Handler_initialization( - node, - maximum_nodes, - maximum_global_objects - ); -#endif -} diff --git a/c/src/exec/score/src/objectallocate.c b/c/src/exec/score/src/objectallocate.c deleted file mode 100644 index 9d7193fc7a..0000000000 --- a/c/src/exec/score/src/objectallocate.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Allocate - * - * DESCRIPTION: - * - * This function allocates a object control block from - * the inactive chain of free object control blocks. - */ - -Objects_Control *_Objects_Allocate( - Objects_Information *information -) -{ - Objects_Control *the_object = - (Objects_Control *) _Chain_Get( &information->Inactive ); - - if ( information->auto_extend ) { - /* - * If the list is empty then we are out of objects and need to - * extend information base. - */ - - if ( !the_object ) { - _Objects_Extend_information( information ); - the_object = (Objects_Control *) _Chain_Get( &information->Inactive ); - } - - if ( the_object ) { - unsigned32 block; - - block = _Objects_Get_index( the_object->id ) - - _Objects_Get_index( information->minimum_id ); - block /= information->allocation_size; - - information->inactive_per_block[ block ]--; - information->inactive--; - } - } - - return the_object; -} diff --git a/c/src/exec/score/src/objectallocatebyindex.c b/c/src/exec/score/src/objectallocatebyindex.c deleted file mode 100644 index 6de641ae0c..0000000000 --- a/c/src/exec/score/src/objectallocatebyindex.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Allocate_by_index - * - * DESCRIPTION: - * - * This function allocates the object control block - * specified by the index from the inactive chain of - * free object control blocks. - */ - -Objects_Control *_Objects_Allocate_by_index( - Objects_Information *information, - unsigned32 index, - unsigned32 sizeof_control -) -{ - Objects_Control *the_object; - - if ( index && information->maximum >= index ) { - the_object = information->local_table[ index ]; - if ( the_object ) - return NULL; - - /* XXX - * This whole section of code needs to be addressed. - * + The 0 should be dealt with more properly so we can autoextend. - * + The pointer arithmetic is probably too expensive. - * + etc. - */ - - the_object = (Objects_Control *) _Addresses_Add_offset( - information->object_blocks[ 0 ], - (sizeof_control * (index - 1)) - ); - _Chain_Extract( &the_object->Node ); - - return the_object; - } - - /* - * Autoextend will have to be thought out as it applies - * to user assigned indices. - */ - - return NULL; -} diff --git a/c/src/exec/score/src/objectclearname.c b/c/src/exec/score/src/objectclearname.c deleted file mode 100644 index 639a9de458..0000000000 --- a/c/src/exec/score/src/objectclearname.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Clear_name - * - * This method clears the specified name so that no caller can do a name to - * ID/object lookup past this point. - */ - -void _Objects_Clear_name( - void *name, - unsigned32 length -) -{ - unsigned32 index; - unsigned32 maximum = length / OBJECTS_NAME_ALIGNMENT; - unsigned32 *name_ptr = (unsigned32 *) name; - - for ( index=0 ; index < maximum ; index++ ) - *name_ptr++ = 0; -} diff --git a/c/src/exec/score/src/objectcomparenameraw.c b/c/src/exec/score/src/objectcomparenameraw.c deleted file mode 100644 index 13962c811a..0000000000 --- a/c/src/exec/score/src/objectcomparenameraw.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Compare_name_raw - * - * XXX - */ - -boolean _Objects_Compare_name_raw( - void *name_1, - void *name_2, - unsigned32 length -) -{ -#if 0 - unsigned32 *name_1_p = (unsigned32 *) name_1; - unsigned32 *name_2_p = (unsigned32 *) name_2; - unsigned32 tmp_length = length / OBJECTS_NAME_ALIGNMENT; -#endif - - if ( name_1 == name_2 ) - return TRUE; - return FALSE; - -#if 0 - while ( tmp_length-- ) - if ( *name_1_p++ != *name_2_p++ ) - return FALSE; - - return TRUE; -#endif -} diff --git a/c/src/exec/score/src/objectcomparenamestring.c b/c/src/exec/score/src/objectcomparenamestring.c deleted file mode 100644 index b743eda0da..0000000000 --- a/c/src/exec/score/src/objectcomparenamestring.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-2002. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -#include <string.h> - -/*PAGE - * - * _Objects_Compare_name_string - * - * This routine compares the name of an object with the specified string. - * - * Input parameters: - * name_1 - one name - * name_2 - other name - * length - maximum length to compare - * - * Output parameters: - * returns - TRUE on a match - */ - -boolean _Objects_Compare_name_string( - void *name_1, - void *name_2, - unsigned32 length -) -{ - if ( !strncmp( name_1, name_2, length ) ) - return TRUE; - return FALSE; -} diff --git a/c/src/exec/score/src/objectcopynameraw.c b/c/src/exec/score/src/objectcopynameraw.c deleted file mode 100644 index 74eb94afc1..0000000000 --- a/c/src/exec/score/src/objectcopynameraw.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Copy_name_raw - * - * XXX - */ - -void _Objects_Copy_name_raw( - void *source, - void *destination, - unsigned32 length -) -{ - unsigned32 *source_p = (unsigned32 *) source; - unsigned32 *destination_p = (unsigned32 *) destination; - unsigned32 tmp_length = length / OBJECTS_NAME_ALIGNMENT; - - while ( tmp_length-- ) - *destination_p++ = *source_p++; -} diff --git a/c/src/exec/score/src/objectcopynamestring.c b/c/src/exec/score/src/objectcopynamestring.c deleted file mode 100644 index eb196f3d25..0000000000 --- a/c/src/exec/score/src/objectcopynamestring.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Copy_name_string - * - * XXX - */ - -void _Objects_Copy_name_string( - void *source, - void *destination -) -{ - unsigned8 *source_p = (unsigned8 *) source; - unsigned8 *destination_p = (unsigned8 *) destination; - - *destination_p = '\0'; - if ( source_p ) { - do { - *destination_p++ = *source_p; - } while ( *source_p++ ); - } -} diff --git a/c/src/exec/score/src/objectextendinformation.c b/c/src/exec/score/src/objectextendinformation.c deleted file mode 100644 index ddd38e29c5..0000000000 --- a/c/src/exec/score/src/objectextendinformation.c +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -#include <string.h> /* for memcpy() */ - -/*PAGE - * - * _Objects_Extend_information - * - * This routine extends all object information related data structures. - * - * Input parameters: - * information - object information table - * - * Output parameters: NONE - */ - -void _Objects_Extend_information( - Objects_Information *information -) -{ - Objects_Control *the_object; - void *name_area; - Chain_Control Inactive; - unsigned32 block_count; - unsigned32 block; - unsigned32 index_base; - unsigned32 minimum_index; - unsigned32 index; - - /* - * Search for a free block of indexes. The block variable ends up set - * to block_count + 1 if the table needs to be extended. - */ - - minimum_index = _Objects_Get_index( information->minimum_id ); - index_base = minimum_index; - block = 0; - - if ( information->maximum < minimum_index ) - block_count = 0; - else { - block_count = information->maximum / information->allocation_size; - - for ( ; block < block_count; block++ ) { - if ( information->object_blocks[ block ] == NULL ) - break; - else - index_base += information->allocation_size; - } - } - - /* - * If the index_base is the maximum we need to grow the tables. - */ - - if (index_base >= information->maximum ) { - ISR_Level level; - void **object_blocks; - Objects_Name *name_table; - unsigned32 *inactive_per_block; - Objects_Control **local_table; - unsigned32 maximum; - void *old_tables; - - /* - * Growing the tables means allocating a new area, doing a copy and - * updating the information table. - * - * If the maximum is minimum we do not have a table to copy. First - * time through. - * - * The allocation has : - * - * void *objects[block_count]; - * unsigned32 inactive_count[block_count]; - * Objects_Name *name_table[block_count]; - * Objects_Control *local_table[maximum]; - * - * This is the order in memory. Watch changing the order. See the memcpy - * below. - */ - - /* - * Up the block count and maximum - */ - - block_count++; - - maximum = information->maximum + information->allocation_size; - - /* - * Allocate the tables and break it up. - */ - - if ( information->auto_extend ) { - object_blocks = (void**) - _Workspace_Allocate( - block_count * - (sizeof(void *) + sizeof(unsigned32) + sizeof(Objects_Name *)) + - ((maximum + minimum_index) * sizeof(Objects_Control *)) - ); - - if ( !object_blocks ) - return; - } - else { - object_blocks = (void**) - _Workspace_Allocate_or_fatal_error( - block_count * - (sizeof(void *) + sizeof(unsigned32) + sizeof(Objects_Name *)) + - ((maximum + minimum_index) * sizeof(Objects_Control *)) - ); - } - - /* - * Break the block into the various sections. - * - */ - - inactive_per_block = (unsigned32 *) _Addresses_Add_offset( - object_blocks, block_count * sizeof(void*) ); - name_table = (Objects_Name *) _Addresses_Add_offset( - inactive_per_block, block_count * sizeof(unsigned32) ); - local_table = (Objects_Control **) _Addresses_Add_offset( - name_table, block_count * sizeof(Objects_Name *) ); - - /* - * Take the block count down. Saves all the (block_count - 1) - * in the copies. - */ - - block_count--; - - if ( information->maximum > minimum_index ) { - - /* - * Copy each section of the table over. This has to be performed as - * separate parts as size of each block has changed. - */ - - memcpy( object_blocks, - information->object_blocks, - block_count * sizeof(void*) ); - memcpy( inactive_per_block, - information->inactive_per_block, - block_count * sizeof(unsigned32) ); - memcpy( name_table, - information->name_table, - block_count * sizeof(Objects_Name *) ); - memcpy( local_table, - information->local_table, - (information->maximum + minimum_index) * sizeof(Objects_Control *) ); - } - else { - - /* - * Deal with the special case of the 0 to minimum_index - */ - for ( index = 0; index < minimum_index; index++ ) { - local_table[ index ] = NULL; - } - } - - /* - * Initialise the new entries in the table. - */ - - object_blocks[block_count] = NULL; - inactive_per_block[block_count] = 0; - name_table[block_count] = NULL; - - for ( index=index_base ; - index < ( information->allocation_size + index_base ); - index++ ) { - local_table[ index ] = NULL; - } - - _ISR_Disable( level ); - - old_tables = information->object_blocks; - - information->object_blocks = object_blocks; - information->inactive_per_block = inactive_per_block; - information->name_table = name_table; - information->local_table = local_table; - information->maximum = maximum; - information->maximum_id = _Objects_Build_id( - information->the_api, - information->the_class, - _Objects_Local_node, - information->maximum - ); - - _ISR_Enable( level ); - - if ( old_tables ) - _Workspace_Free( old_tables ); - - block_count++; - } - - /* - * Allocate the name table, and the objects - */ - - if ( information->auto_extend ) { - information->object_blocks[ block ] = - _Workspace_Allocate( - (information->allocation_size * information->name_length) + - (information->allocation_size * information->size) - ); - - if ( !information->object_blocks[ block ] ) - return; - } - else { - information->object_blocks[ block ] = - _Workspace_Allocate_or_fatal_error( - (information->allocation_size * information->name_length) + - (information->allocation_size * information->size) - ); - } - - name_area = (Objects_Name *) _Addresses_Add_offset( - information->object_blocks[ block ], - (information->allocation_size * information->size) - ); - information->name_table[ block ] = name_area; - - /* - * Initialize objects .. add to a local chain first. - */ - - _Chain_Initialize( - &Inactive, - information->object_blocks[ block ], - information->allocation_size, - information->size - ); - - /* - * Move from the local chain, initialise, then append to the inactive chain - */ - - index = index_base; - - while ( (the_object = (Objects_Control *) _Chain_Get( &Inactive ) ) != NULL ) { - - the_object->id = _Objects_Build_id( - information->the_api, - information->the_class, - _Objects_Local_node, - index - ); - - the_object->name = (void *) name_area; - - name_area = _Addresses_Add_offset( name_area, information->name_length ); - - _Chain_Append( &information->Inactive, &the_object->Node ); - - index++; - } - - information->inactive_per_block[ block ] = information->allocation_size; - information->inactive += information->allocation_size; -} diff --git a/c/src/exec/score/src/objectfree.c b/c/src/exec/score/src/objectfree.c deleted file mode 100644 index cf337efa8c..0000000000 --- a/c/src/exec/score/src/objectfree.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Free - * - * DESCRIPTION: - * - * This function frees a object control block to the - * inactive chain of free object control blocks. - */ - -void _Objects_Free( - Objects_Information *information, - Objects_Control *the_object -) -{ - unsigned32 allocation_size = information->allocation_size; - - _Chain_Append( &information->Inactive, &the_object->Node ); - - if ( information->auto_extend ) { - unsigned32 block; - - block = - _Objects_Get_index( the_object->id ) - _Objects_Get_index( information->minimum_id ); - block /= information->allocation_size; - - information->inactive_per_block[ block ]++; - information->inactive++; - - /* - * Check if the threshold level has been met of - * 1.5 x allocation_size are free. - */ - - if ( information->inactive > ( allocation_size + ( allocation_size >> 1 ) ) ) { - _Objects_Shrink_information( information ); - } - } -} diff --git a/c/src/exec/score/src/objectget.c b/c/src/exec/score/src/objectget.c deleted file mode 100644 index 8a551c6741..0000000000 --- a/c/src/exec/score/src/objectget.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Get - * - * This routine sets the object pointer for the given - * object id based on the given object information structure. - * - * Input parameters: - * information - pointer to entry in table for this class - * id - object id to search for - * location - address of where to store the location - * - * Output parameters: - * returns - address of object if local - * location - one of the following: - * OBJECTS_ERROR - invalid object ID - * OBJECTS_REMOTE - remote object - * OBJECTS_LOCAL - local object - */ - -Objects_Control *_Objects_Get( - Objects_Information *information, - Objects_Id id, - Objects_Locations *location -) -{ - Objects_Control *the_object; - unsigned32 index; - -#if defined(RTEMS_MULTIPROCESSING) - index = id - information->minimum_id + 1; -#else - /* index = _Objects_Get_index( id ); */ - index = id & 0x0000ffff; - /* This should work but doesn't always :( */ - /* index = (unsigned16) id; */ -#endif - - if ( information->maximum >= index ) { - _Thread_Disable_dispatch(); - if ( (the_object = information->local_table[ index ]) != NULL ) { - *location = OBJECTS_LOCAL; - return the_object; - } - _Thread_Enable_dispatch(); - *location = OBJECTS_ERROR; - return NULL; - } - *location = OBJECTS_ERROR; - -#if defined(RTEMS_MULTIPROCESSING) - _Objects_MP_Is_remote( information, id, location, &the_object ); - return the_object; -#else - return NULL; -#endif -} diff --git a/c/src/exec/score/src/objectgetbyindex.c b/c/src/exec/score/src/objectgetbyindex.c deleted file mode 100644 index c99e0bc7ed..0000000000 --- a/c/src/exec/score/src/objectgetbyindex.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Get_by_index - * - * This routine sets the object pointer for the given - * object id based on the given object information structure. - * - * Input parameters: - * information - pointer to entry in table for this class - * index - object index to check for - * location - address of where to store the location - * - * Output parameters: - * returns - address of object if local - * location - one of the following: - * OBJECTS_ERROR - invalid object ID - * OBJECTS_REMOTE - remote object - * OBJECTS_LOCAL - local object - */ - -Objects_Control *_Objects_Get_by_index( - Objects_Information *information, - unsigned32 index, - Objects_Locations *location -) -{ - Objects_Control *the_object; - - if ( information->maximum >= index ) { - _Thread_Disable_dispatch(); - the_object = information->local_table[ index ]; - if ( the_object ) { - *location = OBJECTS_LOCAL; - return( the_object ); - } - _Thread_Enable_dispatch(); - *location = OBJECTS_ERROR; - return( NULL ); - } - - /* - * With just an index, you can't access a remote object. - */ - - *location = OBJECTS_ERROR; - return NULL; -} diff --git a/c/src/exec/score/src/objectgetisr.c b/c/src/exec/score/src/objectgetisr.c deleted file mode 100644 index 18ca18cd5c..0000000000 --- a/c/src/exec/score/src/objectgetisr.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Get_isr_disable - * - * This routine sets the object pointer for the given - * object id based on the given object information structure. - * - * Input parameters: - * information - pointer to entry in table for this class - * id - object id to search for - * location - address of where to store the location - * level - pointer to previous interrupt level - * - * Output parameters: - * returns - address of object if local - * location - one of the following: - * OBJECTS_ERROR - invalid object ID - * OBJECTS_REMOTE - remote object - * OBJECTS_LOCAL - local object - * *level - previous interrupt level - */ - -Objects_Control *_Objects_Get_isr_disable( - Objects_Information *information, - Objects_Id id, - Objects_Locations *location, - ISR_Level *level_p -) -{ - Objects_Control *the_object; - unsigned32 index; - ISR_Level level; - -#if defined(RTEMS_MULTIPROCESSING) - index = id - information->minimum_id + 1; -#else - /* index = _Objects_Get_index( id ); */ - index = id & 0x0000ffff; - /* This should work but doesn't always :( */ - /* index = (unsigned16) id; */ -#endif - - _ISR_Disable( level ); - if ( information->maximum >= index ) { - if ( (the_object = information->local_table[ index ]) != NULL ) { - *location = OBJECTS_LOCAL; - *level_p = level; - return the_object; - } - _ISR_Enable( level ); - *location = OBJECTS_ERROR; - return NULL; - } - _ISR_Enable( level ); - *location = OBJECTS_ERROR; - -#if defined(RTEMS_MULTIPROCESSING) - _Objects_MP_Is_remote( information, id, location, &the_object ); - return the_object; -#else - return NULL; -#endif -} diff --git a/c/src/exec/score/src/objectgetnext.c b/c/src/exec/score/src/objectgetnext.c deleted file mode 100644 index ba3cea04e2..0000000000 --- a/c/src/exec/score/src/objectgetnext.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Get_next - * - * Like _Objects_Get, but considers the 'id' as a "hint" and - * finds next valid one after that point. - * Mostly used for monitor and debug traversal of an object. - * - * Input parameters: - * information - pointer to entry in table for this class - * id - object id to search for - * location - address of where to store the location - * next_id - address to store next id to try - * - * Output parameters: - * returns - address of object if local - * location - one of the following: - * OBJECTS_ERROR - invalid object ID - * OBJECTS_REMOTE - remote object - * OBJECTS_LOCAL - local object - * next_id - will contain a reasonable "next" id to continue traversal - * - * NOTE: - * assumes can add '1' to an id to get to next index. - */ - -Objects_Control * -_Objects_Get_next( - Objects_Information *information, - Objects_Id id, - Objects_Locations *location_p, - Objects_Id *next_id_p -) -{ - Objects_Control *object; - Objects_Id next_id; - - if (_Objects_Get_index(id) == OBJECTS_ID_INITIAL_INDEX) - next_id = information->minimum_id; - else - next_id = id; - - do { - /* walked off end of list? */ - if (_Objects_Get_index(next_id) > information->maximum) - { - *location_p = OBJECTS_ERROR; - goto final; - } - - /* try to grab one */ - object = _Objects_Get(information, next_id, location_p); - - next_id++; - - } while (*location_p != OBJECTS_LOCAL); - - *next_id_p = next_id; - return object; - -final: - *next_id_p = OBJECTS_ID_FINAL; - return 0; -} diff --git a/c/src/exec/score/src/objectgetnoprotection.c b/c/src/exec/score/src/objectgetnoprotection.c deleted file mode 100644 index f1ca407218..0000000000 --- a/c/src/exec/score/src/objectgetnoprotection.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Object Handler -- Object Get - * - * - * COPYRIGHT (c) 1989-2002. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Get_no_protection - * - * This routine sets the object pointer for the given - * object id based on the given object information structure. - * - * Input parameters: - * information - pointer to entry in table for this class - * id - object id to search for - * location - address of where to store the location - * - * Output parameters: - * returns - address of object if local - * location - one of the following: - * OBJECTS_ERROR - invalid object ID - * OBJECTS_REMOTE - remote object - * OBJECTS_LOCAL - local object - */ - -Objects_Control *_Objects_Get_no_protection( - Objects_Information *information, - Objects_Id id, - Objects_Locations *location -) -{ - Objects_Control *the_object; - unsigned32 index; - -#if defined(RTEMS_MULTIPROCESSING) - index = id - information->minimum_id + 1; -#else - /* index = _Objects_Get_index( id ); */ - index = id & 0x0000ffff; - /* This should work but doesn't always :( */ - /* index = (unsigned16) id; */ -#endif - - if ( information->maximum >= index ) { - if ( (the_object = information->local_table[ index ]) != NULL ) { - *location = OBJECTS_LOCAL; - return the_object; - } - *location = OBJECTS_ERROR; - return NULL; - } - *location = OBJECTS_ERROR; - -/* - * Not supported for multiprocessing - */ -#if 0 && defined(RTEMS_MULTIPROCESSING) - _Objects_MP_Is_remote( information, id, location, &the_object ); - return the_object; -#endif - return NULL; -} diff --git a/c/src/exec/score/src/objectinitializeinformation.c b/c/src/exec/score/src/objectinitializeinformation.c deleted file mode 100644 index 02f09236f3..0000000000 --- a/c/src/exec/score/src/objectinitializeinformation.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Initialize_information - * - * This routine initializes all object information related data structures. - * - * Input parameters: - * information - object information table - * maximum - maximum objects of this class - * size - size of this object's control block - * is_string - TRUE if names for this object are strings - * maximum_name_length - maximum length of each object's name - * When multiprocessing is configured, - * supports_global - TRUE if this is a global object class - * extract_callout - pointer to threadq extract callout if MP - * - * Output parameters: NONE - */ - -void _Objects_Initialize_information( - Objects_Information *information, - Objects_APIs the_api, - unsigned32 the_class, - unsigned32 maximum, - unsigned32 size, - boolean is_string, - unsigned32 maximum_name_length -#if defined(RTEMS_MULTIPROCESSING) - , - boolean supports_global, - Objects_Thread_queue_Extract_callout *extract -#endif -) -{ - static Objects_Control *null_local_table = NULL; - unsigned32 minimum_index; - unsigned32 name_length; -#if defined(RTEMS_MULTIPROCESSING) - unsigned32 index; -#endif - - information->the_api = the_api; - information->the_class = the_class; - information->is_string = is_string; - - information->local_table = 0; - information->name_table = 0; - information->inactive_per_block = 0; - information->object_blocks = 0; - - information->inactive = 0; - - /* - * Set the entry in the object information table. - */ - - _Objects_Information_table[ the_api ][ the_class ] = information; - - /* - * Set the size of the object - */ - - information->size = size; - - /* - * Are we operating in unlimited, or auto-extend mode - */ - - information->auto_extend = (maximum & OBJECTS_UNLIMITED_OBJECTS) ? TRUE : FALSE; - maximum &= ~OBJECTS_UNLIMITED_OBJECTS; - - /* - * The allocation unit is the maximum value - */ - - information->allocation_size = maximum; - - /* - * Provide a null local table entry for the case of any empty table. - */ - - information->local_table = &null_local_table; - - /* - * Calculate minimum and maximum Id's - */ - - if ( maximum == 0 ) minimum_index = 0; - else minimum_index = 1; - - information->minimum_id = - _Objects_Build_id( the_api, the_class, _Objects_Local_node, minimum_index ); - - /* - * Calculate the maximum name length - */ - - name_length = maximum_name_length; - - if ( name_length & (OBJECTS_NAME_ALIGNMENT-1) ) - name_length = (name_length + OBJECTS_NAME_ALIGNMENT) & - ~(OBJECTS_NAME_ALIGNMENT-1); - - information->name_length = name_length; - - _Chain_Initialize_empty( &information->Inactive ); - - /* - * Initialize objects .. if there are any - */ - - if ( maximum ) { - - /* - * Reset the maximum value. It will be updated when the information is - * extended. - */ - - information->maximum = 0; - - /* - * Always have the maximum size available so the current performance - * figures are create are met. If the user moves past the maximum - * number then a performance hit is taken. - */ - - _Objects_Extend_information( information ); - - } - - /* - * Take care of multiprocessing - */ - -#if defined(RTEMS_MULTIPROCESSING) - information->extract = extract; - - if ( supports_global == TRUE && _System_state_Is_multiprocessing ) { - - information->global_table = - (Chain_Control *) _Workspace_Allocate_or_fatal_error( - (_Objects_Maximum_nodes + 1) * sizeof(Chain_Control) - ); - - for ( index=1; index <= _Objects_Maximum_nodes ; index++ ) - _Chain_Initialize_empty( &information->global_table[ index ] ); - } - else - information->global_table = NULL; -#endif -} diff --git a/c/src/exec/score/src/objectmp.c b/c/src/exec/score/src/objectmp.c deleted file mode 100644 index bbd2f18cc5..0000000000 --- a/c/src/exec/score/src/objectmp.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Multiprocessing Support for the Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/interr.h> -#include <rtems/score/object.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/thread.h> - -/*PAGE - * - * _Objects_MP_Handler_initialization - * - */ - -void _Objects_MP_Handler_initialization ( - unsigned32 node, - unsigned32 maximum_nodes, - unsigned32 maximum_global_objects -) -{ - _Objects_MP_Maximum_global_objects = maximum_global_objects; - - if ( maximum_global_objects == 0 ) { - _Chain_Initialize_empty( &_Objects_MP_Inactive_global_objects ); - return; - } - - _Chain_Initialize( - &_Objects_MP_Inactive_global_objects, - _Workspace_Allocate_or_fatal_error( - maximum_global_objects * sizeof( Objects_MP_Control ) - ), - maximum_global_objects, - sizeof( Objects_MP_Control ) - ); - -} - -/*PAGE - * - * _Objects_MP_Open - * - */ - -void _Objects_MP_Open ( - Objects_Information *information, - Objects_MP_Control *the_global_object, - unsigned32 the_name, /* XXX -- wrong for variable */ - Objects_Id the_id -) -{ - the_global_object->Object.id = the_id; - the_global_object->name = the_name; - - _Chain_Prepend( - &information->global_table[ _Objects_Get_node( the_id ) ], - &the_global_object->Object.Node - ); - -} - -/*PAGE - * - * _Objects_MP_Allocate_and_open - * - */ - -boolean _Objects_MP_Allocate_and_open ( - Objects_Information *information, - unsigned32 the_name, /* XXX -- wrong for variable */ - Objects_Id the_id, - boolean is_fatal_error -) -{ - Objects_MP_Control *the_global_object; - - the_global_object = _Objects_MP_Allocate_global_object(); - if ( _Objects_MP_Is_null_global_object( the_global_object ) ) { - - if ( is_fatal_error == FALSE ) - return FALSE; - - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_OUT_OF_GLOBAL_OBJECTS - ); - - } - - _Objects_MP_Open( information, the_global_object, the_name, the_id ); - - return TRUE; -} - -/*PAGE - * - * _Objects_MP_Close - * - */ - -void _Objects_MP_Close ( - Objects_Information *information, - Objects_Id the_id -) -{ - Chain_Control *the_chain; - Chain_Node *the_node; - Objects_MP_Control *the_object; - - the_chain = &information->global_table[ _Objects_Get_node( the_id ) ]; - - for ( the_node = the_chain->first ; - !_Chain_Is_tail( the_chain, the_node ) ; - the_node = the_node->next ) { - - the_object = (Objects_MP_Control *) the_node; - - if ( _Objects_Are_ids_equal( the_object->Object.id, the_id ) ) { - - _Chain_Extract( the_node ); - _Objects_MP_Free_global_object( the_object ); - return; - } - - } - - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_INVALID_GLOBAL_ID - ); -} - -/*PAGE - * - * _Objects_MP_Global_name_search - * - */ - -Objects_Name_to_id_errors _Objects_MP_Global_name_search ( - Objects_Information *information, - Objects_Name the_name, - unsigned32 nodes_to_search, - Objects_Id *the_id -) -{ - unsigned32 low_node; - unsigned32 high_node; - unsigned32 node_index; - Chain_Control *the_chain; - Chain_Node *the_node; - Objects_MP_Control *the_object; - unsigned32 name_to_use = *(unsigned32 *)the_name; /* XXX variable */ - - if ( nodes_to_search > _Objects_Maximum_nodes ) - return OBJECTS_INVALID_NODE; - - if ( information->global_table == NULL ) - return OBJECTS_INVALID_NAME; - - if ( nodes_to_search == OBJECTS_SEARCH_ALL_NODES || - nodes_to_search == OBJECTS_SEARCH_OTHER_NODES ) { - low_node = 1; - high_node = _Objects_Maximum_nodes; - } else { - low_node = - high_node = nodes_to_search; - } - - _Thread_Disable_dispatch(); - - for ( node_index = low_node ; node_index <= high_node ; node_index++ ) { - - /* - * NOTE: The local node was search (if necessary) by - * _Objects_Name_to_id before this was invoked. - */ - - if ( !_Objects_Is_local_node( node_index ) ) { - the_chain = &information->global_table[ node_index ]; - - for ( the_node = the_chain->first ; - !_Chain_Is_tail( the_chain, the_node ) ; - the_node = the_node->next ) { - - the_object = (Objects_MP_Control *) the_node; - - if ( the_object->name == name_to_use ) { - *the_id = the_object->Object.id; - _Thread_Enable_dispatch(); - return OBJECTS_SUCCESSFUL; - } - } - } - } - - _Thread_Enable_dispatch(); - return OBJECTS_INVALID_NAME; -} - -/*PAGE - * - * _Objects_MP_Is_remote - * - */ - -void _Objects_MP_Is_remote ( - Objects_Information *information, - Objects_Id the_id, - Objects_Locations *location, - Objects_Control **the_object -) -{ - unsigned32 node; - Chain_Control *the_chain; - Chain_Node *the_node; - Objects_MP_Control *the_global_object; - - node = _Objects_Get_node( the_id ); - - /* - * NOTE: The local node was search (if necessary) by - * _Objects_Name_to_id before this was invoked. - * - * The NODE field of an object id cannot be 0 - * because 0 is an invalid node number. - */ - - if ( node == 0 || - _Objects_Is_local_node( node ) || - node > _Objects_Maximum_nodes || - information->global_table == NULL ) { - - *location = OBJECTS_ERROR; - *the_object = NULL; - return; - } - - _Thread_Disable_dispatch(); - - the_chain = &information->global_table[ node ]; - - for ( the_node = the_chain->first ; - !_Chain_Is_tail( the_chain, the_node ) ; - the_node = the_node->next ) { - - the_global_object = (Objects_MP_Control *) the_node; - - if ( _Objects_Are_ids_equal( the_global_object->Object.id, the_id ) ) { - _Thread_Unnest_dispatch(); - *location = OBJECTS_REMOTE; - *the_object = (Objects_Control *) the_global_object; - return; - } - } - - _Thread_Enable_dispatch(); - *location = OBJECTS_ERROR; - *the_object = NULL; - -} diff --git a/c/src/exec/score/src/objectnametoid.c b/c/src/exec/score/src/objectnametoid.c deleted file mode 100644 index 3bbf20900c..0000000000 --- a/c/src/exec/score/src/objectnametoid.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Name_to_id - * - * These kernel routines search the object table(s) for the given - * object name and returns the associated object id. - * - * Input parameters: - * information - object information - * name - user defined object name - * node - node indentifier (0 indicates any node) - * id - address of return ID - * - * Output parameters: - * id - object id - * OBJECTS_SUCCESSFUL - if successful - * error code - if unsuccessful - */ - -Objects_Name_to_id_errors _Objects_Name_to_id( - Objects_Information *information, - Objects_Name name, - unsigned32 node, - Objects_Id *id -) -{ - boolean search_local_node; - Objects_Control *the_object; - unsigned32 index; - unsigned32 name_length; - Objects_Name_comparators compare_them; - - if ( name == 0 ) - return OBJECTS_INVALID_NAME; - - search_local_node = FALSE; - - if ( information->maximum != 0 && - (node == OBJECTS_SEARCH_ALL_NODES || node == OBJECTS_SEARCH_LOCAL_NODE || - _Objects_Is_local_node( node ) ) ) - search_local_node = TRUE; - - if ( search_local_node ) { - name_length = information->name_length; - - if ( information->is_string ) compare_them = _Objects_Compare_name_string; - else compare_them = _Objects_Compare_name_raw; - - for ( index = 1; index <= information->maximum; index++ ) { - the_object = information->local_table[ index ]; - if ( !the_object || !the_object->name ) - continue; - - if ( (*compare_them)( name, the_object->name, name_length ) ) { - *id = the_object->id; - return OBJECTS_SUCCESSFUL; - } - } - } - - if ( _Objects_Is_local_node( node ) || node == OBJECTS_SEARCH_LOCAL_NODE ) - return OBJECTS_INVALID_NAME; - -#if defined(RTEMS_MULTIPROCESSING) - return ( _Objects_MP_Global_name_search( information, name, node, id ) ); -#else - return OBJECTS_INVALID_NAME; -#endif -} diff --git a/c/src/exec/score/src/objectshrinkinformation.c b/c/src/exec/score/src/objectshrinkinformation.c deleted file mode 100644 index 136e6b1686..0000000000 --- a/c/src/exec/score/src/objectshrinkinformation.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Object Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/address.h> -#include <rtems/score/chain.h> -#include <rtems/score/object.h> -#if defined(RTEMS_MULTIPROCESSING) -#include <rtems/score/objectmp.h> -#endif -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Objects_Shrink_information - * - * This routine shrinks object information related data structures. - * The object's name and object space are released. The local_table - * etc block does not shrink. The InActive list needs to be scanned - * to find the objects are remove them. - * Input parameters: - * information - object information table - * the_block - the block to remove - * - * Output parameters: NONE - */ - -void _Objects_Shrink_information( - Objects_Information *information -) -{ - Objects_Control *the_object; - Objects_Control *extract_me; - unsigned32 block_count; - unsigned32 block; - unsigned32 index_base; - unsigned32 index; - - /* - * Search the list to find block or chunnk with all objects inactive. - */ - - index_base = _Objects_Get_index( information->minimum_id ); - block_count = ( information->maximum - index_base ) / information->allocation_size; - - for ( block = 0; block < block_count; block++ ) { - if ( information->inactive_per_block[ block ] == information->allocation_size ) { - - /* - * XXX - Not to sure how to use a chain where you need to iterate and - * and remove elements. - */ - - the_object = (Objects_Control *) information->Inactive.first; - - /* - * Assume the Inactive chain is never empty at this point - */ - - do { - index = _Objects_Get_index( the_object->id ); - - if ((index >= index_base) && - (index < (index_base + information->allocation_size))) { - - /* - * Get the next node before the node is extracted - */ - - extract_me = the_object; - - if ( !_Chain_Is_last( &the_object->Node ) ) - the_object = (Objects_Control *) the_object->Node.next; - else - the_object = NULL; - - _Chain_Extract( &extract_me->Node ); - } - else { - the_object = (Objects_Control *) the_object->Node.next; - } - } - while ( the_object && !_Chain_Is_last( &the_object->Node ) ); - - /* - * Free the memory and reset the structures in the object' information - */ - - _Workspace_Free( information->object_blocks[ block ] ); - information->name_table[ block ] = NULL; - information->object_blocks[ block ] = NULL; - information->inactive_per_block[ block ] = 0; - - information->inactive -= information->allocation_size; - - return; - } - - index_base += information->allocation_size; - } -} diff --git a/c/src/exec/score/src/thread.c b/c/src/exec/score/src/thread.c deleted file mode 100644 index a05dd0fd75..0000000000 --- a/c/src/exec/score/src/thread.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Handler_initialization - * - * This routine initializes all thread manager related data structures. - * - * Input parameters: - * ticks_per_timeslice - clock ticks per quantum - * maximum_proxies - number of proxies to initialize - * - * Output parameters: NONE - */ - -void _Thread_Handler_initialization( - unsigned32 ticks_per_timeslice, - unsigned32 maximum_extensions, - unsigned32 maximum_proxies -) -{ - unsigned32 index; - - /* - * BOTH stacks hooks must be set or both must be NULL. - * Do not allow mixture. - */ - - if ( !( ( _CPU_Table.stack_allocate_hook == 0 ) - == ( _CPU_Table.stack_free_hook == 0 ) ) ) - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_BAD_STACK_HOOK - ); - - _Context_Switch_necessary = FALSE; - _Thread_Executing = NULL; - _Thread_Heir = NULL; -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) - _Thread_Allocated_fp = NULL; -#endif - - _Thread_Do_post_task_switch_extension = 0; - - _Thread_Maximum_extensions = maximum_extensions; - - _Thread_Ticks_per_timeslice = ticks_per_timeslice; - - _Thread_Ready_chain = (Chain_Control *) _Workspace_Allocate_or_fatal_error( - (PRIORITY_MAXIMUM + 1) * sizeof(Chain_Control) - ); - - for ( index=0; index <= PRIORITY_MAXIMUM ; index++ ) - _Chain_Initialize_empty( &_Thread_Ready_chain[ index ] ); - -#if defined(RTEMS_MULTIPROCESSING) - _Thread_MP_Handler_initialization( maximum_proxies ); -#endif - - /* - * Initialize this class of objects. - */ - - _Objects_Initialize_information( - &_Thread_Internal_information, - OBJECTS_INTERNAL_API, - OBJECTS_INTERNAL_THREADS, - ( _System_state_Is_multiprocessing ) ? 2 : 1, - sizeof( Thread_Control ), - /* size of this object's control block */ - TRUE, /* TRUE if names for this object are strings */ - 8 /* maximum length of each object's name */ -#if defined(RTEMS_MULTIPROCESSING) - , - FALSE, /* TRUE if this is a global object class */ - NULL /* Proxy extraction support callout */ -#endif - ); - -} - diff --git a/c/src/exec/score/src/threadchangepriority.c b/c/src/exec/score/src/threadchangepriority.c deleted file mode 100644 index 65c16a6305..0000000000 --- a/c/src/exec/score/src/threadchangepriority.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Change_priority - * - * This kernel routine changes the priority of the thread. The - * thread chain is adjusted if necessary. - * - * Input parameters: - * the_thread - pointer to thread control block - * new_priority - ultimate priority - * prepend_it - TRUE if the thread should be prepended to the chain - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * ready chain - * select heir - */ - -void _Thread_Change_priority( - Thread_Control *the_thread, - Priority_Control new_priority, - boolean prepend_it -) -{ - ISR_Level level; - /* boolean do_prepend = FALSE; */ - - /* - * If this is a case where prepending the task to its priority is - * potentially desired, then we need to consider whether to do it. - * This usually occurs when a task lowers its priority implcitly as - * the result of losing inherited priority. Normal explicit priority - * change calls (e.g. rtems_task_set_priority) should always do an - * append not a prepend. - */ - - /* - * Techically, the prepend should conditional on the thread lowering - * its priority but that does allow cxd2004 of the acvc 2.0.1 to - * pass with rtems 4.0.0. This should change when gnat redoes its - * priority scheme. - */ -/* - if ( prepend_it && - _Thread_Is_executing( the_thread ) && - new_priority >= the_thread->current_priority ) - prepend_it = TRUE; -*/ - - _Thread_Set_transient( the_thread ); - - if ( the_thread->current_priority != new_priority ) - _Thread_Set_priority( the_thread, new_priority ); - - _ISR_Disable( level ); - - the_thread->current_state = - _States_Clear( STATES_TRANSIENT, the_thread->current_state ); - - if ( ! _States_Is_ready( the_thread->current_state ) ) { - /* - * XXX If a task is to be reordered while blocked on a priority - * XXX priority ordered thread queue, then this is where that - * XXX should occur. - */ - _ISR_Enable( level ); - return; - } - - _Priority_Add_to_bit_map( &the_thread->Priority_map ); - if ( prepend_it ) - _Chain_Prepend_unprotected( the_thread->ready, &the_thread->Object.Node ); - else - _Chain_Append_unprotected( the_thread->ready, &the_thread->Object.Node ); - - _ISR_Flash( level ); - - _Thread_Calculate_heir(); - - if ( !_Thread_Is_executing_also_the_heir() && - _Thread_Executing->is_preemptible ) - _Context_Switch_necessary = TRUE; - _ISR_Enable( level ); -} diff --git a/c/src/exec/score/src/threadclearstate.c b/c/src/exec/score/src/threadclearstate.c deleted file mode 100644 index 8a4ae80417..0000000000 --- a/c/src/exec/score/src/threadclearstate.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Clear_state - * - * This kernel routine clears the appropriate states in the - * requested thread. The thread ready chain is adjusted if - * necessary and the Heir thread is set accordingly. - * - * Input parameters: - * the_thread - pointer to thread control block - * state - state set to clear - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * priority map - * select heir - */ - - -void _Thread_Clear_state( - Thread_Control *the_thread, - States_Control state -) -{ - ISR_Level level; - States_Control current_state; - - _ISR_Disable( level ); - current_state = the_thread->current_state; - - if ( current_state & state ) { - current_state = - the_thread->current_state = _States_Clear( state, current_state ); - - if ( _States_Is_ready( current_state ) ) { - - _Priority_Add_to_bit_map( &the_thread->Priority_map ); - - _Chain_Append_unprotected(the_thread->ready, &the_thread->Object.Node); - - _ISR_Flash( level ); - - if ( the_thread->current_priority < _Thread_Heir->current_priority ) { - _Thread_Heir = the_thread; - if ( _Thread_Executing->is_preemptible || - the_thread->current_priority == 0 ) - _Context_Switch_necessary = TRUE; - } - } - } - _ISR_Enable( level ); -} diff --git a/c/src/exec/score/src/threadclose.c b/c/src/exec/score/src/threadclose.c deleted file mode 100644 index b589461eaa..0000000000 --- a/c/src/exec/score/src/threadclose.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/* - * _Thread_Close - * - * DESCRIPTION: - * - * This routine frees all memory associated with the specified - * thread and removes it from the local object table so no further - * operations on this thread are allowed. - */ - -void _Thread_Close( - Objects_Information *information, - Thread_Control *the_thread -) -{ - _Objects_Close( information, &the_thread->Object ); - - _Thread_Set_state( the_thread, STATES_TRANSIENT ); - - if ( !_Thread_queue_Extract_with_proxy( the_thread ) ) { - if ( _Watchdog_Is_active( &the_thread->Timer ) ) - (void) _Watchdog_Remove( &the_thread->Timer ); - } - - _User_extensions_Thread_delete( the_thread ); - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) -#if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE ) - if ( _Thread_Is_allocated_fp( the_thread ) ) - _Thread_Deallocate_fp(); -#endif - the_thread->fp_context = NULL; - - if ( the_thread->Start.fp_context ) - (void) _Workspace_Free( the_thread->Start.fp_context ); -#endif - - _Thread_Stack_Free( the_thread ); - - if ( the_thread->extensions ) - (void) _Workspace_Free( the_thread->extensions ); - - the_thread->Start.stack = NULL; - the_thread->extensions = NULL; -} diff --git a/c/src/exec/score/src/threadcreateidle.c b/c/src/exec/score/src/threadcreateidle.c deleted file mode 100644 index 32d8254507..0000000000 --- a/c/src/exec/score/src/threadcreateidle.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Create_idle - */ - -char *_Thread_Idle_name = "IDLE"; - -void _Thread_Create_idle( void ) -{ - void *idle; - unsigned32 idle_task_stack_size; - - /* - * The entire workspace is zeroed during its initialization. Thus, all - * fields not explicitly assigned were explicitly zeroed by - * _Workspace_Initialization. - */ - - _Thread_Idle = _Thread_Internal_allocate(); - - /* - * Initialize the IDLE task. - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) - idle = (void *) _CPU_Thread_Idle_body; -#else - idle = (void *) _Thread_Idle_body; -#endif - - if ( _CPU_Table.idle_task ) - idle = _CPU_Table.idle_task; - - idle_task_stack_size = _CPU_Table.idle_task_stack_size; - if ( idle_task_stack_size < STACK_MINIMUM_SIZE ) - idle_task_stack_size = STACK_MINIMUM_SIZE; - - _Thread_Initialize( - &_Thread_Internal_information, - _Thread_Idle, - NULL, /* allocate the stack */ - idle_task_stack_size, - CPU_IDLE_TASK_IS_FP, - PRIORITY_MAXIMUM, - TRUE, /* preemptable */ - THREAD_CPU_BUDGET_ALGORITHM_NONE, - NULL, /* no budget algorithm callout */ - 0, /* all interrupts enabled */ - _Thread_Idle_name - ); - - /* - * WARNING!!! This is necessary to "kick" start the system and - * MUST be done before _Thread_Start is invoked. - */ - - _Thread_Heir = - _Thread_Executing = _Thread_Idle; - - _Thread_Start( - _Thread_Idle, - THREAD_START_NUMERIC, - idle, - NULL, - 0 - ); - -} diff --git a/c/src/exec/score/src/threaddelayended.c b/c/src/exec/score/src/threaddelayended.c deleted file mode 100644 index bb8f05296c..0000000000 --- a/c/src/exec/score/src/threaddelayended.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Delay_ended - * - * This routine processes a thread whose delay period has ended. - * It is called by the watchdog handler. - * - * Input parameters: - * id - thread id - * - * Output parameters: NONE - */ - -void _Thread_Delay_ended( - Objects_Id id, - void *ignored -) -{ - Thread_Control *the_thread; - Objects_Locations location; - - the_thread = _Thread_Get( id, &location ); - switch ( location ) { - case OBJECTS_ERROR: - case OBJECTS_REMOTE: /* impossible */ - break; - case OBJECTS_LOCAL: - _Thread_Unblock( the_thread ); - _Thread_Unnest_dispatch(); - break; - } -} diff --git a/c/src/exec/score/src/threaddispatch.c b/c/src/exec/score/src/threaddispatch.c deleted file mode 100644 index eedc8cc9ee..0000000000 --- a/c/src/exec/score/src/threaddispatch.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Dispatch - * - * This kernel routine determines if a dispatch is needed, and if so - * dispatches to the heir thread. Once the heir is running an attempt - * is made to dispatch any ASRs. - * - * ALTERNATE ENTRY POINTS: - * void _Thread_Enable_dispatch(); - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * dispatch thread - * no dispatch thread - */ - -#if ( CPU_INLINE_ENABLE_DISPATCH == FALSE ) -void _Thread_Enable_dispatch( void ) -{ - if ( --_Thread_Dispatch_disable_level ) - return; - _Thread_Dispatch(); -} -#endif - -void _Thread_Dispatch( void ) -{ - Thread_Control *executing; - Thread_Control *heir; - ISR_Level level; - - executing = _Thread_Executing; - _ISR_Disable( level ); - while ( _Context_Switch_necessary == TRUE ) { - heir = _Thread_Heir; - _Thread_Dispatch_disable_level = 1; - _Context_Switch_necessary = FALSE; - _Thread_Executing = heir; - executing->rtems_ada_self = rtems_ada_self; - rtems_ada_self = heir->rtems_ada_self; - _ISR_Enable( level ); - - heir->ticks_executed++; - - /* - * Switch libc's task specific data. - */ - if ( _Thread_libc_reent ) { - executing->libc_reent = *_Thread_libc_reent; - *_Thread_libc_reent = heir->libc_reent; - } - - _User_extensions_Thread_switch( executing, heir ); - - if ( heir->budget_algorithm == THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE ) - heir->cpu_time_budget = _Thread_Ticks_per_timeslice; - - /* - * If the CPU has hardware floating point, then we must address saving - * and restoring it as part of the context switch. - * - * The second conditional compilation section selects the algorithm used - * to context switch between floating point tasks. The deferred algorithm - * can be significantly better in a system with few floating point tasks - * because it reduces the total number of save and restore FP context - * operations. However, this algorithm can not be used on all CPUs due - * to unpredictable use of FP registers by some compilers for integer - * operations. - */ - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) -#if ( CPU_USE_DEFERRED_FP_SWITCH != TRUE ) - if ( executing->fp_context != NULL ) - _Context_Save_fp( &executing->fp_context ); -#endif -#endif - - _Context_Switch( &executing->Registers, &heir->Registers ); - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) -#if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE ) - if ( (executing->fp_context != NULL) && !_Thread_Is_allocated_fp( executing ) ) { - if ( _Thread_Allocated_fp != NULL ) - _Context_Save_fp( &_Thread_Allocated_fp->fp_context ); - _Context_Restore_fp( &executing->fp_context ); - _Thread_Allocated_fp = executing; - } -#else - if ( executing->fp_context != NULL ) - _Context_Restore_fp( &executing->fp_context ); -#endif -#endif - - executing = _Thread_Executing; - - _ISR_Disable( level ); - } - - _Thread_Dispatch_disable_level = 0; - - _ISR_Enable( level ); - - if ( _Thread_Do_post_task_switch_extension || - executing->do_post_task_switch_extension ) { - executing->do_post_task_switch_extension = FALSE; - _API_extensions_Run_postswitch(); - } - -} diff --git a/c/src/exec/score/src/threadevaluatemode.c b/c/src/exec/score/src/threadevaluatemode.c deleted file mode 100644 index edbfa5b882..0000000000 --- a/c/src/exec/score/src/threadevaluatemode.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Evaluate_mode - * - * XXX - */ - -boolean _Thread_Evaluate_mode( void ) -{ - Thread_Control *executing; - - executing = _Thread_Executing; - - if ( !_States_Is_ready( executing->current_state ) || - ( !_Thread_Is_heir( executing ) && executing->is_preemptible ) ) { - _Context_Switch_necessary = TRUE; - return TRUE; - } - - return FALSE; -} diff --git a/c/src/exec/score/src/threadget.c b/c/src/exec/score/src/threadget.c deleted file mode 100644 index c8747f76fa..0000000000 --- a/c/src/exec/score/src/threadget.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Get - * - * NOTE: If we are not using static inlines, this must be a real - * subroutine call. - * - * NOTE: XXX... This routine may be able to be optimized. - */ - -#ifndef USE_INLINES - -Thread_Control *_Thread_Get ( - Objects_Id id, - Objects_Locations *location -) -{ - unsigned32 the_api; - unsigned32 the_class; - Objects_Information *information; - Thread_Control *tp = (Thread_Control *) 0; - - if ( _Objects_Are_ids_equal( id, OBJECTS_ID_OF_SELF ) ) { - _Thread_Disable_dispatch(); - *location = OBJECTS_LOCAL; - tp = _Thread_Executing; - goto done; - } - - the_api = _Objects_Get_API( id ); - if ( the_api && the_api > OBJECTS_APIS_LAST ) { - *location = OBJECTS_ERROR; - goto done; - } - - the_class = _Objects_Get_class( id ); - if ( the_class != 1 ) { /* threads are always first class :) */ - *location = OBJECTS_ERROR; - goto done; - } - - information = _Objects_Information_table[ the_api ][ the_class ]; - - if ( !information ) { - *location = OBJECTS_ERROR; - goto done; - } - - tp = (Thread_Control *) _Objects_Get( information, id, location ); - -done: - return tp; -} - -#endif diff --git a/c/src/exec/score/src/threadhandler.c b/c/src/exec/score/src/threadhandler.c deleted file mode 100644 index ec09654c5a..0000000000 --- a/c/src/exec/score/src/threadhandler.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Handler - * - * This routine is the "primal" entry point for all threads. - * _Context_Initialize() dummies up the thread's initial context - * to cause the first Context_Switch() to jump to _Thread_Handler(). - * - * This routine is the default thread exitted error handler. It is - * returned to when a thread exits. The configured fatal error handler - * is invoked to process the exit. - * - * NOTE: - * - * On entry, it is assumed all interrupts are blocked and that this - * routine needs to set the initial isr level. This may or may not - * actually be needed by the context switch routine and as a result - * interrupts may already be at there proper level. Either way, - * setting the initial isr level properly here is safe. - * - * Currently this is only really needed for the posix port, - * ref: _Context_Switch in unix/cpu.c - * - * Input parameters: NONE - * - * Output parameters: NONE - */ - -void _Thread_Handler( void ) -{ - ISR_Level level; - Thread_Control *executing; -#if defined(__USE_INIT_FINI__) || defined(__USE__MAIN__) - static char doneConstructors; - char doneCons; -#endif - - executing = _Thread_Executing; - - /* - * have to put level into a register for those cpu's that use - * inline asm here - */ - - level = executing->Start.isr_level; - _ISR_Set_level(level); - -#if defined(__USE_INIT_FINI__) || defined(__USE__MAIN__) - doneCons = doneConstructors; - doneConstructors = 1; -#endif - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) -#if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE ) - if ( (executing->fp_context != NULL) && !_Thread_Is_allocated_fp( executing ) ) { - if ( _Thread_Allocated_fp != NULL ) - _Context_Save_fp( &_Thread_Allocated_fp->fp_context ); - _Thread_Allocated_fp = executing; - } -#endif -#endif - - - /* - * Take care that 'begin' extensions get to complete before - * 'switch' extensions can run. This means must keep dispatch - * disabled until all 'begin' extensions complete. - */ - - _User_extensions_Thread_begin( executing ); - - /* - * At this point, the dispatch disable level BETTER be 1. - */ - - _Thread_Enable_dispatch(); -#if defined(__USE_INIT_FINI__) - if (!doneCons) - _init (); -#endif -#if defined(__USE__MAIN__) - if (!doneCons) - __main (); -#endif - - - switch ( executing->Start.prototype ) { - case THREAD_START_NUMERIC: - executing->Wait.return_argument = - (*(Thread_Entry_numeric) executing->Start.entry_point)( - executing->Start.numeric_argument - ); - break; - case THREAD_START_POINTER: - executing->Wait.return_argument = - (*(Thread_Entry_pointer) executing->Start.entry_point)( - executing->Start.pointer_argument - ); - break; - case THREAD_START_BOTH_POINTER_FIRST: - executing->Wait.return_argument = - (*(Thread_Entry_both_pointer_first) executing->Start.entry_point)( - executing->Start.pointer_argument, - executing->Start.numeric_argument - ); - break; - case THREAD_START_BOTH_NUMERIC_FIRST: - executing->Wait.return_argument = - (*(Thread_Entry_both_numeric_first) executing->Start.entry_point)( - executing->Start.numeric_argument, - executing->Start.pointer_argument - ); - break; - } - - /* - * In the switch above, the return code from the user thread body - * was placed in return_argument. This assumed that if it returned - * anything (which is not supporting in all APIs), then it would be - * able to fit in a (void *). - */ - - _User_extensions_Thread_exitted( executing ); - - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_THREAD_EXITTED - ); -} diff --git a/c/src/exec/score/src/threadidlebody.c b/c/src/exec/score/src/threadidlebody.c deleted file mode 100644 index 93b90a12cd..0000000000 --- a/c/src/exec/score/src/threadidlebody.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Idle_body - * - * This kernel routine is the idle thread. The idle thread runs any time - * no other thread is ready to run. This thread loops forever with - * interrupts enabled. - * - * Input parameters: - * ignored - this parameter is ignored - * - * Output parameters: NONE - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == FALSE) -Thread _Thread_Idle_body( - unsigned32 ignored -) -{ - for( ; ; ) ; -} -#endif diff --git a/c/src/exec/score/src/threadinitialize.c b/c/src/exec/score/src/threadinitialize.c deleted file mode 100644 index e850e3fe1f..0000000000 --- a/c/src/exec/score/src/threadinitialize.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Initialize - * - * This routine initializes the specified the thread. It allocates - * all memory associated with this thread. It completes by adding - * the thread to the local object table so operations on this - * thread id are allowed. - */ - -boolean _Thread_Initialize( - Objects_Information *information, - Thread_Control *the_thread, - void *stack_area, - unsigned32 stack_size, - boolean is_fp, - Priority_Control priority, - boolean is_preemptible, - Thread_CPU_budget_algorithms budget_algorithm, - Thread_CPU_budget_algorithm_callout budget_callout, - unsigned32 isr_level, - Objects_Name name -) -{ - unsigned32 actual_stack_size = 0; - void *stack = NULL; -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) - void *fp_area; -#endif - void *extensions_area; - - /* - * Initialize the Ada self pointer - */ - - the_thread->rtems_ada_self = NULL; - - /* - * Allocate and Initialize the stack for this thread. - */ - - - if ( !stack_area ) { - if ( !_Stack_Is_enough( stack_size ) ) - actual_stack_size = STACK_MINIMUM_SIZE; - else - actual_stack_size = stack_size; - - actual_stack_size = _Thread_Stack_Allocate( the_thread, actual_stack_size ); - - if ( !actual_stack_size ) - return FALSE; /* stack allocation failed */ - - stack = the_thread->Start.stack; - the_thread->Start.core_allocated_stack = TRUE; - } else { - stack = stack_area; - actual_stack_size = stack_size; - the_thread->Start.core_allocated_stack = FALSE; - } - - _Stack_Initialize( - &the_thread->Start.Initial_stack, - stack, - actual_stack_size - ); - - /* - * Allocate the floating point area for this thread - */ - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) - if ( is_fp ) { - - fp_area = _Workspace_Allocate( CONTEXT_FP_SIZE ); - if ( !fp_area ) { - _Thread_Stack_Free( the_thread ); - return FALSE; - } - fp_area = _Context_Fp_start( fp_area, 0 ); - - } else - fp_area = NULL; - - the_thread->fp_context = fp_area; - the_thread->Start.fp_context = fp_area; -#endif - - /* - * Clear the libc reent hook. - */ - - the_thread->libc_reent = NULL; - - /* - * Allocate the extensions area for this thread - */ - - if ( _Thread_Maximum_extensions ) { - extensions_area = _Workspace_Allocate( - (_Thread_Maximum_extensions + 1) * sizeof( void * ) - ); - - if ( !extensions_area ) { -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) - if ( fp_area ) - (void) _Workspace_Free( fp_area ); -#endif - - _Thread_Stack_Free( the_thread ); - - return FALSE; - } - } else - extensions_area = NULL; - - the_thread->extensions = (void **) extensions_area; - - /* - * Clear the extensions area so extension users can determine - * if they are linked to the thread. An extension user may - * create the extension long after tasks have been created - * so they cannot rely on the thread create user extension - * call. - */ - - if ( the_thread->extensions ) { - int i; - for ( i = 0; i < (_Thread_Maximum_extensions + 1); i++ ) - the_thread->extensions[i] = NULL; - } - - /* - * General initialization - */ - - the_thread->Start.is_preemptible = is_preemptible; - the_thread->Start.budget_algorithm = budget_algorithm; - the_thread->Start.budget_callout = budget_callout; - - switch ( budget_algorithm ) { - case THREAD_CPU_BUDGET_ALGORITHM_NONE: - case THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE: - break; - case THREAD_CPU_BUDGET_ALGORITHM_EXHAUST_TIMESLICE: - the_thread->cpu_time_budget = _Thread_Ticks_per_timeslice; - break; - case THREAD_CPU_BUDGET_ALGORITHM_CALLOUT: - break; - } - - the_thread->Start.isr_level = isr_level; - - the_thread->current_state = STATES_DORMANT; - the_thread->resource_count = 0; - the_thread->suspend_count = 0; - the_thread->real_priority = priority; - the_thread->Start.initial_priority = priority; - the_thread->ticks_executed = 0; - - _Thread_Set_priority( the_thread, priority ); - - /* - * Open the object - */ - - _Objects_Open( information, &the_thread->Object, name ); - - /* - * Invoke create extensions - */ - - if ( !_User_extensions_Thread_create( the_thread ) ) { - - if ( extensions_area ) - (void) _Workspace_Free( extensions_area ); - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) - if ( fp_area ) - (void) _Workspace_Free( fp_area ); -#endif - - _Thread_Stack_Free( the_thread ); - - return FALSE; - } - - return TRUE; - -} diff --git a/c/src/exec/score/src/threadloadenv.c b/c/src/exec/score/src/threadloadenv.c deleted file mode 100644 index af1233f709..0000000000 --- a/c/src/exec/score/src/threadloadenv.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Load_environment - * - * Load starting environment for another thread from its start area in the - * thread. Only called from t_restart and t_start. - * - * Input parameters: - * the_thread - thread control block pointer - * - * Output parameters: NONE - */ - -void _Thread_Load_environment( - Thread_Control *the_thread -) -{ - boolean is_fp = FALSE; - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) - if ( the_thread->Start.fp_context ) { - the_thread->fp_context = the_thread->Start.fp_context; - _Context_Initialize_fp( &the_thread->fp_context ); - is_fp = TRUE; - } -#endif - - the_thread->do_post_task_switch_extension = FALSE; - the_thread->is_preemptible = the_thread->Start.is_preemptible; - the_thread->budget_algorithm = the_thread->Start.budget_algorithm; - the_thread->budget_callout = the_thread->Start.budget_callout; - - _Context_Initialize( - &the_thread->Registers, - the_thread->Start.Initial_stack.area, - the_thread->Start.Initial_stack.size, - the_thread->Start.isr_level, - _Thread_Handler, - is_fp - ); - -} diff --git a/c/src/exec/score/src/threadmp.c b/c/src/exec/score/src/threadmp.c deleted file mode 100644 index 58a183ba87..0000000000 --- a/c/src/exec/score/src/threadmp.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Multiprocessing Support for the Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/priority.h> -#include <rtems/score/thread.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/isr.h> - -/*PAGE - * - * _Thread_MP_Handler_initialization - * - */ - -void _Thread_MP_Handler_initialization ( - unsigned32 maximum_proxies -) -{ - - _Chain_Initialize_empty( &_Thread_MP_Active_proxies ); - - if ( maximum_proxies == 0 ) { - _Chain_Initialize_empty( &_Thread_MP_Inactive_proxies ); - return; - } - - - _Chain_Initialize( - &_Thread_MP_Inactive_proxies, - _Workspace_Allocate_or_fatal_error( - maximum_proxies * sizeof( Thread_Proxy_control ) - ), - maximum_proxies, - sizeof( Thread_Proxy_control ) - ); - -} - -/*PAGE - * - * _Thread_MP_Allocate_proxy - * - */ - -Thread_Control *_Thread_MP_Allocate_proxy ( - States_Control the_state -) -{ - Thread_Control *the_thread; - Thread_Proxy_control *the_proxy; - - the_thread = (Thread_Control *)_Chain_Get( &_Thread_MP_Inactive_proxies ); - - if ( !_Thread_Is_null( the_thread ) ) { - - the_proxy = (Thread_Proxy_control *) the_thread; - - _Thread_Executing->Wait.return_code = THREAD_STATUS_PROXY_BLOCKING; - - the_proxy->receive_packet = _Thread_MP_Receive->receive_packet; - - the_proxy->Object.id = _Thread_MP_Receive->receive_packet->source_tid; - - the_proxy->current_priority = - _Thread_MP_Receive->receive_packet->source_priority; - - the_proxy->current_state = _States_Set( STATES_DORMANT, the_state ); - - the_proxy->Wait = _Thread_Executing->Wait; - - _Chain_Append( &_Thread_MP_Active_proxies, &the_proxy->Active ); - - return the_thread; - } - - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_OUT_OF_PROXIES - ); - - /* - * NOTE: The following return insures that the compiler will - * think that all paths return a value. - */ - - return NULL; -} - -/*PAGE - * - * _Thread_MP_Find_proxy - * - */ - -/* - * The following macro provides the offset of the Active element - * in the Thread_Proxy_control structure. This is the logical - * equivalent of the POSITION attribute in Ada. - */ - -#define _Thread_MP_Proxy_Active_offset \ - ((unsigned32)&(((Thread_Proxy_control *)0))->Active) - -Thread_Control *_Thread_MP_Find_proxy ( - Objects_Id the_id -) -{ - - Chain_Node *proxy_node; - Thread_Control *the_thread; - ISR_Level level; - -restart: - - _ISR_Disable( level ); - - for ( proxy_node = _Thread_MP_Active_proxies.first; - !_Chain_Is_tail( &_Thread_MP_Active_proxies, proxy_node ) ; - ) { - - the_thread = (Thread_Control *) _Addresses_Subtract_offset( - proxy_node, - _Thread_MP_Proxy_Active_offset - ); - - if ( _Objects_Are_ids_equal( the_thread->Object.id, the_id ) ) { - _ISR_Enable( level ); - return the_thread; - } - - _ISR_Flash( level ); - - proxy_node = proxy_node->next; - - /* - * A proxy which is only dormant is not in a blocking state. - * Therefore, we are looking at proxy which has been moved from - * active to inactive chain (by an ISR) and need to restart - * the search. - */ - - if ( _States_Is_only_dormant( the_thread->current_state ) ) { - _ISR_Enable( level ); - goto restart; - } - } - - _ISR_Enable( level ); - return NULL; -} diff --git a/c/src/exec/score/src/threadq.c b/c/src/exec/score/src/threadq.c deleted file mode 100644 index a216a4ffcd..0000000000 --- a/c/src/exec/score/src/threadq.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Initialize - * - * This routine initializes the specified threadq. - * - * Input parameters: - * the_thread_queue - pointer to a threadq header - * discipline - queueing discipline - * state - state of waiting threads - * timeout_status - return on a timeout - * - * Output parameters: NONE - */ - -void _Thread_queue_Initialize( - Thread_queue_Control *the_thread_queue, - Thread_queue_Disciplines the_discipline, - States_Control state, - unsigned32 timeout_status -) -{ - unsigned32 index; - - the_thread_queue->state = state; - the_thread_queue->discipline = the_discipline; - the_thread_queue->timeout_status = timeout_status; - the_thread_queue->sync_state = THREAD_QUEUE_SYNCHRONIZED; - - switch ( the_discipline ) { - case THREAD_QUEUE_DISCIPLINE_FIFO: - _Chain_Initialize_empty( &the_thread_queue->Queues.Fifo ); - break; - case THREAD_QUEUE_DISCIPLINE_PRIORITY: - for( index=0 ; - index < TASK_QUEUE_DATA_NUMBER_OF_PRIORITY_HEADERS ; - index++) - _Chain_Initialize_empty( &the_thread_queue->Queues.Priority[index] ); - break; - } - -} diff --git a/c/src/exec/score/src/threadqdequeue.c b/c/src/exec/score/src/threadqdequeue.c deleted file mode 100644 index dcb64099d0..0000000000 --- a/c/src/exec/score/src/threadqdequeue.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Dequeue - * - * This routine removes a thread from the specified threadq. If the - * threadq discipline is FIFO, it unblocks a thread, and cancels its - * timeout timer. Priority discipline is processed elsewhere. - * - * Input parameters: - * the_thread_queue - pointer to threadq - * - * Output parameters: - * returns - thread dequeued or NULL - * - * INTERRUPT LATENCY: - * check sync - */ - -Thread_Control *_Thread_queue_Dequeue( - Thread_queue_Control *the_thread_queue -) -{ - Thread_Control *the_thread; - - switch ( the_thread_queue->discipline ) { - case THREAD_QUEUE_DISCIPLINE_FIFO: - the_thread = _Thread_queue_Dequeue_fifo( the_thread_queue ); - break; - case THREAD_QUEUE_DISCIPLINE_PRIORITY: - the_thread = _Thread_queue_Dequeue_priority( the_thread_queue ); - break; - default: /* this is only to prevent warnings */ - the_thread = NULL; - break; - } - - return( the_thread ); -} - diff --git a/c/src/exec/score/src/threadqdequeuefifo.c b/c/src/exec/score/src/threadqdequeuefifo.c deleted file mode 100644 index 2e3c84fe45..0000000000 --- a/c/src/exec/score/src/threadqdequeuefifo.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Dequeue_fifo - * - * This routine removes a thread from the specified threadq. - * - * Input parameters: - * the_thread_queue - pointer to threadq - * - * Output parameters: - * returns - thread dequeued or NULL - * - * INTERRUPT LATENCY: - * check sync - * FIFO - */ - -Thread_Control *_Thread_queue_Dequeue_fifo( - Thread_queue_Control *the_thread_queue -) -{ - ISR_Level level; - Thread_Control *the_thread; - - _ISR_Disable( level ); - if ( !_Chain_Is_empty( &the_thread_queue->Queues.Fifo ) ) { - - the_thread = (Thread_Control *) - _Chain_Get_first_unprotected( &the_thread_queue->Queues.Fifo ); - - if ( !_Watchdog_Is_active( &the_thread->Timer ) ) { - _ISR_Enable( level ); - _Thread_Unblock( the_thread ); - } else { - _Watchdog_Deactivate( &the_thread->Timer ); - _ISR_Enable( level ); - (void) _Watchdog_Remove( &the_thread->Timer ); - _Thread_Unblock( the_thread ); - } - -#if defined(RTEMS_MULTIPROCESSING) - if ( !_Objects_Is_local_id( the_thread->Object.id ) ) - _Thread_MP_Free_proxy( the_thread ); -#endif - - return the_thread; - } - - switch ( the_thread_queue->sync_state ) { - case THREAD_QUEUE_SYNCHRONIZED: - case THREAD_QUEUE_SATISFIED: - _ISR_Enable( level ); - return NULL; - - case THREAD_QUEUE_NOTHING_HAPPENED: - case THREAD_QUEUE_TIMEOUT: - the_thread_queue->sync_state = THREAD_QUEUE_SATISFIED; - _ISR_Enable( level ); - return _Thread_Executing; - } - return NULL; /* this is only to prevent warnings */ -} - diff --git a/c/src/exec/score/src/threadqdequeuepriority.c b/c/src/exec/score/src/threadqdequeuepriority.c deleted file mode 100644 index 0ca29eeabf..0000000000 --- a/c/src/exec/score/src/threadqdequeuepriority.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Dequeue_priority - * - * This routine removes a thread from the specified PRIORITY based - * threadq, unblocks it, and cancels its timeout timer. - * - * Input parameters: - * the_thread_queue - pointer to thread queue - * - * Output parameters: - * returns - thread dequeued or NULL - * - * INTERRUPT LATENCY: - * only case - */ - -Thread_Control *_Thread_queue_Dequeue_priority( - Thread_queue_Control *the_thread_queue -) -{ - unsigned32 index; - ISR_Level level; - Thread_Control *the_thread = NULL; /* just to remove warnings */ - Thread_Control *new_first_thread; - Chain_Node *new_first_node; - Chain_Node *new_second_node; - Chain_Node *last_node; - Chain_Node *next_node; - Chain_Node *previous_node; - - _ISR_Disable( level ); - for( index=0 ; - index < TASK_QUEUE_DATA_NUMBER_OF_PRIORITY_HEADERS ; - index++ ) { - if ( !_Chain_Is_empty( &the_thread_queue->Queues.Priority[ index ] ) ) { - the_thread = (Thread_Control *) - the_thread_queue->Queues.Priority[ index ].first; - goto dequeue; - } - } - - switch ( the_thread_queue->sync_state ) { - case THREAD_QUEUE_SYNCHRONIZED: - case THREAD_QUEUE_SATISFIED: - _ISR_Enable( level ); - return NULL; - - case THREAD_QUEUE_NOTHING_HAPPENED: - case THREAD_QUEUE_TIMEOUT: - the_thread_queue->sync_state = THREAD_QUEUE_SATISFIED; - _ISR_Enable( level ); - return _Thread_Executing; - } - -dequeue: - new_first_node = the_thread->Wait.Block2n.first; - new_first_thread = (Thread_Control *) new_first_node; - next_node = the_thread->Object.Node.next; - previous_node = the_thread->Object.Node.previous; - - if ( !_Chain_Is_empty( &the_thread->Wait.Block2n ) ) { - last_node = the_thread->Wait.Block2n.last; - new_second_node = new_first_node->next; - - previous_node->next = new_first_node; - next_node->previous = new_first_node; - new_first_node->next = next_node; - new_first_node->previous = previous_node; - - if ( !_Chain_Has_only_one_node( &the_thread->Wait.Block2n ) ) { - /* > two threads on 2-n */ - new_second_node->previous = - _Chain_Head( &new_first_thread->Wait.Block2n ); - - new_first_thread->Wait.Block2n.first = new_second_node; - new_first_thread->Wait.Block2n.last = last_node; - - last_node->next = _Chain_Tail( &new_first_thread->Wait.Block2n ); - } - } else { - previous_node->next = next_node; - next_node->previous = previous_node; - } - - if ( !_Watchdog_Is_active( &the_thread->Timer ) ) { - _ISR_Enable( level ); - _Thread_Unblock( the_thread ); - } else { - _Watchdog_Deactivate( &the_thread->Timer ); - _ISR_Enable( level ); - (void) _Watchdog_Remove( &the_thread->Timer ); - _Thread_Unblock( the_thread ); - } - -#if defined(RTEMS_MULTIPROCESSING) - if ( !_Objects_Is_local_id( the_thread->Object.id ) ) - _Thread_MP_Free_proxy( the_thread ); -#endif - return( the_thread ); -} - diff --git a/c/src/exec/score/src/threadqenqueue.c b/c/src/exec/score/src/threadqenqueue.c deleted file mode 100644 index fb4d907c78..0000000000 --- a/c/src/exec/score/src/threadqenqueue.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Enqueue - * - * This routine blocks a thread, places it on a thread, and optionally - * starts a timeout timer. - * - * Input parameters: - * the_thread_queue - pointer to threadq - * timeout - interval to wait - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * only case - */ - -void _Thread_queue_Enqueue( - Thread_queue_Control *the_thread_queue, - Watchdog_Interval timeout -) -{ - Thread_Control *the_thread; - - the_thread = _Thread_Executing; - -#if defined(RTEMS_MULTIPROCESSING) - if ( _Thread_MP_Is_receive( the_thread ) && the_thread->receive_packet ) - the_thread = _Thread_MP_Allocate_proxy( the_thread_queue->state ); - else -#endif - _Thread_Set_state( the_thread, the_thread_queue->state ); - - if ( timeout ) { - _Watchdog_Initialize( - &the_thread->Timer, - _Thread_queue_Timeout, - the_thread->Object.id, - NULL - ); - - _Watchdog_Insert_ticks( &the_thread->Timer, timeout ); - } - - switch( the_thread_queue->discipline ) { - case THREAD_QUEUE_DISCIPLINE_FIFO: - _Thread_queue_Enqueue_fifo( the_thread_queue, the_thread, timeout ); - break; - case THREAD_QUEUE_DISCIPLINE_PRIORITY: - _Thread_queue_Enqueue_priority( the_thread_queue, the_thread, timeout ); - break; - } -} - diff --git a/c/src/exec/score/src/threadqenqueuefifo.c b/c/src/exec/score/src/threadqenqueuefifo.c deleted file mode 100644 index 5ba902198e..0000000000 --- a/c/src/exec/score/src/threadqenqueuefifo.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Enqueue_fifo - * - * This routine blocks a thread, places it on a thread, and optionally - * starts a timeout timer. - * - * Input parameters: - * the_thread_queue - pointer to threadq - * the_thread - pointer to the thread to block - * timeout - interval to wait - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * only case - */ - -void _Thread_queue_Enqueue_fifo ( - Thread_queue_Control *the_thread_queue, - Thread_Control *the_thread, - Watchdog_Interval timeout -) -{ - ISR_Level level; - Thread_queue_States sync_state; - - _ISR_Disable( level ); - - sync_state = the_thread_queue->sync_state; - the_thread_queue->sync_state = THREAD_QUEUE_SYNCHRONIZED; - - switch ( sync_state ) { - case THREAD_QUEUE_SYNCHRONIZED: - /* - * This should never happen. It indicates that someone did not - * enter a thread queue critical section. - */ - break; - - case THREAD_QUEUE_NOTHING_HAPPENED: - _Chain_Append_unprotected( - &the_thread_queue->Queues.Fifo, - &the_thread->Object.Node - ); - _ISR_Enable( level ); - return; - - case THREAD_QUEUE_TIMEOUT: - the_thread->Wait.return_code = the_thread->Wait.queue->timeout_status; - _ISR_Enable( level ); - break; - - case THREAD_QUEUE_SATISFIED: - if ( _Watchdog_Is_active( &the_thread->Timer ) ) { - _Watchdog_Deactivate( &the_thread->Timer ); - _ISR_Enable( level ); - (void) _Watchdog_Remove( &the_thread->Timer ); - } else - _ISR_Enable( level ); - break; - } - - /* - * Global objects with thread queue's should not be operated on from an - * ISR. But the sync code still must allow short timeouts to be processed - * correctly. - */ - - _Thread_Unblock( the_thread ); - -#if defined(RTEMS_MULTIPROCESSING) - if ( !_Objects_Is_local_id( the_thread->Object.id ) ) - _Thread_MP_Free_proxy( the_thread ); -#endif - -} - diff --git a/c/src/exec/score/src/threadqenqueuepriority.c b/c/src/exec/score/src/threadqenqueuepriority.c deleted file mode 100644 index a3a49cd7dc..0000000000 --- a/c/src/exec/score/src/threadqenqueuepriority.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Enqueue_priority - * - * This routine blocks a thread, places it on a thread, and optionally - * starts a timeout timer. - * - * Input parameters: - * the_thread_queue - pointer to threadq - * thread - thread to insert - * timeout - timeout interval in ticks - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * forward less than - * forward equal - */ - -void _Thread_queue_Enqueue_priority( - Thread_queue_Control *the_thread_queue, - Thread_Control *the_thread, - Watchdog_Interval timeout -) -{ - Priority_Control search_priority; - Thread_Control *search_thread; - ISR_Level level; - Chain_Control *header; - unsigned32 header_index; - Chain_Node *the_node; - Chain_Node *next_node; - Chain_Node *previous_node; - Chain_Node *search_node; - Priority_Control priority; - States_Control block_state; - Thread_queue_States sync_state; - - _Chain_Initialize_empty( &the_thread->Wait.Block2n ); - - priority = the_thread->current_priority; - header_index = _Thread_queue_Header_number( priority ); - header = &the_thread_queue->Queues.Priority[ header_index ]; - block_state = the_thread_queue->state; - - if ( _Thread_queue_Is_reverse_search( priority ) ) - goto restart_reverse_search; - -restart_forward_search: - search_priority = PRIORITY_MINIMUM - 1; - _ISR_Disable( level ); - search_thread = (Thread_Control *) header->first; - while ( !_Chain_Is_tail( header, (Chain_Node *)search_thread ) ) { - search_priority = search_thread->current_priority; - if ( priority <= search_priority ) - break; - -#if ( CPU_UNROLL_ENQUEUE_PRIORITY == TRUE ) - search_thread = (Thread_Control *) search_thread->Object.Node.next; - if ( _Chain_Is_tail( header, (Chain_Node *)search_thread ) ) - break; - search_priority = search_thread->current_priority; - if ( priority <= search_priority ) - break; -#endif - _ISR_Flash( level ); - if ( !_States_Are_set( search_thread->current_state, block_state) ) { - _ISR_Enable( level ); - goto restart_forward_search; - } - search_thread = - (Thread_Control *)search_thread->Object.Node.next; - } - - if ( the_thread_queue->sync_state != THREAD_QUEUE_NOTHING_HAPPENED ) - goto synchronize; - - the_thread_queue->sync_state = THREAD_QUEUE_SYNCHRONIZED; - - if ( priority == search_priority ) - goto equal_priority; - - search_node = (Chain_Node *) search_thread; - previous_node = search_node->previous; - the_node = (Chain_Node *) the_thread; - - the_node->next = search_node; - the_node->previous = previous_node; - previous_node->next = the_node; - search_node->previous = the_node; - _ISR_Enable( level ); - return; - -restart_reverse_search: - search_priority = PRIORITY_MAXIMUM + 1; - - _ISR_Disable( level ); - search_thread = (Thread_Control *) header->last; - while ( !_Chain_Is_head( header, (Chain_Node *)search_thread ) ) { - search_priority = search_thread->current_priority; - if ( priority >= search_priority ) - break; -#if ( CPU_UNROLL_ENQUEUE_PRIORITY == TRUE ) - search_thread = (Thread_Control *) search_thread->Object.Node.previous; - if ( _Chain_Is_head( header, (Chain_Node *)search_thread ) ) - break; - search_priority = search_thread->current_priority; - if ( priority >= search_priority ) - break; -#endif - _ISR_Flash( level ); - if ( !_States_Are_set( search_thread->current_state, block_state) ) { - _ISR_Enable( level ); - goto restart_reverse_search; - } - search_thread = (Thread_Control *) - search_thread->Object.Node.previous; - } - - if ( the_thread_queue->sync_state != THREAD_QUEUE_NOTHING_HAPPENED ) - goto synchronize; - - the_thread_queue->sync_state = THREAD_QUEUE_SYNCHRONIZED; - - if ( priority == search_priority ) - goto equal_priority; - - search_node = (Chain_Node *) search_thread; - next_node = search_node->next; - the_node = (Chain_Node *) the_thread; - - the_node->next = next_node; - the_node->previous = search_node; - search_node->next = the_node; - next_node->previous = the_node; - _ISR_Enable( level ); - return; - -equal_priority: /* add at end of priority group */ - search_node = _Chain_Tail( &search_thread->Wait.Block2n ); - previous_node = search_node->previous; - the_node = (Chain_Node *) the_thread; - - the_node->next = search_node; - the_node->previous = previous_node; - previous_node->next = the_node; - search_node->previous = the_node; - _ISR_Enable( level ); - return; - -synchronize: - - sync_state = the_thread_queue->sync_state; - the_thread_queue->sync_state = THREAD_QUEUE_SYNCHRONIZED; - - switch ( sync_state ) { - case THREAD_QUEUE_SYNCHRONIZED: - /* - * This should never happen. It indicates that someone did not - * enter a thread queue critical section. - */ - break; - - case THREAD_QUEUE_NOTHING_HAPPENED: - /* - * This should never happen. All of this was dealt with above. - */ - break; - - case THREAD_QUEUE_TIMEOUT: - the_thread->Wait.return_code = the_thread->Wait.queue->timeout_status; - _ISR_Enable( level ); - break; - - case THREAD_QUEUE_SATISFIED: - if ( _Watchdog_Is_active( &the_thread->Timer ) ) { - _Watchdog_Deactivate( &the_thread->Timer ); - _ISR_Enable( level ); - (void) _Watchdog_Remove( &the_thread->Timer ); - } else - _ISR_Enable( level ); - break; - } - - /* - * Global objects with thread queue's should not be operated on from an - * ISR. But the sync code still must allow short timeouts to be processed - * correctly. - */ - - _Thread_Unblock( the_thread ); - -#if defined(RTEMS_MULTIPROCESSING) - if ( !_Objects_Is_local_id( the_thread->Object.id ) ) - _Thread_MP_Free_proxy( the_thread ); -#endif -} - diff --git a/c/src/exec/score/src/threadqextract.c b/c/src/exec/score/src/threadqextract.c deleted file mode 100644 index 0514b2d932..0000000000 --- a/c/src/exec/score/src/threadqextract.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Extract - * - * This routine removes a specific thread from the specified threadq, - * deletes any timeout, and unblocks the thread. - * - * Input parameters: - * the_thread_queue - pointer to a threadq header - * the_thread - pointer to a thread control block - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: NONE - */ - -void _Thread_queue_Extract( - Thread_queue_Control *the_thread_queue, - Thread_Control *the_thread -) -{ - switch ( the_thread_queue->discipline ) { - case THREAD_QUEUE_DISCIPLINE_FIFO: - _Thread_queue_Extract_fifo( the_thread_queue, the_thread ); - break; - case THREAD_QUEUE_DISCIPLINE_PRIORITY: - _Thread_queue_Extract_priority( the_thread_queue, the_thread ); - break; - } -} - diff --git a/c/src/exec/score/src/threadqextractfifo.c b/c/src/exec/score/src/threadqextractfifo.c deleted file mode 100644 index d2f23d38ea..0000000000 --- a/c/src/exec/score/src/threadqextractfifo.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Extract_fifo - * - * This routine removes a specific thread from the specified threadq, - * deletes any timeout, and unblocks the thread. - * - * Input parameters: - * the_thread_queue - pointer to a threadq header - * the_thread - pointer to the thread to block - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * EXTRACT_FIFO - */ - -void _Thread_queue_Extract_fifo( - Thread_queue_Control *the_thread_queue, - Thread_Control *the_thread -) -{ - ISR_Level level; - - _ISR_Disable( level ); - - if ( !_States_Is_waiting_on_thread_queue( the_thread->current_state ) ) { - _ISR_Enable( level ); - return; - } - - _Chain_Extract_unprotected( &the_thread->Object.Node ); - - if ( !_Watchdog_Is_active( &the_thread->Timer ) ) { - _ISR_Enable( level ); - } else { - _Watchdog_Deactivate( &the_thread->Timer ); - _ISR_Enable( level ); - (void) _Watchdog_Remove( &the_thread->Timer ); - } - - _Thread_Unblock( the_thread ); - -#if defined(RTEMS_MULTIPROCESSING) - if ( !_Objects_Is_local_id( the_thread->Object.id ) ) - _Thread_MP_Free_proxy( the_thread ); -#endif - -} - diff --git a/c/src/exec/score/src/threadqextractpriority.c b/c/src/exec/score/src/threadqextractpriority.c deleted file mode 100644 index 57c9c54137..0000000000 --- a/c/src/exec/score/src/threadqextractpriority.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Extract_priority - * - * This routine removes a specific thread from the specified threadq, - * deletes any timeout, and unblocks the thread. - * - * Input parameters: - * the_thread_queue - pointer to a threadq header - * the_thread - pointer to a thread control block - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * EXTRACT_PRIORITY - */ - -void _Thread_queue_Extract_priority( - Thread_queue_Control *the_thread_queue, - Thread_Control *the_thread -) -{ - ISR_Level level; - Chain_Node *the_node; - Chain_Node *next_node; - Chain_Node *previous_node; - Thread_Control *new_first_thread; - Chain_Node *new_first_node; - Chain_Node *new_second_node; - Chain_Node *last_node; - - the_node = (Chain_Node *) the_thread; - _ISR_Disable( level ); - if ( _States_Is_waiting_on_thread_queue( the_thread->current_state ) ) { - next_node = the_node->next; - previous_node = the_node->previous; - - if ( !_Chain_Is_empty( &the_thread->Wait.Block2n ) ) { - new_first_node = the_thread->Wait.Block2n.first; - new_first_thread = (Thread_Control *) new_first_node; - last_node = the_thread->Wait.Block2n.last; - new_second_node = new_first_node->next; - - previous_node->next = new_first_node; - next_node->previous = new_first_node; - new_first_node->next = next_node; - new_first_node->previous = previous_node; - - if ( !_Chain_Has_only_one_node( &the_thread->Wait.Block2n ) ) { - /* > two threads on 2-n */ - new_second_node->previous = - _Chain_Head( &new_first_thread->Wait.Block2n ); - new_first_thread->Wait.Block2n.first = new_second_node; - - new_first_thread->Wait.Block2n.last = last_node; - last_node->next = _Chain_Tail( &new_first_thread->Wait.Block2n ); - } - } else { - previous_node->next = next_node; - next_node->previous = previous_node; - } - - if ( !_Watchdog_Is_active( &the_thread->Timer ) ) { - _ISR_Enable( level ); - _Thread_Unblock( the_thread ); - } else { - _Watchdog_Deactivate( &the_thread->Timer ); - _ISR_Enable( level ); - (void) _Watchdog_Remove( &the_thread->Timer ); - _Thread_Unblock( the_thread ); - } - -#if defined(RTEMS_MULTIPROCESSING) - if ( !_Objects_Is_local_id( the_thread->Object.id ) ) - _Thread_MP_Free_proxy( the_thread ); -#endif - } - else - _ISR_Enable( level ); -} - diff --git a/c/src/exec/score/src/threadqextractwithproxy.c b/c/src/exec/score/src/threadqextractwithproxy.c deleted file mode 100644 index 5c47b215ae..0000000000 --- a/c/src/exec/score/src/threadqextractwithproxy.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Extract_with_proxy - * - * This routine extracts the_thread from the_thread_queue - * and ensures that if there is a proxy for this task on - * another node, it is also dealt with. - * - * XXX - */ - -boolean _Thread_queue_Extract_with_proxy( - Thread_Control *the_thread -) -{ - States_Control state; - Objects_Information *the_information; - Objects_Thread_queue_Extract_callout proxy_extract_callout; - - state = the_thread->current_state; - - if ( _States_Is_waiting_on_thread_queue( state ) ) { - if ( _States_Is_waiting_for_rpc_reply( state ) && - _States_Is_locally_blocked( state ) ) { - - the_information = _Objects_Get_information( the_thread->Wait.id ); - - proxy_extract_callout = - (Objects_Thread_queue_Extract_callout) the_information->extract; - - if ( proxy_extract_callout ) - (*proxy_extract_callout)( the_thread ); - } - _Thread_queue_Extract( the_thread->Wait.queue, the_thread ); - - return TRUE; - } - return FALSE; -} - diff --git a/c/src/exec/score/src/threadqfirst.c b/c/src/exec/score/src/threadqfirst.c deleted file mode 100644 index 0057429376..0000000000 --- a/c/src/exec/score/src/threadqfirst.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_First - * - * This routines returns a pointer to the first thread on the - * specified threadq. - * - * Input parameters: - * the_thread_queue - pointer to thread queue - * - * Output parameters: - * returns - first thread or NULL - */ - -Thread_Control *_Thread_queue_First( - Thread_queue_Control *the_thread_queue -) -{ - Thread_Control *the_thread; - - switch ( the_thread_queue->discipline ) { - case THREAD_QUEUE_DISCIPLINE_FIFO: - the_thread = _Thread_queue_First_fifo( the_thread_queue ); - break; - case THREAD_QUEUE_DISCIPLINE_PRIORITY: - the_thread = _Thread_queue_First_priority( the_thread_queue ); - break; - default: /* this is only to prevent warnings */ - the_thread = NULL; - break; - } - - return the_thread; -} - diff --git a/c/src/exec/score/src/threadqfirstfifo.c b/c/src/exec/score/src/threadqfirstfifo.c deleted file mode 100644 index f1b92f2fd2..0000000000 --- a/c/src/exec/score/src/threadqfirstfifo.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_First_fifo - * - * This routines returns a pointer to the first thread on the - * specified threadq. - * - * Input parameters: - * the_thread_queue - pointer to threadq - * - * Output parameters: - * returns - first thread or NULL - */ - -Thread_Control *_Thread_queue_First_fifo( - Thread_queue_Control *the_thread_queue -) -{ - if ( !_Chain_Is_empty( &the_thread_queue->Queues.Fifo ) ) - return (Thread_Control *) the_thread_queue->Queues.Fifo.first; - - return NULL; -} - diff --git a/c/src/exec/score/src/threadqfirstpriority.c b/c/src/exec/score/src/threadqfirstpriority.c deleted file mode 100644 index dbab132ef6..0000000000 --- a/c/src/exec/score/src/threadqfirstpriority.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_First_priority - * - * This routines returns a pointer to the first thread on the - * specified threadq. - * - * Input parameters: - * the_thread_queue - pointer to thread queue - * - * Output parameters: - * returns - first thread or NULL - */ - -Thread_Control *_Thread_queue_First_priority ( - Thread_queue_Control *the_thread_queue -) -{ - unsigned32 index; - - for( index=0 ; - index < TASK_QUEUE_DATA_NUMBER_OF_PRIORITY_HEADERS ; - index++ ) { - if ( !_Chain_Is_empty( &the_thread_queue->Queues.Priority[ index ] ) ) - return (Thread_Control *) - the_thread_queue->Queues.Priority[ index ].first; - } - return NULL; -} diff --git a/c/src/exec/score/src/threadqflush.c b/c/src/exec/score/src/threadqflush.c deleted file mode 100644 index 4d97ff60ab..0000000000 --- a/c/src/exec/score/src/threadqflush.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Flush - * - * This kernel routine flushes the given thread queue. - * - * Input parameters: - * the_thread_queue - pointer to threadq to be flushed - * remote_extract_callout - pointer to routine which extracts a remote thread - * status - status to return to the thread - * - * Output parameters: NONE - */ - -void _Thread_queue_Flush( - Thread_queue_Control *the_thread_queue, - Thread_queue_Flush_callout remote_extract_callout, - unsigned32 status -) -{ - Thread_Control *the_thread; - - while ( (the_thread = _Thread_queue_Dequeue( the_thread_queue )) ) { -#if defined(RTEMS_MULTIPROCESSING) - if ( !_Objects_Is_local_id( the_thread->Object.id ) ) - ( *remote_extract_callout )( the_thread ); - else -#endif - the_thread->Wait.return_code = status; - } -} - diff --git a/c/src/exec/score/src/threadqtimeout.c b/c/src/exec/score/src/threadqtimeout.c deleted file mode 100644 index 7ac2c04186..0000000000 --- a/c/src/exec/score/src/threadqtimeout.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Thread Queue Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/chain.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/states.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/tqdata.h> - -/*PAGE - * - * _Thread_queue_Timeout - * - * This routine processes a thread which timeouts while waiting on - * a thread queue. It is called by the watchdog handler. - * - * Input parameters: - * id - thread id - * - * Output parameters: NONE - */ - -void _Thread_queue_Timeout( - Objects_Id id, - void *ignored -) -{ - Thread_Control *the_thread; - Thread_queue_Control *the_thread_queue; - Objects_Locations location; - - the_thread = _Thread_Get( id, &location ); - switch ( location ) { - case OBJECTS_ERROR: - case OBJECTS_REMOTE: /* impossible */ - break; - case OBJECTS_LOCAL: - the_thread_queue = the_thread->Wait.queue; - - /* - * If the_thread_queue is not synchronized, then it is either - * "nothing happened", "timeout", or "satisfied". If the_thread - * is the executing thread, then it is in the process of blocking - * and it is the thread which is responsible for the synchronization - * process. - * - * If it is not satisfied, then it is "nothing happened" and - * this is the "timeout" transition. After a request is satisfied, - * a timeout is not allowed to occur. - */ - - if ( the_thread_queue->sync_state != THREAD_QUEUE_SYNCHRONIZED && - _Thread_Is_executing( the_thread ) ) { - if ( the_thread_queue->sync_state != THREAD_QUEUE_SATISFIED ) - the_thread_queue->sync_state = THREAD_QUEUE_TIMEOUT; - } else { - the_thread->Wait.return_code = the_thread->Wait.queue->timeout_status; - _Thread_queue_Extract( the_thread->Wait.queue, the_thread ); - } - _Thread_Unnest_dispatch(); - break; - } -} - diff --git a/c/src/exec/score/src/threadready.c b/c/src/exec/score/src/threadready.c deleted file mode 100644 index 35525e787a..0000000000 --- a/c/src/exec/score/src/threadready.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Ready - * - * This kernel routine readies the requested thread, the thread chain - * is adjusted. A new heir thread may be selected. - * - * Input parameters: - * the_thread - pointer to thread control block - * - * Output parameters: NONE - * - * NOTE: This routine uses the "blocking" heir selection mechanism. - * This insures the correct heir after a thread restart. - * - * INTERRUPT LATENCY: - * ready chain - * select heir - */ - -void _Thread_Ready( - Thread_Control *the_thread -) -{ - ISR_Level level; - Thread_Control *heir; - - _ISR_Disable( level ); - - the_thread->current_state = STATES_READY; - - _Priority_Add_to_bit_map( &the_thread->Priority_map ); - - _Chain_Append_unprotected( the_thread->ready, &the_thread->Object.Node ); - - _ISR_Flash( level ); - - _Thread_Calculate_heir(); - - heir = _Thread_Heir; - - if ( !_Thread_Is_executing( heir ) && _Thread_Executing->is_preemptible ) - _Context_Switch_necessary = TRUE; - - _ISR_Enable( level ); -} diff --git a/c/src/exec/score/src/threadreset.c b/c/src/exec/score/src/threadreset.c deleted file mode 100644 index 52c975ec17..0000000000 --- a/c/src/exec/score/src/threadreset.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/* - * _Thread_Reset - * - * DESCRIPTION: - * - * This routine resets a thread to its initial stat but does - * not actually restart it. Some APIs do this in separate - * operations and this division helps support this. - */ - -void _Thread_Reset( - Thread_Control *the_thread, - void *pointer_argument, - unsigned32 numeric_argument -) -{ - the_thread->resource_count = 0; - the_thread->suspend_count = 0; - the_thread->is_preemptible = the_thread->Start.is_preemptible; - the_thread->budget_algorithm = the_thread->Start.budget_algorithm; - the_thread->budget_callout = the_thread->Start.budget_callout; - - the_thread->Start.pointer_argument = pointer_argument; - the_thread->Start.numeric_argument = numeric_argument; - - if ( !_Thread_queue_Extract_with_proxy( the_thread ) ) { - - if ( _Watchdog_Is_active( &the_thread->Timer ) ) - (void) _Watchdog_Remove( &the_thread->Timer ); - } - - if ( the_thread->current_priority != the_thread->Start.initial_priority ) { - the_thread->real_priority = the_thread->Start.initial_priority; - _Thread_Set_priority( the_thread, the_thread->Start.initial_priority ); - } -} - diff --git a/c/src/exec/score/src/threadresettimeslice.c b/c/src/exec/score/src/threadresettimeslice.c deleted file mode 100644 index 480009b403..0000000000 --- a/c/src/exec/score/src/threadresettimeslice.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Reset_timeslice - * - * This routine will remove the running thread from the ready chain - * and place it immediately at the rear of this chain and then the - * timeslice counter is reset. The heir THREAD will be updated if - * the running is also the currently the heir. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * ready chain - * select heir - */ - -void _Thread_Reset_timeslice( void ) -{ - ISR_Level level; - Thread_Control *executing; - Chain_Control *ready; - - executing = _Thread_Executing; - ready = executing->ready; - _ISR_Disable( level ); - if ( _Chain_Has_only_one_node( ready ) ) { - _ISR_Enable( level ); - return; - } - _Chain_Extract_unprotected( &executing->Object.Node ); - _Chain_Append_unprotected( ready, &executing->Object.Node ); - - _ISR_Flash( level ); - - if ( _Thread_Is_heir( executing ) ) - _Thread_Heir = (Thread_Control *) ready->first; - - _Context_Switch_necessary = TRUE; - - _ISR_Enable( level ); -} diff --git a/c/src/exec/score/src/threadrestart.c b/c/src/exec/score/src/threadrestart.c deleted file mode 100644 index f2b6e9ddbb..0000000000 --- a/c/src/exec/score/src/threadrestart.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/* - * _Thread_Restart - * - * DESCRIPTION: - * - * This support routine restarts the specified task in a way that the - * next time this thread executes, it will begin execution at its - * original starting point. - */ - -boolean _Thread_Restart( - Thread_Control *the_thread, - void *pointer_argument, - unsigned32 numeric_argument -) -{ - if ( !_States_Is_dormant( the_thread->current_state ) ) { - - _Thread_Set_transient( the_thread ); - - _Thread_Reset( the_thread, pointer_argument, numeric_argument ); - - _Thread_Load_environment( the_thread ); - - _Thread_Ready( the_thread ); - - _User_extensions_Thread_restart( the_thread ); - - if ( _Thread_Is_executing ( the_thread ) ) - _Thread_Restart_self(); - - return TRUE; - } - - return FALSE; -} diff --git a/c/src/exec/score/src/threadresume.c b/c/src/exec/score/src/threadresume.c deleted file mode 100644 index 221d6a0fc0..0000000000 --- a/c/src/exec/score/src/threadresume.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Resume - * - * This kernel routine clears the SUSPEND state if the suspend_count - * drops below one. If the force parameter is set the suspend_count - * is forced back to zero. The thread ready chain is adjusted if - * necessary and the Heir thread is set accordingly. - * - * Input parameters: - * the_thread - pointer to thread control block - * force - force the suspend count back to 0 - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * priority map - * select heir - */ - - -void _Thread_Resume( - Thread_Control *the_thread, - boolean force -) -{ - - ISR_Level level; - States_Control current_state; - - _ISR_Disable( level ); - - if ( force == TRUE ) - the_thread->suspend_count = 0; - else - the_thread->suspend_count--; - - if ( the_thread->suspend_count > 0 ) { - _ISR_Enable( level ); - return; - } - - current_state = the_thread->current_state; - if ( current_state & STATES_SUSPENDED ) { - current_state = - the_thread->current_state = _States_Clear(STATES_SUSPENDED, current_state); - - if ( _States_Is_ready( current_state ) ) { - - _Priority_Add_to_bit_map( &the_thread->Priority_map ); - - _Chain_Append_unprotected(the_thread->ready, &the_thread->Object.Node); - - _ISR_Flash( level ); - - if ( the_thread->current_priority < _Thread_Heir->current_priority ) { - _Thread_Heir = the_thread; - if ( _Thread_Executing->is_preemptible || - the_thread->current_priority == 0 ) - _Context_Switch_necessary = TRUE; - } - } - } - - _ISR_Enable( level ); -} diff --git a/c/src/exec/score/src/threadrotatequeue.c b/c/src/exec/score/src/threadrotatequeue.c deleted file mode 100644 index 0c436e22a9..0000000000 --- a/c/src/exec/score/src/threadrotatequeue.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Rotate_Ready_Queue - * - * This kernel routine will rotate the ready queue. - * remove the running THREAD from the ready chain - * and place it immediatly at the rear of this chain. Reset timeslice - * and yield the processor functions both use this routine, therefore if - * reset is TRUE and this is the only thread on the chain then the - * timeslice counter is reset. The heir THREAD will be updated if the - * running is also the currently the heir. - * - * Input parameters: - * Priority of the queue we wish to modify. - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * ready chain - * select heir - */ - -void _Thread_Rotate_Ready_Queue( - Priority_Control priority -) -{ - ISR_Level level; - Thread_Control *executing; - Chain_Control *ready; - Chain_Node *node; - - ready = &_Thread_Ready_chain[ priority ]; - executing = _Thread_Executing; - - if ( ready == executing->ready ) { - _Thread_Yield_processor(); - return; - } - - _ISR_Disable( level ); - - if ( !_Chain_Is_empty( ready ) ) { - if (!_Chain_Has_only_one_node( ready ) ) { - node = _Chain_Get_first_unprotected( ready ); - _Chain_Append_unprotected( ready, node ); - } - } - - _ISR_Flash( level ); - - if ( _Thread_Heir->ready == ready ) - _Thread_Heir = (Thread_Control *) ready->first; - - if ( executing != _Thread_Heir ) - _Context_Switch_necessary = TRUE; - - _ISR_Enable( level ); -} - - - - - - diff --git a/c/src/exec/score/src/threadsetpriority.c b/c/src/exec/score/src/threadsetpriority.c deleted file mode 100644 index a4641ae43f..0000000000 --- a/c/src/exec/score/src/threadsetpriority.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Set_priority - * - * This directive enables and disables several modes of - * execution for the requesting thread. - * - * Input parameters: - * the_thread - pointer to thread priority - * new_priority - new priority - * - * Output: NONE - */ - -void _Thread_Set_priority( - Thread_Control *the_thread, - Priority_Control new_priority -) -{ - the_thread->current_priority = new_priority; - the_thread->ready = &_Thread_Ready_chain[ new_priority ]; - - _Priority_Initialize_information( &the_thread->Priority_map, new_priority ); -} diff --git a/c/src/exec/score/src/threadsetstate.c b/c/src/exec/score/src/threadsetstate.c deleted file mode 100644 index 286cacd56a..0000000000 --- a/c/src/exec/score/src/threadsetstate.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Set_state - * - * This kernel routine sets the requested state in the THREAD. The - * THREAD chain is adjusted if necessary. - * - * Input parameters: - * the_thread - pointer to thread control block - * state - state to be set - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * ready chain - * select map - */ - -void _Thread_Set_state( - Thread_Control *the_thread, - States_Control state -) -{ - ISR_Level level; - Chain_Control *ready; - - ready = the_thread->ready; - _ISR_Disable( level ); - if ( !_States_Is_ready( the_thread->current_state ) ) { - the_thread->current_state = - _States_Set( state, the_thread->current_state ); - _ISR_Enable( level ); - return; - } - - the_thread->current_state = state; - - if ( _Chain_Has_only_one_node( ready ) ) { - - _Chain_Initialize_empty( ready ); - _Priority_Remove_from_bit_map( &the_thread->Priority_map ); - - } else - _Chain_Extract_unprotected( &the_thread->Object.Node ); - - _ISR_Flash( level ); - - if ( _Thread_Is_heir( the_thread ) ) - _Thread_Calculate_heir(); - - if ( _Thread_Is_executing( the_thread ) ) - _Context_Switch_necessary = TRUE; - - _ISR_Enable( level ); -} diff --git a/c/src/exec/score/src/threadsettransient.c b/c/src/exec/score/src/threadsettransient.c deleted file mode 100644 index 9a08bddbbb..0000000000 --- a/c/src/exec/score/src/threadsettransient.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Set_transient - * - * This kernel routine places the requested thread in the transient state - * which will remove it from the ready queue, if necessary. No - * rescheduling is necessary because it is assumed that the transient - * state will be cleared before dispatching is enabled. - * - * Input parameters: - * the_thread - pointer to thread control block - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * only case - */ - -void _Thread_Set_transient( - Thread_Control *the_thread -) -{ - ISR_Level level; - unsigned32 old_state; - Chain_Control *ready; - - ready = the_thread->ready; - _ISR_Disable( level ); - - old_state = the_thread->current_state; - the_thread->current_state = _States_Set( STATES_TRANSIENT, old_state ); - - if ( _States_Is_ready( old_state ) ) { - if ( _Chain_Has_only_one_node( ready ) ) { - - _Chain_Initialize_empty( ready ); - _Priority_Remove_from_bit_map( &the_thread->Priority_map ); - - } else - _Chain_Extract_unprotected( &the_thread->Object.Node ); - } - - _ISR_Enable( level ); - -} diff --git a/c/src/exec/score/src/threadstackallocate.c b/c/src/exec/score/src/threadstackallocate.c deleted file mode 100644 index 583b672f19..0000000000 --- a/c/src/exec/score/src/threadstackallocate.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Stack_Allocate - * - * Allocate the requested stack space for the thread. - * return the actual size allocated after any adjustment - * or return zero if the allocation failed. - * Set the Start.stack field to the address of the stack - */ - -unsigned32 _Thread_Stack_Allocate( - Thread_Control *the_thread, - unsigned32 stack_size -) -{ - void *stack_addr = 0; - - if ( !_Stack_Is_enough( stack_size ) ) - stack_size = STACK_MINIMUM_SIZE; - - /* - * Call ONLY the CPU table stack allocate hook, _or_ the - * the RTEMS workspace allocate. This is so the stack free - * routine can call the correct deallocation routine. - */ - - if ( _CPU_Table.stack_allocate_hook ) - { - stack_addr = (*_CPU_Table.stack_allocate_hook)( stack_size ); - } else { - - /* - * First pad the requested size so we allocate enough memory - * so the context initialization can align it properly. The address - * returned the workspace allocate must be directly stored in the - * stack control block because it is later used in the free sequence. - * - * Thus it is the responsibility of the CPU dependent code to - * get and keep the stack adjust factor, the stack alignment, and - * the context initialization sequence in sync. - */ - - stack_size = _Stack_Adjust_size( stack_size ); - stack_addr = _Workspace_Allocate( stack_size ); - } - - if ( !stack_addr ) - stack_size = 0; - - the_thread->Start.stack = stack_addr; - - return stack_size; -} diff --git a/c/src/exec/score/src/threadstackfree.c b/c/src/exec/score/src/threadstackfree.c deleted file mode 100644 index 1a8abeade8..0000000000 --- a/c/src/exec/score/src/threadstackfree.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/* - * _Thread_Stack_Free - * - * Deallocate the Thread's stack. - */ - -void _Thread_Stack_Free( - Thread_Control *the_thread -) -{ - /* - * If the API provided the stack space, then don't free it. - */ - - if ( !the_thread->Start.core_allocated_stack ) - return; - - /* - * Call ONLY the CPU table stack free hook, or the - * the RTEMS workspace free. This is so the free - * routine properly matches the allocation of the stack. - */ - - if ( _CPU_Table.stack_free_hook ) - (*_CPU_Table.stack_free_hook)( the_thread->Start.Initial_stack.area ); - else - _Workspace_Free( the_thread->Start.Initial_stack.area ); -} diff --git a/c/src/exec/score/src/threadstart.c b/c/src/exec/score/src/threadstart.c deleted file mode 100644 index ac36618c63..0000000000 --- a/c/src/exec/score/src/threadstart.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/* - * _Thread_Start - * - * DESCRIPTION: - * - * This routine initializes the executable information for a thread - * and makes it ready to execute. After this routine executes, the - * thread competes with all other threads for CPU time. - */ - -boolean _Thread_Start( - Thread_Control *the_thread, - Thread_Start_types the_prototype, - void *entry_point, - void *pointer_argument, - unsigned32 numeric_argument -) -{ - if ( _States_Is_dormant( the_thread->current_state ) ) { - - the_thread->Start.entry_point = (Thread_Entry) entry_point; - - the_thread->Start.prototype = the_prototype; - the_thread->Start.pointer_argument = pointer_argument; - the_thread->Start.numeric_argument = numeric_argument; - - _Thread_Load_environment( the_thread ); - - _Thread_Ready( the_thread ); - - _User_extensions_Thread_start( the_thread ); - - return TRUE; - } - - return FALSE; - -} diff --git a/c/src/exec/score/src/threadstartmultitasking.c b/c/src/exec/score/src/threadstartmultitasking.c deleted file mode 100644 index 0e58f77420..0000000000 --- a/c/src/exec/score/src/threadstartmultitasking.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Start_multitasking - * - * This kernel routine readies the requested thread, the thread chain - * is adjusted. A new heir thread may be selected. - * - * Input parameters: - * system_thread - pointer to system initialization thread control block - * idle_thread - pointer to idle thread control block - * - * Output parameters: NONE - * - * NOTE: This routine uses the "blocking" heir selection mechanism. - * This insures the correct heir after a thread restart. - * - * INTERRUPT LATENCY: - * ready chain - * select heir - */ - -void _Thread_Start_multitasking( void ) -{ - /* - * The system is now multitasking and completely initialized. - * This system thread now either "goes away" in a single processor - * system or "turns into" the server thread in an MP system. - */ - - _System_state_Set( SYSTEM_STATE_UP ); - - _Context_Switch_necessary = FALSE; - - _Thread_Executing = _Thread_Heir; - - /* - * Get the init task(s) running. - * - * Note: Thread_Dispatch() is normally used to dispatch threads. As - * part of its work, Thread_Dispatch() restores floating point - * state for the heir task. - * - * This code avoids Thread_Dispatch(), and so we have to restore - * (actually initialize) the floating point state "by hand". - * - * Ignore the CPU_USE_DEFERRED_FP_SWITCH because we must always - * switch in the first thread if it is FP. - */ - - -#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) - /* - * don't need to worry about saving BSP's floating point state - */ - - if ( _Thread_Heir->fp_context != NULL ) - _Context_Restore_fp( &_Thread_Heir->fp_context ); -#endif - - _Context_Switch( &_Thread_BSP_context, &_Thread_Heir->Registers ); -} diff --git a/c/src/exec/score/src/threadsuspend.c b/c/src/exec/score/src/threadsuspend.c deleted file mode 100644 index fe66b715e0..0000000000 --- a/c/src/exec/score/src/threadsuspend.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Suspend - * - * This kernel routine sets the SUSPEND state in the THREAD. The - * THREAD chain and suspend count are adjusted if necessary. - * - * Input parameters: - * the_thread - pointer to thread control block - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * ready chain - * select map - */ - -void _Thread_Suspend( - Thread_Control *the_thread -) -{ - ISR_Level level; - Chain_Control *ready; - - ready = the_thread->ready; - _ISR_Disable( level ); - the_thread->suspend_count++; - if ( !_States_Is_ready( the_thread->current_state ) ) { - the_thread->current_state = - _States_Set( STATES_SUSPENDED, the_thread->current_state ); - _ISR_Enable( level ); - return; - } - - the_thread->current_state = STATES_SUSPENDED; - - if ( _Chain_Has_only_one_node( ready ) ) { - - _Chain_Initialize_empty( ready ); - _Priority_Remove_from_bit_map( &the_thread->Priority_map ); - - } else - _Chain_Extract_unprotected( &the_thread->Object.Node ); - - _ISR_Flash( level ); - - if ( _Thread_Is_heir( the_thread ) ) - _Thread_Calculate_heir(); - - if ( _Thread_Is_executing( the_thread ) ) - _Context_Switch_necessary = TRUE; - - _ISR_Enable( level ); -} diff --git a/c/src/exec/score/src/threadtickletimeslice.c b/c/src/exec/score/src/threadtickletimeslice.c deleted file mode 100644 index 24ef516506..0000000000 --- a/c/src/exec/score/src/threadtickletimeslice.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Tickle_timeslice - * - * This scheduler routine determines if timeslicing is enabled - * for the currently executing thread and, if so, updates the - * timeslice count and checks for timeslice expiration. - * - * Input parameters: NONE - * - * Output parameters: NONE - */ - -void _Thread_Tickle_timeslice( void ) -{ - Thread_Control *executing; - - executing = _Thread_Executing; - - /* - * Increment the number of ticks this thread has been executing - */ - - executing->ticks_executed++; - - /* - * If the thread is not preemptible or is not ready, then - * just return. - */ - - if ( !executing->is_preemptible ) - return; - - if ( !_States_Is_ready( executing->current_state ) ) - return; - - /* - * The cpu budget algorithm determines what happens next. - */ - - switch ( executing->budget_algorithm ) { - case THREAD_CPU_BUDGET_ALGORITHM_NONE: - break; - - case THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE: - case THREAD_CPU_BUDGET_ALGORITHM_EXHAUST_TIMESLICE: - if ( --executing->cpu_time_budget == 0 ) { - _Thread_Reset_timeslice(); - executing->cpu_time_budget = _Thread_Ticks_per_timeslice; - } - break; - - case THREAD_CPU_BUDGET_ALGORITHM_CALLOUT: - if ( --executing->cpu_time_budget == 0 ) - (*executing->budget_callout)( executing ); - break; - } -} diff --git a/c/src/exec/score/src/threadyieldprocessor.c b/c/src/exec/score/src/threadyieldprocessor.c deleted file mode 100644 index b46a6b1474..0000000000 --- a/c/src/exec/score/src/threadyieldprocessor.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Thread Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/apiext.h> -#include <rtems/score/context.h> -#include <rtems/score/interr.h> -#include <rtems/score/isr.h> -#include <rtems/score/object.h> -#include <rtems/score/priority.h> -#include <rtems/score/states.h> -#include <rtems/score/sysstate.h> -#include <rtems/score/thread.h> -#include <rtems/score/threadq.h> -#include <rtems/score/userext.h> -#include <rtems/score/wkspace.h> - -/*PAGE - * - * _Thread_Yield_processor - * - * This kernel routine will remove the running THREAD from the ready chain - * and place it immediatly at the rear of this chain. Reset timeslice - * and yield the processor functions both use this routine, therefore if - * reset is TRUE and this is the only thread on the chain then the - * timeslice counter is reset. The heir THREAD will be updated if the - * running is also the currently the heir. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * INTERRUPT LATENCY: - * ready chain - * select heir - */ - -void _Thread_Yield_processor( void ) -{ - ISR_Level level; - Thread_Control *executing; - Chain_Control *ready; - - executing = _Thread_Executing; - ready = executing->ready; - _ISR_Disable( level ); - if ( !_Chain_Has_only_one_node( ready ) ) { - _Chain_Extract_unprotected( &executing->Object.Node ); - _Chain_Append_unprotected( ready, &executing->Object.Node ); - - _ISR_Flash( level ); - - if ( _Thread_Is_heir( executing ) ) - _Thread_Heir = (Thread_Control *) ready->first; - _Context_Switch_necessary = TRUE; - } - else if ( !_Thread_Is_heir( executing ) ) - _Context_Switch_necessary = TRUE; - - _ISR_Enable( level ); -} diff --git a/c/src/exec/score/src/userext.c b/c/src/exec/score/src/userext.c deleted file mode 100644 index d652c29568..0000000000 --- a/c/src/exec/score/src/userext.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * User Extension Handler - * - * NOTE: XXX - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/userext.h> - -/*PAGE - * - * _User_extensions_Thread_create - */ - -boolean _User_extensions_Thread_create ( - Thread_Control *the_thread -) -{ - Chain_Node *the_node; - User_extensions_Control *the_extension; - boolean status; - - for ( the_node = _User_extensions_List.first ; - !_Chain_Is_tail( &_User_extensions_List, the_node ) ; - the_node = the_node->next ) { - - the_extension = (User_extensions_Control *) the_node; - - if ( the_extension->Callouts.thread_create != NULL ) { - status = (*the_extension->Callouts.thread_create)( - _Thread_Executing, - the_thread - ); - if ( !status ) - return FALSE; - } - } - - return TRUE; -} - -/*PAGE - * - * _User_extensions_Thread_delete - */ - -void _User_extensions_Thread_delete ( - Thread_Control *the_thread -) -{ - Chain_Node *the_node; - User_extensions_Control *the_extension; - - for ( the_node = _User_extensions_List.last ; - !_Chain_Is_head( &_User_extensions_List, the_node ) ; - the_node = the_node->previous ) { - - the_extension = (User_extensions_Control *) the_node; - - if ( the_extension->Callouts.thread_delete != NULL ) - (*the_extension->Callouts.thread_delete)( - _Thread_Executing, - the_thread - ); - } -} - -/*PAGE - * - * _User_extensions_Thread_start - * - */ - -void _User_extensions_Thread_start ( - Thread_Control *the_thread -) -{ - Chain_Node *the_node; - User_extensions_Control *the_extension; - - for ( the_node = _User_extensions_List.first ; - !_Chain_Is_tail( &_User_extensions_List, the_node ) ; - the_node = the_node->next ) { - - the_extension = (User_extensions_Control *) the_node; - - if ( the_extension->Callouts.thread_start != NULL ) - (*the_extension->Callouts.thread_start)( - _Thread_Executing, - the_thread - ); - } -} - -/*PAGE - * - * _User_extensions_Thread_restart - * - */ - -void _User_extensions_Thread_restart ( - Thread_Control *the_thread -) -{ - Chain_Node *the_node; - User_extensions_Control *the_extension; - - for ( the_node = _User_extensions_List.first ; - !_Chain_Is_tail( &_User_extensions_List, the_node ) ; - the_node = the_node->next ) { - - the_extension = (User_extensions_Control *) the_node; - - if ( the_extension->Callouts.thread_restart != NULL ) - (*the_extension->Callouts.thread_restart)( - _Thread_Executing, - the_thread - ); - } -} - -/*PAGE - * - * _User_extensions_Thread_begin - * - */ - -void _User_extensions_Thread_begin ( - Thread_Control *executing -) -{ - Chain_Node *the_node; - User_extensions_Control *the_extension; - - for ( the_node = _User_extensions_List.first ; - !_Chain_Is_tail( &_User_extensions_List, the_node ) ; - the_node = the_node->next ) { - - the_extension = (User_extensions_Control *) the_node; - - if ( the_extension->Callouts.thread_begin != NULL ) - (*the_extension->Callouts.thread_begin)( executing ); - } -} - -/*PAGE - * - * _User_extensions_Thread_exitted - */ - -void _User_extensions_Thread_exitted ( - Thread_Control *executing -) -{ - Chain_Node *the_node; - User_extensions_Control *the_extension; - - for ( the_node = _User_extensions_List.last ; - !_Chain_Is_head( &_User_extensions_List, the_node ) ; - the_node = the_node->previous ) { - - the_extension = (User_extensions_Control *) the_node; - - if ( the_extension->Callouts.thread_exitted != NULL ) - (*the_extension->Callouts.thread_exitted)( executing ); - } -} - -/*PAGE - * - * _User_extensions_Fatal - */ - -void _User_extensions_Fatal ( - Internal_errors_Source the_source, - boolean is_internal, - unsigned32 the_error -) -{ - Chain_Node *the_node; - User_extensions_Control *the_extension; - - for ( the_node = _User_extensions_List.last ; - !_Chain_Is_head( &_User_extensions_List, the_node ) ; - the_node = the_node->previous ) { - - the_extension = (User_extensions_Control *) the_node; - - if ( the_extension->Callouts.fatal != NULL ) - (*the_extension->Callouts.fatal)( the_source, is_internal, the_error ); - } -} - - diff --git a/c/src/exec/score/src/watchdog.c b/c/src/exec/score/src/watchdog.c deleted file mode 100644 index 1bdbc5ae3d..0000000000 --- a/c/src/exec/score/src/watchdog.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Watchdog Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/watchdog.h> - -/*PAGE - * - * _Watchdog_Handler_initialization - * - * This routine initializes the watchdog handler. - * - * Input parameters: NONE - * - * Output parameters: NONE - */ - -void _Watchdog_Handler_initialization( void ) -{ - _Watchdog_Sync_count = 0; - _Watchdog_Sync_level = 0; - _Watchdog_Ticks_since_boot = 0; - - _Chain_Initialize_empty( &_Watchdog_Ticks_chain ); - _Chain_Initialize_empty( &_Watchdog_Seconds_chain ); -} diff --git a/c/src/exec/score/src/watchdogadjust.c b/c/src/exec/score/src/watchdogadjust.c deleted file mode 100644 index 6926743f32..0000000000 --- a/c/src/exec/score/src/watchdogadjust.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Watchdog Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/watchdog.h> - -/*PAGE - * - * _Watchdog_Adjust - * - * This routine adjusts the delta chain backward or forward in response - * to a time change. - * - * Input parameters: - * header - pointer to the delta chain to be adjusted - * direction - forward or backward adjustment to delta chain - * units - units to adjust - * - * Output parameters: - */ - -void _Watchdog_Adjust( - Chain_Control *header, - Watchdog_Adjust_directions direction, - Watchdog_Interval units -) -{ - if ( !_Chain_Is_empty( header ) ) { - switch ( direction ) { - case WATCHDOG_BACKWARD: - _Watchdog_First( header )->delta_interval += units; - break; - case WATCHDOG_FORWARD: - while ( units ) { - if ( units < _Watchdog_First( header )->delta_interval ) { - _Watchdog_First( header )->delta_interval -= units; - break; - } else { - units -= _Watchdog_First( header )->delta_interval; - _Watchdog_First( header )->delta_interval = 1; - _Watchdog_Tickle( header ); - if ( _Chain_Is_empty( header ) ) - break; - } - } - break; - } - } -} - diff --git a/c/src/exec/score/src/watchdoginsert.c b/c/src/exec/score/src/watchdoginsert.c deleted file mode 100644 index 43c1eacd76..0000000000 --- a/c/src/exec/score/src/watchdoginsert.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Watchdog Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/watchdog.h> - -/*PAGE - * - * _Watchdog_Insert - * - * This routine inserts a watchdog timer on to the appropriate delta - * chain while updating the delta interval counters. - */ - -void _Watchdog_Insert( - Chain_Control *header, - Watchdog_Control *the_watchdog -) -{ - ISR_Level level; - Watchdog_Control *after; - unsigned32 insert_isr_nest_level; - Watchdog_Interval delta_interval; - - - insert_isr_nest_level = _ISR_Nest_level; - the_watchdog->state = WATCHDOG_BEING_INSERTED; - - _Watchdog_Sync_count++; -restart: - delta_interval = the_watchdog->initial; - - _ISR_Disable( level ); - - for ( after = _Watchdog_First( header ) ; - ; - after = _Watchdog_Next( after ) ) { - - if ( delta_interval == 0 || !_Watchdog_Next( after ) ) - break; - - if ( delta_interval < after->delta_interval ) { - after->delta_interval -= delta_interval; - break; - } - - delta_interval -= after->delta_interval; - - /* - * If you experience problems comment out the _ISR_Flash line. - * 3.2.0 was the first release with this critical section redesigned. - * Under certain circumstances, the PREVIOUS critical section algorithm - * used around this flash point allowed interrupts to execute - * which violated the design assumptions. The critical section - * mechanism used here WAS redesigned to address this. - */ - - _ISR_Flash( level ); - - if ( the_watchdog->state != WATCHDOG_BEING_INSERTED ) { - goto exit_insert; - } - - if ( _Watchdog_Sync_level > insert_isr_nest_level ) { - _Watchdog_Sync_level = insert_isr_nest_level; - _ISR_Enable( level ); - goto restart; - } - } - - _Watchdog_Activate( the_watchdog ); - - the_watchdog->delta_interval = delta_interval; - - _Chain_Insert_unprotected( after->Node.previous, &the_watchdog->Node ); - - the_watchdog->start_time = _Watchdog_Ticks_since_boot; - -exit_insert: - _Watchdog_Sync_level = insert_isr_nest_level; - _Watchdog_Sync_count--; - _ISR_Enable( level ); -} - diff --git a/c/src/exec/score/src/watchdogremove.c b/c/src/exec/score/src/watchdogremove.c deleted file mode 100644 index f3b5d8e5a1..0000000000 --- a/c/src/exec/score/src/watchdogremove.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Watchdog Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/watchdog.h> - -/*PAGE - * - * _Watchdog_Remove - * - * The routine removes a watchdog from a delta chain and updates - * the delta counters of the remaining watchdogs. - */ - -Watchdog_States _Watchdog_Remove( - Watchdog_Control *the_watchdog -) -{ - ISR_Level level; - Watchdog_States previous_state; - Watchdog_Control *next_watchdog; - - _ISR_Disable( level ); - previous_state = the_watchdog->state; - switch ( previous_state ) { - case WATCHDOG_INACTIVE: - break; - - case WATCHDOG_BEING_INSERTED: - - /* - * It is not actually on the chain so just change the state and - * the Insert operation we interrupted will be aborted. - */ - the_watchdog->state = WATCHDOG_INACTIVE; - break; - - case WATCHDOG_ACTIVE: - case WATCHDOG_REMOVE_IT: - - the_watchdog->state = WATCHDOG_INACTIVE; - next_watchdog = _Watchdog_Next( the_watchdog ); - - if ( _Watchdog_Next(next_watchdog) ) - next_watchdog->delta_interval += the_watchdog->delta_interval; - - if ( _Watchdog_Sync_count ) - _Watchdog_Sync_level = _ISR_Nest_level; - - _Chain_Extract_unprotected( &the_watchdog->Node ); - break; - } - the_watchdog->stop_time = _Watchdog_Ticks_since_boot; - - _ISR_Enable( level ); - return( previous_state ); -} - diff --git a/c/src/exec/score/src/watchdogtickle.c b/c/src/exec/score/src/watchdogtickle.c deleted file mode 100644 index fe07f566ff..0000000000 --- a/c/src/exec/score/src/watchdogtickle.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Watchdog Handler - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/watchdog.h> - -/*PAGE - * - * _Watchdog_Tickle - * - * This routine decrements the delta counter in response to a tick. The - * delta chain is updated accordingly. - * - * Input parameters: - * header - pointer to the delta chain to be tickled - * - * Output parameters: NONE - */ - -void _Watchdog_Tickle( - Chain_Control *header -) -{ - Watchdog_Control *the_watchdog; - - if ( _Chain_Is_empty( header ) ) - return; - - the_watchdog = _Watchdog_First( header ); - the_watchdog->delta_interval--; - if ( the_watchdog->delta_interval != 0 ) - return; - - do { - switch( _Watchdog_Remove( the_watchdog ) ) { - case WATCHDOG_ACTIVE: - (*the_watchdog->routine)( - the_watchdog->id, - the_watchdog->user_data - ); - break; - - case WATCHDOG_INACTIVE: - /* - * This state indicates that the watchdog is not on any chain. - * Thus, it is NOT on a chain being tickled. This case should - * never occur. - */ - break; - - case WATCHDOG_BEING_INSERTED: - /* - * This state indicates that the watchdog is in the process of - * BEING inserted on the chain. Thus, it can NOT be on a chain - * being tickled. This case should never occur. - */ - break; - - case WATCHDOG_REMOVE_IT: - break; - } - the_watchdog = _Watchdog_First( header ); - } while ( !_Chain_Is_empty( header ) && - (the_watchdog->delta_interval == 0) ); -} diff --git a/c/src/exec/score/src/wkspace.c b/c/src/exec/score/src/wkspace.c deleted file mode 100644 index 4ae6c6c118..0000000000 --- a/c/src/exec/score/src/wkspace.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Workspace Handler - * - * XXX - * - * NOTE: - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/interr.h> - -/*PAGE - * - * _Workspace_Handler_initialization - */ - -void _Workspace_Handler_initialization( - void *starting_address, - unsigned32 size -) -{ - unsigned32 *zero_out_array; - unsigned32 index; - unsigned32 memory_available; - - if ( !starting_address || !_Addresses_Is_aligned( starting_address ) ) - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_INVALID_WORKSPACE_ADDRESS - ); - - if ( _CPU_Table.do_zero_of_workspace ) { - for( zero_out_array = (unsigned32 *) starting_address, index = 0 ; - index < size / sizeof( unsigned32 ) ; - index++ ) - zero_out_array[ index ] = 0; - } - - memory_available = _Heap_Initialize( - &_Workspace_Area, - starting_address, - size, - CPU_HEAP_ALIGNMENT - ); - - if ( memory_available == 0 ) - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_TOO_LITTLE_WORKSPACE - ); -} - -/*PAGE - * - * _Workspace_Allocate_or_fatal_error - * - */ - -void *_Workspace_Allocate_or_fatal_error( - unsigned32 size -) -{ - void *memory; - - memory = _Workspace_Allocate( size ); - - if ( memory == NULL ) - _Internal_error_Occurred( - INTERNAL_ERROR_CORE, - TRUE, - INTERNAL_ERROR_WORKSPACE_ALLOCATION - ); - - return memory; -} |