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authorJoel Sherrill <joel.sherrill@OARcorp.com>2002-04-18 13:18:11 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2002-04-18 13:18:11 +0000
commite80ac7f6c253169db44455b883783b134a469a51 (patch)
treea12f781d2aa23d95d0c3b225c731c8e24fe60950 /c/src/exec/score/cpu
parent2002-04-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de> (diff)
downloadrtems-e80ac7f6c253169db44455b883783b134a469a51.tar.bz2
2002-04-18 Jay Monkman <jtm@smoothsmoothie.com>
* rtems/score/cpu.h (CPU_ISR_Disable and CPU_ISR_Enable): Correct them where they correctly inform the compiler about the register they are modifying.
Diffstat (limited to 'c/src/exec/score/cpu')
-rw-r--r--c/src/exec/score/cpu/arm/ChangeLog6
-rw-r--r--c/src/exec/score/cpu/arm/rtems/score/cpu.h14
2 files changed, 14 insertions, 6 deletions
diff --git a/c/src/exec/score/cpu/arm/ChangeLog b/c/src/exec/score/cpu/arm/ChangeLog
index 75f773c7e9..5714cdc740 100644
--- a/c/src/exec/score/cpu/arm/ChangeLog
+++ b/c/src/exec/score/cpu/arm/ChangeLog
@@ -1,3 +1,9 @@
+2002-04-18 Jay Monkman <jtm@smoothsmoothie.com>
+
+ * rtems/score/cpu.h (CPU_ISR_Disable and CPU_ISR_Enable): Correct them
+ where they correctly inform the compiler about the register they
+ are modifying.
+
2001-04-03 Joel Sherrill <joel@OARcorp.com>
* Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
diff --git a/c/src/exec/score/cpu/arm/rtems/score/cpu.h b/c/src/exec/score/cpu/arm/rtems/score/cpu.h
index ebe494504b..a626068e2c 100644
--- a/c/src/exec/score/cpu/arm/rtems/score/cpu.h
+++ b/c/src/exec/score/cpu/arm/rtems/score/cpu.h
@@ -540,9 +540,10 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
#define _CPU_ISR_Disable( _level ) \
{ \
(_level) = 0; \
- asm volatile ("MRS r0, cpsr \n" ); \
- asm volatile ("ORR r0, r0, #0xc0 \n" ); \
- asm volatile ("MSR cpsr, r0 \n" ); \
+ asm volatile ("MRS r0, cpsr \n" \
+ "ORR r0, r0, #0xc0 \n" \
+ "MSR cpsr, r0 \n" \
+ : : : "r0"); \
}
/*
@@ -553,9 +554,10 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
#define _CPU_ISR_Enable( _level ) \
{ \
- asm volatile ("MRS r0, cpsr \n" ); \
- asm volatile ("AND r0, r0, #0xFFFFFF3F \n" ); \
- asm volatile ("MSR cpsr, r0 \n" ); \
+ asm volatile ("MRS r0, cpsr \n" \
+ "AND r0, r0, #0xFFFFFF3F \n" \
+ "MSR cpsr, r0 \n" \
+ : : : "r0" ); \
}
/*