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authorJoel Sherrill <joel.sherrill@OARcorp.com>2000-11-21 14:03:17 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2000-11-21 14:03:17 +0000
commit669a6dc364abfbeaafc94b007a0cf639f9e55a0d (patch)
treeefe9db8e80fb6ac8cd8caf57109aa49493efe487 /c/src/exec/score/cpu/sparc
parent2000-11-21 Jiri Gaisler <jgais@ws.estec.esa.nl> (diff)
downloadrtems-669a6dc364abfbeaafc94b007a0cf639f9e55a0d.tar.bz2
2000-11-21 Jiri Gaisler <jgais@ws.estec.esa.nl>
* cpu_asm.S: Fix for CPUs with FPU revision B or C.
Diffstat (limited to 'c/src/exec/score/cpu/sparc')
-rw-r--r--c/src/exec/score/cpu/sparc/ChangeLog4
-rw-r--r--c/src/exec/score/cpu/sparc/cpu_asm.S13
2 files changed, 14 insertions, 3 deletions
diff --git a/c/src/exec/score/cpu/sparc/ChangeLog b/c/src/exec/score/cpu/sparc/ChangeLog
index 0c2efb42b0..296886878a 100644
--- a/c/src/exec/score/cpu/sparc/ChangeLog
+++ b/c/src/exec/score/cpu/sparc/ChangeLog
@@ -1,3 +1,7 @@
+2000-11-21 Jiri Gaisler <jgais@ws.estec.esa.nl>
+
+ * cpu_asm.S: Fix for CPUs with FPU revision B or C.
+
2000-11-14 Jiri Gaisler <jgais@ws.estec.esa.nl>
* cpu.c, rtems/cpu/sparc.h: Make floating point optional based
diff --git a/c/src/exec/score/cpu/sparc/cpu_asm.S b/c/src/exec/score/cpu/sparc/cpu_asm.S
index 20d686c330..e7c2cf68db 100644
--- a/c/src/exec/score/cpu/sparc/cpu_asm.S
+++ b/c/src/exec/score/cpu/sparc/cpu_asm.S
@@ -11,6 +11,13 @@
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
+ * Ported to ERC32 implementation of the SPARC by On-Line Applications
+ * Research Corporation (OAR) under contract to the European Space
+ * Agency (ESA).
+ *
+ * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
+ * European Space Agency.
+ *
* $Id$
*/
@@ -490,13 +497,14 @@ dont_switch_stacks:
* when the interrupt handler returns.
*/
+ mov %l0, %g5
+ and %l3, 0x0ff, %g4
+
/* This is a fix for ERC32 with FPU rev.B or rev.C */
#if defined(FPU_REVB)
- mov %l0, %g5
- and %l3, 0x0ff, %g4
subcc %g4, 0x08, %g0
be fpu_revb
subcc %g4, 0x11, %g0
@@ -555,7 +563,6 @@ __sparc_fq:
#else
- mov %l0, %g5
subcc %g4, 0x11, %g0
bl dont_fix_pil
subcc %g4, 0x1f, %g0