diff options
| author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2002-07-22 09:46:48 +0000 |
|---|---|---|
| committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2002-07-22 09:46:48 +0000 |
| commit | 2b3e9d9b244e279ef5693a7cf5dacc7903164af5 (patch) | |
| tree | 955e5242d4d08a8ec747c8350f55003bb9d4b519 /c/src/exec/score/cpu/sparc | |
| parent | Remove everything. (diff) | |
| download | rtems-2b3e9d9b244e279ef5693a7cf5dacc7903164af5.tar.bz2 | |
Remove, moved to cpukit.
Diffstat (limited to 'c/src/exec/score/cpu/sparc')
| -rw-r--r-- | c/src/exec/score/cpu/sparc/.cvsignore | 14 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sparc/ChangeLog | 143 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sparc/Makefile.am | 54 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sparc/README | 110 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sparc/asm.h | 123 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sparc/configure.ac | 30 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sparc/cpu.c | 331 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sparc/cpu_asm.S | 795 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sparc/rtems/.cvsignore | 2 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sparc/rtems/score/.cvsignore | 2 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sparc/rtems/score/cpu.h | 1000 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sparc/rtems/score/sparc.h | 266 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sparc/rtems/score/types.h | 56 |
13 files changed, 0 insertions, 2926 deletions
diff --git a/c/src/exec/score/cpu/sparc/.cvsignore b/c/src/exec/score/cpu/sparc/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/sparc/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/sparc/ChangeLog b/c/src/exec/score/cpu/sparc/ChangeLog deleted file mode 100644 index d672b28816..0000000000 --- a/c/src/exec/score/cpu/sparc/ChangeLog +++ /dev/null @@ -1,143 +0,0 @@ -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.S: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-04-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * cpu.c: Remove call to sparc_init_tbr/NO_TABLE_MOVE. - * rtems/score/cpu.h: Remove NO_TABLE_MOVE conditional code. - - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/sparctypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * cpu.c: Replace NO_TABLE_MOVE-support by external function - (code moved to libcpu/sparc/tbr/tbr.c). - * cpu.h: Replace NO_TABLE_MOVE-support by external function - (code moved to libcpu/sparc/tbr/tbr.h). - * sparc.h: Add sparc_init_tbr (implemented in libcpu/sparc/tbr/tbr.c). - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2002-01-31 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Reflect 2002-01-23 changes. - -2001-01-30 Joel Sherrill <joel@OARcorp.com> - - * Makefile.am: Corrected so .h files from rtems/score/ are installed. - -2002-01-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-27 Jiri Gaisler <jiri@gaisler.com> - - * cpu_asm.S: Small patch to fix a bug in the rtems sparc port. The - bug has been there all the time, but only hits the leon bsp since the - leon cpu has a 5-stage pipeline (erc32 has 4 stages). - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - * cpu_asm.S: Modify to properly dereference _ISR_Vector_table - now that it is dynamically allocated. - -2000-12-06 Joel Sherrill <joel@OARcorp.com> - - * cpu.c: Added include of <rtems/rtems/cache.h> to eliminate warning. - -2000-11-21 Jiri Gaisler <jgais@ws.estec.esa.nl> - - * cpu_asm.S: Fix for CPUs with FPU revision B or C. - -2000-11-14 Jiri Gaisler <jgais@ws.estec.esa.nl> - - * cpu.c, rtems/cpu/sparc.h: Make floating point optional based - on gcc arguments. Do not initialize FP context if there is - no FPU. Flush instruction cache after installing RTEMS trap handler. - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/sparc/Makefile.am b/c/src/exec/score/cpu/sparc/Makefile.am deleted file mode 100644 index 68153cba62..0000000000 --- a/c/src/exec/score/cpu/sparc/Makefile.am +++ /dev/null @@ -1,54 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS= asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/sparc.h \ - rtems/score/cpu.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/sparc/README b/c/src/exec/score/cpu/sparc/README deleted file mode 100644 index c4c2200075..0000000000 --- a/c/src/exec/score/cpu/sparc/README +++ /dev/null @@ -1,110 +0,0 @@ -# -# $Id$ -# - -This file discusses SPARC specific issues which are important to -this port. The primary topics in this file are: - - + Global Register Usage - + Stack Frame - + EF bit in the PSR - - -Global Register Usage -===================== - -This information on register usage is based heavily on a comment in the -file gcc-2.7.0/config/sparc/sparc.h in the the gcc 2.7.0 source. - - + g0 is hardwired to 0 - + On non-v9 systems: - - g1 is free to use as temporary. - - g2-g4 are reserved for applications. Gcc normally uses them as - temporaries, but this can be disabled via the -mno-app-regs option. - - g5 through g7 are reserved for the operating system. - + On v9 systems: - - g1 and g5 are free to use as temporaries. - - g2-g4 are reserved for applications (the compiler will not normally use - them, but they can be used as temporaries with -mapp-regs). - - g6-g7 are reserved for the operating system. - - NOTE: As of gcc 2.7.0 register g1 was used in the following scenarios: - - + as a temporary by the 64 bit sethi pattern - + when restoring call-preserved registers in large stack frames - -RTEMS places no constraints on the usage of the global registers. Although -gcc assumes that either g5-g7 (non-V9) or g6-g7 (V9) are reserved for the -operating system, RTEMS does not assume any special use for them. - - - -Stack Frame -=========== - -The stack grows downward (i.e. to lower addresses) on the SPARC architecture. - -The following is the organization of the stack frame: - - - - | ............... | - fp | | - +-------------------------------+ - | | - | Local registers, temporaries, | - | and saved floats | x bytes - | | - sp + x +-------------------------------+ - | | - | outgoing parameters past | - | the sixth one | x bytes - | | - sp + 92 +-------------------------------+ * - | | * - | area for callee to save | * - | register arguments | * 24 bytes - | | * - sp + 68 +-------------------------------+ * - | | * - | structure return pointer | * 4 bytes - | | * - sp + 64 +-------------------------------+ * - | | * - | local register set | * 32 bytes - | | * - sp + 32 +-------------------------------+ * - | | * - | input register set | * 32 bytes - | | * - sp +-------------------------------+ * - - -* = minimal stack frame - -x = optional components - -EF bit in the PSR -================= - -The EF (enable floating point unit) in the PSR is utilized in this port to -prevent non-floating point tasks from performing floating point -operations. This bit is maintained as part of the integer context. -However, the floating point context is switched BEFORE the integer -context. Thus the EF bit in place at the time of the FP switch may -indicate that FP operations are disabled. This occurs on certain task -switches, when the EF bit will be 0 for the outgoing task and thus a fault -will be generated on the first FP operation of the FP context save. - -The remedy for this is to enable FP access as the first step in both the -save and restore of the FP context area. This bit will be subsequently -reloaded by the integer context switch. - -Two of the scenarios which demonstrate this problem are outlined below: - -1. When the first FP task is switched to. The system tasks are not FP and -thus would be unable to restore the FP context of the incoming task. - -2. On a deferred FP context switch. In this case, the system might switch -from FP Task A to non-FP Task B and then to FP Task C. In this scenario, -the floating point state must technically be saved by a non-FP task. diff --git a/c/src/exec/score/cpu/sparc/asm.h b/c/src/exec/score/cpu/sparc/asm.h deleted file mode 100644 index c89f19e050..0000000000 --- a/c/src/exec/score/cpu/sparc/asm.h +++ /dev/null @@ -1,123 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. - * - * $Id$ - */ - -#ifndef __SPARC_ASM_h -#define __SPARC_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif - -#include <rtems/score/cpuopts.h> -#include <rtems/score/cpu.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */ -/* XXX The following ifdef magic fixes the problem but results in a warning */ -/* XXX when compiling assembly code. */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -/* - * Entry for traps which jump to a programmer-specified trap handler. - */ - -#define TRAP(_vector, _handler) \ - mov %psr, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - mov _vector, %l3 - -/* - * Used for the reset trap to avoid a supervisor instruction - */ - -#define RTRAP(_vector, _handler) \ - mov %g0, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - mov _vector, %l3 - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/sparc/configure.ac b/c/src/exec/score/cpu/sparc/configure.ac deleted file mode 100644 index bfd62c0c70..0000000000 --- a/c/src/exec/score/cpu/sparc/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-sparc],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/sparc/cpu.c b/c/src/exec/score/cpu/sparc/cpu.c deleted file mode 100644 index 7fb8d58bc1..0000000000 --- a/c/src/exec/score/cpu/sparc/cpu.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * SPARC Dependent Source - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/rtems/cache.h> - -/* - * This initializes the set of opcodes placed in each trap - * table entry. The routine which installs a handler is responsible - * for filling in the fields for the _handler address and the _vector - * trap type. - * - * The constants following this structure are masks for the fields which - * must be filled in when the handler is installed. - */ - -const CPU_Trap_table_entry _CPU_Trap_slot_template = { - 0xa1480000, /* mov %psr, %l0 */ - 0x29000000, /* sethi %hi(_handler), %l4 */ - 0x81c52000, /* jmp %l4 + %lo(_handler) */ - 0xa6102000 /* mov _vector, %l3 */ -}; - -/*PAGE - * - * _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * Input Parameters: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - * - * Output Parameters: NONE - * - * NOTE: There is no need to save the pointer to the thread dispatch routine. - * The SPARC's assembly code can reference it directly with no problems. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - void *pointer; - -#if (SPARC_HAS_FPU == 1) - - /* - * This seems to be the most appropriate way to obtain an initial - * FP context on the SPARC. The NULL fp context is copied it to - * the task's FP context during Context_Initialize. - */ - - pointer = &_CPU_Null_fp_context; - _CPU_Context_save_fp( &pointer ); -#endif - - /* - * Grab our own copy of the user's CPU table. - */ - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * Input Parameters: NONE - * - * Output Parameters: - * returns the current interrupt level (PIL field of the PSR) - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 level; - - sparc_get_interrupt_level( level ); - - return level; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * This routine installs the specified handler as a "raw" non-executive - * supported trap handler (a.k.a. interrupt service routine). - * - * Input Parameters: - * vector - trap table entry number plus synchronous - * vs. asynchronous information - * new_handler - address of the handler to be installed - * old_handler - pointer to an address of the handler previously installed - * - * Output Parameters: NONE - * *new_handler - address of the handler previously installed - * - * NOTE: - * - * On the SPARC, there are really only 256 vectors. However, the executive - * has no easy, fast, reliable way to determine which traps are synchronous - * and which are asynchronous. By default, synchronous traps return to the - * instruction which caused the interrupt. So if you install a software - * trap handler as an executive interrupt handler (which is desirable since - * RTEMS takes care of window and register issues), then the executive needs - * to know that the return address is to the trap rather than the instruction - * following the trap. - * - * So vectors 0 through 255 are treated as regular asynchronous traps which - * provide the "correct" return address. Vectors 256 through 512 are assumed - * by the executive to be synchronous and to require that the return address - * be fudged. - * - * If you use this mechanism to install a trap handler which must reexecute - * the instruction which caused the trap, then it should be installed as - * an asynchronous trap. This will avoid the executive changing the return - * address. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - unsigned32 real_vector; - CPU_Trap_table_entry *tbr; - CPU_Trap_table_entry *slot; - unsigned32 u32_tbr; - unsigned32 u32_handler; - - /* - * Get the "real" trap number for this vector ignoring the synchronous - * versus asynchronous indicator included with our vector numbers. - */ - - real_vector = SPARC_REAL_TRAP_NUMBER( vector ); - - /* - * Get the current base address of the trap table and calculate a pointer - * to the slot we are interested in. - */ - - sparc_get_tbr( u32_tbr ); - - u32_tbr &= 0xfffff000; - - tbr = (CPU_Trap_table_entry *) u32_tbr; - - slot = &tbr[ real_vector ]; - - /* - * Get the address of the old_handler from the trap table. - * - * NOTE: The old_handler returned will be bogus if it does not follow - * the RTEMS model. - */ - -#define HIGH_BITS_MASK 0xFFFFFC00 -#define HIGH_BITS_SHIFT 10 -#define LOW_BITS_MASK 0x000003FF - - if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) { - u32_handler = - ((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) | - (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK); - *old_handler = (proc_ptr) u32_handler; - } else - *old_handler = 0; - - /* - * Copy the template to the slot and then fix it. - */ - - *slot = _CPU_Trap_slot_template; - - u32_handler = (unsigned32) new_handler; - - slot->mov_vector_l3 |= vector; - slot->sethi_of_handler_to_l4 |= - (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT; - slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK); - - /* need to flush icache after this !!! */ - - rtems_cache_invalidate_entire_instruction(); - -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * new_handler - replacement ISR for this vector number - * old_handler - pointer to former ISR for this vector number - * - * Output parameters: - * *old_handler - former ISR for this vector number - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - unsigned32 real_vector; - proc_ptr ignored; - - /* - * Get the "real" trap number for this vector ignoring the synchronous - * versus asynchronous indicator included with our vector numbers. - */ - - real_vector = SPARC_REAL_TRAP_NUMBER( vector ); - - /* - * Return the previous ISR handler. - */ - - *old_handler = _ISR_Vector_table[ real_vector ]; - - /* - * Install the wrapper so this ISR can be invoked properly. - */ - - _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ real_vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Context_Initialize - * - * This kernel routine initializes the basic non-FP context area associated - * with each thread. - * - * Input parameters: - * the_context - pointer to the context area - * stack_base - address of memory for the SPARC - * size - size in bytes of the stack area - * new_level - interrupt level for this context area - * entry_point - the starting execution point for this this context - * is_fp - TRUE if this context is associated with an FP thread - * - * Output parameters: NONE - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - unsigned32 *stack_base, - unsigned32 size, - unsigned32 new_level, - void *entry_point, - boolean is_fp -) -{ - unsigned32 stack_high; /* highest "stack aligned" address */ - unsigned32 the_size; - unsigned32 tmp_psr; - - /* - * On CPUs with stacks which grow down (i.e. SPARC), we build the stack - * based on the stack_high address. - */ - - stack_high = ((unsigned32)(stack_base) + size); - stack_high &= ~(CPU_STACK_ALIGNMENT - 1); - - the_size = size & ~(CPU_STACK_ALIGNMENT - 1); - - /* - * See the README in this directory for a diagram of the stack. - */ - - the_context->o7 = ((unsigned32) entry_point) - 8; - the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE; - the_context->i6_fp = stack_high; - - /* - * Build the PSR for the task. Most everything can be 0 and the - * CWP is corrected during the context switch. - * - * The EF bit determines if the floating point unit is available. - * The FPU is ONLY enabled if the context is associated with an FP task - * and this SPARC model has an FPU. - */ - - sparc_get_psr( tmp_psr ); - tmp_psr &= ~SPARC_PSR_PIL_MASK; - tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; - tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ - -#if (SPARC_HAS_FPU == 1) - /* - * If this bit is not set, then a task gets a fault when it accesses - * a floating point register. This is a nice way to detect floating - * point tasks which are not currently declared as such. - */ - - if ( is_fp ) - tmp_psr |= SPARC_PSR_EF_MASK; -#endif - the_context->psr = tmp_psr; -} diff --git a/c/src/exec/score/cpu/sparc/cpu_asm.S b/c/src/exec/score/cpu/sparc/cpu_asm.S deleted file mode 100644 index b5ef4ebf69..0000000000 --- a/c/src/exec/score/cpu/sparc/cpu_asm.S +++ /dev/null @@ -1,795 +0,0 @@ -/* cpu_asm.s - * - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Ported to ERC32 implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - * - * $Id$ - */ - -#include <asm.h> - -#if (SPARC_HAS_FPU == 1) - -/* - * void _CPU_Context_save_fp( - * void **fp_context_ptr - * ) - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * NOTE: See the README in this directory for information on the - * management of the "EF" bit in the PSR. - */ - - .align 4 - PUBLIC(_CPU_Context_save_fp) -SYM(_CPU_Context_save_fp): - save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp - - /* - * The following enables the floating point unit. - */ - - mov %psr, %l0 - sethi %hi(SPARC_PSR_EF_MASK), %l1 - or %l1, %lo(SPARC_PSR_EF_MASK), %l1 - or %l0, %l1, %l0 - mov %l0, %psr ! **** ENABLE FLOAT ACCESS **** - nop; nop; nop; ! Need three nops before EF is - ld [%i0], %l0 ! active due to pipeline delay!!! - std %f0, [%l0 + FO_F1_OFFSET] - std %f2, [%l0 + F2_F3_OFFSET] - std %f4, [%l0 + F4_F5_OFFSET] - std %f6, [%l0 + F6_F7_OFFSET] - std %f8, [%l0 + F8_F9_OFFSET] - std %f10, [%l0 + F1O_F11_OFFSET] - std %f12, [%l0 + F12_F13_OFFSET] - std %f14, [%l0 + F14_F15_OFFSET] - std %f16, [%l0 + F16_F17_OFFSET] - std %f18, [%l0 + F18_F19_OFFSET] - std %f20, [%l0 + F2O_F21_OFFSET] - std %f22, [%l0 + F22_F23_OFFSET] - std %f24, [%l0 + F24_F25_OFFSET] - std %f26, [%l0 + F26_F27_OFFSET] - std %f28, [%l0 + F28_F29_OFFSET] - std %f30, [%l0 + F3O_F31_OFFSET] - st %fsr, [%l0 + FSR_OFFSET] - ret - restore - -/* - * void _CPU_Context_restore_fp( - * void **fp_context_ptr - * ) - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * NOTE: See the README in this directory for information on the - * management of the "EF" bit in the PSR. - */ - - .align 4 - PUBLIC(_CPU_Context_restore_fp) -SYM(_CPU_Context_restore_fp): - save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE , %sp - - /* - * The following enables the floating point unit. - */ - - mov %psr, %l0 - sethi %hi(SPARC_PSR_EF_MASK), %l1 - or %l1, %lo(SPARC_PSR_EF_MASK), %l1 - or %l0, %l1, %l0 - mov %l0, %psr ! **** ENABLE FLOAT ACCESS **** - nop; nop; nop; ! Need three nops before EF is - ld [%i0], %l0 ! active due to pipeline delay!!! - ldd [%l0 + FO_F1_OFFSET], %f0 - ldd [%l0 + F2_F3_OFFSET], %f2 - ldd [%l0 + F4_F5_OFFSET], %f4 - ldd [%l0 + F6_F7_OFFSET], %f6 - ldd [%l0 + F8_F9_OFFSET], %f8 - ldd [%l0 + F1O_F11_OFFSET], %f10 - ldd [%l0 + F12_F13_OFFSET], %f12 - ldd [%l0 + F14_F15_OFFSET], %f14 - ldd [%l0 + F16_F17_OFFSET], %f16 - ldd [%l0 + F18_F19_OFFSET], %f18 - ldd [%l0 + F2O_F21_OFFSET], %f20 - ldd [%l0 + F22_F23_OFFSET], %f22 - ldd [%l0 + F24_F25_OFFSET], %f24 - ldd [%l0 + F26_F27_OFFSET], %f26 - ldd [%l0 + F28_F29_OFFSET], %f28 - ldd [%l0 + F3O_F31_OFFSET], %f30 - ld [%l0 + FSR_OFFSET], %fsr - ret - restore - -#endif /* SPARC_HAS_FPU */ - -/* - * void _CPU_Context_switch( - * Context_Control *run, - * Context_Control *heir - * ) - * - * This routine performs a normal non-FP context switch. - */ - - .align 4 - PUBLIC(_CPU_Context_switch) -SYM(_CPU_Context_switch): - ! skip g0 - st %g1, [%o0 + G1_OFFSET] ! save the global registers - std %g2, [%o0 + G2_OFFSET] - std %g4, [%o0 + G4_OFFSET] - std %g6, [%o0 + G6_OFFSET] - - std %l0, [%o0 + L0_OFFSET] ! save the local registers - std %l2, [%o0 + L2_OFFSET] - std %l4, [%o0 + L4_OFFSET] - std %l6, [%o0 + L6_OFFSET] - - std %i0, [%o0 + I0_OFFSET] ! save the input registers - std %i2, [%o0 + I2_OFFSET] - std %i4, [%o0 + I4_OFFSET] - std %i6, [%o0 + I6_FP_OFFSET] - - std %o0, [%o0 + O0_OFFSET] ! save the output registers - std %o2, [%o0 + O2_OFFSET] - std %o4, [%o0 + O4_OFFSET] - std %o6, [%o0 + O6_SP_OFFSET] - - rd %psr, %o2 - st %o2, [%o0 + PSR_OFFSET] ! save status register - - /* - * This is entered from _CPU_Context_restore with: - * o1 = context to restore - * o2 = psr - */ - - PUBLIC(_CPU_Context_restore_heir) -SYM(_CPU_Context_restore_heir): - /* - * Flush all windows with valid contents except the current one. - * In examining the set register windows, one may logically divide - * the windows into sets (some of which may be empty) based on their - * current status: - * - * + current (i.e. in use), - * + used (i.e. a restore would not trap) - * + invalid (i.e. 1 in corresponding bit in WIM) - * + unused - * - * Either the used or unused set of windows may be empty. - * - * NOTE: We assume only one bit is set in the WIM at a time. - * - * Given a CWP of 5 and a WIM of 0x1, the registers are divided - * into sets as follows: - * - * + 0 - invalid - * + 1-4 - unused - * + 5 - current - * + 6-7 - used - * - * In this case, we only would save the used windows -- 6 and 7. - * - * Traps are disabled for the same logical period as in a - * flush all windows trap handler. - * - * Register Usage while saving the windows: - * g1 = current PSR - * g2 = current wim - * g3 = CWP - * g4 = wim scratch - * g5 = scratch - */ - - ld [%o1 + PSR_OFFSET], %g1 ! g1 = saved psr - - and %o2, SPARC_PSR_CWP_MASK, %g3 ! g3 = CWP - ! g1 = psr w/o cwp - andn %g1, SPARC_PSR_ET_MASK | SPARC_PSR_CWP_MASK, %g1 - or %g1, %g3, %g1 ! g1 = heirs psr - mov %g1, %psr ! restore status register and - ! **** DISABLE TRAPS **** - mov %wim, %g2 ! g2 = wim - mov 1, %g4 - sll %g4, %g3, %g4 ! g4 = WIM mask for CW invalid - -save_frame_loop: - sll %g4, 1, %g5 ! rotate the "wim" left 1 - srl %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4 - or %g4, %g5, %g4 ! g4 = wim if we do one restore - - /* - * If a restore would not underflow, then continue. - */ - - andcc %g4, %g2, %g0 ! Any windows to flush? - bnz done_flushing ! No, then continue - nop - - restore ! back one window - - /* - * Now save the window just as if we overflowed to it. - */ - - std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET] - std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET] - std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET] - std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET] - - std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET] - std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET] - std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET] - std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET] - - ba save_frame_loop - nop - -done_flushing: - - add %g3, 1, %g3 ! calculate desired WIM - and %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3 - mov 1, %g4 - sll %g4, %g3, %g4 ! g4 = new WIM - mov %g4, %wim - - or %g1, SPARC_PSR_ET_MASK, %g1 - mov %g1, %psr ! **** ENABLE TRAPS **** - ! and restore CWP - nop - nop - nop - - ! skip g0 - ld [%o1 + G1_OFFSET], %g1 ! restore the global registers - ldd [%o1 + G2_OFFSET], %g2 - ldd [%o1 + G4_OFFSET], %g4 - ldd [%o1 + G6_OFFSET], %g6 - - ldd [%o1 + L0_OFFSET], %l0 ! restore the local registers - ldd [%o1 + L2_OFFSET], %l2 - ldd [%o1 + L4_OFFSET], %l4 - ldd [%o1 + L6_OFFSET], %l6 - - ldd [%o1 + I0_OFFSET], %i0 ! restore the output registers - ldd [%o1 + I2_OFFSET], %i2 - ldd [%o1 + I4_OFFSET], %i4 - ldd [%o1 + I6_FP_OFFSET], %i6 - - ldd [%o1 + O2_OFFSET], %o2 ! restore the output registers - ldd [%o1 + O4_OFFSET], %o4 - ldd [%o1 + O6_SP_OFFSET], %o6 - ! do o0/o1 last to avoid destroying heir context pointer - ldd [%o1 + O0_OFFSET], %o0 ! overwrite heir pointer - - jmp %o7 + 8 ! return - nop ! delay slot - -/* - * void _CPU_Context_restore( - * Context_Control *new_context - * ) - * - * This routine is generally used only to perform restart self. - * - * NOTE: It is unnecessary to reload some registers. - */ - - .align 4 - PUBLIC(_CPU_Context_restore) -SYM(_CPU_Context_restore): - save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp - rd %psr, %o2 - ba SYM(_CPU_Context_restore_heir) - mov %i0, %o1 ! in the delay slot - -/* - * void _ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - * We enter this handler from the 4 instructions in the trap table with - * the following registers assumed to be set as shown: - * - * l0 = PSR - * l1 = PC - * l2 = nPC - * l3 = trap type - * - * NOTE: By an executive defined convention, trap type is between 0 and 255 if - * it is an asynchonous trap and 256 and 511 if it is synchronous. - */ - - .align 4 - PUBLIC(_ISR_Handler) -SYM(_ISR_Handler): - /* - * Fix the return address for synchronous traps. - */ - - andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0 - ! Is this a synchronous trap? - be,a win_ovflow ! No, then skip the adjustment - nop ! DELAY - mov %l1, %l6 ! save trapped pc for debug info - mov %l2, %l1 ! do not return to the instruction - add %l2, 4, %l2 ! indicated - -win_ovflow: - /* - * Save the globals this block uses. - * - * These registers are not restored from the locals. Their contents - * are saved directly from the locals into the ISF below. - */ - - mov %g4, %l4 ! save the globals this block uses - mov %g5, %l5 - - /* - * When at a "window overflow" trap, (wim == (1 << cwp)). - * If we get here like that, then process a window overflow. - */ - - rd %wim, %g4 - srl %g4, %l0, %g5 ! g5 = win >> cwp ; shift count and CWP - ! are LS 5 bits ; how convenient :) - cmp %g5, 1 ! Is this an invalid window? - bne dont_do_the_window ! No, then skip all this stuff - ! we are using the delay slot - - /* - * The following is same as a 1 position right rotate of WIM - */ - - srl %g4, 1, %g5 ! g5 = WIM >> 1 - sll %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4 - ! g4 = WIM << (Number Windows - 1) - or %g4, %g5, %g4 ! g4 = (WIM >> 1) | - ! (WIM << (Number Windows - 1)) - - /* - * At this point: - * - * g4 = the new WIM - * g5 is free - */ - - /* - * Since we are tinkering with the register windows, we need to - * make sure that all the required information is in global registers. - */ - - save ! Save into the window - wr %g4, 0, %wim ! WIM = new WIM - nop ! delay slots - nop - nop - - /* - * Now save the window just as if we overflowed to it. - */ - - std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET] - std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET] - std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET] - std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET] - - std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET] - std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET] - std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET] - std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET] - - restore - nop - -dont_do_the_window: - /* - * Global registers %g4 and %g5 are saved directly from %l4 and - * %l5 directly into the ISF below. - */ - -save_isf: - - /* - * Save the state of the interrupted task -- especially the global - * registers -- in the Interrupt Stack Frame. Note that the ISF - * includes a regular minimum stack frame which will be used if - * needed by register window overflow and underflow handlers. - * - * REGISTERS SAME AS AT _ISR_Handler - */ - - sub %fp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp - ! make space for ISF - - std %l0, [%sp + ISF_PSR_OFFSET] ! save psr, PC - st %l2, [%sp + ISF_NPC_OFFSET] ! save nPC - st %g1, [%sp + ISF_G1_OFFSET] ! save g1 - std %g2, [%sp + ISF_G2_OFFSET] ! save g2, g3 - std %l4, [%sp + ISF_G4_OFFSET] ! save g4, g5 -- see above - std %g6, [%sp + ISF_G6_OFFSET] ! save g6, g7 - - std %i0, [%sp + ISF_I0_OFFSET] ! save i0, i1 - std %i2, [%sp + ISF_I2_OFFSET] ! save i2, i3 - std %i4, [%sp + ISF_I4_OFFSET] ! save i4, i5 - std %i6, [%sp + ISF_I6_FP_OFFSET] ! save i6/fp, i7 - - rd %y, %g1 - st %g1, [%sp + ISF_Y_OFFSET] ! save y - st %l6, [%sp + ISF_TPC_OFFSET] ! save real trapped pc - - mov %sp, %o1 ! 2nd arg to ISR Handler - - /* - * Increment ISR nest level and Thread dispatch disable level. - * - * Register usage for this section: - * - * l4 = _Thread_Dispatch_disable_level pointer - * l5 = _ISR_Nest_level pointer - * l6 = _Thread_Dispatch_disable_level value - * l7 = _ISR_Nest_level value - * - * NOTE: It is assumed that l4 - l7 will be preserved until the ISR - * nest and thread dispatch disable levels are unnested. - */ - - sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4 - ld [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6 - sethi %hi(SYM(_ISR_Nest_level)), %l5 - ld [%l5 + %lo(SYM(_ISR_Nest_level))], %l7 - - add %l6, 1, %l6 - st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))] - - add %l7, 1, %l7 - st %l7, [%l5 + %lo(SYM(_ISR_Nest_level))] - - /* - * If ISR nest level was zero (now 1), then switch stack. - */ - - mov %sp, %fp - subcc %l7, 1, %l7 ! outermost interrupt handler? - bnz dont_switch_stacks ! No, then do not switch stacks - - sethi %hi(SYM(_CPU_Interrupt_stack_high)), %g4 - ld [%g4 + %lo(SYM(_CPU_Interrupt_stack_high))], %sp - -dont_switch_stacks: - /* - * Make sure we have a place on the stack for the window overflow - * trap handler to write into. At this point it is safe to - * enable traps again. - */ - - sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp - - /* - * Check if we have an external interrupt (trap 0x11 - 0x1f). If so, - * set the PIL in the %psr to mask off interrupts with lower priority. - * The original %psr in %l0 is not modified since it will be restored - * when the interrupt handler returns. - */ - - mov %l0, %g5 - and %l3, 0x0ff, %g4 - -/* This is a fix for ERC32 with FPU rev.B or rev.C */ - -#if defined(FPU_REVB) - - - subcc %g4, 0x08, %g0 - be fpu_revb - subcc %g4, 0x11, %g0 - bl dont_fix_pil - subcc %g4, 0x1f, %g0 - bg dont_fix_pil - sll %g4, 8, %g4 - and %g4, SPARC_PSR_PIL_MASK, %g4 - andn %l0, SPARC_PSR_PIL_MASK, %g5 - or %g4, %g5, %g5 - srl %l0, 12, %g4 - andcc %g4, 1, %g0 - be dont_fix_pil - nop - ba,a enable_irq - - -fpu_revb: - srl %l0, 12, %g4 ! check if EF is set in %psr - andcc %g4, 1, %g0 - be dont_fix_pil ! if FPU disabled than continue as normal - and %l3, 0xff, %g4 - subcc %g4, 0x08, %g0 - bne enable_irq ! if not a FPU exception then do two fmovs - set __sparc_fq, %g4 - st %fsr, [%g4] ! if FQ is not empty and FQ[1] = fmovs - ld [%g4], %g4 ! than this is bug 3.14 - srl %g4, 13, %g4 - andcc %g4, 1, %g0 - be dont_fix_pil - set __sparc_fq, %g4 - std %fq, [%g4] - ld [%g4+4], %g4 - set 0x81a00020, %g5 - subcc %g4, %g5, %g0 - bne,a dont_fix_pil2 - wr %l0, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** - ba,a simple_return - -enable_irq: - or %g5, SPARC_PSR_PIL_MASK, %g4 - wr %g4, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** - nop; nop; nop - fmovs %f0, %f0 - ba dont_fix_pil - fmovs %f0, %f0 - - .data - .global __sparc_fq - .align 8 -__sparc_fq: - .word 0,0 - - .text -/* end of ERC32 FPU rev.B/C fix */ - -#else - - subcc %g4, 0x11, %g0 - bl dont_fix_pil - subcc %g4, 0x1f, %g0 - bg dont_fix_pil - sll %g4, 8, %g4 - and %g4, SPARC_PSR_PIL_MASK, %g4 - andn %l0, SPARC_PSR_PIL_MASK, %g5 - or %g4, %g5, %g5 -#endif - -dont_fix_pil: - wr %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** -dont_fix_pil2: - - /* - * Vector to user's handler. - * - * NOTE: TBR may no longer have vector number in it since - * we just enabled traps. It is definitely in l3. - */ - - sethi %hi(SYM(_ISR_Vector_table)), %g4 - ld [%g4+%lo(SYM(_ISR_Vector_table))], %g4 - and %l3, 0xFF, %g5 ! remove synchronous trap indicator - sll %g5, 2, %g5 ! g5 = offset into table - ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ] - - - ! o1 = 2nd arg = address of the ISF - ! WAS LOADED WHEN ISF WAS SAVED!!! - mov %l3, %o0 ! o0 = 1st arg = vector number - call %g4, 0 - nop ! delay slot - - /* - * Redisable traps so we can finish up the interrupt processing. - * This is a VERY conservative place to do this. - * - * NOTE: %l0 has the PSR which was in place when we took the trap. - */ - - mov %l0, %psr ! **** DISABLE TRAPS **** - - /* - * Decrement ISR nest level and Thread dispatch disable level. - * - * Register usage for this section: - * - * l4 = _Thread_Dispatch_disable_level pointer - * l5 = _ISR_Nest_level pointer - * l6 = _Thread_Dispatch_disable_level value - * l7 = _ISR_Nest_level value - */ - - sub %l6, 1, %l6 - st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))] - - st %l7, [%l5 + %lo(SYM(_ISR_Nest_level))] - - /* - * If dispatching is disabled (includes nested interrupt case), - * then do a "simple" exit. - */ - - orcc %l6, %g0, %g0 ! Is dispatching disabled? - bnz simple_return ! Yes, then do a "simple" exit - nop ! delay slot - - /* - * If a context switch is necessary, then do fudge stack to - * return to the interrupt dispatcher. - */ - - sethi %hi(SYM(_Context_Switch_necessary)), %l4 - ld [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5 - - orcc %l5, %g0, %g0 ! Is thread switch necessary? - bnz SYM(_ISR_Dispatch) ! yes, then invoke the dispatcher - nop ! delay slot - - /* - * Finally, check to see if signals were sent to the currently - * executing task. If so, we need to invoke the interrupt dispatcher. - */ - - sethi %hi(SYM(_ISR_Signals_to_thread_executing)), %l6 - ld [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7 - - orcc %l7, %g0, %g0 ! Were signals sent to the currently - ! executing thread? - bz simple_return ! yes, then invoke the dispatcher - ! use the delay slot to clear the signals - ! to the currently executing task flag - st %g0, [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))] - - - /* - * Invoke interrupt dispatcher. - */ - - PUBLIC(_ISR_Dispatch) -SYM(_ISR_Dispatch): - - /* - * The following subtract should get us back on the interrupted - * tasks stack and add enough room to invoke the dispatcher. - * When we enable traps, we are mostly back in the context - * of the task and subsequent interrupts can operate normally. - */ - - sub %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp - - or %l0, SPARC_PSR_ET_MASK, %l7 ! l7 = PSR with ET=1 - mov %l7, %psr ! **** ENABLE TRAPS **** - nop - nop - nop - - call SYM(_Thread_Dispatch), 0 - nop - - /* - * The CWP in place at this point may be different from - * that which was in effect at the beginning of the ISR if we - * have been context switched between the beginning of this invocation - * of _ISR_Handler and this point. Thus the CWP and WIM should - * not be changed back to their values at ISR entry time. Any - * changes to the PSR must preserve the CWP. - */ - -simple_return: - ld [%fp + ISF_Y_OFFSET], %l5 ! restore y - wr %l5, 0, %y - - ldd [%fp + ISF_PSR_OFFSET], %l0 ! restore psr, PC - ld [%fp + ISF_NPC_OFFSET], %l2 ! restore nPC - rd %psr, %l3 - and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP - andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task - or %l3, %l0, %l0 ! install it later... - andn %l0, SPARC_PSR_ET_MASK, %l0 - - /* - * Restore tasks global and out registers - */ - - mov %fp, %g1 - - ! g1 is restored later - ldd [%fp + ISF_G2_OFFSET], %g2 ! restore g2, g3 - ldd [%fp + ISF_G4_OFFSET], %g4 ! restore g4, g5 - ldd [%fp + ISF_G6_OFFSET], %g6 ! restore g6, g7 - - ldd [%fp + ISF_I0_OFFSET], %i0 ! restore i0, i1 - ldd [%fp + ISF_I2_OFFSET], %i2 ! restore i2, i3 - ldd [%fp + ISF_I4_OFFSET], %i4 ! restore i4, i5 - ldd [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7 - - /* - * Registers: - * - * ALL global registers EXCEPT G1 and the input registers have - * already been restored and thuse off limits. - * - * The following is the contents of the local registers: - * - * l0 = original psr - * l1 = return address (i.e. PC) - * l2 = nPC - * l3 = CWP - */ - - /* - * if (CWP + 1) is an invalid window then we need to reload it. - * - * WARNING: Traps should now be disabled - */ - - mov %l0, %psr ! **** DISABLE TRAPS **** - nop - nop - nop - rd %wim, %l4 - add %l0, 1, %l6 ! l6 = cwp + 1 - and %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it - srl %l4, %l6, %l5 ! l5 = win >> cwp + 1 ; shift count - ! and CWP are conveniently LS 5 bits - cmp %l5, 1 ! Is tasks window invalid? - bne good_task_window - - /* - * The following code is the same as a 1 position left rotate of WIM. - */ - - sll %l4, 1, %l5 ! l5 = WIM << 1 - srl %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4 - ! l4 = WIM >> (Number Windows - 1) - or %l4, %l5, %l4 ! l4 = (WIM << 1) | - ! (WIM >> (Number Windows - 1)) - - /* - * Now restore the window just as if we underflowed to it. - */ - - wr %l4, 0, %wim ! WIM = new WIM - nop ! must delay after writing WIM - nop - nop - restore ! now into the tasks window - - ldd [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0 - ldd [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2 - ldd [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4 - ldd [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6 - ldd [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0 - ldd [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2 - ldd [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4 - ldd [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6 - ! reload of sp clobbers ISF - save ! Back to ISR dispatch window - -good_task_window: - - mov %l0, %psr ! **** DISABLE TRAPS **** - ! and restore condition codes. - ld [%g1 + ISF_G1_OFFSET], %g1 ! restore g1 - jmp %l1 ! transfer control and - rett %l2 ! go back to tasks window - -/* end of file */ diff --git a/c/src/exec/score/cpu/sparc/rtems/.cvsignore b/c/src/exec/score/cpu/sparc/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/sparc/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/sparc/rtems/score/.cvsignore b/c/src/exec/score/cpu/sparc/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/sparc/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/sparc/rtems/score/cpu.h b/c/src/exec/score/cpu/sparc/rtems/score/cpu.h deleted file mode 100644 index 3194c07f3b..0000000000 --- a/c/src/exec/score/cpu/sparc/rtems/score/cpu.h +++ /dev/null @@ -1,1000 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the port of - * the executive to the SPARC processor. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/sparc.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * This parameter could go either way on the SPARC. The interrupt flash - * code is relatively lengthy given the requirements for nops following - * writes to the psr. But if the clock speed were high enough, this would - * not represent a great deal of time. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does the executive manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * The SPARC does not have a dedicated HW interrupt stack and one has - * been implemented in SW. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * The SPARC does not have a dedicated HW interrupt stack. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Do we allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the FLOATING_POINT task attribute is supported. - * If FALSE, then the FLOATING_POINT task attribute is ignored. - */ - -#if ( SPARC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks FLOATING_POINT tasks implicitly? - * - * If TRUE, then the FLOATING_POINT task attribute is assumed. - * If FALSE, then the FLOATING_POINT task attribute is followed. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * The stack grows to lower addresses on the SPARC. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical data structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The SPARC does not appear to have particularly strict alignment - * requirements. This value was chosen to take advantages of caches. - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * The SPARC has 16 interrupt levels in the PIL field of the PSR. - */ - -#define CPU_MODES_INTERRUPT_MASK 0x0000000F - -/* - * This structure represents the organization of the minimum stack frame - * for the SPARC. More framing information is required in certain situaions - * such as when there are a large number of out parameters or when the callee - * must save floating point registers. - */ - -#ifndef ASM - -typedef struct { - unsigned32 l0; - unsigned32 l1; - unsigned32 l2; - unsigned32 l3; - unsigned32 l4; - unsigned32 l5; - unsigned32 l6; - unsigned32 l7; - unsigned32 i0; - unsigned32 i1; - unsigned32 i2; - unsigned32 i3; - unsigned32 i4; - unsigned32 i5; - unsigned32 i6_fp; - unsigned32 i7; - void *structure_return_address; - /* - * The following are for the callee to save the register arguments in - * should this be necessary. - */ - unsigned32 saved_arg0; - unsigned32 saved_arg1; - unsigned32 saved_arg2; - unsigned32 saved_arg3; - unsigned32 saved_arg4; - unsigned32 saved_arg5; - unsigned32 pad0; -} CPU_Minimum_stack_frame; - -#endif /* ASM */ - -#define CPU_STACK_FRAME_L0_OFFSET 0x00 -#define CPU_STACK_FRAME_L1_OFFSET 0x04 -#define CPU_STACK_FRAME_L2_OFFSET 0x08 -#define CPU_STACK_FRAME_L3_OFFSET 0x0c -#define CPU_STACK_FRAME_L4_OFFSET 0x10 -#define CPU_STACK_FRAME_L5_OFFSET 0x14 -#define CPU_STACK_FRAME_L6_OFFSET 0x18 -#define CPU_STACK_FRAME_L7_OFFSET 0x1c -#define CPU_STACK_FRAME_I0_OFFSET 0x20 -#define CPU_STACK_FRAME_I1_OFFSET 0x24 -#define CPU_STACK_FRAME_I2_OFFSET 0x28 -#define CPU_STACK_FRAME_I3_OFFSET 0x2c -#define CPU_STACK_FRAME_I4_OFFSET 0x30 -#define CPU_STACK_FRAME_I5_OFFSET 0x34 -#define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 -#define CPU_STACK_FRAME_I7_OFFSET 0x3c -#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 -#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 -#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 -#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c -#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 -#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 -#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 -#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c - -#define CPU_MINIMUM_STACK_FRAME_SIZE 0x60 - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On the SPARC, we are relatively conservative in that we save most - * of the CPU state in the context area. The ET (enable trap) bit and - * the CWP (current window pointer) fields of the PSR are considered - * system wide resources and are not maintained on a per-thread basis. - */ - -#ifndef ASM - -typedef struct { - /* - * Using a double g0_g1 will put everything in this structure on a - * double word boundary which allows us to use double word loads - * and stores safely in the context switch. - */ - double g0_g1; - unsigned32 g2; - unsigned32 g3; - unsigned32 g4; - unsigned32 g5; - unsigned32 g6; - unsigned32 g7; - - unsigned32 l0; - unsigned32 l1; - unsigned32 l2; - unsigned32 l3; - unsigned32 l4; - unsigned32 l5; - unsigned32 l6; - unsigned32 l7; - - unsigned32 i0; - unsigned32 i1; - unsigned32 i2; - unsigned32 i3; - unsigned32 i4; - unsigned32 i5; - unsigned32 i6_fp; - unsigned32 i7; - - unsigned32 o0; - unsigned32 o1; - unsigned32 o2; - unsigned32 o3; - unsigned32 o4; - unsigned32 o5; - unsigned32 o6_sp; - unsigned32 o7; - - unsigned32 psr; -} Context_Control; - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control for assembly routines. - */ - -#define G0_OFFSET 0x00 -#define G1_OFFSET 0x04 -#define G2_OFFSET 0x08 -#define G3_OFFSET 0x0C -#define G4_OFFSET 0x10 -#define G5_OFFSET 0x14 -#define G6_OFFSET 0x18 -#define G7_OFFSET 0x1C - -#define L0_OFFSET 0x20 -#define L1_OFFSET 0x24 -#define L2_OFFSET 0x28 -#define L3_OFFSET 0x2C -#define L4_OFFSET 0x30 -#define L5_OFFSET 0x34 -#define L6_OFFSET 0x38 -#define L7_OFFSET 0x3C - -#define I0_OFFSET 0x40 -#define I1_OFFSET 0x44 -#define I2_OFFSET 0x48 -#define I3_OFFSET 0x4C -#define I4_OFFSET 0x50 -#define I5_OFFSET 0x54 -#define I6_FP_OFFSET 0x58 -#define I7_OFFSET 0x5C - -#define O0_OFFSET 0x60 -#define O1_OFFSET 0x64 -#define O2_OFFSET 0x68 -#define O3_OFFSET 0x6C -#define O4_OFFSET 0x70 -#define O5_OFFSET 0x74 -#define O6_SP_OFFSET 0x78 -#define O7_OFFSET 0x7C - -#define PSR_OFFSET 0x80 - -#define CONTEXT_CONTROL_SIZE 0x84 - -/* - * The floating point context area. - */ - -#ifndef ASM - -typedef struct { - double f0_f1; - double f2_f3; - double f4_f5; - double f6_f7; - double f8_f9; - double f10_f11; - double f12_f13; - double f14_f15; - double f16_f17; - double f18_f19; - double f20_f21; - double f22_f23; - double f24_f25; - double f26_f27; - double f28_f29; - double f30_f31; - unsigned32 fsr; -} Context_Control_fp; - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control_fp for assembly routines. - */ - -#define FO_F1_OFFSET 0x00 -#define F2_F3_OFFSET 0x08 -#define F4_F5_OFFSET 0x10 -#define F6_F7_OFFSET 0x18 -#define F8_F9_OFFSET 0x20 -#define F1O_F11_OFFSET 0x28 -#define F12_F13_OFFSET 0x30 -#define F14_F15_OFFSET 0x38 -#define F16_F17_OFFSET 0x40 -#define F18_F19_OFFSET 0x48 -#define F2O_F21_OFFSET 0x50 -#define F22_F23_OFFSET 0x58 -#define F24_F25_OFFSET 0x60 -#define F26_F27_OFFSET 0x68 -#define F28_F29_OFFSET 0x70 -#define F3O_F31_OFFSET 0x78 -#define FSR_OFFSET 0x80 - -#define CONTEXT_CONTROL_FP_SIZE 0x84 - -#ifndef ASM - -/* - * Context saved on stack for an interrupt. - * - * NOTE: The PSR, PC, and NPC are only saved in this structure for the - * benefit of the user's handler. - */ - -typedef struct { - CPU_Minimum_stack_frame Stack_frame; - unsigned32 psr; - unsigned32 pc; - unsigned32 npc; - unsigned32 g1; - unsigned32 g2; - unsigned32 g3; - unsigned32 g4; - unsigned32 g5; - unsigned32 g6; - unsigned32 g7; - unsigned32 i0; - unsigned32 i1; - unsigned32 i2; - unsigned32 i3; - unsigned32 i4; - unsigned32 i5; - unsigned32 i6_fp; - unsigned32 i7; - unsigned32 y; - unsigned32 tpc; -} CPU_Interrupt_frame; - -#endif /* ASM */ - -/* - * Offsets of fields with CPU_Interrupt_frame for assembly routines. - */ - -#define ISF_STACK_FRAME_OFFSET 0x00 -#define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00 -#define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04 -#define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08 -#define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c -#define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10 -#define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14 -#define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18 -#define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c -#define ISF_G6_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x20 -#define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24 -#define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28 -#define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c -#define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30 -#define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34 -#define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38 -#define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c -#define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40 -#define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44 -#define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 -#define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c - -#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 -#ifndef ASM - -/* - * The following table contains the information required to configure - * the processor specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access SPARC specific additions to the CPU Table - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -/* - * This variable is contains the initialize context for the FP unit. - * It is filled in by _CPU_Initialize and copied into the task's FP - * context area during _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT; - -/* - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. Thus - * both must be present if either is. - * - * The SPARC supports a software based interrupt stack and these - * are required. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * The following type defines an entry in the SPARC's trap table. - * - * NOTE: The instructions chosen are RTEMS dependent although one is - * obligated to use two of the four instructions to perform a - * long jump. The other instructions load one register with the - * trap type (a.k.a. vector) and another with the psr. - */ - -typedef struct { - unsigned32 mov_psr_l0; /* mov %psr, %l0 */ - unsigned32 sethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */ - unsigned32 jmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */ - unsigned32 mov_vector_l3; /* mov _vector, %l3 */ -} CPU_Trap_table_entry; - -/* - * This is the set of opcodes for the instructions loaded into a trap - * table entry. The routine which installs a handler is responsible - * for filling in the fields for the _handler address and the _vector - * trap type. - * - * The constants following this structure are masks for the fields which - * must be filled in when the handler is installed. - */ - -extern const CPU_Trap_table_entry _CPU_Trap_slot_template; - -/* - * The size of the floating point context area. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by the executive. - * - * On the SPARC, there are really only 256 vectors. However, the executive - * has no easy, fast, reliable way to determine which traps are synchronous - * and which are asynchronous. By default, synchronous traps return to the - * instruction which caused the interrupt. So if you install a software - * trap handler as an executive interrupt handler (which is desirable since - * RTEMS takes care of window and register issues), then the executive needs - * to know that the return address is to the trap rather than the instruction - * following the trap. - * - * So vectors 0 through 255 are treated as regular asynchronous traps which - * provide the "correct" return address. Vectors 256 through 512 are assumed - * by the executive to be synchronous and to require that the return address - * be fudged. - * - * If you use this mechanism to install a trap handler which must reexecute - * the instruction which caused the trap, then it should be installed as - * an asynchronous trap. This will avoid the executive changing the return - * address. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 - -#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 -#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) -#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) - -#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all tests. This insures - * that a "reasonable" small application should not have any problems. - * - * This appears to be a fairly generous number for the SPARC since - * represents a call depth of about 20 routines based on the minimum - * stack frame. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * On the SPARC, this is required for double word loads and stores. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * The alignment restrictions for the SPARC are not that strict but this - * should unsure that the stack is always sufficiently alignment that the - * window overflow, underflow, and flush routines can use double word loads - * and stores. - */ - -#define CPU_STACK_ALIGNMENT 16 - -#ifndef ASM - -extern unsigned int sparc_disable_interrupts(); -extern void sparc_enable_interrupts(); - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for a critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level ) \ - (_level) = sparc_disable_interrupts() - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of a critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - sparc_enable_interrupts( _level ) -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level ) \ - sparc_flash_interrupts( _level ) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a straight fashion are undefined. - */ - -#define _CPU_ISR_Set_level( _newlevel ) \ - sparc_enable_interrupts( _newlevel << 8) - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * NOTE: Implemented as a subroutine for the SPARC port. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - unsigned32 *stack_base, - unsigned32 size, - unsigned32 new_level, - void *entry_point, - boolean is_fp -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. - * - * On the SPARC, this is is relatively painless but requires a small - * amount of wrapper code before using the regular restore code in - * of the context switch. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The FP context area for the SPARC is a simple structure and nothing - * special is required to find the "starting load point" - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * - * The SPARC allows us to use the simple initialization model - * in which an "initial" FP context was saved into _CPU_Null_fp_context - * at CPU initialization and it is simply copied into the destination - * context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } while (0) - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - do { \ - unsigned32 level; \ - \ - level = sparc_disable_interrupts(); \ - asm volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ - while (1); /* loop forever */ \ - } while (0) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - -#if ( SPARC_HAS_BITSCAN == 0 ) -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE -#else -#error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Bitfield handler macros */ - -/* Priority handler handler macros */ - -/* - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - -#if ( SPARC_HAS_BITSCAN == 1 ) -#error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs new_handler to be directly called from the trap - * table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) - -/* - * _CPU_Thread_Idle_body - * - * Some SPARC implementations have low power, sleep, or idle modes. This - * tries to take advantage of those models. - */ - -void _CPU_Thread_Idle_body( void ); - -#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* - * CPU_swap_u32 - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if you come across a better - * way for the SPARC PLEASE use it. The most common way to swap a 32-bit - * entity as shown below is not any more efficient on the SPARC. - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * It is not obvious how the SPARC can do significantly better than the - * generic code. gcc 2.7.0 only generates about 12 instructions for the - * following code at optimization level four (i.e. -O4). - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#endif ASM - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/sparc/rtems/score/sparc.h b/c/src/exec/score/cpu/sparc/rtems/score/sparc.h deleted file mode 100644 index e6d7690702..0000000000 --- a/c/src/exec/score/cpu/sparc/rtems/score/sparc.h +++ /dev/null @@ -1,266 +0,0 @@ -/* sparc.h - * - * This include file contains information pertaining to the SPARC - * processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef _INCLUDE_SPARC_h -#define _INCLUDE_SPARC_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "sparc" family. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - * - * Currently recognized feature flags: - * - * + SPARC_HAS_FPU - * 0 - no HW FPU - * 1 - has HW FPU (assumed to be compatible w/90C602) - * - * + SPARC_HAS_BITSCAN - * 0 - does not have scan instructions - * 1 - has scan instruction (not currently implemented) - * - * + SPARC_NUMBER_OF_REGISTER_WINDOWS - * 8 is the most common number supported by SPARC implementations. - * SPARC_PSR_CWP_MASK is derived from this value. - */ - -/* - * Some higher end SPARCs have a bitscan instructions. It would - * be nice to take advantage of them. Right now, there is no - * port to a CPU model with this feature and no (untested) code - * that is based on this feature flag. - */ - -#define SPARC_HAS_BITSCAN 0 - -/* - * This should be OK until a port to a higher end SPARC processor - * is made that has more than 8 register windows. If this cannot - * be determined based on multilib settings (v7/v8/v9), then the - * cpu_asm.S code that depends on this will have to move to libcpu. - */ - -#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8 - -/* - * This should be determined based on some soft float derived - * cpp predefine but gcc does not currently give us that information. - */ - - -#if defined(_SOFT_FLOAT) -#define SPARC_HAS_FPU 0 -#else -#define SPARC_HAS_FPU 1 -#endif - -#if SPARC_HAS_FPU -#define CPU_MODEL_NAME "w/FPU" -#else -#define CPU_MODEL_NAME "w/soft-float" -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "SPARC" - -/* - * Miscellaneous constants - */ - -/* - * PSR masks and starting bit positions - * - * NOTE: Reserved bits are ignored. - */ - -#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8) -#define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */ -#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16) -#define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */ -#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32) -#define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */ -#else -#error "Unsupported number of register windows for this cpu" -#endif - -#define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */ -#define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */ -#define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */ -#define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */ -#define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */ -#define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */ -#define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */ -#define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */ -#define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */ - -#define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */ -#define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */ -#define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */ -#define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */ -#define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */ -#define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */ -#define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */ -#define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */ -#define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */ -#define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */ - -#ifndef ASM - -/* - * Standard nop - */ - -#define nop() \ - do { \ - asm volatile ( "nop" ); \ - } while ( 0 ) - -/* - * Get and set the PSR - */ - -#define sparc_get_psr( _psr ) \ - do { \ - (_psr) = 0; \ - asm volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \ - } while ( 0 ) - -#define sparc_set_psr( _psr ) \ - do { \ - asm volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \ - nop(); \ - nop(); \ - nop(); \ - } while ( 0 ) - -/* - * Get and set the TBR - */ - -#define sparc_get_tbr( _tbr ) \ - do { \ - (_tbr) = 0; /* to avoid unitialized warnings */ \ - asm volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \ - } while ( 0 ) - -#define sparc_set_tbr( _tbr ) \ - do { \ - asm volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \ - } while ( 0 ) - -/* - * Get and set the WIM - */ - -#define sparc_get_wim( _wim ) \ - do { \ - asm volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \ - } while ( 0 ) - -#define sparc_set_wim( _wim ) \ - do { \ - asm volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \ - nop(); \ - nop(); \ - nop(); \ - } while ( 0 ) - -/* - * Get and set the Y - */ - -#define sparc_get_y( _y ) \ - do { \ - asm volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \ - } while ( 0 ) - -#define sparc_set_y( _y ) \ - do { \ - asm volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \ - } while ( 0 ) - -/* - * Manipulate the interrupt level in the psr - * - */ - -/* -#define sparc_disable_interrupts( _level ) \ - do { \ - register unsigned int _newlevel; \ - \ - sparc_get_psr( _level ); \ - (_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \ - sparc_set_psr( _newlevel ); \ - } while ( 0 ) - -#define sparc_enable_interrupts( _level ) \ - do { \ - unsigned int _tmp; \ - \ - sparc_get_psr( _tmp ); \ - _tmp &= ~SPARC_PSR_PIL_MASK; \ - _tmp |= (_level) & SPARC_PSR_PIL_MASK; \ - sparc_set_psr( _tmp ); \ - } while ( 0 ) -*/ - -#define sparc_flash_interrupts( _level ) \ - do { \ - register unsigned32 _ignored = 0; \ - \ - sparc_enable_interrupts( (_level) ); \ - sparc_disable_interrupts( _ignored ); \ - } while ( 0 ) - -/* -#define sparc_set_interrupt_level( _new_level ) \ - do { \ - register unsigned32 _new_psr_level = 0; \ - \ - sparc_get_psr( _new_psr_level ); \ - _new_psr_level &= ~SPARC_PSR_PIL_MASK; \ - _new_psr_level |= \ - (((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \ - sparc_set_psr( _new_psr_level ); \ - } while ( 0 ) -*/ - -#define sparc_get_interrupt_level( _level ) \ - do { \ - register unsigned32 _psr_level = 0; \ - \ - sparc_get_psr( _psr_level ); \ - (_level) = \ - (_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \ - } while ( 0 ) - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_SPARC_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/sparc/rtems/score/types.h b/c/src/exec/score/cpu/sparc/rtems/score/types.h deleted file mode 100644 index 5e81acb4c7..0000000000 --- a/c/src/exec/score/cpu/sparc/rtems/score/types.h +++ /dev/null @@ -1,56 +0,0 @@ -/* sparctypes.h - * - * This include file contains type definitions pertaining to the - * SPARC processor family. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __SPARC_TYPES_h -#define __SPARC_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void sparc_isr; -typedef void ( *sparc_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ |