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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-07-09 17:08:48 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-07-09 17:08:48 +0000 |
commit | b73e57bffe6cf60b1817bb2fc244a2f0c602bd5c (patch) | |
tree | 410140b91a7df0566d9f6db8acf7d1a3aa5317cf /c/src/exec/score/cpu/sparc/rtems | |
parent | Make sure pthread init stack size is always set. (diff) | |
download | rtems-b73e57bffe6cf60b1817bb2fc244a2f0c602bd5c.tar.bz2 |
Patch from Jiri Gaisler <jgais@ws.estec.esa.nl>:
+ interrupt masking correction
+ FPU rev.B workaround
+ minor erc32 related fixes
Diffstat (limited to '')
-rw-r--r-- | c/src/exec/score/cpu/sparc/rtems/score/cpu.h | 10 | ||||
-rw-r--r-- | c/src/exec/score/cpu/sparc/rtems/score/sparc.h | 6 |
2 files changed, 11 insertions, 5 deletions
diff --git a/c/src/exec/score/cpu/sparc/rtems/score/cpu.h b/c/src/exec/score/cpu/sparc/rtems/score/cpu.h index cf50f035d6..7a55ae5d0d 100644 --- a/c/src/exec/score/cpu/sparc/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/sparc/rtems/score/cpu.h @@ -725,6 +725,9 @@ SCORE_EXTERN unsigned8 _CPU_Trap_Table_area[ 8192 ] #ifndef ASM +extern unsigned int sparc_disable_interrupts(); +extern void sparc_enable_interrupts(); + /* ISR handler macros */ /* @@ -733,7 +736,7 @@ SCORE_EXTERN unsigned8 _CPU_Trap_Table_area[ 8192 ] */ #define _CPU_ISR_Disable( _level ) \ - sparc_disable_interrupts( _level ) + (_level) = sparc_disable_interrupts() /* * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). @@ -743,7 +746,6 @@ SCORE_EXTERN unsigned8 _CPU_Trap_Table_area[ 8192 ] #define _CPU_ISR_Enable( _level ) \ sparc_enable_interrupts( _level ) - /* * This temporarily restores the interrupt to _level before immediately * disabling them again. This is used to divide long critical @@ -761,7 +763,7 @@ SCORE_EXTERN unsigned8 _CPU_Trap_Table_area[ 8192 ] */ #define _CPU_ISR_Set_level( _newlevel ) \ - sparc_set_interrupt_level( _newlevel ) + sparc_enable_interrupts( _newlevel << 8) unsigned32 _CPU_ISR_Get_level( void ); @@ -840,7 +842,7 @@ void _CPU_Context_Initialize( do { \ unsigned32 level; \ \ - sparc_disable_interrupts( level ); \ + level = sparc_disable_interrupts(); \ asm volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ while (1); /* loop forever */ \ } while (0) diff --git a/c/src/exec/score/cpu/sparc/rtems/score/sparc.h b/c/src/exec/score/cpu/sparc/rtems/score/sparc.h index 283548728a..a8f2122c44 100644 --- a/c/src/exec/score/cpu/sparc/rtems/score/sparc.h +++ b/c/src/exec/score/cpu/sparc/rtems/score/sparc.h @@ -196,6 +196,7 @@ extern "C" { * */ +/* #define sparc_disable_interrupts( _level ) \ do { \ register unsigned int _newlevel; \ @@ -204,7 +205,7 @@ extern "C" { (_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \ sparc_set_psr( _newlevel ); \ } while ( 0 ) - + #define sparc_enable_interrupts( _level ) \ do { \ unsigned int _tmp; \ @@ -214,6 +215,7 @@ extern "C" { _tmp |= (_level) & SPARC_PSR_PIL_MASK; \ sparc_set_psr( _tmp ); \ } while ( 0 ) +*/ #define sparc_flash_interrupts( _level ) \ do { \ @@ -223,6 +225,7 @@ extern "C" { sparc_disable_interrupts( _ignored ); \ } while ( 0 ) +/* #define sparc_set_interrupt_level( _new_level ) \ do { \ register unsigned32 _new_psr_level = 0; \ @@ -233,6 +236,7 @@ extern "C" { (((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \ sparc_set_psr( _new_psr_level ); \ } while ( 0 ) +*/ #define sparc_get_interrupt_level( _level ) \ do { \ |