Part of the automake VI patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>:

> 4) rtems-rc-19990202-0.diff /reorg-score-cpu.sh
>
> reorg-score-cpu.sh reorganizes the cpu/<cpu>/* subdirectories in a
> similar manner than previous reorg scripts did. rtems-rc-19990202-0.diff
> contains the diffs after reorg-score-cpu.sh has been run on a
> rtems-19981215 snapshot + my patches up to rtems-rc-19990131-2.diff.
>
> This patch is rather nasty and may break something. However, I've tested
> it for about 10 different target/bsp pairs and believe to have shaken
> out most bugs.

I wonder about the following .h files that were not moved:

a29k/asm.h
a29k/cpu_asm.h
i386/asm.h
i960/asm.h
m68k/asm.h
m68k/m68302.h
m68k/m68360.h
m68k/qsm.h
m68k/sim.h
mips64orion/asm.h
mips64orion/cpu_asm.h
mips64orion/mips64orion.h
no_cpu/asm.h
no_cpu/cpu_asm.h
powerpc/asm.h
powerpc/mpc860.h
sh/asm.h
sparc/asm.h
sparc/erc32.h

12 files changed, 2164 insertions, 0 deletions

diff --git a/c/src/exec/score/cpu/sh/rtems/Makefile.in b/c/src/exec/score/cpu/sh/rtems/Makefile.in
new file mode 100644
index 0000000000..17f18d020a
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/Makefile.in
@@ -0,0 +1,14 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/directory.cfg
+
+SUB_DIRS = score
diff --git a/c/src/exec/score/cpu/sh/rtems/score/Makefile.in b/c/src/exec/score/cpu/sh/rtems/score/Makefile.in
new file mode 100644
index 0000000000..68703874c4
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/score/Makefile.in
@@ -0,0 +1,59 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+# C source names, if any, go here -- minus the .c
+C_PIECES=
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_PIECES=cpu.h shtypes.h sh.h sh_io.h cpu_isps.h iosh7030.h
+H_FILES=$(H_PIECES:%=$(srcdir)/%)
+
+# Assembly source names, if any, go here -- minus the .S
+S_PIECES=
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
+OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS +=
+CFLAGS   += 
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS += $(BUILT_SOURCES)
+
+# Install the program(s), appending _g or _p as appropriate.
+# for include files, just use $(INSTALL)
+all: install-headers
+
+install-headers: ${H_FILES}
+	$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
+
+preinstall: install-headers
diff --git a/c/src/exec/score/cpu/sh/rtems/score/cpu.h b/c/src/exec/score/cpu/sh/rtems/score/cpu.h
new file mode 100644
index 0000000000..0a67679b5e
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/score/cpu.h
@@ -0,0 +1,875 @@
+/*
+ *  This include file contains information pertaining to the Hitachi SH
+ *  processor.
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * 
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef _SH_CPU_h
+#define _SH_CPU_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/sh.h>              /* pick up machine definitions */
+#ifndef ASM
+#include <rtems/score/shtypes.h>
+#endif
+
+/* conditional compilation parameters */
+
+/*
+ *  Should the calls to _Thread_Enable_dispatch be inlined?
+ *
+ *  If TRUE, then they are inlined.
+ *  If FALSE, then a subroutine call is made.
+ *
+ *  Basically this is an example of the classic trade-off of size
+ *  versus speed.  Inlining the call (TRUE) typically increases the
+ *  size of RTEMS while speeding up the enabling of dispatching.
+ *  [NOTE: In general, the _Thread_Dispatch_disable_level will
+ *  only be 0 or 1 unless you are in an interrupt handler and that
+ *  interrupt handler invokes the executive.]  When not inlined
+ *  something calls _Thread_Enable_dispatch which in turns calls
+ *  _Thread_Dispatch.  If the enable dispatch is inlined, then
+ *  one subroutine call is avoided entirely.]
+ */
+
+#define CPU_INLINE_ENABLE_DISPATCH       FALSE
+
+/*
+ *  Should the body of the search loops in _Thread_queue_Enqueue_priority
+ *  be unrolled one time?  In unrolled each iteration of the loop examines
+ *  two "nodes" on the chain being searched.  Otherwise, only one node
+ *  is examined per iteration.
+ *
+ *  If TRUE, then the loops are unrolled.
+ *  If FALSE, then the loops are not unrolled.
+ *
+ *  The primary factor in making this decision is the cost of disabling
+ *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ *  body of the loop.  On some CPUs, the flash is more expensive than
+ *  one iteration of the loop body.  In this case, it might be desirable
+ *  to unroll the loop.  It is important to note that on some CPUs, this
+ *  code is the longest interrupt disable period in RTEMS.  So it is
+ *  necessary to strike a balance when setting this parameter.
+ */
+
+#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
+
+/*
+ *  Does RTEMS manage a dedicated interrupt stack in software?
+ *
+ *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
+ *  If FALSE, nothing is done.
+ *
+ *  If the CPU supports a dedicated interrupt stack in hardware,
+ *  then it is generally the responsibility of the BSP to allocate it
+ *  and set it up.
+ *
+ *  If the CPU does not support a dedicated interrupt stack, then
+ *  the porter has two options: (1) execute interrupts on the
+ *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ *  interrupt stack.
+ *
+ *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ *
+ *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ *  possible that both are FALSE for a particular CPU.  Although it
+ *  is unclear what that would imply about the interrupt processing
+ *  procedure on that CPU.
+ */
+
+#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
+#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
+
+/*
+ * We define the interrupt stack in the linker script
+ */
+#define CPU_ALLOCATE_INTERRUPT_STACK FALSE 
+
+/*
+ *  Does the RTEMS invoke the user's ISR with the vector number and
+ *  a pointer to the saved interrupt frame (1) or just the vector 
+ *  number (0)?
+ */
+
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/*
+ *  Does the CPU have hardware floating point?
+ *
+ *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ *
+ *  We currently support sh1 only, which has no FPU, other SHes have an FPU
+ *
+ *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
+ *  It indicates whether or not this CPU model has FP support.  For
+ *  example, it would be possible to have an i386_nofp CPU model
+ *  which set this to false to indicate that you have an i386 without
+ *  an i387 and wish to leave floating point support out of RTEMS.
+ */
+
+#define CPU_HARDWARE_FP     FALSE
+
+/*
+ *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ *
+ *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ *
+ *  So far, the only CPU in which this option has been used is the
+ *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
+ *  floating point registers to perform integer multiplies.  If
+ *  a function which you would not think utilize the FP unit DOES,
+ *  then one can not easily predict which tasks will use the FP hardware.
+ *  In this case, this option should be TRUE.
+ *
+ *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ */
+
+#define CPU_ALL_TASKS_ARE_FP     FALSE
+
+/*
+ *  Should the IDLE task have a floating point context?
+ *
+ *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ *  and it has a floating point context which is switched in and out.
+ *  If FALSE, then the IDLE task does not have a floating point context.
+ *
+ *  Setting this to TRUE negatively impacts the time required to preempt
+ *  the IDLE task from an interrupt because the floating point context
+ *  must be saved as part of the preemption.
+ */
+
+#define CPU_IDLE_TASK_IS_FP      FALSE
+
+/*
+ *  Should the saving of the floating point registers be deferred
+ *  until a context switch is made to another different floating point
+ *  task?
+ *
+ *  If TRUE, then the floating point context will not be stored until
+ *  necessary.  It will remain in the floating point registers and not
+ *  disturned until another floating point task is switched to.
+ *
+ *  If FALSE, then the floating point context is saved when a floating
+ *  point task is switched out and restored when the next floating point
+ *  task is restored.  The state of the floating point registers between
+ *  those two operations is not specified.
+ *
+ *  If the floating point context does NOT have to be saved as part of
+ *  interrupt dispatching, then it should be safe to set this to TRUE.
+ *
+ *  Setting this flag to TRUE results in using a different algorithm
+ *  for deciding when to save and restore the floating point context.
+ *  The deferred FP switch algorithm minimizes the number of times
+ *  the FP context is saved and restored.  The FP context is not saved
+ *  until a context switch is made to another, different FP task.
+ *  Thus in a system with only one FP task, the FP context will never
+ *  be saved or restored.
+ */
+
+#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
+
+/*
+ *  Does this port provide a CPU dependent IDLE task implementation?
+ *
+ *  If TRUE, then the routine _CPU_Thread_Idle_body
+ *  must be provided and is the default IDLE thread body instead of
+ *  _CPU_Thread_Idle_body.
+ *
+ *  If FALSE, then use the generic IDLE thread body if the BSP does
+ *  not provide one.
+ *
+ *  This is intended to allow for supporting processors which have
+ *  a low power or idle mode.  When the IDLE thread is executed, then
+ *  the CPU can be powered down.
+ *
+ *  The order of precedence for selecting the IDLE thread body is:
+ *
+ *    1.  BSP provided
+ *    2.  CPU dependent (if provided)
+ *    3.  generic (if no BSP and no CPU dependent)
+ */
+
+#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
+
+/*
+ *  Does the stack grow up (toward higher addresses) or down
+ *  (toward lower addresses)?
+ *
+ *  If TRUE, then the grows upward.
+ *  If FALSE, then the grows toward smaller addresses.
+ */
+
+#define CPU_STACK_GROWS_UP               FALSE
+
+/*
+ *  The following is the variable attribute used to force alignment
+ *  of critical RTEMS structures.  On some processors it may make
+ *  sense to have these aligned on tighter boundaries than
+ *  the minimum requirements of the compiler in order to have as
+ *  much of the critical data area as possible in a cache line.
+ *
+ *  The placement of this macro in the declaration of the variables
+ *  is based on the syntactically requirements of the GNU C
+ *  "__attribute__" extension.  For example with GNU C, use
+ *  the following to force a structures to a 32 byte boundary.
+ *
+ *      __attribute__ ((aligned (32)))
+ *
+ *  NOTE:  Currently only the Priority Bit Map table uses this feature.
+ *         To benefit from using this, the data must be heavily
+ *         used so it will stay in the cache and used frequently enough
+ *         in the executive to justify turning this on.
+ */
+
+#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16)))
+
+/*
+ *  Define what is required to specify how the network to host conversion
+ *  routines are handled.
+ *
+ *  NOTE: SHes can be big or little endian, the default is big endian
+ */
+
+#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
+
+/* __LITTLE_ENDIAN__ is defined if -ml is given to gcc */
+#if defined(__LITTLE_ENDIAN__)
+#define CPU_BIG_ENDIAN                           FALSE
+#define CPU_LITTLE_ENDIAN                        TRUE
+#else
+#define CPU_BIG_ENDIAN                           TRUE
+#define CPU_LITTLE_ENDIAN                        FALSE
+#endif
+ 
+/*
+ *  The following defines the number of bits actually used in the
+ *  interrupt field of the task mode.  How those bits map to the
+ *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
+ */
+
+#define CPU_MODES_INTERRUPT_MASK   0x0000000f
+
+/*
+ *  Processor defined structures
+ *
+ *  Examples structures include the descriptor tables from the i386
+ *  and the processor control structure on the i960ca.
+ */
+
+/* may need to put some structures here.  */
+
+/*
+ * Contexts
+ *
+ *  Generally there are 2 types of context to save.
+ *     1. Interrupt registers to save
+ *     2. Task level registers to save
+ *
+ *  This means we have the following 3 context items:
+ *     1. task level context stuff::  Context_Control
+ *     2. floating point task stuff:: Context_Control_fp
+ *     3. special interrupt level context :: Context_Control_interrupt
+ *
+ *  On some processors, it is cost-effective to save only the callee
+ *  preserved registers during a task context switch.  This means
+ *  that the ISR code needs to save those registers which do not
+ *  persist across function calls.  It is not mandatory to make this
+ *  distinctions between the caller/callee saves registers for the
+ *  purpose of minimizing context saved during task switch and on interrupts.
+ *  If the cost of saving extra registers is minimal, simplicity is the
+ *  choice.  Save the same context on interrupt entry as for tasks in
+ *  this case.
+ *
+ *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ *  care should be used in designing the context area.
+ *
+ *  On some CPUs with hardware floating point support, the Context_Control_fp
+ *  structure will not be used or it simply consist of an array of a
+ *  fixed number of bytes.   This is done when the floating point context
+ *  is dumped by a "FP save context" type instruction and the format
+ *  is not really defined by the CPU.  In this case, there is no need
+ *  to figure out the exact format -- only the size.  Of course, although
+ *  this is enough information for RTEMS, it is probably not enough for
+ *  a debugger such as gdb.  But that is another problem.
+ */
+
+typedef struct {
+  unsigned32 *r15;	/* stack pointer */
+
+  unsigned32 macl;
+  unsigned32 mach;
+  unsigned32 *pr;
+
+  unsigned32 *r14;	/* frame pointer/call saved */
+
+  unsigned32 r13;	/* call saved */
+  unsigned32 r12;	/* call saved */
+  unsigned32 r11;	/* call saved */
+  unsigned32 r10;	/* call saved */
+  unsigned32 r9;	/* call saved */
+  unsigned32 r8;	/* call saved */
+
+  unsigned32 *r7;	/* arg in */
+  unsigned32 *r6;	/* arg in */
+
+#if 0
+  unsigned32 *r5;	/* arg in */
+  unsigned32 *r4;	/* arg in */
+#endif
+
+  unsigned32 *r3;	/* scratch */
+  unsigned32 *r2;	/* scratch */
+  unsigned32 *r1;	/* scratch */
+
+  unsigned32 *r0;	/* arg return */
+
+  unsigned32 gbr;
+  unsigned32 sr; 
+
+} Context_Control;
+
+typedef struct {
+} Context_Control_fp;
+
+typedef struct {
+} CPU_Interrupt_frame;
+
+
+/*
+ *  The following table contains the information required to configure
+ *  the SH processor specific parameters.
+ */
+
+typedef struct {
+  void       (*pretasking_hook)( void );
+  void       (*predriver_hook)( void );
+  void       (*postdriver_hook)( void );
+  void       (*idle_task)( void );
+  boolean      do_zero_of_workspace;
+  unsigned32   idle_task_stack_size;
+  unsigned32   interrupt_stack_size;
+  unsigned32   extra_mpci_receive_server_stack;
+  void *     (*stack_allocate_hook)( unsigned32 );
+  void       (*stack_free_hook)( void* );
+  /* end of fields required on all CPUs */
+}   rtems_cpu_table;
+
+/*
+ *  This variable is optional.  It is used on CPUs on which it is difficult
+ *  to generate an "uninitialized" FP context.  It is filled in by
+ *  _CPU_Initialize and copied into the task's FP context area during
+ *  _CPU_Context_Initialize.
+ */
+
+/*
+SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
+*/
+
+/*
+ *  On some CPUs, RTEMS supports a software managed interrupt stack.
+ *  This stack is allocated by the Interrupt Manager and the switch
+ *  is performed in _ISR_Handler.  These variables contain pointers
+ *  to the lowest and highest addresses in the chunk of memory allocated
+ *  for the interrupt stack.  Since it is unknown whether the stack
+ *  grows up or down (in general), this give the CPU dependent
+ *  code the option of picking the version it wants to use.
+ *
+ *  NOTE: These two variables are required if the macro
+ *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ */
+
+SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
+SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
+
+/*
+ *  With some compilation systems, it is difficult if not impossible to
+ *  call a high-level language routine from assembly language.  This
+ *  is especially true of commercial Ada compilers and name mangling
+ *  C++ ones.  This variable can be optionally defined by the CPU porter
+ *  and contains the address of the routine _Thread_Dispatch.  This
+ *  can make it easier to invoke that routine at the end of the interrupt
+ *  sequence (if a dispatch is necessary).
+ */
+
+SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
+
+/*
+ *  Nothing prevents the porter from declaring more CPU specific variables.
+ */
+
+/* XXX: if needed, put more variables here */
+
+/*
+ *  The size of the floating point context area.  On some CPUs this
+ *  will not be a "sizeof" because the format of the floating point
+ *  area is not defined -- only the size is.  This is usually on
+ *  CPUs with a "floating point save context" instruction.
+ */
+
+#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
+
+/*
+ *  Amount of extra stack (above minimum stack size) required by
+ *  MPCI receive server thread.  Remember that in a multiprocessor
+ *  system this thread must exist and be able to process all directives.
+ */
+
+#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
+
+/*
+ *  This defines the number of entries in the ISR_Vector_table managed
+ *  by RTEMS.
+ */
+
+#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
+#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
+
+/*
+ *  Should be large enough to run all RTEMS tests.  This insures
+ *  that a "reasonable" small application should not have any problems.
+ *
+ *  We have been able to run the sptests with this value, but have not
+ *  been able to run the tmtest suite.
+ */
+
+#define CPU_STACK_MINIMUM_SIZE          4096
+
+/*
+ *  CPU's worst alignment requirement for data types on a byte boundary.  This
+ *  alignment does not take into account the requirements for the stack.
+ */
+
+#define CPU_ALIGNMENT              4
+
+/*
+ *  This number corresponds to the byte alignment requirement for the
+ *  heap handler.  This alignment requirement may be stricter than that
+ *  for the data types alignment specified by CPU_ALIGNMENT.  It is
+ *  common for the heap to follow the same alignment requirement as
+ *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
+ *  then this should be set to CPU_ALIGNMENT.
+ *
+ *  NOTE:  This does not have to be a power of 2.  It does have to
+ *         be greater or equal to than CPU_ALIGNMENT.
+ */
+
+#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
+
+/*
+ *  This number corresponds to the byte alignment requirement for memory
+ *  buffers allocated by the partition manager.  This alignment requirement
+ *  may be stricter than that for the data types alignment specified by
+ *  CPU_ALIGNMENT.  It is common for the partition to follow the same
+ *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
+ *  enough for the partition, then this should be set to CPU_ALIGNMENT.
+ *
+ *  NOTE:  This does not have to be a power of 2.  It does have to
+ *         be greater or equal to than CPU_ALIGNMENT.
+ */
+
+#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
+
+/*
+ *  This number corresponds to the byte alignment requirement for the
+ *  stack.  This alignment requirement may be stricter than that for the
+ *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
+ *  is strict enough for the stack, then this should be set to 0.
+ *
+ *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
+ */
+
+#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
+
+/* ISR handler macros */
+
+/*
+ *  Disable all interrupts for an RTEMS critical section.  The previous
+ *  level is returned in _level.
+ */
+
+#define _CPU_ISR_Disable( _level) \
+  sh_disable_interrupts( _level )
+
+/*
+ *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ *  This indicates the end of an RTEMS critical section.  The parameter
+ *  _level is not modified.
+ */
+
+#define _CPU_ISR_Enable( _level) \
+   sh_enable_interrupts( _level)
+
+/*
+ *  This temporarily restores the interrupt to _level before immediately
+ *  disabling them again.  This is used to divide long RTEMS critical
+ *  sections into two or more parts.  The parameter _level is not
+ * modified.
+ */
+
+#define _CPU_ISR_Flash( _level) \
+  sh_flash_interrupts( _level)
+
+/*
+ *  Map interrupt level in task mode onto the hardware that the CPU
+ *  actually provides.  Currently, interrupt levels which do not
+ *  map onto the CPU in a generic fashion are undefined.  Someday,
+ *  it would be nice if these were "mapped" by the application
+ *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
+ *  8 - 255 would be available for bsp/application specific meaning.
+ *  This could be used to manage a programmable interrupt controller
+ *  via the rtems_task_mode directive.
+ */
+
+#define _CPU_ISR_Set_level( _newlevel) \
+  sh_set_interrupt_level(_newlevel)
+
+unsigned32 _CPU_ISR_Get_level( void );
+
+/* end of ISR handler macros */
+
+/* Context handler macros */
+
+/*
+ *  Initialize the context to a state suitable for starting a
+ *  task after a context restore operation.  Generally, this
+ *  involves:
+ *
+ *     - setting a starting address
+ *     - preparing the stack
+ *     - preparing the stack and frame pointers
+ *     - setting the proper interrupt level in the context
+ *     - initializing the floating point context
+ *
+ *  This routine generally does not set any unnecessary register
+ *  in the context.  The state of the "general data" registers is
+ *  undefined at task start time.
+ *
+ *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
+ *        point thread.  This is typically only used on CPUs where the
+ *        FPU may be easily disabled by software such as on the SPARC
+ *        where the PSR contains an enable FPU bit.
+ */
+
+/* 
+ * FIXME: defined as a function for debugging - should be a macro
+ */
+SCORE_EXTERN void _CPU_Context_Initialize(
+  Context_Control       *_the_context,
+  void                  *_stack_base,
+  unsigned32            _size,
+  unsigned32            _isr,
+  void    (*_entry_point)(void),
+  int                   _is_fp );
+
+/*
+ *  This routine is responsible for somehow restarting the currently
+ *  executing task.  If you are lucky, then all that is necessary
+ *  is restoring the context.  Otherwise, there will need to be
+ *  a special assembly routine which does something special in this
+ *  case.  Context_Restore should work most of the time.  It will
+ *  not work if restarting self conflicts with the stack frame
+ *  assumptions of restoring a context.
+ */
+
+#define _CPU_Context_Restart_self( _the_context ) \
+   _CPU_Context_restore( (_the_context) );
+
+/*
+ *  The purpose of this macro is to allow the initial pointer into
+ *  a floating point context area (used to save the floating point
+ *  context) to be at an arbitrary place in the floating point
+ *  context area.
+ *
+ *  This is necessary because some FP units are designed to have
+ *  their context saved as a stack which grows into lower addresses.
+ *  Other FP units can be saved by simply moving registers into offsets
+ *  from the base of the context area.  Finally some FP units provide
+ *  a "dump context" instruction which could fill in from high to low
+ *  or low to high based on the whim of the CPU designers.
+ */
+
+#define _CPU_Context_Fp_start( _base, _offset ) \
+   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
+
+/*
+ *  This routine initializes the FP context area passed to it to.
+ *  There are a few standard ways in which to initialize the
+ *  floating point context.  The code included for this macro assumes
+ *  that this is a CPU in which a "initial" FP context was saved into
+ *  _CPU_Null_fp_context and it simply copies it to the destination
+ *  context passed to it.
+ *
+ *  Other models include (1) not doing anything, and (2) putting
+ *  a "null FP status word" in the correct place in the FP context.
+ *  SH has no FPU !!!!!!!!!!!!
+ */
+
+#define _CPU_Context_Initialize_fp( _destination ) \
+  {  }
+
+/* end of Context handler macros */
+
+/* Fatal Error manager macros */
+
+/*
+ * FIXME: Trap32 ???
+ *
+ *  This routine copies _error into a known place -- typically a stack
+ *  location or a register, optionally disables interrupts, and
+ *  invokes a Trap32 Instruction which returns to the breakpoint
+ *  routine of cmon.
+ */
+
+#ifdef BSP_FATAL_HALT
+  /* we manage the fatal error in the board support package */
+  void bsp_fatal_halt( unsigned32 _error);
+#define _CPU_Fatal_halt( _error ) bsp_fatal_halt( _error)
+#else
+#define _CPU_Fatal_halt( _error)\
+{ \
+  asm volatile("mov.l %0,r0"::"m" (_error)); \
+  asm volatile("trapa #34"); \
+}
+#endif
+
+/* end of Fatal Error manager macros */
+
+/* Bitfield handler macros */
+
+/*
+ *  This routine sets _output to the bit number of the first bit
+ *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
+ *  This type may be either 16 or 32 bits wide although only the 16
+ *  least significant bits will be used.
+ *
+ *  There are a number of variables in using a "find first bit" type
+ *  instruction.
+ *
+ *    (1) What happens when run on a value of zero?
+ *    (2) Bits may be numbered from MSB to LSB or vice-versa.
+ *    (3) The numbering may be zero or one based.
+ *    (4) The "find first bit" instruction may search from MSB or LSB.
+ *
+ *  RTEMS guarantees that (1) will never happen so it is not a concern.
+ *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
+ *  _CPU_Priority_bits_index().  These three form a set of routines
+ *  which must logically operate together.  Bits in the _value are
+ *  set and cleared based on masks built by _CPU_Priority_mask().
+ *  The basic major and minor values calculated by _Priority_Major()
+ *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
+ *  to properly range between the values returned by the "find first bit"
+ *  instruction.  This makes it possible for _Priority_Get_highest() to
+ *  calculate the major and directly index into the minor table.
+ *  This mapping is necessary to ensure that 0 (a high priority major/minor)
+ *  is the first bit found.
+ *
+ *  This entire "find first bit" and mapping process depends heavily
+ *  on the manner in which a priority is broken into a major and minor
+ *  components with the major being the 4 MSB of a priority and minor
+ *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
+ *  to the lowest priority.
+ *
+ *  If your CPU does not have a "find first bit" instruction, then
+ *  there are ways to make do without it.  Here are a handful of ways
+ *  to implement this in software:
+ *
+ *    - a series of 16 bit test instructions
+ *    - a "binary search using if's"
+ *    - _number = 0
+ *      if _value > 0x00ff
+ *        _value >>=8
+ *        _number = 8;
+ *
+ *      if _value > 0x0000f
+ *        _value >=8
+ *        _number += 4
+ *
+ *      _number += bit_set_table[ _value ]
+ *
+ *    where bit_set_table[ 16 ] has values which indicate the first
+ *      bit set
+ */
+
+#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
+#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
+
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+
+extern unsigned8 _bit_set_table[];
+
+#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
+  { \
+      _output = 0;\
+      if(_value > 0x00ff) \
+      { _value >>= 8; _output = 8; } \
+      if(_value > 0x000f) \
+	{ _output += 4; _value >>= 4; } \
+      _output += _bit_set_table[ _value]; }
+
+#endif
+
+/* end of Bitfield handler macros */
+
+/*
+ *  This routine builds the mask which corresponds to the bit fields
+ *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
+ *  for that routine.
+ */
+
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+
+#define _CPU_Priority_Mask( _bit_number ) \
+  ( 1 << (_bit_number) )
+
+#endif
+
+/*
+ *  This routine translates the bit numbers returned by
+ *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
+ *  a major or minor component of a priority.  See the discussion
+ *  for that routine.
+ */
+
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+
+#define _CPU_Priority_bits_index( _priority ) \
+  (_priority)
+
+#endif
+
+/* end of Priority handler macros */
+
+/* functions */
+
+/*
+ *  _CPU_Initialize
+ *
+ *  This routine performs CPU dependent initialization.
+ */
+
+void _CPU_Initialize(
+  rtems_cpu_table  *cpu_table,
+  void      (*thread_dispatch)
+);
+
+/*
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  This routine installs a "raw" interrupt handler directly into the 
+ *  processor's vector table.
+ */
+ 
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
+ *  _CPU_ISR_install_vector
+ *
+ *  This routine installs an interrupt vector.
+ */
+
+void _CPU_ISR_install_vector(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/*
+ *  _CPU_Install_interrupt_stack
+ *
+ *  This routine installs the hardware interrupt stack pointer.
+ *
+ *  NOTE:  It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
+ *         is TRUE.
+ */
+
+void _CPU_Install_interrupt_stack( void );
+
+/*
+ *  _CPU_Thread_Idle_body
+ *
+ *  This routine is the CPU dependent IDLE thread body.
+ *
+ *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
+ *         is TRUE.
+ */
+
+void _CPU_Thread_Idle_body( void );
+
+/*
+ *  _CPU_Context_switch
+ *
+ *  This routine switches from the run context to the heir context.
+ */
+
+void _CPU_Context_switch(
+  Context_Control  *run,
+  Context_Control  *heir
+);
+
+/*
+ *  _CPU_Context_restore
+ *
+ *  This routine is generally used only to restart self in an
+ *  efficient manner.  It may simply be a label in _CPU_Context_switch.
+ */
+
+void _CPU_Context_restore(
+  Context_Control *new_context
+);
+
+/*
+ *  _CPU_Context_save_fp
+ *
+ *  This routine saves the floating point context passed to it.
+ */
+
+void _CPU_Context_save_fp(
+  void **fp_context_ptr
+);
+
+/*
+ *  _CPU_Context_restore_fp
+ *
+ *  This routine restores the floating point context passed to it.
+ */
+
+void _CPU_Context_restore_fp(
+  void **fp_context_ptr
+);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/cpu_isps.h b/c/src/exec/score/cpu/sh/rtems/score/cpu_isps.h
new file mode 100644
index 0000000000..3f9baf1ad2
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/score/cpu_isps.h
@@ -0,0 +1,165 @@
+/*
+ *  This include file contains information pertaining to the Hitachi SH
+ *  processor.
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * 
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __CPU_ISPS_H
+#define __CPU_ISPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/shtypes.h>
+
+extern void __ISR_Handler( unsigned32 vector );
+
+
+/*
+ * interrupt vector table offsets
+ */
+#define NMI_ISP_V 11
+#define USB_ISP_V 12
+#define IRQ0_ISP_V 64
+#define IRQ1_ISP_V 65
+#define IRQ2_ISP_V 66
+#define IRQ3_ISP_V 67
+#define IRQ4_ISP_V 68
+#define IRQ5_ISP_V 69
+#define IRQ6_ISP_V 70
+#define IRQ7_ISP_V 71
+#define DMA0_ISP_V 72
+#define DMA1_ISP_V 74
+#define DMA2_ISP_V 76
+#define DMA3_ISP_V 78
+
+#define IMIA0_ISP_V 80
+#define IMIB0_ISP_V 81
+#define OVI0_ISP_V 82
+
+#define IMIA1_ISP_V 84
+#define IMIB1_ISP_V 85
+#define OVI1_ISP_V 86
+
+#define IMIA2_ISP_V 88
+#define IMIB2_ISP_V 89
+#define OVI2_ISP_V 90
+
+#define IMIA3_ISP_V 92
+#define IMIB3_ISP_V 93
+#define OVI3_ISP_V 94
+
+#define IMIA4_ISP_V 96
+#define IMIB4_ISP_V 97
+#define OVI4_ISP_V 98
+
+#define ERI0_ISP_V 100
+#define RXI0_ISP_V 101
+#define TXI0_ISP_V 102
+#define TEI0_ISP_V 103
+
+#define ERI1_ISP_V 104
+#define RXI1_ISP_V 105
+#define TXI1_ISP_V 106
+#define TEI1_ISP_V 107
+
+#define PRT_ISP_V 108
+#define ADU_ISP_V 109
+#define WDT_ISP_V 112
+#define DREF_ISP_V 113
+
+
+/* dummy ISP */
+extern void _dummy_isp( void );
+
+/* Non Maskable Interrupt */
+extern void _nmi_isp( void );
+
+/* User Break Controller */
+extern void _usb_isp( void );
+
+/* External interrupts 0-7 */
+extern void _irq0_isp( void );
+extern void _irq1_isp( void );
+extern void _irq2_isp( void );
+extern void _irq3_isp( void );
+extern void _irq4_isp( void );
+extern void _irq5_isp( void );
+extern void _irq6_isp( void );
+extern void _irq7_isp( void );
+
+/* DMA - Controller */
+extern void _dma0_isp( void );
+extern void _dma1_isp( void );
+extern void _dma2_isp( void );
+extern void _dma3_isp( void );
+
+/* Interrupt Timer Unit */
+/* Timer 0 */
+extern void _imia0_isp( void );
+extern void _imib0_isp( void );
+extern void _ovi0_isp( void );
+/* Timer 1 */
+extern void _imia1_isp( void );
+extern void _imib1_isp( void );
+extern void _ovi1_isp( void );
+/* Timer 2 */
+extern void _imia2_isp( void );
+extern void _imib2_isp( void );
+extern void _ovi2_isp( void );
+/* Timer 3 */
+extern void _imia3_isp( void );
+extern void _imib3_isp( void );
+extern void _ovi3_isp( void );
+/* Timer 4 */
+extern void _imia4_isp( void );
+extern void _imib4_isp( void );
+extern void _ovi4_isp( void );
+
+/* seriell interfaces */
+extern void _eri0_isp( void );
+extern void _rxi0_isp( void );
+extern void _txi0_isp( void );
+extern void _tei0_isp( void );
+extern void _eri1_isp( void );
+extern void _rxi1_isp( void );
+extern void _txi1_isp( void );
+extern void _tei1_isp( void );
+
+/* Parity Control Unit of the Bus State Controllers */
+extern void _prt_isp( void );
+
+/* ADC */
+extern void _adu_isp( void );
+
+/* Watchdog Timer */
+extern void _wdt_isp( void );
+
+/* DRAM refresh control unit of bus state controller */
+extern void _dref_isp( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/iosh7030.h b/c/src/exec/score/cpu/sh/rtems/score/iosh7030.h
new file mode 100644
index 0000000000..48463aed47
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/score/iosh7030.h
@@ -0,0 +1,223 @@
+/*
+ *  This include file contains information pertaining to the Hitachi SH
+ *  processor.
+ *
+ *  NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which 
+ *  contained no copyright notice.
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * 
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __IOSH7030_H
+#define __IOSH7030_H
+
+/*
+ * After each line is explained whether the access is char short or long.
+ * The functions read/writeb, w, l, 8, 16, 32 can be found 
+ * in exec/score/cpu/sh/sh_io.h
+ *
+ * 8 bit  == char     ( readb, writeb, read8, write8)
+ * 16 bit == short    ( readw, writew, read16, write16 )
+ * 32 bit == long     ( readl, writel, read32, write32 )
+ */
+
+#define SCI0_SMR 	0x05fffec0 /* char  */
+#define SCI0_BRR 	0x05fffec1 /* char  */
+#define SCI0_SCR 	0x05fffec2 /* char  */
+#define SCI0_TDR 	0x05fffec3 /* char  */
+#define SCI0_SSR 	0x05fffec4 /* char  */
+#define SCI0_RDR 	0x05fffec5 /* char  */
+
+#define SCI1_SMR 	0x05fffec8 /* char  */
+#define SCI1_BRR 	0x05fffec9 /* char  */
+#define SCI1_SCR 	0x05fffeca /* char  */
+#define SCI1_TDR 	0x05fffecb /* char  */
+#define SCI1_SSR 	0x05fffecc /* char  */
+#define SCI1_RDR 	0x05fffecd /* char  */
+
+
+#define ADDRAH 		0x05fffee0 /* char  */
+#define ADDRAL 		0x05fffee1 /* char  */
+#define ADDRBH 		0x05fffee2 /* char  */
+#define ADDRBL 		0x05fffee3 /* char  */
+#define ADDRCH 		0x05fffee4 /* char  */
+#define ADDRCL 		0x05fffee5 /* char  */
+#define ADDRDH 		0x05fffee6 /* char  */
+#define ADDRDL 		0x05fffee7 /* char  */
+#define AD_DRA 		0x05fffee0 /* short */
+#define AD_DRB 		0x05fffee2 /* short */
+#define AD_DRC 		0x05fffee4 /* short */
+#define AD_DRD 		0x05fffee6 /* short */
+#define ADCSR  		0x05fffee8 /* char  */
+#define ADCR   		0x05fffee9 /* char  */
+
+/*ITU SHARED*/
+#define ITU_TSTR  	0x05ffff00 /* char  */
+#define ITU_TSNC  	0x05ffff01 /* char  */
+#define ITU_TMDR  	0x05ffff02 /* char  */
+#define ITU_TFCR  	0x05ffff03 /* char  */
+
+/*ITU CHANNEL 0*/
+#define ITU_TCR0  	0x05ffff04 /* char  */
+#define ITU_TIOR0 	0x05ffff05 /* char  */
+#define ITU_TIER0 	0x05ffff06 /* char  */
+#define ITU_TSR0  	0x05ffff07 /* char  */
+#define ITU_TCNT0 	0x05ffff08 /* short */
+#define ITU_GRA0  	0x05ffff0a /* short */
+#define ITU_GRB0  	0x05ffff0c /* short */
+
+ /*ITU CHANNEL 1*/
+#define ITU_TCR1  	0x05ffff0E /* char  */
+#define ITU_TIOR1 	0x05ffff0F /* char  */
+#define ITU_TIER1 	0x05ffff10 /* char  */
+#define ITU_TSR1  	0x05ffff11 /* char  */
+#define ITU_TCNT1 	0x05ffff12 /* short */
+#define ITU_GRA1  	0x05ffff14 /* short */
+#define ITU_GRB1  	0x05ffff16 /* short */
+
+
+ /*ITU CHANNEL 2*/
+#define ITU_TCR2  	0x05ffff18 /* char  */
+#define ITU_TIOR2 	0x05ffff19 /* char  */
+#define ITU_TIER2 	0x05ffff1A /* char  */
+#define ITU_TSR2  	0x05ffff1B /* char  */
+#define ITU_TCNT2 	0x05ffff1C /* short */
+#define ITU_GRA2  	0x05ffff1E /* short */
+#define ITU_GRB2  	0x05ffff20 /* short */
+
+ /*ITU CHANNEL 3*/
+#define ITU_TCR3  	0x05ffff22 /* char  */
+#define ITU_TIOR3 	0x05ffff23 /* char  */
+#define ITU_TIER3 	0x05ffff24 /* char  */
+#define ITU_TSR3  	0x05ffff25 /* char  */
+#define ITU_TCNT3 	0x05ffff26 /* short */
+#define ITU_GRA3  	0x05ffff28 /* short */
+#define ITU_GRB3  	0x05ffff2A /* short */
+#define ITU_BRA3  	0x05ffff2C /* short */
+#define ITU_BRB3  	0x05ffff2E /* short */
+
+ /*ITU CHANNELS 0-4 SHARED*/
+#define ITU_TOCR  	0x05ffff31 /* char  */
+
+ /*ITU CHANNEL 4*/
+#define ITU_TCR4  	0x05ffff32 /* char  */
+#define ITU_TIOR4 	0x05ffff33 /* char  */
+#define ITU_TIER4 	0x05ffff34 /* char  */
+#define ITU_TSR4  	0x05ffff35 /* char  */
+#define ITU_TCNT4 	0x05ffff36 /* short */
+#define ITU_GRA4  	0x05ffff38 /* short */
+#define ITU_GRB4  	0x05ffff3A /* short */
+#define ITU_BRA4  	0x05ffff3C /* short */
+#define ITU_BRB4  	0x05ffff3E /* short */
+
+ /*DMAC CHANNELS 0-3 SHARED*/
+#define DMAOR           0x05ffff48 /* short */
+
+ /*DMAC CHANNEL 0*/
+#define DMA_SAR0        0x05ffff40 /* long  */
+#define DMA_DAR0        0x05ffff44 /* long  */
+#define DMA_TCR0        0x05ffff4a /* short */
+#define DMA_CHCR0       0x05ffff4e /* short */
+
+ /*DMAC CHANNEL 1*/
+#define DMA_SAR1        0x05ffff50 /* long  */
+#define DMA_DAR1        0x05ffff54 /* long  */
+#define DMA_TCR1        0x05fffF5a /* short */
+#define DMA_CHCR1       0x05ffff5e /* short */
+
+ /*DMAC CHANNEL 3*/
+#define DMA_SAR3        0x05ffff60 /* long  */
+#define DMA_DAR3        0x05ffff64 /* long  */
+#define DMA_TCR3        0x05fffF6a /* short */
+#define DMA_CHCR3       0x05ffff6e /* short */
+
+/*DMAC CHANNEL 4*/
+#define DMA_SAR4        0x05ffff70 /* long  */
+#define DMA_DAR4        0x05ffff74 /* long  */
+#define DMA_TCR4        0x05fffF7a /* short */
+#define DMA_CHCR4       0x05ffff7e /* short */
+
+/*INTC*/
+#define INTC_IPRA 	0x05ffff84 /* short */
+#define INTC_IPRB 	0x05ffff86 /* short */
+#define INTC_IPRC 	0x05ffff88 /* short */
+#define INTC_IPRD 	0x05ffff8A /* short */
+#define INTC_IPRE 	0x05ffff8C /* short */
+#define INTC_ICR  	0x05ffff8E /* short */
+
+/*UBC*/
+#define UBC_BARH  	0x05ffff90 /* short */
+#define UBC_BARL  	0x05ffff92 /* short */
+#define UBC_BAMRH 	0x05ffff94 /* short */
+#define UBC_BAMRL 	0x05ffff96 /* short */
+#define UBC_BBR   	0x05ffff98 /* short */
+
+/*BSC*/
+#define BSC_BCR   	0x05ffffA0 /* short */
+#define BSC_WCR1  	0x05ffffA2 /* short */
+#define BSC_WCR2  	0x05ffffA4 /* short */
+#define BSC_WCR3  	0x05ffffA6 /* short */
+#define BSC_DCR   	0x05ffffA8 /* short */
+#define BSC_PCR   	0x05ffffAA /* short */
+#define BSC_RCR   	0x05ffffAC /* short */
+#define BSC_RTCSR 	0x05ffffAE /* short */
+#define BSC_RTCNT 	0x05ffffB0 /* short */
+#define BSC_RTCOR 	0x05ffffB2 /* short */
+
+/*WDT*/
+#define WDT_TCSR  	0x05ffffB8 /* char  */
+#define WDT_TCNT  	0x05ffffB9 /* char  */
+#define WDT_RSTCSR 	0x05ffffBB /* char  */
+
+/*POWER DOWN STATE*/
+#define PDT_SBYCR 	0x05ffffBC /* char  */
+
+/*PORT A*/
+#define PADR 		0x05ffffC0 /* short */
+
+/*PORT B*/
+#define PBDR 		0x05ffffC2 /* short */
+
+ /*PORT C*/
+#define PCDR 		0x05ffffD0 /* short */
+
+/*PFC*/
+#define PFC_PAIOR 	0x05ffffC4 /* short */
+#define PFC_PBIOR 	0x05ffffC6 /* short */
+#define PFC_PACR1 	0x05ffffC8 /* short */
+#define PFC_PACR2 	0x05ffffCA /* short */
+#define PFC_PBCR1 	0x05ffffCC /* short */
+#define PFC_PBCR2 	0x05ffffCE /* short */
+#define PFC_CASCR 	0x05ffffEE /* short */
+
+/*TPC*/
+#define TPC_TPMR 	0x05ffffF0 /* short */
+#define TPC_TPCR 	0x05ffffF1 /* short */
+#define TPC_NDERH 	0x05ffffF2 /* short */
+#define TPC_NDERL 	0x05ffffF3 /* short */
+#define TPC_NDRB 	0x05ffffF4 /* char  */
+#define TPC_NDRA 	0x05ffff5F /* char  */
+#define TPC_NDRB1 	0x05ffffF6 /* char  */
+#define TPC_NDRA1 	0x05ffffF7 /* char  */
+
+#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/iosh7032.h b/c/src/exec/score/cpu/sh/rtems/score/iosh7032.h
new file mode 100644
index 0000000000..48463aed47
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/score/iosh7032.h
@@ -0,0 +1,223 @@
+/*
+ *  This include file contains information pertaining to the Hitachi SH
+ *  processor.
+ *
+ *  NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which 
+ *  contained no copyright notice.
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * 
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __IOSH7030_H
+#define __IOSH7030_H
+
+/*
+ * After each line is explained whether the access is char short or long.
+ * The functions read/writeb, w, l, 8, 16, 32 can be found 
+ * in exec/score/cpu/sh/sh_io.h
+ *
+ * 8 bit  == char     ( readb, writeb, read8, write8)
+ * 16 bit == short    ( readw, writew, read16, write16 )
+ * 32 bit == long     ( readl, writel, read32, write32 )
+ */
+
+#define SCI0_SMR 	0x05fffec0 /* char  */
+#define SCI0_BRR 	0x05fffec1 /* char  */
+#define SCI0_SCR 	0x05fffec2 /* char  */
+#define SCI0_TDR 	0x05fffec3 /* char  */
+#define SCI0_SSR 	0x05fffec4 /* char  */
+#define SCI0_RDR 	0x05fffec5 /* char  */
+
+#define SCI1_SMR 	0x05fffec8 /* char  */
+#define SCI1_BRR 	0x05fffec9 /* char  */
+#define SCI1_SCR 	0x05fffeca /* char  */
+#define SCI1_TDR 	0x05fffecb /* char  */
+#define SCI1_SSR 	0x05fffecc /* char  */
+#define SCI1_RDR 	0x05fffecd /* char  */
+
+
+#define ADDRAH 		0x05fffee0 /* char  */
+#define ADDRAL 		0x05fffee1 /* char  */
+#define ADDRBH 		0x05fffee2 /* char  */
+#define ADDRBL 		0x05fffee3 /* char  */
+#define ADDRCH 		0x05fffee4 /* char  */
+#define ADDRCL 		0x05fffee5 /* char  */
+#define ADDRDH 		0x05fffee6 /* char  */
+#define ADDRDL 		0x05fffee7 /* char  */
+#define AD_DRA 		0x05fffee0 /* short */
+#define AD_DRB 		0x05fffee2 /* short */
+#define AD_DRC 		0x05fffee4 /* short */
+#define AD_DRD 		0x05fffee6 /* short */
+#define ADCSR  		0x05fffee8 /* char  */
+#define ADCR   		0x05fffee9 /* char  */
+
+/*ITU SHARED*/
+#define ITU_TSTR  	0x05ffff00 /* char  */
+#define ITU_TSNC  	0x05ffff01 /* char  */
+#define ITU_TMDR  	0x05ffff02 /* char  */
+#define ITU_TFCR  	0x05ffff03 /* char  */
+
+/*ITU CHANNEL 0*/
+#define ITU_TCR0  	0x05ffff04 /* char  */
+#define ITU_TIOR0 	0x05ffff05 /* char  */
+#define ITU_TIER0 	0x05ffff06 /* char  */
+#define ITU_TSR0  	0x05ffff07 /* char  */
+#define ITU_TCNT0 	0x05ffff08 /* short */
+#define ITU_GRA0  	0x05ffff0a /* short */
+#define ITU_GRB0  	0x05ffff0c /* short */
+
+ /*ITU CHANNEL 1*/
+#define ITU_TCR1  	0x05ffff0E /* char  */
+#define ITU_TIOR1 	0x05ffff0F /* char  */
+#define ITU_TIER1 	0x05ffff10 /* char  */
+#define ITU_TSR1  	0x05ffff11 /* char  */
+#define ITU_TCNT1 	0x05ffff12 /* short */
+#define ITU_GRA1  	0x05ffff14 /* short */
+#define ITU_GRB1  	0x05ffff16 /* short */
+
+
+ /*ITU CHANNEL 2*/
+#define ITU_TCR2  	0x05ffff18 /* char  */
+#define ITU_TIOR2 	0x05ffff19 /* char  */
+#define ITU_TIER2 	0x05ffff1A /* char  */
+#define ITU_TSR2  	0x05ffff1B /* char  */
+#define ITU_TCNT2 	0x05ffff1C /* short */
+#define ITU_GRA2  	0x05ffff1E /* short */
+#define ITU_GRB2  	0x05ffff20 /* short */
+
+ /*ITU CHANNEL 3*/
+#define ITU_TCR3  	0x05ffff22 /* char  */
+#define ITU_TIOR3 	0x05ffff23 /* char  */
+#define ITU_TIER3 	0x05ffff24 /* char  */
+#define ITU_TSR3  	0x05ffff25 /* char  */
+#define ITU_TCNT3 	0x05ffff26 /* short */
+#define ITU_GRA3  	0x05ffff28 /* short */
+#define ITU_GRB3  	0x05ffff2A /* short */
+#define ITU_BRA3  	0x05ffff2C /* short */
+#define ITU_BRB3  	0x05ffff2E /* short */
+
+ /*ITU CHANNELS 0-4 SHARED*/
+#define ITU_TOCR  	0x05ffff31 /* char  */
+
+ /*ITU CHANNEL 4*/
+#define ITU_TCR4  	0x05ffff32 /* char  */
+#define ITU_TIOR4 	0x05ffff33 /* char  */
+#define ITU_TIER4 	0x05ffff34 /* char  */
+#define ITU_TSR4  	0x05ffff35 /* char  */
+#define ITU_TCNT4 	0x05ffff36 /* short */
+#define ITU_GRA4  	0x05ffff38 /* short */
+#define ITU_GRB4  	0x05ffff3A /* short */
+#define ITU_BRA4  	0x05ffff3C /* short */
+#define ITU_BRB4  	0x05ffff3E /* short */
+
+ /*DMAC CHANNELS 0-3 SHARED*/
+#define DMAOR           0x05ffff48 /* short */
+
+ /*DMAC CHANNEL 0*/
+#define DMA_SAR0        0x05ffff40 /* long  */
+#define DMA_DAR0        0x05ffff44 /* long  */
+#define DMA_TCR0        0x05ffff4a /* short */
+#define DMA_CHCR0       0x05ffff4e /* short */
+
+ /*DMAC CHANNEL 1*/
+#define DMA_SAR1        0x05ffff50 /* long  */
+#define DMA_DAR1        0x05ffff54 /* long  */
+#define DMA_TCR1        0x05fffF5a /* short */
+#define DMA_CHCR1       0x05ffff5e /* short */
+
+ /*DMAC CHANNEL 3*/
+#define DMA_SAR3        0x05ffff60 /* long  */
+#define DMA_DAR3        0x05ffff64 /* long  */
+#define DMA_TCR3        0x05fffF6a /* short */
+#define DMA_CHCR3       0x05ffff6e /* short */
+
+/*DMAC CHANNEL 4*/
+#define DMA_SAR4        0x05ffff70 /* long  */
+#define DMA_DAR4        0x05ffff74 /* long  */
+#define DMA_TCR4        0x05fffF7a /* short */
+#define DMA_CHCR4       0x05ffff7e /* short */
+
+/*INTC*/
+#define INTC_IPRA 	0x05ffff84 /* short */
+#define INTC_IPRB 	0x05ffff86 /* short */
+#define INTC_IPRC 	0x05ffff88 /* short */
+#define INTC_IPRD 	0x05ffff8A /* short */
+#define INTC_IPRE 	0x05ffff8C /* short */
+#define INTC_ICR  	0x05ffff8E /* short */
+
+/*UBC*/
+#define UBC_BARH  	0x05ffff90 /* short */
+#define UBC_BARL  	0x05ffff92 /* short */
+#define UBC_BAMRH 	0x05ffff94 /* short */
+#define UBC_BAMRL 	0x05ffff96 /* short */
+#define UBC_BBR   	0x05ffff98 /* short */
+
+/*BSC*/
+#define BSC_BCR   	0x05ffffA0 /* short */
+#define BSC_WCR1  	0x05ffffA2 /* short */
+#define BSC_WCR2  	0x05ffffA4 /* short */
+#define BSC_WCR3  	0x05ffffA6 /* short */
+#define BSC_DCR   	0x05ffffA8 /* short */
+#define BSC_PCR   	0x05ffffAA /* short */
+#define BSC_RCR   	0x05ffffAC /* short */
+#define BSC_RTCSR 	0x05ffffAE /* short */
+#define BSC_RTCNT 	0x05ffffB0 /* short */
+#define BSC_RTCOR 	0x05ffffB2 /* short */
+
+/*WDT*/
+#define WDT_TCSR  	0x05ffffB8 /* char  */
+#define WDT_TCNT  	0x05ffffB9 /* char  */
+#define WDT_RSTCSR 	0x05ffffBB /* char  */
+
+/*POWER DOWN STATE*/
+#define PDT_SBYCR 	0x05ffffBC /* char  */
+
+/*PORT A*/
+#define PADR 		0x05ffffC0 /* short */
+
+/*PORT B*/
+#define PBDR 		0x05ffffC2 /* short */
+
+ /*PORT C*/
+#define PCDR 		0x05ffffD0 /* short */
+
+/*PFC*/
+#define PFC_PAIOR 	0x05ffffC4 /* short */
+#define PFC_PBIOR 	0x05ffffC6 /* short */
+#define PFC_PACR1 	0x05ffffC8 /* short */
+#define PFC_PACR2 	0x05ffffCA /* short */
+#define PFC_PBCR1 	0x05ffffCC /* short */
+#define PFC_PBCR2 	0x05ffffCE /* short */
+#define PFC_CASCR 	0x05ffffEE /* short */
+
+/*TPC*/
+#define TPC_TPMR 	0x05ffffF0 /* short */
+#define TPC_TPCR 	0x05ffffF1 /* short */
+#define TPC_NDERH 	0x05ffffF2 /* short */
+#define TPC_NDERL 	0x05ffffF3 /* short */
+#define TPC_NDRB 	0x05ffffF4 /* char  */
+#define TPC_NDRA 	0x05ffff5F /* char  */
+#define TPC_NDRB1 	0x05ffffF6 /* char  */
+#define TPC_NDRA1 	0x05ffffF7 /* char  */
+
+#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/ispsh7032.h b/c/src/exec/score/cpu/sh/rtems/score/ispsh7032.h
new file mode 100644
index 0000000000..3f9baf1ad2
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/score/ispsh7032.h
@@ -0,0 +1,165 @@
+/*
+ *  This include file contains information pertaining to the Hitachi SH
+ *  processor.
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * 
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __CPU_ISPS_H
+#define __CPU_ISPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/shtypes.h>
+
+extern void __ISR_Handler( unsigned32 vector );
+
+
+/*
+ * interrupt vector table offsets
+ */
+#define NMI_ISP_V 11
+#define USB_ISP_V 12
+#define IRQ0_ISP_V 64
+#define IRQ1_ISP_V 65
+#define IRQ2_ISP_V 66
+#define IRQ3_ISP_V 67
+#define IRQ4_ISP_V 68
+#define IRQ5_ISP_V 69
+#define IRQ6_ISP_V 70
+#define IRQ7_ISP_V 71
+#define DMA0_ISP_V 72
+#define DMA1_ISP_V 74
+#define DMA2_ISP_V 76
+#define DMA3_ISP_V 78
+
+#define IMIA0_ISP_V 80
+#define IMIB0_ISP_V 81
+#define OVI0_ISP_V 82
+
+#define IMIA1_ISP_V 84
+#define IMIB1_ISP_V 85
+#define OVI1_ISP_V 86
+
+#define IMIA2_ISP_V 88
+#define IMIB2_ISP_V 89
+#define OVI2_ISP_V 90
+
+#define IMIA3_ISP_V 92
+#define IMIB3_ISP_V 93
+#define OVI3_ISP_V 94
+
+#define IMIA4_ISP_V 96
+#define IMIB4_ISP_V 97
+#define OVI4_ISP_V 98
+
+#define ERI0_ISP_V 100
+#define RXI0_ISP_V 101
+#define TXI0_ISP_V 102
+#define TEI0_ISP_V 103
+
+#define ERI1_ISP_V 104
+#define RXI1_ISP_V 105
+#define TXI1_ISP_V 106
+#define TEI1_ISP_V 107
+
+#define PRT_ISP_V 108
+#define ADU_ISP_V 109
+#define WDT_ISP_V 112
+#define DREF_ISP_V 113
+
+
+/* dummy ISP */
+extern void _dummy_isp( void );
+
+/* Non Maskable Interrupt */
+extern void _nmi_isp( void );
+
+/* User Break Controller */
+extern void _usb_isp( void );
+
+/* External interrupts 0-7 */
+extern void _irq0_isp( void );
+extern void _irq1_isp( void );
+extern void _irq2_isp( void );
+extern void _irq3_isp( void );
+extern void _irq4_isp( void );
+extern void _irq5_isp( void );
+extern void _irq6_isp( void );
+extern void _irq7_isp( void );
+
+/* DMA - Controller */
+extern void _dma0_isp( void );
+extern void _dma1_isp( void );
+extern void _dma2_isp( void );
+extern void _dma3_isp( void );
+
+/* Interrupt Timer Unit */
+/* Timer 0 */
+extern void _imia0_isp( void );
+extern void _imib0_isp( void );
+extern void _ovi0_isp( void );
+/* Timer 1 */
+extern void _imia1_isp( void );
+extern void _imib1_isp( void );
+extern void _ovi1_isp( void );
+/* Timer 2 */
+extern void _imia2_isp( void );
+extern void _imib2_isp( void );
+extern void _ovi2_isp( void );
+/* Timer 3 */
+extern void _imia3_isp( void );
+extern void _imib3_isp( void );
+extern void _ovi3_isp( void );
+/* Timer 4 */
+extern void _imia4_isp( void );
+extern void _imib4_isp( void );
+extern void _ovi4_isp( void );
+
+/* seriell interfaces */
+extern void _eri0_isp( void );
+extern void _rxi0_isp( void );
+extern void _txi0_isp( void );
+extern void _tei0_isp( void );
+extern void _eri1_isp( void );
+extern void _rxi1_isp( void );
+extern void _txi1_isp( void );
+extern void _tei1_isp( void );
+
+/* Parity Control Unit of the Bus State Controllers */
+extern void _prt_isp( void );
+
+/* ADC */
+extern void _adu_isp( void );
+
+/* Watchdog Timer */
+extern void _wdt_isp( void );
+
+/* DRAM refresh control unit of bus state controller */
+extern void _dref_isp( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/sh.h b/c/src/exec/score/cpu/sh/rtems/score/sh.h
new file mode 100644
index 0000000000..03d9077d3e
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/score/sh.h
@@ -0,0 +1,186 @@
+/*  sh.h
+ *
+ *  This include file contains information pertaining to the Hitachi SH
+ *  processor.
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
+ * 
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef _sh_h
+#define _sh_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This file contains the information required to build
+ *  RTEMS for a particular member of the "SH" family.
+ *  
+ *  It does  this by setting variables to indicate which implementation
+ *  dependent features are present in a particular member of the family.
+ */
+ 
+#if defined(sh7032)
+
+#define CPU_MODEL_NAME  "SH 7032"
+
+#define SH_HAS_FPU 	0
+
+/*
+ * If the following macro is set to 0 there will be no software irq stack
+ */
+#define SH_HAS_SEPARATE_STACKS 1
+
+#else
+ 
+#error "Unsupported CPU Model"
+ 
+#endif
+
+/*
+ *  Define the name of the CPU family.
+ */
+
+#define CPU_NAME "Hitachi SH"
+
+#ifndef ASM
+
+/*
+ * Mask for disabling interrupts
+ */
+#define SH_IRQDIS_VALUE 0xf0
+
+#define sh_disable_interrupts( _level ) \
+  asm volatile ( \
+    "stc sr,%0\n\t" \
+    "ldc %1,sr\n\t"\
+  : "=r" (_level ) \
+  : "r" (SH_IRQDIS_VALUE) ); 
+
+#define sh_enable_interrupts( _level ) \
+  asm volatile( "ldc %0,sr\n\t" \
+    "nop\n\t" \
+    :: "r" (_level) );
+
+/*
+ *  This temporarily restores the interrupt to _level before immediately
+ *  disabling them again.  This is used to divide long RTEMS critical
+ *  sections into two or more parts.  The parameter _level is not
+ *  modified.
+ */
+     
+#define sh_flash_interrupts( _level ) \
+  asm volatile( \
+    "ldc %1,sr\n\t" \
+    "nop\n\t" \
+    "ldc %0,sr\n\t" \
+    "nop\n\t" \
+    : : "r" (SH_IRQDIS_VALUE), "r" (_level) );
+
+#define sh_get_interrupt_level( _level ) \
+{ \
+  register unsigned32 _tmpsr ; \
+  \
+  asm volatile( "stc sr, %0" : "=r" (_tmpsr) ); \
+  _level = (_tmpsr & 0xf0) >> 4 ; \
+}
+
+#define sh_set_interrupt_level( _newlevel ) \
+{ \
+  register unsigned32 _tmpsr; \
+  \
+  asm volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \
+  _tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \
+  asm  volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \
+}
+
+/*
+ *  The following routine swaps the endian format of an unsigned int.
+ *  It must be static because it is referenced indirectly.
+ */
+ 
+static inline unsigned int sh_swap_u32(
+  unsigned int value
+)
+{
+  register unsigned int swapped;
+  
+  asm volatile ( 
+    "swap.b %1,%0; "
+    "swap.w %0,%0; "
+    "swap.b %0,%0" 
+    : "=r" (swapped) 
+    : "r"  (value) );
+
+  return( swapped );
+}
+
+static inline unsigned int sh_swap_u16(
+  unsigned int value
+)
+{
+  register unsigned int swapped ;
+
+  asm volatile ( "swap.b %1,%0" : "=r" (swapped) : "r"  (value) );
+
+  return( swapped );
+}
+
+#define CPU_swap_u32( value ) sh_swap_u32( value )
+#define CPU_swap_u16( value ) sh_swap_u16( value )
+
+/*
+ *  Simple spin delay in microsecond units for device drivers.
+ *  This is very dependent on the clock speed of the target.
+ *
+ *  Since we don't have a real time clock, this is a very rough
+ *  approximation, assuming that each cycle of the delay loop takes
+ *  approx. 4 machine cycles.
+ *
+ *  e.g.: MHZ = 20 =>     5e-8 secs per instruction
+ *                 => 4 * 5e-8 secs per delay loop
+ */
+
+#define sh_delay( microseconds ) \
+{ register unsigned int _delay = (microseconds) * (MHZ / 4 ); \
+  asm volatile ( \
+"0:	add  #-1,%0\n \
+	nop\n \
+	cmp/pl %0\n \
+	bt 0b\
+	nop" \
+    :: "r" (_delay) );  \
+}
+
+#define CPU_delay( microseconds ) sh_delay( microseconds )
+
+extern unsigned int sh_set_irq_priority( 
+  unsigned int irq, 
+  unsigned int prio );
+
+#endif /* !ASM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/sh_io.h b/c/src/exec/score/cpu/sh/rtems/score/sh_io.h
new file mode 100644
index 0000000000..2a9111e307
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/score/sh_io.h
@@ -0,0 +1,48 @@
+/*
+ * These are some macros to access memory mapped devices
+ * on the SH7000-architecture.
+ *
+ * Inspired from the linux kernel's include/asm/io.h
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1996-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * 
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef _asm_io_h
+#define _asm_io_h
+ 
+#define readb(addr) 	(*(volatile unsigned char *) (addr))
+#define readw(addr) 	(*(volatile unsigned short *) (addr))
+#define readl(addr) 	(*(volatile unsigned int *) (addr))
+#define read8(addr)     (*(volatile unsigned8 *) (addr))
+#define read16(addr)    (*(volatile unsigned16 *) (addr))
+#define read32(addr)    (*(volatile unsigned32 *) (addr))
+
+#define writeb(b,addr) 	((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b,addr) 	((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b,addr) 	((*(volatile unsigned int *) (addr)) = (b))
+#define write8(b,addr) 	((*(volatile unsigned8  *) (addr)) = (b))
+#define write16(b,addr) ((*(volatile unsigned16 *) (addr)) = (b))
+#define write32(b,addr) ((*(volatile unsigned32 *) (addr)) = (b))
+
+#define inb(addr)	readb(addr)
+#define outb(b,addr)	writeb(b,addr)
+
+#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/shtypes.h b/c/src/exec/score/cpu/sh/rtems/score/shtypes.h
new file mode 100644
index 0000000000..853479c13b
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/score/shtypes.h
@@ -0,0 +1,67 @@
+/*
+ *  This include file contains information pertaining to the Hitachi SH
+ *  processor.
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __CPU_SH_TYPES_h
+#define __CPU_SH_TYPES_h
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+typedef unsigned char  unsigned8;      		/* unsigned 8-bit  integer */
+typedef unsigned short unsigned16;     		/* unsigned 16-bit integer */
+typedef unsigned int   unsigned32;     		/* unsigned 32-bit integer */
+typedef unsigned long long unsigned64; 		/* unsigned 64-bit integer */
+
+typedef unsigned16     Priority_Bit_map_control;
+
+typedef signed char      signed8;      		/* 8-bit  signed integer */
+typedef signed short     signed16;     		/* 16-bit signed integer */
+typedef signed int       signed32;     		/* 32-bit signed integer */
+typedef signed long long signed64;     		/* 64 bit signed integer */
+
+typedef unsigned16 boolean;     		/* Boolean value, external */
+						/* data bus has 16 bits  */
+
+typedef float          single_precision;     	/* single precision float */
+typedef double         double_precision;     	/* double precision float */
+
+typedef void sh_isr;
+typedef void ( *sh_isr_entry )( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif
+
diff --git a/c/src/exec/score/cpu/sh/rtems/score/types.h b/c/src/exec/score/cpu/sh/rtems/score/types.h
new file mode 100644
index 0000000000..853479c13b
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/rtems/score/types.h
@@ -0,0 +1,67 @@
+/*
+ *  This include file contains information pertaining to the Hitachi SH
+ *  processor.
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __CPU_SH_TYPES_h
+#define __CPU_SH_TYPES_h
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+typedef unsigned char  unsigned8;      		/* unsigned 8-bit  integer */
+typedef unsigned short unsigned16;     		/* unsigned 16-bit integer */
+typedef unsigned int   unsigned32;     		/* unsigned 32-bit integer */
+typedef unsigned long long unsigned64; 		/* unsigned 64-bit integer */
+
+typedef unsigned16     Priority_Bit_map_control;
+
+typedef signed char      signed8;      		/* 8-bit  signed integer */
+typedef signed short     signed16;     		/* 16-bit signed integer */
+typedef signed int       signed32;     		/* 32-bit signed integer */
+typedef signed long long signed64;     		/* 64 bit signed integer */
+
+typedef unsigned16 boolean;     		/* Boolean value, external */
+						/* data bus has 16 bits  */
+
+typedef float          single_precision;     	/* single precision float */
+typedef double         double_precision;     	/* double precision float */
+
+typedef void sh_isr;
+typedef void ( *sh_isr_entry )( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif
+
diff --git a/c/src/exec/score/cpu/sh/wrap/Makefile.in b/c/src/exec/score/cpu/sh/wrap/Makefile.in
new file mode 100644
index 0000000000..ccd4b51e28
--- /dev/null
+++ b/c/src/exec/score/cpu/sh/wrap/Makefile.in
@@ -0,0 +1,72 @@
+#
+# $Id$
+#
+# *** NOTE *** This Makefile violates RTEMS Makefile standards.
+# This Makefile picks up sources from outside this directory
+# and installs relocatible objects outside of this directory.
+# This behavior is a work-around for RTEMS Makefile's missing 
+# ability to compile inside of directories containing subdirectories.
+# This directory will disapear once automake will be introduced.
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+VPATH = @srcdir@/..
+RTEMS_ROOT = @top_srcdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+RELS=../$(ARCH)/rtems-cpu.rel
+
+# C source names, if any, go here -- minus the .c
+C_PIECES = cpu cpu_asm cpu_isps rtems
+C_FILES=$(C_PIECES:%=%.c)
+C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
+
+H_PIECES = asm.h
+H_FILES=$(H_PIECES:%=$(srcdir)/../%)
+
+# Assembly source names, if any, go here -- minus the .S
+S_PIECES = 
+S_FILES=$(S_PIECES:%=%.S)
+S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
+
+SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
+OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+DEFINES  +=
+CPPFLAGS += -I$(srcdir)/..
+CFLAGS   += $(CFLAGS_OS_V)
+
+LD_PATHS  +=
+LD_LIBS   +=
+LDFLAGS   +=
+
+#
+# Add your list of files to delete here.  The config files
+#  already know how to delete some stuff, so you may want
+#  to just run 'make clean' first to see what gets missed.
+#  'make clobber' already includes 'make clean'
+#
+
+CLEAN_ADDITIONS += ../$(ARCH)
+CLOBBER_ADDITIONS +=
+
+../$(ARCH)/rtems-cpu.rel: $(OBJS)
+	test -d ../$(ARCH) || mkdir ../$(ARCH)
+	$(make-rel)
+
+all:    ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
+
+# Install the program(s), appending _g or _p as appropriate.
+# for include files, just use $(INSTALL)
+install:  all
+
+preinstall: ${ARCH}
+	$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)