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authorRalf Corsepius <ralf.corsepius@rtems.org>2002-07-22 09:46:48 +0000
committerRalf Corsepius <ralf.corsepius@rtems.org>2002-07-22 09:46:48 +0000
commit2b3e9d9b244e279ef5693a7cf5dacc7903164af5 (patch)
tree955e5242d4d08a8ec747c8350f55003bb9d4b519 /c/src/exec/score/cpu/powerpc
parentRemove everything. (diff)
downloadrtems-2b3e9d9b244e279ef5693a7cf5dacc7903164af5.tar.bz2
Remove, moved to cpukit.
Diffstat (limited to 'c/src/exec/score/cpu/powerpc')
-rw-r--r--c/src/exec/score/cpu/powerpc/.cvsignore14
-rw-r--r--c/src/exec/score/cpu/powerpc/ChangeLog164
-rw-r--r--c/src/exec/score/cpu/powerpc/Makefile.am76
-rw-r--r--c/src/exec/score/cpu/powerpc/asm.h292
-rw-r--r--c/src/exec/score/cpu/powerpc/configure.ac30
-rw-r--r--c/src/exec/score/cpu/powerpc/rtems/.cvsignore2
-rw-r--r--c/src/exec/score/cpu/powerpc/rtems/new-exceptions/cpu.h979
-rw-r--r--c/src/exec/score/cpu/powerpc/rtems/old-exceptions/cpu.h1198
-rw-r--r--c/src/exec/score/cpu/powerpc/rtems/powerpc/registers.h307
-rw-r--r--c/src/exec/score/cpu/powerpc/rtems/score/.cvsignore2
-rw-r--r--c/src/exec/score/cpu/powerpc/rtems/score/cpu.h19
-rw-r--r--c/src/exec/score/cpu/powerpc/rtems/score/ppc.h733
-rw-r--r--c/src/exec/score/cpu/powerpc/rtems/score/types.h72
13 files changed, 0 insertions, 3888 deletions
diff --git a/c/src/exec/score/cpu/powerpc/.cvsignore b/c/src/exec/score/cpu/powerpc/.cvsignore
deleted file mode 100644
index d29e5050f5..0000000000
--- a/c/src/exec/score/cpu/powerpc/.cvsignore
+++ /dev/null
@@ -1,14 +0,0 @@
-Makefile
-Makefile.in
-aclocal.m4
-autom4te.cache
-config.cache
-config.guess
-config.log
-config.status
-config.sub
-configure
-depcomp
-install-sh
-missing
-mkinstalldirs
diff --git a/c/src/exec/score/cpu/powerpc/ChangeLog b/c/src/exec/score/cpu/powerpc/ChangeLog
deleted file mode 100644
index d25f14e2b1..0000000000
--- a/c/src/exec/score/cpu/powerpc/ChangeLog
+++ /dev/null
@@ -1,164 +0,0 @@
-2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: RTEMS_TOP(../../../..).
-
-2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Remove RTEMS_PROJECT_ROOT.
-
-2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Add RTEMS_PROG_CCAS
-
-2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
- Add AC_PROG_RANLIB.
-
-2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
- Use ../../../aclocal.
-
-2002-05-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/score/ppc.h: Remove PPC_DEBUG_MODEL.
-
-2001-05-14 Till Straumann <strauman@slac.stanford.edu>
-
- * rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add
- support for the MPC74000 (AKA G4); there is no AltiVec support yet,
- however.
-2002-04-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/score/ppc.h: Remove rtems_multilib.
- Add mpc555 (Based on comments from Sergei Organov <osv@javad.ru>).
- * rtems/old-exceptions/cpu.h: Remove _CPU_Data_Cache_Block_Flush.
- Remove _CPU_Data_Cache_Block_Invalidate.
-
-2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * asm.h: Include cpuopts.h instead of targopts.h.
- * rtems/new-exceptions/cpu.h: Relocated from
- libbsp/powerpc/support/new_exception_processing/rtems/score/cpu.h
- * rtems/old-exceptions/cpu.h: Relocated from
- c/src/lib/libbsp/powerpc/support/old_exception_processing/rtems/score/cpu.h
- * rtems/powerpc/registers.h: Relocated and renamed from
- libcpu/powerpc/shared/include/cpu.h.
- * rtems/score/cpu.h: New.
- * Makefile.am: Reflect changes above.
-
-2001-04-03 Joel Sherrill <joel@OARcorp.com>
-
- * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
- * rtems/score/ppctypes.h: Removed.
- * rtems/score/types.h: New file via CVS magic.
- * Makefile.am, rtems/score/cpu.h: Account for name change.
-
-2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac:
- AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
- AM_INIT_AUTOMAKE([no-define foreign 1.6]).
- * Makefile.am: Remove AUTOMAKE_OPTIONS.
-
-2002-01-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Reflect changes from 2002-01-23.
-
-2002-01-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/Makefile.am: Removed.
- * rtems/score/Makefile.am: Removed.
- * configure.ac: Reflect changes above.
- AC_CONFIG_SRCDIR(asm.h).
-
-2002-01-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/Makefile.am: New.
- * rtems/.cvsignore: New.
- * rtems/score/Makefile.am: New.
- * rtems/score/.cvsignore: New.
- * rtems/score/ppc.h: Relocated from shared/.
- * rtems/score/ppctypes.h: Relocated from shared/.
- * asm.h: Relocated from shared/.
- * shared/Makefile.am: Removed.
- * shared/asm.h: Removed.
- * shared/ppc.h: Removed.
- * shared/ppctypes.h: Removed.
- * shared/.cvsignore: Removed.
- * Makefile.am: Reflect changes above.
- * configure.ac: Reflect changes above.
-
-2001-11-28 Joel Sherrill <joel@OARcorp.com>,
-
- This was tracked as PR91.
- * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
- is used to specify if the port uses the standard macro for this (FALSE).
- A TRUE setting indicates the port provides its own implementation.
-
-2001-11-14 Joel Sherrill <joel@OARcorp.com>
-
- * shared/ppc.h: The mpc8260 uses the new exception processing model
- and thus does not need to define PPC_USE_SPRG.
-
-2001-11-14 Andrew Dachs <A.Dachs@SSTL.co.uk>
-
- * shared/ppc.h: mpc8260 has double FPU not single FPU.
-
-2001-11-08 Dennis Ehlin (ECS) <Dennis.Ehlin@ecs.ericsson.se>
-
- This modification is part of the submitted modifications necessary to
- support the IBM PPC405 family. This submission was reviewed by
- Thomas Doerfler <Thomas.Doerfler@imd-systems.de> who ensured it did
- not negatively impact the ppc403 BSPs. The submission and tracking
- process was captured as PR50.
- * shared/asm.h, shared/ppc.h: Added PPC405 support.
-
-2001-10-22 Andy Dachs <a.dachs@sstl.co.uk>
-
- * shared/ppc.h: Added mpc8260 support.
-
-2001-10-12 Joel Sherrill <joel@OARcorp.com>
-
- * shared/ppctypes.h: Fixed typo.
-
-2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * .cvsignore: Add autom4te.cache for autoconf > 2.52.
- * configure.in: Remove.
- * configure.ac: New file, generated from configure.in by autoupdate.
-
-2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * shared/Makefile.am: Use 'PREINSTALL_FILES ='.
-
-2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am, rtems/score/Makefile.am:
- Apply include_*HEADERS instead of H_FILES.
-
-2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
-
-2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
-
-2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
- Switch to GNU canonicalization.
-
-2000-10-20 Joel Sherrill <joel@OARcorp.com>
-
- * shared/ppc.h: For multilibs, derive PPC_HAS_FPU from _SOFT_FLOAT.
-
-2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Include compile.am.
-
-2000-08-10 Joel Sherrill <joel@OARcorp.com>
-
- * ChangeLog: New file.
diff --git a/c/src/exec/score/cpu/powerpc/Makefile.am b/c/src/exec/score/cpu/powerpc/Makefile.am
deleted file mode 100644
index 4c7146f274..0000000000
--- a/c/src/exec/score/cpu/powerpc/Makefile.am
+++ /dev/null
@@ -1,76 +0,0 @@
-##
-## $Id$
-##
-
-ACLOCAL_AMFLAGS = -I ../../../aclocal
-
-include $(top_srcdir)/../../../automake/multilib.am
-include $(top_srcdir)/../../../automake/compile.am
-include $(top_srcdir)/../../../automake/lib.am
-
-$(PROJECT_INCLUDE)/%.h: %.h
- $(INSTALL_DATA) $< $@
-
-$(PROJECT_INCLUDE):
- $(mkinstalldirs) $@
-
-$(PROJECT_INCLUDE)/rtems:
- $(mkinstalldirs) $@
-
-$(PROJECT_INCLUDE)/rtems/score:
- $(mkinstalldirs) $@
-
-include_HEADERS = asm.h
-PREINSTALL_FILES = $(PROJECT_INCLUDE) \
- $(include_HEADERS:%=$(PROJECT_INCLUDE)/%)
-
-include_rtems_scoredir = $(includedir)/rtems/score
-include_rtems_score_HEADERS = \
- rtems/score/ppc.h \
- rtems/score/types.h
-include_rtems_score_HEADERS += rtems/score/cpu.h
-
-$(PROJECT_INCLUDE)/rtems/old-exceptions:
- $(mkinstalldirs) $@
-
-include_rtems_old_exceptionsdir = $(includedir)/rtems/old-exceptions
-include_rtems_old_exceptions_HEADERS = rtems/old-exceptions/cpu.h
-
-$(PROJECT_INCLUDE)/rtems/new-exceptions:
- $(mkinstalldirs) $@
-
-include_rtems_new_exceptionsdir = $(includedir)/rtems/new-exceptions
-include_rtems_new_exceptions_HEADERS = rtems/new-exceptions/cpu.h
-
-
-$(PROJECT_INCLUDE)/rtems/powerpc:
- $(mkinstalldirs) $@
-
-include_rtems_powerpcdir = $(includedir)/rtems/powerpc
-include_rtems_powerpc_HEADERS = rtems/powerpc/registers.h
-
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \
- $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h)
-
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/old-exceptions \
- $(include_rtems_old_exceptions_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h)
-
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/new-exceptions \
- $(include_rtems_new_exceptions_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h)
-
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/powerpc \
- $(include_rtems_powerpc_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h)
-
-# $(PROJECT_RELEASE)/lib$(MULTISUBDIR)/rtems$(LIB_VARIANT).o: $(ARCH)/rtems.o
-# $(INSTALL_DATA) $< $@
-
-# $(REL): $(rtems_cpu_rel_OBJECTS)
-# $(make-rel)
-
-
-# TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib$(MULTISUBDIR)/rtems$(LIB_VARIANT).o
-
-all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \
- $(TMPINSTALL_FILES)
-
-include $(top_srcdir)/../../../automake/local.am
diff --git a/c/src/exec/score/cpu/powerpc/asm.h b/c/src/exec/score/cpu/powerpc/asm.h
deleted file mode 100644
index 419202eb26..0000000000
--- a/c/src/exec/score/cpu/powerpc/asm.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/* asm.h
- *
- * This include file attempts to address the problems
- * caused by incompatible flavors of assemblers and
- * toolsets. It primarily addresses variations in the
- * use of leading underscores on symbols and the requirement
- * that register names be preceded by a %.
- *
- *
- * NOTE: The spacing in the use of these macros
- * is critical to them working as advertised.
- *
- * COPYRIGHT:
- *
- * This file is based on similar code found in newlib available
- * from ftp.cygnus.com. The file which was used had no copyright
- * notice. This file is freely distributable as long as the source
- * of the file is noted. This file is:
- *
- * COPYRIGHT (c) 1995.
- * i-cubed ltd.
- *
- * COPYRIGHT (c) 1994.
- * On-Line Applications Research Corporation (OAR).
- *
- * $Id$
- */
-
-#ifndef __PPC_ASM_h
-#define __PPC_ASM_h
-
-/*
- * Indicate we are in an assembly file and get the basic CPU definitions.
- */
-
-#ifndef ASM
-#define ASM
-#endif
-#include <rtems/score/cpuopts.h>
-#include <rtems/score/ppc.h>
-
-/*
- * Recent versions of GNU cpp define variables which indicate the
- * need for underscores and percents. If not using GNU cpp or
- * the version does not support this, then you will obviously
- * have to define these as appropriate.
- */
-
-#ifndef __USER_LABEL_PREFIX__
-#define __USER_LABEL_PREFIX__
-#endif
-
-#ifndef __REGISTER_PREFIX__
-#define __REGISTER_PREFIX__
-#endif
-
-#ifndef __FLOAT_REGISTER_PREFIX__
-#define __FLOAT_REGISTER_PREFIX__ __REGISTER_PREFIX__
-#endif
-
-#if (PPC_ABI == PPC_ABI_POWEROPEN)
-#ifndef __PROC_LABEL_PREFIX__
-#define __PROC_LABEL_PREFIX__ .
-#endif
-#endif
-
-#ifndef __PROC_LABEL_PREFIX__
-#define __PROC_LABEL_PREFIX__ __USER_LABEL_PREFIX__
-#endif
-
-/* ANSI concatenation macros. */
-
-#define CONCAT1(a, b) CONCAT2(a, b)
-#define CONCAT2(a, b) a ## b
-
-/* Use the right prefix for global labels. */
-
-#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
-
-/* Use the right prefix for procedure labels. */
-
-#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x)
-
-/* Use the right prefix for registers. */
-
-#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
-
-/* Use the right prefix for floating point registers. */
-
-#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x)
-
-/*
- * define macros for all of the registers on this CPU
- *
- * EXAMPLE: #define d0 REG (d0)
- */
-#define r0 REG(0)
-#define r1 REG(1)
-#define r2 REG(2)
-#define r3 REG(3)
-#define r4 REG(4)
-#define r5 REG(5)
-#define r6 REG(6)
-#define r7 REG(7)
-#define r8 REG(8)
-#define r9 REG(9)
-#define r10 REG(10)
-#define r11 REG(11)
-#define r12 REG(12)
-#define r13 REG(13)
-#define r14 REG(14)
-#define r15 REG(15)
-#define r16 REG(16)
-#define r17 REG(17)
-#define r18 REG(18)
-#define r19 REG(19)
-#define r20 REG(20)
-#define r21 REG(21)
-#define r22 REG(22)
-#define r23 REG(23)
-#define r24 REG(24)
-#define r25 REG(25)
-#define r26 REG(26)
-#define r27 REG(27)
-#define r28 REG(28)
-#define r29 REG(29)
-#define r30 REG(30)
-#define r31 REG(31)
-#define f0 FREG(0)
-#define f1 FREG(1)
-#define f2 FREG(2)
-#define f3 FREG(3)
-#define f4 FREG(4)
-#define f5 FREG(5)
-#define f6 FREG(6)
-#define f7 FREG(7)
-#define f8 FREG(8)
-#define f9 FREG(9)
-#define f10 FREG(10)
-#define f11 FREG(11)
-#define f12 FREG(12)
-#define f13 FREG(13)
-#define f14 FREG(14)
-#define f15 FREG(15)
-#define f16 FREG(16)
-#define f17 FREG(17)
-#define f18 FREG(18)
-#define f19 FREG(19)
-#define f20 FREG(20)
-#define f21 FREG(21)
-#define f22 FREG(22)
-#define f23 FREG(23)
-#define f24 FREG(24)
-#define f25 FREG(25)
-#define f26 FREG(26)
-#define f27 FREG(27)
-#define f28 FREG(28)
-#define f29 FREG(29)
-#define f30 FREG(30)
-#define f31 FREG(31)
-
-/*
- * Some special purpose registers (SPRs).
- */
-#define srr0 0x01a
-#define srr1 0x01b
-#if defined(ppc403) || defined(ppc405)
-#define srr2 0x3de /* IBM 400 series only */
-#define srr3 0x3df /* IBM 400 series only */
-#endif /* ppc403 or ppc405 */
-
-#define sprg0 0x110
-#define sprg1 0x111
-#define sprg2 0x112
-#define sprg3 0x113
-
-#define dar 0x013 /* Data Address Register */
-#define dec 0x016 /* Decrementer Register */
-
-#if defined(ppc403) || defined(ppc405)
-/* the following SPR/DCR registers exist only in IBM 400 series */
-#define dear 0x3d5
-#define evpr 0x3d6 /* SPR: exception vector prefix register */
-#define iccr 0x3fb /* SPR: instruction cache control reg. */
-#define dccr 0x3fa /* SPR: data cache control reg. */
-
-#if defined (ppc403)
-#define exisr 0x040 /* DCR: external interrupt status register */
-#define exier 0x042 /* DCR: external interrupt enable register */
-#endif /* ppc403 */
-#if defined(ppc405)
-#define exisr 0x0C0 /* DCR: external interrupt status register */
-#define exier 0x0C2 /* DCR: external interrupt enable register */
-#endif /* ppc405 */
-
-#define br0 0x080 /* DCR: memory bank register 0 */
-#define br1 0x081 /* DCR: memory bank register 1 */
-#define br2 0x082 /* DCR: memory bank register 2 */
-#define br3 0x083 /* DCR: memory bank register 3 */
-#define br4 0x084 /* DCR: memory bank register 4 */
-#define br5 0x085 /* DCR: memory bank register 5 */
-#define br6 0x086 /* DCR: memory bank register 6 */
-#define br7 0x087 /* DCR: memory bank register 7 */
-/* end of IBM400 series register definitions */
-
-#elif defined(mpc860) || defined(mpc821)
-/* The following registers are for the MPC8x0 */
-#define der 0x095 /* Debug Enable Register */
-#define ictrl 0x09E /* Instruction Support Control Register */
-#define immr 0x27E /* Internal Memory Map Register */
-/* end of MPC8x0 registers */
-#endif
-
-/*
- * Following must be tailor for a particular flavor of the C compiler.
- * They may need to put underscores in front of the symbols.
- */
-
-#define PUBLIC_VAR(sym) .globl SYM (sym)
-#define EXTERN_VAR(sym) .extern SYM (sym)
-#define PUBLIC_PROC(sym) .globl PROC (sym)
-#define EXTERN_PROC(sym) .extern PROC (sym)
-
-/* Other potentially assembler specific operations */
-#if PPC_ASM == PPC_ASM_ELF
-#define ALIGN(n,p) .align p
-#define DESCRIPTOR(x) \
- .section .descriptors,"aw"; \
- PUBLIC_VAR (x); \
-SYM (x):; \
- .long PROC (x); \
- .long s.got; \
- .long 0
-
-#define EXT_SYM_REF(x) .long x
-#define EXT_PROC_REF(x) .long x
-
-/*
- * Define macros to handle section beginning and ends.
- */
-
-#define BEGIN_CODE_DCL .text
-#define END_CODE_DCL
-#define BEGIN_DATA_DCL .data
-#define END_DATA_DCL
-#define BEGIN_CODE .text
-#define END_CODE
-#define BEGIN_DATA .data
-#define END_DATA
-#define BEGIN_BSS .bss
-#define END_BSS
-#define END
-
-#elif PPC_ASM == PPC_ASM_XCOFF
-#define ALIGN(n,p) .align p
-#define DESCRIPTOR(x) \
- .csect x[DS]; \
- .globl x[DS]; \
- .long PROC (x)[PR]; \
- .long TOC[tc0]
-
-#define EXT_SYM_REF(x) .long x[RW]
-#define EXT_PROC_REF(x) .long x[DS]
-
-/*
- * Define macros to handle section beginning and ends.
- */
-
-#define BEGIN_CODE_DCL .csect .text[PR]
-#define END_CODE_DCL
-#define BEGIN_DATA_DCL .csect .data[RW]
-#define END_DATA_DCL
-#define BEGIN_CODE .csect .text[PR]
-#define END_CODE
-#define BEGIN_DATA .csect .data[RW]
-#define END_DATA
-#define BEGIN_BSS .bss
-#define END_BSS
-#define END
-
-#else
-#error "PPC_ASM_TYPE is not properly defined"
-#endif
-#ifndef PPC_ASM
-#error "PPC_ASM_TYPE is not properly defined"
-#endif
-
-
-#endif
-/* end of include file */
-
-
diff --git a/c/src/exec/score/cpu/powerpc/configure.ac b/c/src/exec/score/cpu/powerpc/configure.ac
deleted file mode 100644
index 41f2aae44d..0000000000
--- a/c/src/exec/score/cpu/powerpc/configure.ac
+++ /dev/null
@@ -1,30 +0,0 @@
-## Process this file with autoconf to produce a configure script.
-##
-## $Id$
-
-AC_PREREQ(2.52)
-AC_INIT([rtems-c-src-exec-score-cpu-powerpc],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com])
-AC_CONFIG_SRCDIR([asm.h])
-RTEMS_TOP(../../../..)
-AC_CONFIG_AUX_DIR(../../../..)
-
-RTEMS_CANONICAL_TARGET_CPU
-
-AM_INIT_AUTOMAKE([no-define foreign 1.6])
-AM_MAINTAINER_MODE
-
-RTEMS_ENV_RTEMSCPU
-
-RTEMS_CHECK_CPU
-RTEMS_CANONICAL_HOST
-
-RTEMS_PROG_CC_FOR_TARGET
-RTEMS_PROG_CCAS
-RTEMS_CANONICALIZE_TOOLS
-AC_PROG_RANLIB
-
-RTEMS_CHECK_NEWLIB
-
-# Explicitly list all Makefiles here
-AC_CONFIG_FILES([Makefile])
-AC_OUTPUT
diff --git a/c/src/exec/score/cpu/powerpc/rtems/.cvsignore b/c/src/exec/score/cpu/powerpc/rtems/.cvsignore
deleted file mode 100644
index 282522db03..0000000000
--- a/c/src/exec/score/cpu/powerpc/rtems/.cvsignore
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile
-Makefile.in
diff --git a/c/src/exec/score/cpu/powerpc/rtems/new-exceptions/cpu.h b/c/src/exec/score/cpu/powerpc/rtems/new-exceptions/cpu.h
deleted file mode 100644
index 6b30c0ed0b..0000000000
--- a/c/src/exec/score/cpu/powerpc/rtems/new-exceptions/cpu.h
+++ /dev/null
@@ -1,979 +0,0 @@
-/* cpu.h
- *
- * This include file contains information pertaining to the PowerPC
- * processor.
- *
- * Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
- * Surrey Satellite Technology Limited (SSTL), 2001
- *
- * Author: Andrew Bray <andy@i-cubed.co.uk>
- *
- * COPYRIGHT (c) 1995 by i-cubed ltd.
- *
- * To anyone who acknowledges that this file is provided "AS IS"
- * without any express or implied warranty:
- * permission to use, copy, modify, and distribute this file
- * for any purpose is hereby granted without fee, provided that
- * the above copyright notice and this notice appears in all
- * copies, and that the name of i-cubed limited not be used in
- * advertising or publicity pertaining to distribution of the
- * software without specific, written prior permission.
- * i-cubed limited makes no representations about the suitability
- * of this software for any purpose.
- *
- * Derived from c/src/exec/cpu/no_cpu/cpu.h:
- *
- * COPYRIGHT (c) 1989-1997.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be found in
- * the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#ifndef __CPU_h
-#define __CPU_h
-
-#ifndef _rtems_score_cpu_h
-#error "You should include <rtems/score/cpu.h>"
-#endif
-
-#include <rtems/powerpc/registers.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* conditional compilation parameters */
-
-/*
- * Should the calls to _Thread_Enable_dispatch be inlined?
- *
- * If TRUE, then they are inlined.
- * If FALSE, then a subroutine call is made.
- *
- * Basically this is an example of the classic trade-off of size
- * versus speed. Inlining the call (TRUE) typically increases the
- * size of RTEMS while speeding up the enabling of dispatching.
- * [NOTE: In general, the _Thread_Dispatch_disable_level will
- * only be 0 or 1 unless you are in an interrupt handler and that
- * interrupt handler invokes the executive.] When not inlined
- * something calls _Thread_Enable_dispatch which in turns calls
- * _Thread_Dispatch. If the enable dispatch is inlined, then
- * one subroutine call is avoided entirely.]
- */
-
-#define CPU_INLINE_ENABLE_DISPATCH FALSE
-
-/*
- * Should the body of the search loops in _Thread_queue_Enqueue_priority
- * be unrolled one time? In unrolled each iteration of the loop examines
- * two "nodes" on the chain being searched. Otherwise, only one node
- * is examined per iteration.
- *
- * If TRUE, then the loops are unrolled.
- * If FALSE, then the loops are not unrolled.
- *
- * The primary factor in making this decision is the cost of disabling
- * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
- * body of the loop. On some CPUs, the flash is more expensive than
- * one iteration of the loop body. In this case, it might be desirable
- * to unroll the loop. It is important to note that on some CPUs, this
- * code is the longest interrupt disable period in RTEMS. So it is
- * necessary to strike a balance when setting this parameter.
- */
-
-#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE
-
-/*
- * Does RTEMS manage a dedicated interrupt stack in software?
- *
- * If TRUE, then a stack is allocated in _ISR_Handler_initialization.
- * If FALSE, nothing is done.
- *
- * If the CPU supports a dedicated interrupt stack in hardware,
- * then it is generally the responsibility of the BSP to allocate it
- * and set it up.
- *
- * If the CPU does not support a dedicated interrupt stack, then
- * the porter has two options: (1) execute interrupts on the
- * stack of the interrupted task, and (2) have RTEMS manage a dedicated
- * interrupt stack.
- *
- * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
- * possible that both are FALSE for a particular CPU. Although it
- * is unclear what that would imply about the interrupt processing
- * procedure on that CPU.
- */
-
-#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
-
-/*
- * Does this CPU have hardware support for a dedicated interrupt stack?
- *
- * If TRUE, then it must be installed during initialization.
- * If FALSE, then no installation is performed.
- *
- * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
- * possible that both are FALSE for a particular CPU. Although it
- * is unclear what that would imply about the interrupt processing
- * procedure on that CPU.
- */
-
-#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
-
-/*
- * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
- *
- * If TRUE, then the memory is allocated during initialization.
- * If FALSE, then the memory is allocated during initialization.
- *
- * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
- * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
- */
-
-#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
-
-/*
- * Does the RTEMS invoke the user's ISR with the vector number and
- * a pointer to the saved interrupt frame (1) or just the vector
- * number (0)?
- */
-
-#define CPU_ISR_PASSES_FRAME_POINTER 0
-
-/*
- * Does the CPU have hardware floating point?
- *
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
- *
- * If there is a FP coprocessor such as the i387 or mc68881, then
- * the answer is TRUE.
- *
- * The macro name "PPC_HAS_FPU" should be made CPU specific.
- * It indicates whether or not this CPU model has FP support. For
- * example, it would be possible to have an i386_nofp CPU model
- * which set this to false to indicate that you have an i386 without
- * an i387 and wish to leave floating point support out of RTEMS.
- */
-
-#if ( PPC_HAS_FPU == 1 )
-#define CPU_HARDWARE_FP TRUE
-#else
-#define CPU_HARDWARE_FP FALSE
-#endif
-
-/*
- * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
- *
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
- *
- * So far, the only CPU in which this option has been used is the
- * HP PA-RISC. The HP C compiler and gcc both implicitly use the
- * floating point registers to perform integer multiplies. If
- * a function which you would not think utilize the FP unit DOES,
- * then one can not easily predict which tasks will use the FP hardware.
- * In this case, this option should be TRUE.
- *
- * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
- */
-
-#define CPU_ALL_TASKS_ARE_FP FALSE
-
-/*
- * Should the IDLE task have a floating point context?
- *
- * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- * and it has a floating point context which is switched in and out.
- * If FALSE, then the IDLE task does not have a floating point context.
- *
- * Setting this to TRUE negatively impacts the time required to preempt
- * the IDLE task from an interrupt because the floating point context
- * must be saved as part of the preemption.
- */
-
-#define CPU_IDLE_TASK_IS_FP FALSE
-
-/*
- * Should the saving of the floating point registers be deferred
- * until a context switch is made to another different floating point
- * task?
- *
- * If TRUE, then the floating point context will not be stored until
- * necessary. It will remain in the floating point registers and not
- * disturned until another floating point task is switched to.
- *
- * If FALSE, then the floating point context is saved when a floating
- * point task is switched out and restored when the next floating point
- * task is restored. The state of the floating point registers between
- * those two operations is not specified.
- *
- * If the floating point context does NOT have to be saved as part of
- * interrupt dispatching, then it should be safe to set this to TRUE.
- *
- * Setting this flag to TRUE results in using a different algorithm
- * for deciding when to save and restore the floating point context.
- * The deferred FP switch algorithm minimizes the number of times
- * the FP context is saved and restored. The FP context is not saved
- * until a context switch is made to another, different FP task.
- * Thus in a system with only one FP task, the FP context will never
- * be saved or restored.
- *
- * Note, however that compilers may use floating point registers/
- * instructions for optimization or they may save/restore FP registers
- * on the stack. You must not use deferred switching in these cases
- * and on the PowerPC attempting to do so will raise a "FP unavailable"
- * exception.
- */
-/*
- * ACB Note: This could make debugging tricky..
- */
-
-/* conservative setting (FALSE); probably doesn't affect performance too much */
-#define CPU_USE_DEFERRED_FP_SWITCH FALSE
-
-/*
- * Does this port provide a CPU dependent IDLE task implementation?
- *
- * If TRUE, then the routine _CPU_Thread_Idle_body
- * must be provided and is the default IDLE thread body instead of
- * _CPU_Thread_Idle_body.
- *
- * If FALSE, then use the generic IDLE thread body if the BSP does
- * not provide one.
- *
- * This is intended to allow for supporting processors which have
- * a low power or idle mode. When the IDLE thread is executed, then
- * the CPU can be powered down.
- *
- * The order of precedence for selecting the IDLE thread body is:
- *
- * 1. BSP provided
- * 2. CPU dependent (if provided)
- * 3. generic (if no BSP and no CPU dependent)
- */
-
-#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
-
-
-/*
- * Does the stack grow up (toward higher addresses) or down
- * (toward lower addresses)?
- *
- * If TRUE, then the grows upward.
- * If FALSE, then the grows toward smaller addresses.
- */
-
-#define CPU_STACK_GROWS_UP FALSE
-
-/*
- * The following is the variable attribute used to force alignment
- * of critical RTEMS structures. On some processors it may make
- * sense to have these aligned on tighter boundaries than
- * the minimum requirements of the compiler in order to have as
- * much of the critical data area as possible in a cache line.
- *
- * The placement of this macro in the declaration of the variables
- * is based on the syntactically requirements of the GNU C
- * "__attribute__" extension. For example with GNU C, use
- * the following to force a structures to a 32 byte boundary.
- *
- * __attribute__ ((aligned (32)))
- *
- * NOTE: Currently only the Priority Bit Map table uses this feature.
- * To benefit from using this, the data must be heavily
- * used so it will stay in the cache and used frequently enough
- * in the executive to justify turning this on.
- */
-
-#define CPU_STRUCTURE_ALIGNMENT \
- __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
-
-/*
- * Define what is required to specify how the network to host conversion
- * routines are handled.
- */
-
-#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
-#define CPU_BIG_ENDIAN TRUE
-#define CPU_LITTLE_ENDIAN FALSE
-
-
-/*
- * Processor defined structures
- *
- * Examples structures include the descriptor tables from the i386
- * and the processor control structure on the i960ca.
- */
-
-/* may need to put some structures here. */
-
-/*
- * Contexts
- *
- * Generally there are 2 types of context to save.
- * 1. Interrupt registers to save
- * 2. Task level registers to save
- *
- * This means we have the following 3 context items:
- * 1. task level context stuff:: Context_Control
- * 2. floating point task stuff:: Context_Control_fp
- * 3. special interrupt level context :: Context_Control_interrupt
- *
- * On some processors, it is cost-effective to save only the callee
- * preserved registers during a task context switch. This means
- * that the ISR code needs to save those registers which do not
- * persist across function calls. It is not mandatory to make this
- * distinctions between the caller/callee saves registers for the
- * purpose of minimizing context saved during task switch and on interrupts.
- * If the cost of saving extra registers is minimal, simplicity is the
- * choice. Save the same context on interrupt entry as for tasks in
- * this case.
- *
- * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- * care should be used in designing the context area.
- *
- * On some CPUs with hardware floating point support, the Context_Control_fp
- * structure will not be used or it simply consist of an array of a
- * fixed number of bytes. This is done when the floating point context
- * is dumped by a "FP save context" type instruction and the format
- * is not really defined by the CPU. In this case, there is no need
- * to figure out the exact format -- only the size. Of course, although
- * this is enough information for RTEMS, it is probably not enough for
- * a debugger such as gdb. But that is another problem.
- */
-
-#ifndef ASM
-
-typedef struct {
- unsigned32 gpr1; /* Stack pointer for all */
- unsigned32 gpr2; /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
- unsigned32 gpr13; /* First non volatile PowerOpen, section ptr SVR4/EABI */
- unsigned32 gpr14; /* Non volatile for all */
- unsigned32 gpr15; /* Non volatile for all */
- unsigned32 gpr16; /* Non volatile for all */
- unsigned32 gpr17; /* Non volatile for all */
- unsigned32 gpr18; /* Non volatile for all */
- unsigned32 gpr19; /* Non volatile for all */
- unsigned32 gpr20; /* Non volatile for all */
- unsigned32 gpr21; /* Non volatile for all */
- unsigned32 gpr22; /* Non volatile for all */
- unsigned32 gpr23; /* Non volatile for all */
- unsigned32 gpr24; /* Non volatile for all */
- unsigned32 gpr25; /* Non volatile for all */
- unsigned32 gpr26; /* Non volatile for all */
- unsigned32 gpr27; /* Non volatile for all */
- unsigned32 gpr28; /* Non volatile for all */
- unsigned32 gpr29; /* Non volatile for all */
- unsigned32 gpr30; /* Non volatile for all */
- unsigned32 gpr31; /* Non volatile for all */
- unsigned32 cr; /* PART of the CR is non volatile for all */
- unsigned32 pc; /* Program counter/Link register */
- unsigned32 msr; /* Initial interrupt level */
-} Context_Control;
-
-typedef struct {
- /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
- * procedure calls. However, this would mean that the interrupt
- * frame had to hold f0-f13, and the fpscr. And as the majority
- * of tasks will not have an FP context, we will save the whole
- * context here.
- */
-#if (PPC_HAS_DOUBLE == 1)
- double f[32];
- double fpscr;
-#else
- float f[32];
- float fpscr;
-#endif
-} Context_Control_fp;
-
-typedef struct CPU_Interrupt_frame {
- unsigned32 stacklink; /* Ensure this is a real frame (also reg1 save) */
- unsigned32 calleeLr; /* link register used by callees: SVR4/EABI */
- /* This is what is left out of the primary contexts */
- unsigned32 gpr0;
- unsigned32 gpr2; /* play safe */
- unsigned32 gpr3;
- unsigned32 gpr4;
- unsigned32 gpr5;
- unsigned32 gpr6;
- unsigned32 gpr7;
- unsigned32 gpr8;
- unsigned32 gpr9;
- unsigned32 gpr10;
- unsigned32 gpr11;
- unsigned32 gpr12;
- unsigned32 gpr13; /* Play safe */
- unsigned32 gpr28; /* For internal use by the IRQ handler */
- unsigned32 gpr29; /* For internal use by the IRQ handler */
- unsigned32 gpr30; /* For internal use by the IRQ handler */
- unsigned32 gpr31; /* For internal use by the IRQ handler */
- unsigned32 cr; /* Bits of this are volatile, so no-one may save */
- unsigned32 ctr;
- unsigned32 xer;
- unsigned32 lr;
- unsigned32 pc;
- unsigned32 msr;
- unsigned32 pad[3];
-} CPU_Interrupt_frame;
-
-/*
- * The following table contains the information required to configure
- * the PowerPC processor specific parameters.
- */
-
-typedef struct {
- void (*pretasking_hook)( void );
- void (*predriver_hook)( void );
- void (*postdriver_hook)( void );
- void (*idle_task)( void );
- boolean do_zero_of_workspace;
- unsigned32 idle_task_stack_size;
- unsigned32 interrupt_stack_size;
- unsigned32 extra_mpci_receive_server_stack;
- void * (*stack_allocate_hook)( unsigned32 );
- void (*stack_free_hook)( void* );
- /* end of fields required on all CPUs */
-
- unsigned32 clicks_per_usec; /* Timer clicks per microsecond */
- boolean exceptions_in_RAM; /* TRUE if in RAM */
-
-#if (defined(ppc403) || defined(mpc860) || defined(mpc821) || defined(mpc8260))
- unsigned32 serial_per_sec; /* Serial clocks per second */
- boolean serial_external_clock;
- boolean serial_xon_xoff;
- boolean serial_cts_rts;
- unsigned32 serial_rate;
- unsigned32 timer_average_overhead; /* Average overhead of timer in ticks */
- unsigned32 timer_least_valid; /* Least valid number from timer */
- boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */
-#endif
-
-#if (defined(mpc860) || defined(mpc821) || defined(mpc8260))
- unsigned32 clock_speed; /* Speed of CPU in Hz */
-#endif
-} rtems_cpu_table;
-
-/*
- * Macros to access required entires in the CPU Table are in
- * the file rtems/system.h.
- */
-
-/*
- * Macros to access PowerPC MPC750 specific additions to the CPU Table
- */
-
-#define rtems_cpu_configuration_get_clicks_per_usec() \
- (_CPU_Table.clicks_per_usec)
-
-#define rtems_cpu_configuration_get_exceptions_in_ram() \
- (_CPU_Table.exceptions_in_RAM)
-
-/*
- * This variable is optional. It is used on CPUs on which it is difficult
- * to generate an "uninitialized" FP context. It is filled in by
- * _CPU_Initialize and copied into the task's FP context area during
- * _CPU_Context_Initialize.
- */
-
-/* EXTERN Context_Control_fp _CPU_Null_fp_context; */
-
-/*
- * On some CPUs, RTEMS supports a software managed interrupt stack.
- * This stack is allocated by the Interrupt Manager and the switch
- * is performed in _ISR_Handler. These variables contain pointers
- * to the lowest and highest addresses in the chunk of memory allocated
- * for the interrupt stack. Since it is unknown whether the stack
- * grows up or down (in general), this give the CPU dependent
- * code the option of picking the version it wants to use.
- *
- * NOTE: These two variables are required if the macro
- * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
- */
-
-SCORE_EXTERN void *_CPU_Interrupt_stack_low;
-SCORE_EXTERN void *_CPU_Interrupt_stack_high;
-
-#endif /* ndef ASM */
-
-/*
- * This defines the number of levels and the mask used to pick those
- * bits out of a thread mode.
- */
-
-#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */
-#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */
-
-/*
- * With some compilation systems, it is difficult if not impossible to
- * call a high-level language routine from assembly language. This
- * is especially true of commercial Ada compilers and name mangling
- * C++ ones. This variable can be optionally defined by the CPU porter
- * and contains the address of the routine _Thread_Dispatch. This
- * can make it easier to invoke that routine at the end of the interrupt
- * sequence (if a dispatch is necessary).
- */
-
-/* EXTERN void (*_CPU_Thread_dispatch_pointer)(); */
-
-/*
- * Nothing prevents the porter from declaring more CPU specific variables.
- */
-
-#ifndef ASM
-
-SCORE_EXTERN struct {
- unsigned32 *Disable_level;
- void *Stack;
- volatile boolean *Switch_necessary;
- boolean *Signal;
-
-} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
-
-#endif /* ndef ASM */
-
-/*
- * The size of the floating point context area. On some CPUs this
- * will not be a "sizeof" because the format of the floating point
- * area is not defined -- only the size is. This is usually on
- * CPUs with a "floating point save context" instruction.
- */
-
-#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
-
-/*
- * (Optional) # of bytes for libmisc/stackchk to check
- * If not specifed, then it defaults to something reasonable
- * for most architectures.
- */
-
-#define CPU_STACK_CHECK_SIZE (128)
-
-/*
- * Amount of extra stack (above minimum stack size) required by
- * MPCI receive server thread. Remember that in a multiprocessor
- * system this thread must exist and be able to process all directives.
- */
-
-#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
-
-/*
- * This defines the number of entries in the ISR_Vector_table managed
- * by RTEMS.
- */
-
-#define CPU_INTERRUPT_NUMBER_OF_VECTORS (PPC_INTERRUPT_MAX)
-#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1)
-
-/*
- * This is defined if the port has a special way to report the ISR nesting
- * level. Most ports maintain the variable _ISR_Nest_level.
- */
-
-#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
-
-/*
- * Should be large enough to run all RTEMS tests. This insures
- * that a "reasonable" small application should not have any problems.
- */
-
-#define CPU_STACK_MINIMUM_SIZE (1024*8)
-
-/*
- * CPU's worst alignment requirement for data types on a byte boundary. This
- * alignment does not take into account the requirements for the stack.
- */
-
-#define CPU_ALIGNMENT (PPC_ALIGNMENT)
-
-/*
- * This number corresponds to the byte alignment requirement for the
- * heap handler. This alignment requirement may be stricter than that
- * for the data types alignment specified by CPU_ALIGNMENT. It is
- * common for the heap to follow the same alignment requirement as
- * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
- * then this should be set to CPU_ALIGNMENT.
- *
- * NOTE: This does not have to be a power of 2. It does have to
- * be greater or equal to than CPU_ALIGNMENT.
- */
-
-#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT)
-
-/*
- * This number corresponds to the byte alignment requirement for memory
- * buffers allocated by the partition manager. This alignment requirement
- * may be stricter than that for the data types alignment specified by
- * CPU_ALIGNMENT. It is common for the partition to follow the same
- * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
- * enough for the partition, then this should be set to CPU_ALIGNMENT.
- *
- * NOTE: This does not have to be a power of 2. It does have to
- * be greater or equal to than CPU_ALIGNMENT.
- */
-
-#define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT)
-
-/*
- * This number corresponds to the byte alignment requirement for the
- * stack. This alignment requirement may be stricter than that for the
- * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
- * is strict enough for the stack, then this should be set to 0.
- *
- * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
- */
-
-#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT)
-
-/*
- * Needed for Interrupt stack
- */
-#define CPU_MINIMUM_STACK_FRAME_SIZE 8
-
-
-/*
- * ISR handler macros
- */
-
-#define _CPU_Initialize_vectors()
-
-/*
- * Disable all interrupts for an RTEMS critical section. The previous
- * level is returned in _isr_cookie.
- */
-
-#ifndef ASM
-
-static inline unsigned32 _CPU_ISR_Get_level( void )
-{
- register unsigned int msr;
- _CPU_MSR_GET(msr);
- if (msr & MSR_EE) return 0;
- else return 1;
-}
-
-static inline void _CPU_ISR_Set_level( unsigned32 level )
-{
- register unsigned int msr;
- _CPU_MSR_GET(msr);
- if (!(level & CPU_MODES_INTERRUPT_MASK)) {
- msr |= MSR_EE;
- }
- else {
- msr &= ~MSR_EE;
- }
- _CPU_MSR_SET(msr);
-}
-
-#define _CPU_ISR_install_vector(irq, new, old) {BSP_panic("_CPU_ISR_install_vector called\n");}
-
-/* Context handler macros */
-
-/*
- * Initialize the context to a state suitable for starting a
- * task after a context restore operation. Generally, this
- * involves:
- *
- * - setting a starting address
- * - preparing the stack
- * - preparing the stack and frame pointers
- * - setting the proper interrupt level in the context
- * - initializing the floating point context
- *
- * This routine generally does not set any unnecessary register
- * in the context. The state of the "general data" registers is
- * undefined at task start time.
- *
- * NOTE: Implemented as a subroutine for the SPARC port.
- */
-
-void _CPU_Context_Initialize(
- Context_Control *the_context,
- unsigned32 *stack_base,
- unsigned32 size,
- unsigned32 new_level,
- void *entry_point,
- boolean is_fp
-);
-
-/*
- * This routine is responsible for somehow restarting the currently
- * executing task. If you are lucky, then all that is necessary
- * is restoring the context. Otherwise, there will need to be
- * a special assembly routine which does something special in this
- * case. Context_Restore should work most of the time. It will
- * not work if restarting self conflicts with the stack frame
- * assumptions of restoring a context.
- */
-
-#define _CPU_Context_Restart_self( _the_context ) \
- _CPU_Context_restore( (_the_context) );
-
-/*
- * The purpose of this macro is to allow the initial pointer into
- * a floating point context area (used to save the floating point
- * context) to be at an arbitrary place in the floating point
- * context area.
- *
- * This is necessary because some FP units are designed to have
- * their context saved as a stack which grows into lower addresses.
- * Other FP units can be saved by simply moving registers into offsets
- * from the base of the context area. Finally some FP units provide
- * a "dump context" instruction which could fill in from high to low
- * or low to high based on the whim of the CPU designers.
- */
-
-#define _CPU_Context_Fp_start( _base, _offset ) \
- ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
-
-/*
- * This routine initializes the FP context area passed to it to.
- * There are a few standard ways in which to initialize the
- * floating point context. The code included for this macro assumes
- * that this is a CPU in which a "initial" FP context was saved into
- * _CPU_Null_fp_context and it simply copies it to the destination
- * context passed to it.
- *
- * Other models include (1) not doing anything, and (2) putting
- * a "null FP status word" in the correct place in the FP context.
- */
-
-#define _CPU_Context_Initialize_fp( _destination ) \
- { \
- ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \
- }
-
-/* end of Context handler macros */
-
-/* Fatal Error manager macros */
-
-/*
- * This routine copies _error into a known place -- typically a stack
- * location or a register, optionally disables interrupts, and
- * halts/stops the CPU.
- */
-
-#define _CPU_Fatal_halt( _error ) \
- _BSP_Fatal_error(_error)
-
-/* end of Fatal Error manager macros */
-
-/* Bitfield handler macros */
-
-/*
- * This routine sets _output to the bit number of the first bit
- * set in _value. _value is of CPU dependent type Priority_Bit_map_control.
- * This type may be either 16 or 32 bits wide although only the 16
- * least significant bits will be used.
- *
- * There are a number of variables in using a "find first bit" type
- * instruction.
- *
- * (1) What happens when run on a value of zero?
- * (2) Bits may be numbered from MSB to LSB or vice-versa.
- * (3) The numbering may be zero or one based.
- * (4) The "find first bit" instruction may search from MSB or LSB.
- *
- * RTEMS guarantees that (1) will never happen so it is not a concern.
- * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
- * _CPU_Priority_Bits_index(). These three form a set of routines
- * which must logically operate together. Bits in the _value are
- * set and cleared based on masks built by _CPU_Priority_mask().
- * The basic major and minor values calculated by _Priority_Major()
- * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
- * to properly range between the values returned by the "find first bit"
- * instruction. This makes it possible for _Priority_Get_highest() to
- * calculate the major and directly index into the minor table.
- * This mapping is necessary to ensure that 0 (a high priority major/minor)
- * is the first bit found.
- *
- * This entire "find first bit" and mapping process depends heavily
- * on the manner in which a priority is broken into a major and minor
- * components with the major being the 4 MSB of a priority and minor
- * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
- * to the lowest priority.
- *
- * If your CPU does not have a "find first bit" instruction, then
- * there are ways to make do without it. Here are a handful of ways
- * to implement this in software:
- *
- * - a series of 16 bit test instructions
- * - a "binary search using if's"
- * - _number = 0
- * if _value > 0x00ff
- * _value >>=8
- * _number = 8;
- *
- * if _value > 0x0000f
- * _value >=8
- * _number += 4
- *
- * _number += bit_set_table[ _value ]
- *
- * where bit_set_table[ 16 ] has values which indicate the first
- * bit set
- */
-
-#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
- { \
- asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
- "1" ((_value))); \
- }
-
-/* end of Bitfield handler macros */
-
-/*
- * This routine builds the mask which corresponds to the bit fields
- * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
- * for that routine.
- */
-
-#define _CPU_Priority_Mask( _bit_number ) \
- ( 0x80000000 >> (_bit_number) )
-
-/*
- * This routine translates the bit numbers returned by
- * _CPU_Bitfield_Find_first_bit() into something suitable for use as
- * a major or minor component of a priority. See the discussion
- * for that routine.
- */
-
-#define _CPU_Priority_bits_index( _priority ) \
- (_priority)
-
-/* end of Priority handler macros */
-
-/* variables */
-
-extern const unsigned32 _CPU_msrs[4];
-
-/* functions */
-
-/*
- * _CPU_Initialize
- *
- * This routine performs CPU dependent initialization.
- */
-
-void _CPU_Initialize(
- rtems_cpu_table *cpu_table,
- void (*thread_dispatch)
-);
-
-
-/*
- * _CPU_Install_interrupt_stack
- *
- * This routine installs the hardware interrupt stack pointer.
- *
- * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
- * is TRUE.
- */
-
-void _CPU_Install_interrupt_stack( void );
-
-/*
- * _CPU_Context_switch
- *
- * This routine switches from the run context to the heir context.
- */
-
-void _CPU_Context_switch(
- Context_Control *run,
- Context_Control *heir
-);
-
-/*
- * _CPU_Context_restore
- *
- * This routine is generallu used only to restart self in an
- * efficient manner. It may simply be a label in _CPU_Context_switch.
- *
- * NOTE: May be unnecessary to reload some registers.
- */
-
-void _CPU_Context_restore(
- Context_Control *new_context
-);
-
-/*
- * _CPU_Context_save_fp
- *
- * This routine saves the floating point context passed to it.
- */
-
-void _CPU_Context_save_fp(
- void **fp_context_ptr
-);
-
-/*
- * _CPU_Context_restore_fp
- *
- * This routine restores the floating point context passed to it.
- */
-
-void _CPU_Context_restore_fp(
- void **fp_context_ptr
-);
-
-void _CPU_Fatal_error(
- unsigned32 _error
-);
-
-/* The following routine swaps the endian format of an unsigned int.
- * It must be static because it is referenced indirectly.
- *
- * This version will work on any processor, but if there is a better
- * way for your CPU PLEASE use it. The most common way to do this is to:
- *
- * swap least significant two bytes with 16-bit rotate
- * swap upper and lower 16-bits
- * swap most significant two bytes with 16-bit rotate
- *
- * Some CPUs have special instructions which swap a 32-bit quantity in
- * a single instruction (e.g. i486). It is probably best to avoid
- * an "endian swapping control bit" in the CPU. One good reason is
- * that interrupts would probably have to be disabled to insure that
- * an interrupt does not try to access the same "chunk" with the wrong
- * endian. Another good reason is that on some CPUs, the endian bit
- * endianness for ALL fetches -- both code and data -- so the code
- * will be fetched incorrectly.
- */
-
-static inline unsigned int CPU_swap_u32(
- unsigned int value
-)
-{
- unsigned32 swapped;
-
- asm volatile("rlwimi %0,%1,8,24,31;"
- "rlwimi %0,%1,24,16,23;"
- "rlwimi %0,%1,8,8,15;"
- "rlwimi %0,%1,24,0,7;" :
- "=&r" ((swapped)) : "r" ((value)));
-
- return( swapped );
-}
-
-#define CPU_swap_u16( value ) \
- (((value&0xff) << 8) | ((value >> 8)&0xff))
-
-#endif /* ndef ASM */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/c/src/exec/score/cpu/powerpc/rtems/old-exceptions/cpu.h b/c/src/exec/score/cpu/powerpc/rtems/old-exceptions/cpu.h
deleted file mode 100644
index 4ab28fc368..0000000000
--- a/c/src/exec/score/cpu/powerpc/rtems/old-exceptions/cpu.h
+++ /dev/null
@@ -1,1198 +0,0 @@
-/* cpu.h
- *
- * This include file contains information pertaining to the PowerPC
- * processor.
- *
- * Author: Andrew Bray <andy@i-cubed.co.uk>
- *
- * COPYRIGHT (c) 1995 by i-cubed ltd.
- *
- * To anyone who acknowledges that this file is provided "AS IS"
- * without any express or implied warranty:
- * permission to use, copy, modify, and distribute this file
- * for any purpose is hereby granted without fee, provided that
- * the above copyright notice and this notice appears in all
- * copies, and that the name of i-cubed limited not be used in
- * advertising or publicity pertaining to distribution of the
- * software without specific, written prior permission.
- * i-cubed limited makes no representations about the suitability
- * of this software for any purpose.
- *
- * Derived from c/src/exec/cpu/no_cpu/cpu.h:
- *
- * COPYRIGHT (c) 1989-1997.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may in
- * the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#ifndef __CPU_h
-#define __CPU_h
-
-#ifndef _rtems_score_cpu_h
-#error "You should include <rtems/score/cpu.h>"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef ASM
-struct CPU_Interrupt_frame;
-typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * );
-#endif
-
-/* conditional compilation parameters */
-
-/*
- * Should the calls to _Thread_Enable_dispatch be inlined?
- *
- * If TRUE, then they are inlined.
- * If FALSE, then a subroutine call is made.
- *
- * Basically this is an example of the classic trade-off of size
- * versus speed. Inlining the call (TRUE) typically increases the
- * size of RTEMS while speeding up the enabling of dispatching.
- * [NOTE: In general, the _Thread_Dispatch_disable_level will
- * only be 0 or 1 unless you are in an interrupt handler and that
- * interrupt handler invokes the executive.] When not inlined
- * something calls _Thread_Enable_dispatch which in turns calls
- * _Thread_Dispatch. If the enable dispatch is inlined, then
- * one subroutine call is avoided entirely.]
- */
-
-#define CPU_INLINE_ENABLE_DISPATCH FALSE
-
-/*
- * Should the body of the search loops in _Thread_queue_Enqueue_priority
- * be unrolled one time? In unrolled each iteration of the loop examines
- * two "nodes" on the chain being searched. Otherwise, only one node
- * is examined per iteration.
- *
- * If TRUE, then the loops are unrolled.
- * If FALSE, then the loops are not unrolled.
- *
- * The primary factor in making this decision is the cost of disabling
- * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
- * body of the loop. On some CPUs, the flash is more expensive than
- * one iteration of the loop body. In this case, it might be desirable
- * to unroll the loop. It is important to note that on some CPUs, this
- * code is the longest interrupt disable period in RTEMS. So it is
- * necessary to strike a balance when setting this parameter.
- */
-
-#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE
-
-/*
- * Does RTEMS manage a dedicated interrupt stack in software?
- *
- * If TRUE, then a stack is allocated in _ISR_Handler_initialization.
- * If FALSE, nothing is done.
- *
- * If the CPU supports a dedicated interrupt stack in hardware,
- * then it is generally the responsibility of the BSP to allocate it
- * and set it up.
- *
- * If the CPU does not support a dedicated interrupt stack, then
- * the porter has two options: (1) execute interrupts on the
- * stack of the interrupted task, and (2) have RTEMS manage a dedicated
- * interrupt stack.
- *
- * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
- * possible that both are FALSE for a particular CPU. Although it
- * is unclear what that would imply about the interrupt processing
- * procedure on that CPU.
- */
-
-#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
-
-/*
- * Does this CPU have hardware support for a dedicated interrupt stack?
- *
- * If TRUE, then it must be installed during initialization.
- * If FALSE, then no installation is performed.
- *
- * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
- * possible that both are FALSE for a particular CPU. Although it
- * is unclear what that would imply about the interrupt processing
- * procedure on that CPU.
- */
-
-/*
- * ACB: This is a lie, but it gets us a handle on a call to set up
- * a variable derived from the top of the interrupt stack.
- */
-
-#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
-
-/*
- * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
- *
- * If TRUE, then the memory is allocated during initialization.
- * If FALSE, then the memory is allocated during initialization.
- *
- * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
- * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
- */
-
-#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
-
-/*
- * Does the RTEMS invoke the user's ISR with the vector number and
- * a pointer to the saved interrupt frame (1) or just the vector
- * number (0)?
- */
-
-#define CPU_ISR_PASSES_FRAME_POINTER 1
-
-/*
- * Does the CPU have hardware floating point?
- *
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
- *
- * If there is a FP coprocessor such as the i387 or mc68881, then
- * the answer is TRUE.
- *
- * The macro name "PPC_HAS_FPU" should be made CPU specific.
- * It indicates whether or not this CPU model has FP support. For
- * example, it would be possible to have an i386_nofp CPU model
- * which set this to false to indicate that you have an i386 without
- * an i387 and wish to leave floating point support out of RTEMS.
- */
-
-#if ( PPC_HAS_FPU == 1 )
-#define CPU_HARDWARE_FP TRUE
-#else
-#define CPU_HARDWARE_FP FALSE
-#endif
-
-/*
- * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
- *
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
- *
- * So far, the only CPU in which this option has been used is the
- * HP PA-RISC. The HP C compiler and gcc both implicitly use the
- * floating point registers to perform integer multiplies. If
- * a function which you would not think utilize the FP unit DOES,
- * then one can not easily predict which tasks will use the FP hardware.
- * In this case, this option should be TRUE.
- *
- * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
- */
-
-#define CPU_ALL_TASKS_ARE_FP FALSE
-
-/*
- * Should the IDLE task have a floating point context?
- *
- * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- * and it has a floating point context which is switched in and out.
- * If FALSE, then the IDLE task does not have a floating point context.
- *
- * Setting this to TRUE negatively impacts the time required to preempt
- * the IDLE task from an interrupt because the floating point context
- * must be saved as part of the preemption.
- */
-
-#define CPU_IDLE_TASK_IS_FP FALSE
-
-/*
- * Should the saving of the floating point registers be deferred
- * until a context switch is made to another different floating point
- * task?
- *
- * If TRUE, then the floating point context will not be stored until
- * necessary. It will remain in the floating point registers and not
- * disturned until another floating point task is switched to.
- *
- * If FALSE, then the floating point context is saved when a floating
- * point task is switched out and restored when the next floating point
- * task is restored. The state of the floating point registers between
- * those two operations is not specified.
- *
- * If the floating point context does NOT have to be saved as part of
- * interrupt dispatching, then it should be safe to set this to TRUE.
- *
- * Setting this flag to TRUE results in using a different algorithm
- * for deciding when to save and restore the floating point context.
- * The deferred FP switch algorithm minimizes the number of times
- * the FP context is saved and restored. The FP context is not saved
- * until a context switch is made to another, different FP task.
- * Thus in a system with only one FP task, the FP context will never
- * be saved or restored.
- */
-/*
- * ACB Note: This could make debugging tricky..
- */
-
-#define CPU_USE_DEFERRED_FP_SWITCH TRUE
-
-/*
- * Does this port provide a CPU dependent IDLE task implementation?
- *
- * If TRUE, then the routine _CPU_Thread_Idle_body
- * must be provided and is the default IDLE thread body instead of
- * _CPU_Thread_Idle_body.
- *
- * If FALSE, then use the generic IDLE thread body if the BSP does
- * not provide one.
- *
- * This is intended to allow for supporting processors which have
- * a low power or idle mode. When the IDLE thread is executed, then
- * the CPU can be powered down.
- *
- * The order of precedence for selecting the IDLE thread body is:
- *
- * 1. BSP provided
- * 2. CPU dependent (if provided)
- * 3. generic (if no BSP and no CPU dependent)
- */
-
-#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
-
-/*
- * Does the stack grow up (toward higher addresses) or down
- * (toward lower addresses)?
- *
- * If TRUE, then the grows upward.
- * If FALSE, then the grows toward smaller addresses.
- */
-
-#define CPU_STACK_GROWS_UP FALSE
-
-/*
- * The following is the variable attribute used to force alignment
- * of critical RTEMS structures. On some processors it may make
- * sense to have these aligned on tighter boundaries than
- * the minimum requirements of the compiler in order to have as
- * much of the critical data area as possible in a cache line.
- *
- * The placement of this macro in the declaration of the variables
- * is based on the syntactically requirements of the GNU C
- * "__attribute__" extension. For example with GNU C, use
- * the following to force a structures to a 32 byte boundary.
- *
- * __attribute__ ((aligned (32)))
- *
- * NOTE: Currently only the Priority Bit Map table uses this feature.
- * To benefit from using this, the data must be heavily
- * used so it will stay in the cache and used frequently enough
- * in the executive to justify turning this on.
- */
-
-#define CPU_STRUCTURE_ALIGNMENT \
- __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
-
-/*
- * Define what is required to specify how the network to host conversion
- * routines are handled.
- */
-
-#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
-#define CPU_BIG_ENDIAN TRUE
-#define CPU_LITTLE_ENDIAN FALSE
-
-/*
- * The following defines the number of bits actually used in the
- * interrupt field of the task mode. How those bits map to the
- * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
- *
- * The interrupt level is bit mapped for the PowerPC family. The
- * bits are set to 0 to indicate that a particular exception source
- * enabled and 1 if it is disabled. This keeps with RTEMS convention
- * that interrupt level 0 means all sources are enabled.
- *
- * The bits are assigned to correspond to enable bits in the MSR.
- */
-
-#define PPC_INTERRUPT_LEVEL_ME 0x01
-#define PPC_INTERRUPT_LEVEL_EE 0x02
-#define PPC_INTERRUPT_LEVEL_CE 0x04
-
-/* XXX should these be maskable? */
-#if 0
-#define PPC_INTERRUPT_LEVEL_DE 0x08
-#define PPC_INTERRUPT_LEVEL_BE 0x10
-#define PPC_INTERRUPT_LEVEL_SE 0x20
-#endif
-
-#define CPU_MODES_INTERRUPT_MASK 0x00000007
-
-/*
- * Processor defined structures
- *
- * Examples structures include the descriptor tables from the i386
- * and the processor control structure on the i960ca.
- */
-
-/* may need to put some structures here. */
-
-/*
- * Contexts
- *
- * Generally there are 2 types of context to save.
- * 1. Interrupt registers to save
- * 2. Task level registers to save
- *
- * This means we have the following 3 context items:
- * 1. task level context stuff:: Context_Control
- * 2. floating point task stuff:: Context_Control_fp
- * 3. special interrupt level context :: Context_Control_interrupt
- *
- * On some processors, it is cost-effective to save only the callee
- * preserved registers during a task context switch. This means
- * that the ISR code needs to save those registers which do not
- * persist across function calls. It is not mandatory to make this
- * distinctions between the caller/callee saves registers for the
- * purpose of minimizing context saved during task switch and on interrupts.
- * If the cost of saving extra registers is minimal, simplicity is the
- * choice. Save the same context on interrupt entry as for tasks in
- * this case.
- *
- * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- * care should be used in designing the context area.
- *
- * On some CPUs with hardware floating point support, the Context_Control_fp
- * structure will not be used or it simply consist of an array of a
- * fixed number of bytes. This is done when the floating point context
- * is dumped by a "FP save context" type instruction and the format
- * is not really defined by the CPU. In this case, there is no need
- * to figure out the exact format -- only the size. Of course, although
- * this is enough information for RTEMS, it is probably not enough for
- * a debugger such as gdb. But that is another problem.
- */
-
-typedef struct {
- unsigned32 gpr1; /* Stack pointer for all */
- unsigned32 gpr2; /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
- unsigned32 gpr13; /* First non volatile PowerOpen, section ptr SVR4/EABI */
- unsigned32 gpr14; /* Non volatile for all */
- unsigned32 gpr15; /* Non volatile for all */
- unsigned32 gpr16; /* Non volatile for all */
- unsigned32 gpr17; /* Non volatile for all */
- unsigned32 gpr18; /* Non volatile for all */
- unsigned32 gpr19; /* Non volatile for all */
- unsigned32 gpr20; /* Non volatile for all */
- unsigned32 gpr21; /* Non volatile for all */
- unsigned32 gpr22; /* Non volatile for all */
- unsigned32 gpr23; /* Non volatile for all */
- unsigned32 gpr24; /* Non volatile for all */
- unsigned32 gpr25; /* Non volatile for all */
- unsigned32 gpr26; /* Non volatile for all */
- unsigned32 gpr27; /* Non volatile for all */
- unsigned32 gpr28; /* Non volatile for all */
- unsigned32 gpr29; /* Non volatile for all */
- unsigned32 gpr30; /* Non volatile for all */
- unsigned32 gpr31; /* Non volatile for all */
- unsigned32 cr; /* PART of the CR is non volatile for all */
- unsigned32 pc; /* Program counter/Link register */
- unsigned32 msr; /* Initial interrupt level */
-} Context_Control;
-
-typedef struct {
- /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
- * procedure calls. However, this would mean that the interrupt
- * frame had to hold f0-f13, and the fpscr. And as the majority
- * of tasks will not have an FP context, we will save the whole
- * context here.
- */
-#if (PPC_HAS_DOUBLE == 1)
- double f[32];
- double fpscr;
-#else
- float f[32];
- float fpscr;
-#endif
-} Context_Control_fp;
-
-typedef struct CPU_Interrupt_frame {
- unsigned32 stacklink; /* Ensure this is a real frame (also reg1 save) */
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
- unsigned32 dummy[13]; /* Used by callees: PowerOpen ABI */
-#else
- unsigned32 dummy[1]; /* Used by callees: SVR4/EABI */
-#endif
- /* This is what is left out of the primary contexts */
- unsigned32 gpr0;
- unsigned32 gpr2; /* play safe */
- unsigned32 gpr3;
- unsigned32 gpr4;
- unsigned32 gpr5;
- unsigned32 gpr6;
- unsigned32 gpr7;
- unsigned32 gpr8;
- unsigned32 gpr9;
- unsigned32 gpr10;
- unsigned32 gpr11;
- unsigned32 gpr12;
- unsigned32 gpr13; /* Play safe */
- unsigned32 gpr28; /* For internal use by the IRQ handler */
- unsigned32 gpr29; /* For internal use by the IRQ handler */
- unsigned32 gpr30; /* For internal use by the IRQ handler */
- unsigned32 gpr31; /* For internal use by the IRQ handler */
- unsigned32 cr; /* Bits of this are volatile, so no-one may save */
- unsigned32 ctr;
- unsigned32 xer;
- unsigned32 lr;
- unsigned32 pc;
- unsigned32 msr;
- unsigned32 pad[3];
-} CPU_Interrupt_frame;
-
-
-/*
- * The following table contains the information required to configure
- * the PowerPC processor specific parameters.
- */
-
-typedef struct {
- void (*pretasking_hook)( void );
- void (*predriver_hook)( void );
- void (*postdriver_hook)( void );
- void (*idle_task)( void );
- boolean do_zero_of_workspace;
- unsigned32 idle_task_stack_size;
- unsigned32 interrupt_stack_size;
- unsigned32 extra_mpci_receive_server_stack;
- void * (*stack_allocate_hook)( unsigned32 );
- void (*stack_free_hook)( void* );
- /* end of fields required on all CPUs */
-
- unsigned32 clicks_per_usec; /* Timer clicks per microsecond */
- void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *);
- boolean exceptions_in_RAM; /* TRUE if in RAM */
-
-#if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821))
- unsigned32 serial_per_sec; /* Serial clocks per second */
- boolean serial_external_clock;
- boolean serial_xon_xoff;
- boolean serial_cts_rts;
- unsigned32 serial_rate;
- unsigned32 timer_average_overhead; /* Average overhead of timer in ticks */
- unsigned32 timer_least_valid; /* Least valid number from timer */
- boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */
-#endif
-
-#if (defined(mpc860) || defined(mpc821))
- unsigned32 clock_speed; /* Speed of CPU in Hz */
-#endif
-} rtems_cpu_table;
-
-/*
- * Macros to access required entires in the CPU Table are in
- * the file rtems/system.h.
- */
-
-/*
- * Macros to access PowerPC specific additions to the CPU Table
- */
-
-#define rtems_cpu_configuration_get_clicks_per_usec() \
- (_CPU_Table.clicks_per_usec)
-
-#define rtems_cpu_configuration_get_spurious_handler() \
- (_CPU_Table.spurious_handler)
-
-#define rtems_cpu_configuration_get_exceptions_in_ram() \
- (_CPU_Table.exceptions_in_RAM)
-
-#if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821))
-
-#define rtems_cpu_configuration_get_serial_per_sec() \
- (_CPU_Table.serial_per_sec)
-
-#define rtems_cpu_configuration_get_serial_external_clock() \
- (_CPU_Table.serial_external_clock)
-
-#define rtems_cpu_configuration_get_serial_xon_xoff() \
- (_CPU_Table.serial_xon_xoff)
-
-#define rtems_cpu_configuration_get_serial_cts_rts() \
- (_CPU_Table.serial_cts_rts)
-
-#define rtems_cpu_configuration_get_serial_rate() \
- (_CPU_Table.serial_rate)
-
-#define rtems_cpu_configuration_get_timer_average_overhead() \
- (_CPU_Table.timer_average_overhead)
-
-#define rtems_cpu_configuration_get_timer_least_valid() \
- (_CPU_Table.timer_least_valid)
-
-#define rtems_cpu_configuration_get_timer_internal_clock() \
- (_CPU_Table.timer_internal_clock)
-
-#endif
-
-#if (defined(mpc860) || defined(mpc821))
-#define rtems_cpu_configuration_get_clock_speed() \
- (_CPU_Table.clock_speed)
-#endif
-
-
-/*
- * The following type defines an entry in the PPC's trap table.
- *
- * NOTE: The instructions chosen are RTEMS dependent although one is
- * obligated to use two of the four instructions to perform a
- * long jump. The other instructions load one register with the
- * trap type (a.k.a. vector) and another with the psr.
- */
-
-typedef struct {
- unsigned32 stwu_r1; /* stwu %r1, -(??+IP_END)(%1)*/
- unsigned32 stw_r0; /* stw %r0, IP_0(%r1) */
- unsigned32 li_r0_IRQ; /* li %r0, _IRQ */
- unsigned32 b_Handler; /* b PROC (_ISR_Handler) */
-} CPU_Trap_table_entry;
-
-/*
- * This variable is optional. It is used on CPUs on which it is difficult
- * to generate an "uninitialized" FP context. It is filled in by
- * _CPU_Initialize and copied into the task's FP context area during
- * _CPU_Context_Initialize.
- */
-
-/* EXTERN Context_Control_fp _CPU_Null_fp_context; */
-
-/*
- * On some CPUs, RTEMS supports a software managed interrupt stack.
- * This stack is allocated by the Interrupt Manager and the switch
- * is performed in _ISR_Handler. These variables contain pointers
- * to the lowest and highest addresses in the chunk of memory allocated
- * for the interrupt stack. Since it is unknown whether the stack
- * grows up or down (in general), this give the CPU dependent
- * code the option of picking the version it wants to use.
- *
- * NOTE: These two variables are required if the macro
- * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
- */
-
-SCORE_EXTERN void *_CPU_Interrupt_stack_low;
-SCORE_EXTERN void *_CPU_Interrupt_stack_high;
-
-/*
- * With some compilation systems, it is difficult if not impossible to
- * call a high-level language routine from assembly language. This
- * is especially true of commercial Ada compilers and name mangling
- * C++ ones. This variable can be optionally defined by the CPU porter
- * and contains the address of the routine _Thread_Dispatch. This
- * can make it easier to invoke that routine at the end of the interrupt
- * sequence (if a dispatch is necessary).
- */
-
-/* EXTERN void (*_CPU_Thread_dispatch_pointer)(); */
-
-/*
- * Nothing prevents the porter from declaring more CPU specific variables.
- */
-
-
-SCORE_EXTERN struct {
- unsigned32 volatile* Nest_level;
- unsigned32 volatile* Disable_level;
- void *Vector_table;
- void *Stack;
-#if (PPC_ABI == PPC_ABI_POWEROPEN)
- unsigned32 Dispatch_r2;
-#else
- unsigned32 Default_r2;
-#if (PPC_ABI != PPC_ABI_GCC27)
- unsigned32 Default_r13;
-#endif
-#endif
- volatile boolean *Switch_necessary;
- boolean *Signal;
-
- unsigned32 msr_initial;
-} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
-
-/*
- * The size of the floating point context area. On some CPUs this
- * will not be a "sizeof" because the format of the floating point
- * area is not defined -- only the size is. This is usually on
- * CPUs with a "floating point save context" instruction.
- */
-
-#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
-
-/*
- * (Optional) # of bytes for libmisc/stackchk to check
- * If not specifed, then it defaults to something reasonable
- * for most architectures.
- */
-
-#define CPU_STACK_CHECK_SIZE (128)
-
-/*
- * Amount of extra stack (above minimum stack size) required by
- * MPCI receive server thread. Remember that in a multiprocessor
- * system this thread must exist and be able to process all directives.
- */
-
-#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
-
-/*
- * This defines the number of entries in the ISR_Vector_table managed
- * by RTEMS.
- */
-
-#define CPU_INTERRUPT_NUMBER_OF_VECTORS (PPC_INTERRUPT_MAX)
-#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1)
-
-/*
- * This is defined if the port has a special way to report the ISR nesting
- * level. Most ports maintain the variable _ISR_Nest_level.
- */
-
-#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
-
-/*
- * Should be large enough to run all RTEMS tests. This insures
- * that a "reasonable" small application should not have any problems.
- */
-
-#define CPU_STACK_MINIMUM_SIZE (1024*8)
-
-/*
- * CPU's worst alignment requirement for data types on a byte boundary. This
- * alignment does not take into account the requirements for the stack.
- */
-
-#define CPU_ALIGNMENT (PPC_ALIGNMENT)
-
-/*
- * This number corresponds to the byte alignment requirement for the
- * heap handler. This alignment requirement may be stricter than that
- * for the data types alignment specified by CPU_ALIGNMENT. It is
- * common for the heap to follow the same alignment requirement as
- * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
- * then this should be set to CPU_ALIGNMENT.
- *
- * NOTE: This does not have to be a power of 2. It does have to
- * be greater or equal to than CPU_ALIGNMENT.
- */
-
-#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT)
-
-/*
- * This number corresponds to the byte alignment requirement for memory
- * buffers allocated by the partition manager. This alignment requirement
- * may be stricter than that for the data types alignment specified by
- * CPU_ALIGNMENT. It is common for the partition to follow the same
- * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
- * enough for the partition, then this should be set to CPU_ALIGNMENT.
- *
- * NOTE: This does not have to be a power of 2. It does have to
- * be greater or equal to than CPU_ALIGNMENT.
- */
-
-#define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT)
-
-/*
- * This number corresponds to the byte alignment requirement for the
- * stack. This alignment requirement may be stricter than that for the
- * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
- * is strict enough for the stack, then this should be set to 0.
- *
- * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
- */
-
-#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT)
-
-/*
- * ISR handler macros
- */
-
-void _CPU_Initialize_vectors(void);
-
-/*
- * Disable all interrupts for an RTEMS critical section. The previous
- * level is returned in _isr_cookie.
- */
-
-#define _CPU_MSR_Value( _msr_value ) \
- do { \
- _msr_value = 0; \
- asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
- } while (0)
-
-#define _CPU_MSR_SET( _msr_value ) \
-{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
-
-#if 0
-#define _CPU_ISR_Disable( _isr_cookie ) \
- { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
- _isr_cookie = 0; \
- asm volatile (
- "mfmsr %0" : \
- "=r" ((_isr_cookie)) : \
- "0" ((_isr_cookie)) \
- ); \
- asm volatile (
- "andc %1,%0,%1" : \
- "=r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
- "0" ((_isr_cookie)), "1" ((_disable_mask)) \
- ); \
- asm volatile (
- "mtmsr %1" : \
- "=r" ((_disable_mask)) : \
- "0" ((_disable_mask)) \
- ); \
- }
-#endif
-
-#define _CPU_ISR_Disable( _isr_cookie ) \
- { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
- _isr_cookie = 0; \
- asm volatile ( \
- "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
- "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
- "0" ((_isr_cookie)), "1" ((_disable_mask)) \
- ); \
- }
-
-/*
- * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- * This indicates the end of an RTEMS critical section. The parameter
- * _isr_cookie is not modified.
- */
-
-#define _CPU_ISR_Enable( _isr_cookie ) \
- { \
- asm volatile ( "mtmsr %0" : \
- "=r" ((_isr_cookie)) : \
- "0" ((_isr_cookie))); \
- }
-
-/*
- * This temporarily restores the interrupt to _isr_cookie before immediately
- * disabling them again. This is used to divide long RTEMS critical
- * sections into two or more parts. The parameter _isr_cookie is not
- * modified.
- *
- * NOTE: The version being used is not very optimized but it does
- * not trip a problem in gcc where the disable mask does not
- * get loaded. Check this for future (post 10/97 gcc versions.
- */
-
-#define _CPU_ISR_Flash( _isr_cookie ) \
- { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
- asm volatile ( \
- "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
- "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
- "0" ((_isr_cookie)), "1" ((_disable_mask)) \
- ); \
- }
-
-/*
- * Map interrupt level in task mode onto the hardware that the CPU
- * actually provides. Currently, interrupt levels which do not
- * map onto the CPU in a generic fashion are undefined. Someday,
- * it would be nice if these were "mapped" by the application
- * via a callout. For example, m68k has 8 levels 0 - 7, levels
- * 8 - 255 would be available for bsp/application specific meaning.
- * This could be used to manage a programmable interrupt controller
- * via the rtems_task_mode directive.
- */
-
-unsigned32 _CPU_ISR_Calculate_level(
- unsigned32 new_level
-);
-
-void _CPU_ISR_Set_level(
- unsigned32 new_level
-);
-
-unsigned32 _CPU_ISR_Get_level( void );
-
-void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-/* end of ISR handler macros */
-
-/*
- * Simple spin delay in microsecond units for device drivers.
- * This is very dependent on the clock speed of the target.
- */
-
-#define CPU_Get_timebase_low( _value ) \
- asm volatile( "mftb %0" : "=r" (_value) )
-
-#define rtems_bsp_delay( _microseconds ) \
- do { \
- unsigned32 start, ticks, now; \
- CPU_Get_timebase_low( start ) ; \
- ticks = (_microseconds) * _CPU_Table.clicks_per_usec; \
- do \
- CPU_Get_timebase_low( now ) ; \
- while (now - start < ticks); \
- } while (0)
-
-#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
- do { \
- unsigned32 start, now; \
- CPU_Get_timebase_low( start ); \
- do \
- CPU_Get_timebase_low( now ); \
- while (now - start < (_cycles)); \
- } while (0)
-
-
-
-/* Context handler macros */
-
-/*
- * Initialize the context to a state suitable for starting a
- * task after a context restore operation. Generally, this
- * involves:
- *
- * - setting a starting address
- * - preparing the stack
- * - preparing the stack and frame pointers
- * - setting the proper interrupt level in the context
- * - initializing the floating point context
- *
- * This routine generally does not set any unnecessary register
- * in the context. The state of the "general data" registers is
- * undefined at task start time.
- *
- * NOTE: Implemented as a subroutine for the SPARC port.
- */
-
-void _CPU_Context_Initialize(
- Context_Control *the_context,
- unsigned32 *stack_base,
- unsigned32 size,
- unsigned32 new_level,
- void *entry_point,
- boolean is_fp
-);
-
-/*
- * This routine is responsible for somehow restarting the currently
- * executing task. If you are lucky, then all that is necessary
- * is restoring the context. Otherwise, there will need to be
- * a special assembly routine which does something special in this
- * case. Context_Restore should work most of the time. It will
- * not work if restarting self conflicts with the stack frame
- * assumptions of restoring a context.
- */
-
-#define _CPU_Context_Restart_self( _the_context ) \
- _CPU_Context_restore( (_the_context) );
-
-/*
- * The purpose of this macro is to allow the initial pointer into
- * a floating point context area (used to save the floating point
- * context) to be at an arbitrary place in the floating point
- * context area.
- *
- * This is necessary because some FP units are designed to have
- * their context saved as a stack which grows into lower addresses.
- * Other FP units can be saved by simply moving registers into offsets
- * from the base of the context area. Finally some FP units provide
- * a "dump context" instruction which could fill in from high to low
- * or low to high based on the whim of the CPU designers.
- */
-
-#define _CPU_Context_Fp_start( _base, _offset ) \
- ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
-
-/*
- * This routine initializes the FP context area passed to it to.
- * There are a few standard ways in which to initialize the
- * floating point context. The code included for this macro assumes
- * that this is a CPU in which a "initial" FP context was saved into
- * _CPU_Null_fp_context and it simply copies it to the destination
- * context passed to it.
- *
- * Other models include (1) not doing anything, and (2) putting
- * a "null FP status word" in the correct place in the FP context.
- */
-
-#define _CPU_Context_Initialize_fp( _destination ) \
- { \
- ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \
- }
-
-/* end of Context handler macros */
-
-/* Fatal Error manager macros */
-
-/*
- * This routine copies _error into a known place -- typically a stack
- * location or a register, optionally disables interrupts, and
- * halts/stops the CPU.
- */
-
-#define _CPU_Fatal_halt( _error ) \
- _CPU_Fatal_error(_error)
-
-/* end of Fatal Error manager macros */
-
-/* Bitfield handler macros */
-
-/*
- * This routine sets _output to the bit number of the first bit
- * set in _value. _value is of CPU dependent type Priority_Bit_map_control.
- * This type may be either 16 or 32 bits wide although only the 16
- * least significant bits will be used.
- *
- * There are a number of variables in using a "find first bit" type
- * instruction.
- *
- * (1) What happens when run on a value of zero?
- * (2) Bits may be numbered from MSB to LSB or vice-versa.
- * (3) The numbering may be zero or one based.
- * (4) The "find first bit" instruction may search from MSB or LSB.
- *
- * RTEMS guarantees that (1) will never happen so it is not a concern.
- * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
- * _CPU_Priority_Bits_index(). These three form a set of routines
- * which must logically operate together. Bits in the _value are
- * set and cleared based on masks built by _CPU_Priority_mask().
- * The basic major and minor values calculated by _Priority_Major()
- * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
- * to properly range between the values returned by the "find first bit"
- * instruction. This makes it possible for _Priority_Get_highest() to
- * calculate the major and directly index into the minor table.
- * This mapping is necessary to ensure that 0 (a high priority major/minor)
- * is the first bit found.
- *
- * This entire "find first bit" and mapping process depends heavily
- * on the manner in which a priority is broken into a major and minor
- * components with the major being the 4 MSB of a priority and minor
- * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
- * to the lowest priority.
- *
- * If your CPU does not have a "find first bit" instruction, then
- * there are ways to make do without it. Here are a handful of ways
- * to implement this in software:
- *
- * - a series of 16 bit test instructions
- * - a "binary search using if's"
- * - _number = 0
- * if _value > 0x00ff
- * _value >>=8
- * _number = 8;
- *
- * if _value > 0x0000f
- * _value >=8
- * _number += 4
- *
- * _number += bit_set_table[ _value ]
- *
- * where bit_set_table[ 16 ] has values which indicate the first
- * bit set
- */
-
-#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
- { \
- asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
- "1" ((_value))); \
- }
-
-/* end of Bitfield handler macros */
-
-/*
- * This routine builds the mask which corresponds to the bit fields
- * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
- * for that routine.
- */
-
-#define _CPU_Priority_Mask( _bit_number ) \
- ( 0x80000000 >> (_bit_number) )
-
-/*
- * This routine translates the bit numbers returned by
- * _CPU_Bitfield_Find_first_bit() into something suitable for use as
- * a major or minor component of a priority. See the discussion
- * for that routine.
- */
-
-#define _CPU_Priority_bits_index( _priority ) \
- (_priority)
-
-/* end of Priority handler macros */
-
-/* variables */
-
-extern const unsigned32 _CPU_msrs[4];
-
-/* functions */
-
-/*
- * _CPU_Initialize
- *
- * This routine performs CPU dependent initialization.
- */
-
-void _CPU_Initialize(
- rtems_cpu_table *cpu_table,
- void (*thread_dispatch)
-);
-
-/*
- * _CPU_ISR_install_vector
- *
- * This routine installs an interrupt vector.
- */
-
-void _CPU_ISR_install_vector(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-/*
- * _CPU_Install_interrupt_stack
- *
- * This routine installs the hardware interrupt stack pointer.
- *
- * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
- * is TRUE.
- */
-
-void _CPU_Install_interrupt_stack( void );
-
-/*
- * _CPU_Context_switch
- *
- * This routine switches from the run context to the heir context.
- */
-
-void _CPU_Context_switch(
- Context_Control *run,
- Context_Control *heir
-);
-
-/*
- * _CPU_Context_restore
- *
- * This routine is generallu used only to restart self in an
- * efficient manner. It may simply be a label in _CPU_Context_switch.
- *
- * NOTE: May be unnecessary to reload some registers.
- */
-
-void _CPU_Context_restore(
- Context_Control *new_context
-);
-
-/*
- * _CPU_Context_save_fp
- *
- * This routine saves the floating point context passed to it.
- */
-
-void _CPU_Context_save_fp(
- void **fp_context_ptr
-);
-
-/*
- * _CPU_Context_restore_fp
- *
- * This routine restores the floating point context passed to it.
- */
-
-void _CPU_Context_restore_fp(
- void **fp_context_ptr
-);
-
-void _CPU_Fatal_error(
- unsigned32 _error
-);
-
-/* The following routine swaps the endian format of an unsigned int.
- * It must be static because it is referenced indirectly.
- *
- * This version will work on any processor, but if there is a better
- * way for your CPU PLEASE use it. The most common way to do this is to:
- *
- * swap least significant two bytes with 16-bit rotate
- * swap upper and lower 16-bits
- * swap most significant two bytes with 16-bit rotate
- *
- * Some CPUs have special instructions which swap a 32-bit quantity in
- * a single instruction (e.g. i486). It is probably best to avoid
- * an "endian swapping control bit" in the CPU. One good reason is
- * that interrupts would probably have to be disabled to insure that
- * an interrupt does not try to access the same "chunk" with the wrong
- * endian. Another good reason is that on some CPUs, the endian bit
- * endianness for ALL fetches -- both code and data -- so the code
- * will be fetched incorrectly.
- */
-
-static inline unsigned int CPU_swap_u32(
- unsigned int value
-)
-{
- unsigned32 swapped;
-
- asm volatile("rlwimi %0,%1,8,24,31;"
- "rlwimi %0,%1,24,16,23;"
- "rlwimi %0,%1,8,8,15;"
- "rlwimi %0,%1,24,0,7;" :
- "=&r" ((swapped)) : "r" ((value)));
-
- return( swapped );
-}
-
-#define CPU_swap_u16( value ) \
- (((value&0xff) << 8) | ((value >> 8)&0xff))
-
-/*
- * Routines to access the decrementer register
- */
-
-#define PPC_Set_decrementer( _clicks ) \
- do { \
- asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
- } while (0)
-
-/*
- * Routines to access the time base register
- */
-
-static inline unsigned64 PPC_Get_timebase_register( void )
-{
- unsigned32 tbr_low;
- unsigned32 tbr_high;
- unsigned32 tbr_high_old;
- unsigned64 tbr;
-
- do {
- asm volatile( "mftbu %0" : "=r" (tbr_high_old));
- asm volatile( "mftb %0" : "=r" (tbr_low));
- asm volatile( "mftbu %0" : "=r" (tbr_high));
- } while ( tbr_high_old != tbr_high );
-
- tbr = tbr_high;
- tbr <<= 32;
- tbr |= tbr_low;
- return tbr;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/c/src/exec/score/cpu/powerpc/rtems/powerpc/registers.h b/c/src/exec/score/cpu/powerpc/rtems/powerpc/registers.h
deleted file mode 100644
index cfc6362a21..0000000000
--- a/c/src/exec/score/cpu/powerpc/rtems/powerpc/registers.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * This file contains some powerpc MSR and registers access definitions.
- *
- * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
- * Canon Centre Recherche France.
- *
- * Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
- * Surrey Satellite Technology Limited
- *
- *
- * The license and distribution terms for this file may be
- * found in found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#ifndef __rtems_powerpc_registers_h
-#define __rtems_powerpc_registers_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Bit encodings for Machine State Register (MSR) */
-#define MSR_POW (1<<18) /* Enable Power Management */
-#define MSR_TGPR (1<<17) /* TLB Update registers in use */
-#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */
-#define MSR_EE (1<<15) /* External Interrupt enable */
-#define MSR_PR (1<<14) /* Supervisor/User privilege */
-#define MSR_FP (1<<13) /* Floating Point enable */
-#define MSR_ME (1<<12) /* Machine Check enable */
-#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
-#define MSR_SE (1<<10) /* Single Step */
-#define MSR_BE (1<<9) /* Branch Trace */
-#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
-#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
-#define MSR_IR (1<<5) /* Instruction MMU enable */
-#define MSR_DR (1<<4) /* Data MMU enable */
-#define MSR_RI (1<<1) /* Recoverable Exception */
-#define MSR_LE (1<<0) /* Little-Endian enable */
-
-#define MSR_ MSR_ME|MSR_RI
-#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
-#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
-
-/* Bit encodings for Hardware Implementation Register (HID0)
- on PowerPC 603, 604, etc. processors (not 601). */
-#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
-#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
-#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
-#define HID0_SBCLK (1<<27)
-#define HID0_EICE (1<<26)
-#define HID0_ECLK (1<<25)
-#define HID0_PAR (1<<24)
-#define HID0_DOZE (1<<23)
-#define HID0_NAP (1<<22)
-#define HID0_SLEEP (1<<21)
-#define HID0_DPM (1<<20)
-#define HID0_ICE (1<<15) /* Instruction Cache Enable */
-#define HID0_DCE (1<<14) /* Data Cache Enable */
-#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
-#define HID0_DLOCK (1<<12) /* Data Cache Lock */
-#define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */
-#define HID0_DCI (1<<10) /* Data Cache Invalidate */
-#define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */
-#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache [Enable] */
-#define HID0_BHTE (1<<2) /* Branch History Table Enable */
-#define HID0_BTCD (1<<1) /* Branch target cache disable */
-
-/* fpscr settings */
-#define FPSCR_FX (1<<31)
-#define FPSCR_FEX (1<<30)
-
-#define _MACH_prep 1
-#define _MACH_Pmac 2 /* pmac or pmac clone (non-chrp) */
-#define _MACH_chrp 4 /* chrp machine */
-#define _MACH_mbx 8 /* Motorola MBX board */
-#define _MACH_apus 16 /* amiga with phase5 powerup */
-#define _MACH_fads 32 /* Motorola FADS board */
-
-/* see residual.h for these */
-#define _PREP_Motorola 0x01 /* motorola prep */
-#define _PREP_Firm 0x02 /* firmworks prep */
-#define _PREP_IBM 0x00 /* ibm prep */
-#define _PREP_Bull 0x03 /* bull prep */
-
-/* these are arbitrary */
-#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
-#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
-
-#define _GLOBAL(n)\
- .globl n;\
-n:
-
-#define TBRU 269 /* Time base Upper/Lower (Reading) */
-#define TBRL 268
-#define TBWU 284 /* Time base Upper/Lower (Writing) */
-#define TBWL 285
-#define XER 1
-#define LR 8
-#define CTR 9
-#define HID0 1008 /* Hardware Implementation */
-#define PVR 287 /* Processor Version */
-#define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */
-#define IBAT0L 529
-#define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */
-#define IBAT1L 531
-#define IBAT2U 532 /* Instruction BAT #2 Upper/Lower */
-#define IBAT2L 533
-#define IBAT3U 534 /* Instruction BAT #3 Upper/Lower */
-#define IBAT3L 535
-#define DBAT0U 536 /* Data BAT #0 Upper/Lower */
-#define DBAT0L 537
-#define DBAT1U 538 /* Data BAT #1 Upper/Lower */
-#define DBAT1L 539
-#define DBAT2U 540 /* Data BAT #2 Upper/Lower */
-#define DBAT2L 541
-#define DBAT3U 542 /* Data BAT #3 Upper/Lower */
-#define DBAT3L 543
-#define DMISS 976 /* TLB Lookup/Refresh registers */
-#define DCMP 977
-#define HASH1 978
-#define HASH2 979
-#define IMISS 980
-#define ICMP 981
-#define RPA 982
-#define SDR1 25 /* MMU hash base register */
-#define DAR 19 /* Data Address Register */
-#define SPR0 272 /* Supervisor Private Registers */
-#define SPRG0 272
-#define SPR1 273
-#define SPRG1 273
-#define SPR2 274
-#define SPRG2 274
-#define SPR3 275
-#define SPRG3 275
-#define DSISR 18
-#define SRR0 26 /* Saved Registers (exception) */
-#define SRR1 27
-#define IABR 1010 /* Instruction Address Breakpoint */
-#define DEC 22 /* Decrementer */
-#define EAR 282 /* External Address Register */
-#define L2CR 1017 /* PPC 750 L2 control register */
-
-#define THRM1 1020
-#define THRM2 1021
-#define THRM3 1022
-#define THRM1_TIN 0x1
-#define THRM1_TIV 0x2
-#define THRM1_THRES (0x7f<<2)
-#define THRM1_TID (1<<29)
-#define THRM1_TIE (1<<30)
-#define THRM1_V (1<<31)
-#define THRM3_E (1<<31)
-
-/* Segment Registers */
-#define SR0 0
-#define SR1 1
-#define SR2 2
-#define SR3 3
-#define SR4 4
-#define SR5 5
-#define SR6 6
-#define SR7 7
-#define SR8 8
-#define SR9 9
-#define SR10 10
-#define SR11 11
-#define SR12 12
-#define SR13 13
-#define SR14 14
-#define SR15 15
-
-#ifndef ASM
-/*
- * Routines to access the time base register
- */
-
-static inline unsigned long long PPC_Get_timebase_register( void )
-{
- unsigned long tbr_low;
- unsigned long tbr_high;
- unsigned long tbr_high_old;
- unsigned long long tbr;
-
- do {
- asm volatile( "mftbu %0" : "=r" (tbr_high_old));
- asm volatile( "mftb %0" : "=r" (tbr_low));
- asm volatile( "mftbu %0" : "=r" (tbr_high));
- } while ( tbr_high_old != tbr_high );
-
- tbr = tbr_high;
- tbr <<= 32;
- tbr |= tbr_low;
- return tbr;
-}
-
-static inline void PPC_Set_timebase_register (unsigned long long tbr)
-{
- unsigned long tbr_low;
- unsigned long tbr_high;
-
- tbr_low = (tbr & 0xffffffff) ;
- tbr_high = (tbr >> 32) & 0xffffffff;
- asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
- asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
-
-}
-#endif
-
-#define _CPU_MSR_GET( _msr_value ) \
- do { \
- _msr_value = 0; \
- asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
- } while (0)
-
-#define _CPU_MSR_SET( _msr_value ) \
-{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
-
-#define _CPU_ISR_Disable( _isr_cookie ) \
- { register unsigned int _disable_mask = MSR_EE; \
- _isr_cookie = 0; \
- asm volatile ( \
- "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
- "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
- "0" ((_isr_cookie)), "1" ((_disable_mask)) \
- ); \
- }
-
-
-/*
- * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- * This indicates the end of an RTEMS critical section. The parameter
- * _isr_cookie is not modified.
- */
-
-#define _CPU_ISR_Enable( _isr_cookie ) \
- { \
- asm volatile ( "mtmsr %0" : \
- "=r" ((_isr_cookie)) : \
- "0" ((_isr_cookie))); \
- }
-
-/*
- * This temporarily restores the interrupt to _isr_cookie before immediately
- * disabling them again. This is used to divide long RTEMS critical
- * sections into two or more parts. The parameter _isr_cookie is not
- * modified.
- *
- * NOTE: The version being used is not very optimized but it does
- * not trip a problem in gcc where the disable mask does not
- * get loaded. Check this for future (post 10/97 gcc versions.
- */
-
-#define _CPU_ISR_Flash( _isr_cookie ) \
- { register unsigned int _disable_mask = MSR_EE; \
- asm volatile ( \
- "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
- "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
- "0" ((_isr_cookie)), "1" ((_disable_mask)) \
- ); \
- }
-
-
-/* end of ISR handler macros */
-
-/*
- * Simple spin delay in microsecond units for device drivers.
- * This is very dependent on the clock speed of the target.
- */
-
-#define CPU_Get_timebase_low( _value ) \
- asm volatile( "mftb %0" : "=r" (_value) )
-
-#define rtems_bsp_delay( _microseconds ) \
- do { \
- unsigned32 start, ticks, now; \
- CPU_Get_timebase_low( start ) ; \
- ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \
- do \
- CPU_Get_timebase_low( now ) ; \
- while (now - start < ticks); \
- } while (0)
-
-#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
- do { \
- unsigned32 start, now; \
- CPU_Get_timebase_low( start ); \
- do \
- CPU_Get_timebase_low( now ); \
- while (now - start < (_cycles)); \
- } while (0)
-
-#define PPC_Set_decrementer( _clicks ) \
- do { \
- asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
- } while (0)
-
-#define PPC_Get_decrementer( _clicks ) \
- asm volatile( "mfdec %0" : "=r" (_clicks) )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __rtems_powerpc_registers_h */
diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/.cvsignore b/c/src/exec/score/cpu/powerpc/rtems/score/.cvsignore
deleted file mode 100644
index 282522db03..0000000000
--- a/c/src/exec/score/cpu/powerpc/rtems/score/.cvsignore
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile
-Makefile.in
diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/cpu.h b/c/src/exec/score/cpu/powerpc/rtems/score/cpu.h
deleted file mode 100644
index 7e181da7f8..0000000000
--- a/c/src/exec/score/cpu/powerpc/rtems/score/cpu.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * $Id$
- */
-
-#ifndef _rtems_score_cpu_h
-#define _rtems_score_cpu_h
-
-#include <rtems/score/ppc.h> /* pick up machine definitions */
-#ifndef ASM
-#include <rtems/score/types.h>
-#endif
-
-#ifdef _OLD_EXCEPTIONS
-#include <rtems/old-exceptions/cpu.h>
-#else
-#include <rtems/new-exceptions/cpu.h>
-#endif
-
-#endif
diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h b/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h
deleted file mode 100644
index 6771919023..0000000000
--- a/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h
+++ /dev/null
@@ -1,733 +0,0 @@
-/* ppc.h
- *
- * This file contains definitions for the IBM/Motorola PowerPC
- * family members.
- *
- * Author: Andrew Bray <andy@i-cubed.co.uk>
- *
- * COPYRIGHT (c) 1995 by i-cubed ltd.
- *
- * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
- * MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
- * Surrey Satellite Technology Limited
- *
- * To anyone who acknowledges that this file is provided "AS IS"
- * without any express or implied warranty:
- * permission to use, copy, modify, and distribute this file
- * for any purpose is hereby granted without fee, provided that
- * the above copyright notice and this notice appears in all
- * copies, and that the name of i-cubed limited not be used in
- * advertising or publicity pertaining to distribution of the
- * software without specific, written prior permission.
- * i-cubed limited makes no representations about the suitability
- * of this software for any purpose.
- *
- * Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
- *
- * COPYRIGHT (c) 1989-1997.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may in
- * the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- *
- * Note:
- * This file is included by both C and assembler code ( -DASM )
- *
- * $Id$
- */
-
-
-#ifndef _INCLUDE_PPC_h
-#define _INCLUDE_PPC_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/types.h>
-
-/*
- * Define the name of the CPU family.
- */
-
-#define CPU_NAME "PowerPC"
-
-/*
- * This file contains the information required to build
- * RTEMS for a particular member of the PowerPC family. It does
- * this by setting variables to indicate which implementation
- * dependent features are present in a particular member
- * of the family.
- *
- * The following architectural feature definitions are defaulted
- * unless specifically set by the model definition:
- *
- * + PPC_INTERRUPT_MAX - 16
- * + PPC_CACHE_ALIGNMENT - 32
- * + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE
- * + PPC_HAS_EXCEPTION_PREFIX - 1
- * + PPC_HAS_FPU - 1
- * + PPC_HAS_DOUBLE - 1 if PPC_HAS_FPU,
- * - 0 otherwise
- * + PPC_USE_MULTIPLE - 0
- */
-
-/*
- * Define the low power mode models
- *
- * Standard: as defined for 603e
- * Nap Mode: nap mode only (604)
- * XXX 403GB, 603, 603e, 604, 821
- */
-
-#define PPC_LOW_POWER_MODE_NONE 0
-#define PPC_LOW_POWER_MODE_STANDARD 1
-
-/*
- * Figure out all CPU Model Feature Flags based upon compiler
- * predefines.
- */
-
-#if defined(ppc403) || defined(ppc405)
-/*
- * IBM 403
- *
- * Developed for 403GA. Book checked for 403GB.
- *
- * Does not have user mode.
- */
-
-#if defined(ppc403)
-#define CPU_MODEL_NAME "PowerPC 403"
-#elif defined (ppc405)
-#define CPU_MODEL_NAME "PowerPC 405"
-#endif
-#define PPC_ALIGNMENT 4
-#define PPC_CACHE_ALIGNMENT 16
-#define PPC_HAS_RFCI 1
-#define PPC_HAS_FPU 0
-#define PPC_USE_MULTIPLE 1
-#define PPC_I_CACHE 2048
-#define PPC_D_CACHE 1024
-
-#define PPC_HAS_EXCEPTION_PREFIX 0
-#define PPC_HAS_EVPR 1
-
-#elif defined(mpc555)
-
-#define CPU_MODEL_NAME "PowerPC 555"
-
-/* Copied from mpc505 */
-#define PPC_ALIGNMENT 4
-#define PPC_CACHE_ALIGNMENT 16
-
-/* Based on comments by Sergei Organov <osv@Javad.RU> */
-#define PPC_I_CACHE 0
-#define PPC_D_CACHE 0
-
-#elif defined(mpc505) || defined(mpc509)
-/*
- * Submitted by Sergei Organov <osv@Javad.RU> as a patch against
- * 3.6.0 long after 4.0 was released. This is just an attempt
- * to get the setting correct.
- */
-
-#define CPU_MODEL_NAME "PowerPC 505/509"
-
-#define PPC_ALIGNMENT 4
-#define PPC_CACHE_ALIGNMENT 16
-#define PPC_I_CACHE 4096
-#define PPC_D_CACHE 0
-
-
-#elif defined(ppc601)
-
-/*
- * Submitted with original port -- book checked only.
- */
-
-#define CPU_MODEL_NAME "PowerPC 601"
-
-#define PPC_ALIGNMENT 8
-#define PPC_USE_MULTIPLE 1
-#define PPC_I_CACHE 0
-#define PPC_D_CACHE 32768
-
-#elif defined(ppc602)
-/*
- * Submitted with original port -- book checked only.
- */
-
-#define CPU_MODEL_NAME "PowerPC 602"
-
-#define PPC_ALIGNMENT 4
-#define PPC_HAS_DOUBLE 0
-#define PPC_I_CACHE 4096
-#define PPC_D_CACHE 4096
-
-#elif defined(ppc603)
-/*
- * Submitted with original port -- book checked only.
- */
-
-#define CPU_MODEL_NAME "PowerPC 603"
-
-#define PPC_ALIGNMENT 8
-#define PPC_I_CACHE 8192
-#define PPC_D_CACHE 8192
-
-#elif defined(ppc603e)
-
-#define CPU_MODEL_NAME "PowerPC 603e"
-/*
- * Submitted with original port.
- *
- * Known to work on real hardware.
- */
-
-#define PPC_ALIGNMENT 8
-#define PPC_I_CACHE 16384
-#define PPC_D_CACHE 16384
-
-#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
-
-#elif defined(mpc604)
-/*
- * Submitted with original port -- book checked only.
- */
-
-#define CPU_MODEL_NAME "PowerPC 604"
-
-#define PPC_ALIGNMENT 8
-#define PPC_I_CACHE 16384
-#define PPC_D_CACHE 16384
-
-#elif defined(mpc860)
-/*
- * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
- * with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
- */
-#define CPU_MODEL_NAME "PowerPC MPC860"
-
-#define PPC_ALIGNMENT 4
-#define PPC_I_CACHE 4096
-#define PPC_D_CACHE 4096
-#define PPC_CACHE_ALIGNMENT 16
-#define PPC_INTERRUPT_MAX 71
-#define PPC_HAS_FPU 0
-#define PPC_HAS_DOUBLE 0
-#define PPC_USE_MULTIPLE 1
-
-#define PPC_MSR_0 0x00009000
-#define PPC_MSR_1 0x00001000
-#define PPC_MSR_2 0x00001000
-#define PPC_MSR_3 0x00000000
-
-#elif defined(mpc821)
-/*
- * Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
- */
-#define CPU_MODEL_NAME "PowerPC MPC821"
-
-#define PPC_ALIGNMENT 4
-#define PPC_I_CACHE 4096
-#define PPC_D_CACHE 4096
-#define PPC_CACHE_ALIGNMENT 16
-#define PPC_INTERRUPT_MAX 71
-#define PPC_HAS_FPU 0
-#define PPC_HAS_DOUBLE 0
-
-#define PPC_MSR_0 0x00009000
-#define PPC_MSR_1 0x00001000
-#define PPC_MSR_2 0x00001000
-#define PPC_MSR_3 0x00000000
-
-#elif defined(mpc750)
-
-#define CPU_MODEL_NAME "PowerPC 750"
-
-#define PPC_ALIGNMENT 8
-#define PPC_I_CACHE 16384
-#define PPC_D_CACHE 16384
-
-#elif defined(mpc7400)
-
-#define CPU_MODEL_NAME "PowerPC 7400"
-
-#define PPC_ALIGNMENT 8
-#define PPC_I_CACHE 32768
-#define PPC_D_CACHE 32768
-
-#elif defined(mpc8260)
-/*
- * Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
- */
-#define CPU_MODEL_NAME "PowerPC MPC8260"
-
-#define PPC_ALIGNMENT 4
-#define PPC_I_CACHE 16384
-#define PPC_D_CACHE 16384
-#define PPC_CACHE_ALIGNMENT 32
-#define PPC_INTERRUPT_MAX 125
-/*#define PPC_HAS_FPU 0 */ /* my 8260 is one the few with no FPU */
-#define PPC_HAS_FPU 1 /* the rest do have one */
-#define PPC_HAS_DOUBLE 1
-#define PPC_USE_MULTIPLE 1
-#else
-
-#error "Unsupported CPU Model"
-
-#endif
-
-/*
- * Application binary interfaces.
- *
- * PPC_ABI MUST be defined as one of these.
- * Only PPC_ABI_POWEROPEN is currently fully supported.
- * Only EABI will be supported in the end when
- * the tools are there.
- * Only big endian is currently supported.
- */
-/*
- * PowerOpen ABI. This is Andy's hack of the
- * PowerOpen ABI to ELF. ELF rather than a
- * XCOFF assembler is used. This may work
- * if PPC_ASM == PPC_ASM_XCOFF is defined.
- */
-#define PPC_ABI_POWEROPEN 0
-/*
- * GCC 2.7.0 munched version of EABI, with
- * PowerOpen calling convention and stack frames,
- * but EABI style indirect function calls.
- */
-#define PPC_ABI_GCC27 1
-/*
- * SVR4 ABI
- */
-#define PPC_ABI_SVR4 2
-/*
- * Embedded ABI
- */
-#define PPC_ABI_EABI 3
-
-/*
- * Default to the EABI used by current GNU tools
- */
-
-#ifndef PPC_ABI
-#define PPC_ABI PPC_ABI_EABI
-#endif
-
-#if (PPC_ABI == PPC_ABI_POWEROPEN)
-#define PPC_STACK_ALIGNMENT 8
-#elif (PPC_ABI == PPC_ABI_GCC27)
-#define PPC_STACK_ALIGNMENT 8
-#elif (PPC_ABI == PPC_ABI_SVR4)
-#define PPC_STACK_ALIGNMENT 16
-#elif (PPC_ABI == PPC_ABI_EABI)
-#define PPC_STACK_ALIGNMENT 8
-#else
-#error "PPC_ABI is not properly defined"
-#endif
-#ifndef PPC_ABI
-#error "PPC_ABI is not properly defined"
-#endif
-
-/*
- * Assemblers.
- * PPC_ASM MUST be defined as one of these.
- *
- * PPC_ASM_ELF: ELF assembler. Currently used for all ABIs.
- * PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI.
- *
- * NOTE: Only PPC_ABI_ELF is currently fully supported.
- */
-
-#define PPC_ASM_ELF 0
-#define PPC_ASM_XCOFF 1
-
-/*
- * Default to the assembler format used by the current GNU tools.
- */
-
-#ifndef PPC_ASM
-#define PPC_ASM PPC_ASM_ELF
-#endif
-
-/*
- * If the maximum number of exception sources has not been defined,
- * then default it to 16.
- */
-
-#ifndef PPC_INTERRUPT_MAX
-#define PPC_INTERRUPT_MAX 16
-#endif
-
-/*
- * Unless specified otherwise, the cache line size is defaulted to 32.
- *
- * The derive the power of 2 the cache line is.
- */
-
-#ifndef PPC_CACHE_ALIGNMENT
-#define PPC_CACHE_ALIGNMENT 32
-#endif
-
-#if (PPC_CACHE_ALIGNMENT == 16)
-#define PPC_CACHE_ALIGN_POWER 4
-#elif (PPC_CACHE_ALIGNMENT == 32)
-#define PPC_CACHE_ALIGN_POWER 5
-#else
-#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
-#endif
-
-/*
- * Unless otherwise specified, assume the model has an IP/EP bit to
- * set the exception address prefix.
- */
-
-#ifndef PPC_HAS_EXCEPTION_PREFIX
-#define PPC_HAS_EXCEPTION_PREFIX 1
-#endif
-
-/*
- * Unless otherwise specified, assume the model does NOT have
- * 403 style EVPR register to set the exception address prefix.
- */
-
-#ifndef PPC_HAS_EVPR
-#define PPC_HAS_EVPR 0
-#endif
-
-/*
- * If no low power mode model was specified, then assume there is none.
- */
-
-#ifndef PPC_LOW_POWER_MODE
-#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
-#endif
-
-/*
- * Unless specified above, then assume the model has FP support.
- */
-
-#ifndef PPC_HAS_FPU
-#define PPC_HAS_FPU 1
-#endif
-
-/*
- * Unless specified above, If the model has FP support, it is assumed to
- * support doubles (8-byte floating point numbers).
- *
- * If the model does NOT have FP support, then the model does
- * NOT have double length FP registers.
- */
-
-#ifndef PPC_HAS_DOUBLE
-#if (PPC_HAS_FPU)
-#define PPC_HAS_DOUBLE 1
-#else
-#define PPC_HAS_DOUBLE 0
-#endif
-#endif
-
-/*
- * Unless specified above, then assume the model does NOT have critical
- * interrupt support.
- */
-
-#ifndef PPC_HAS_RFCI
-#define PPC_HAS_RFCI 0
-#endif
-
-/*
- * Unless specified above, do not use the load/store multiple instructions
- * in a context switch.
- */
-
-#ifndef PPC_USE_MULTIPLE
-#define PPC_USE_MULTIPLE 0
-#endif
-
-/*
- * The following exceptions are not maskable, and are not
- * necessarily predictable, so cannot be offered to RTEMS:
- * Alignment exception - handled by the CPU module
- * Data exceptions.
- * Instruction exceptions.
- */
-
-/*
- * Base Interrupt vectors supported on all models.
- */
-#define PPC_IRQ_SYSTEM_RESET 0 /* 0x00100 - System reset. */
-#define PPC_IRQ_MCHECK 1 /* 0x00200 - Machine check */
-#define PPC_IRQ_PROTECT 2 /* 0x00300 - Protection violation */
-#define PPC_IRQ_ISI 3 /* 0x00400 - Instruction Fetch error */
-#define PPC_IRQ_EXTERNAL 4 /* 0x00500 - External interrupt */
-#define PPC_IRQ_ALIGNMENT 5 /* 0X00600 - Alignment exception */
-#define PPC_IRQ_PROGRAM 6 /* 0x00700 - Program exception */
-#define PPC_IRQ_NOFP 7 /* 0x00800 - Floating point unavailable */
-#define PPC_IRQ_DECREMENTER 8 /* 0x00900 - Decrementer interrupt */
-#define PPC_IRQ_RESERVED_A 9 /* 0x00a00 - Implementation Reserved */
-#define PPC_IRQ_RESERVED_B 10 /* 0x00b00 - Implementation Reserved */
-#define PPC_IRQ_SCALL 11 /* 0x00c00 - System call */
-#define PPC_IRQ_TRACE 12 /* 0x00d00 - Trace Exception */
-#define PPC_IRQ_FP_ASST 13 /* ox00e00 - Floating point assist */
-#define PPC_STD_IRQ_LAST PPC_IRQ_FP_ASST
-
-#define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET
-
-#if defined(ppc403) || defined(ppc405)
-
-#define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
-#define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
-#define PPC_IRQ_FIT (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer */
-#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer */
-#define PPC_IRQ_DEBUG (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions */
-#define PPC_IRQ_LAST PPC_IRQ_DEBUG
-
-#elif defined(mpc505) || defined(mpc509)
-#define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */
-#define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+ 2)
-#define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+ 3)
-#define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+ 4)
-#define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+ 5)
-
-#elif defined(ppc601)
-#define PPC_IRQ_TRACE (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
-#define PPC_IRQ_LAST PPC_IRQ_TRACE
-
-#elif defined(ppc602)
-#define PPC_IRQ_LAST (PPC_STD_IRQ_LAST)
-
-#elif defined(ppc603)
-#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
-#define PPC_IRQ_DATA_LOAD (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
-#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss */
-#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
-#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */
-#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT
-
-#elif defined(ppc603e)
-#define PPC_TLB_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
-#define PPC_TLB_LOAD_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load */
-#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
-#define PPC_IRQ_ADDRBRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
-#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */
-#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT
-
-
-#elif defined(mpc604)
-#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break */
-#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
-#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT
-
-#elif defined(mpc860) || defined(mpc821)
-#define PPC_IRQ_EMULATE (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation */
-#define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
-#define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
-#define PPC_IRQ_INST_ERR (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
-#define PPC_IRQ_DATA_ERR (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
-#define PPC_IRQ_DATA_BPNT (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
-#define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
-#define PPC_IRQ_IO_BPNT (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
-#define PPC_IRQ_DEV_PORT (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
-#define PPC_IRQ_IRQ0 (PPC_STD_IRQ_LAST + 10)
-#define PPC_IRQ_LVL0 (PPC_STD_IRQ_LAST + 11)
-#define PPC_IRQ_IRQ1 (PPC_STD_IRQ_LAST + 12)
-#define PPC_IRQ_LVL1 (PPC_STD_IRQ_LAST + 13)
-#define PPC_IRQ_IRQ2 (PPC_STD_IRQ_LAST + 14)
-#define PPC_IRQ_LVL2 (PPC_STD_IRQ_LAST + 15)
-#define PPC_IRQ_IRQ3 (PPC_STD_IRQ_LAST + 16)
-#define PPC_IRQ_LVL3 (PPC_STD_IRQ_LAST + 17)
-#define PPC_IRQ_IRQ4 (PPC_STD_IRQ_LAST + 18)
-#define PPC_IRQ_LVL4 (PPC_STD_IRQ_LAST + 19)
-#define PPC_IRQ_IRQ5 (PPC_STD_IRQ_LAST + 20)
-#define PPC_IRQ_LVL5 (PPC_STD_IRQ_LAST + 21)
-#define PPC_IRQ_IRQ6 (PPC_STD_IRQ_LAST + 22)
-#define PPC_IRQ_LVL6 (PPC_STD_IRQ_LAST + 23)
-#define PPC_IRQ_IRQ7 (PPC_STD_IRQ_LAST + 24)
-#define PPC_IRQ_LVL7 (PPC_STD_IRQ_LAST + 25)
-#define PPC_IRQ_CPM_ERROR (PPC_STD_IRQ_LAST + 26)
-#define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 27)
-#define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 28)
-#define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 29)
-#define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 30)
-#define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 31)
-#define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 32)
-#define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 33)
-#define PPC_IRQ_CPM_RESERVED_8 (PPC_STD_IRQ_LAST + 34)
-#define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 35)
-#define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 36)
-#define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 37)
-#define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 38)
-#define PPC_IRQ_CPM_RESERVED_D (PPC_STD_IRQ_LAST + 39)
-#define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 40)
-#define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 41)
-#define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 42)
-#define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 43)
-#define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 44)
-#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
-#define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 46)
-#define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 47)
-#define PPC_IRQ_CPM_SDMA_ERROR (PPC_STD_IRQ_LAST + 48)
-#define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 49)
-#define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 50)
-#define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 51)
-#define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 52)
-#define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 53)
-#define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 54)
-#define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 55)
-#define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 56)
-#define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 57)
-
-#define PPC_IRQ_LAST PPC_IRQ_CPM_PC15
-
-#elif defined(mpc8260)
-
-#define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
-#define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
-#define PPC_IRQ_DATA_L_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
-#define PPC_IRQ_DATA_S_MISS (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
-#define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
-#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
-/* 0x1600 - 0x2F00 reserved */
-#define PPC_IRQ_CPM_NONE (PPC_STD_IRQ_LAST + 50)
-#define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 51)
-#define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 52)
-#define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 53)
-#define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 54)
-#define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 55)
-#define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 56)
-#define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 57)
-#define PPC_IRQ_CPM_IDMA3 (PPC_STD_IRQ_LAST + 58)
-#define PPC_IRQ_CPM_IDMA4 (PPC_STD_IRQ_LAST + 59)
-#define PPC_IRQ_CPM_SDMA (PPC_STD_IRQ_LAST + 60)
-#define PPC_IRQ_CPM_RES_A (PPC_STD_IRQ_LAST + 61)
-#define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 62)
-#define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 63)
-#define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 64)
-#define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 65)
-#define PPC_IRQ_CPM_TMCNT (PPC_STD_IRQ_LAST + 66)
-#define PPC_IRQ_CPM_PIT (PPC_STD_IRQ_LAST + 67)
-#define PPC_IRQ_CPM_RES_B (PPC_STD_IRQ_LAST + 68)
-#define PPC_IRQ_CPM_IRQ1 (PPC_STD_IRQ_LAST + 69)
-#define PPC_IRQ_CPM_IRQ2 (PPC_STD_IRQ_LAST + 70)
-#define PPC_IRQ_CPM_IRQ3 (PPC_STD_IRQ_LAST + 71)
-#define PPC_IRQ_CPM_IRQ4 (PPC_STD_IRQ_LAST + 72)
-#define PPC_IRQ_CPM_IRQ5 (PPC_STD_IRQ_LAST + 73)
-#define PPC_IRQ_CPM_IRQ6 (PPC_STD_IRQ_LAST + 74)
-#define PPC_IRQ_CPM_IRQ7 (PPC_STD_IRQ_LAST + 75)
-#define PPC_IRQ_CPM_RES_C (PPC_STD_IRQ_LAST + 76)
-#define PPC_IRQ_CPM_RES_D (PPC_STD_IRQ_LAST + 77)
-#define PPC_IRQ_CPM_RES_E (PPC_STD_IRQ_LAST + 78)
-#define PPC_IRQ_CPM_RES_F (PPC_STD_IRQ_LAST + 79)
-#define PPC_IRQ_CPM_RES_G (PPC_STD_IRQ_LAST + 80)
-#define PPC_IRQ_CPM_RES_H (PPC_STD_IRQ_LAST + 81)
-#define PPC_IRQ_CPM_FCC1 (PPC_STD_IRQ_LAST + 82)
-#define PPC_IRQ_CPM_FCC2 (PPC_STD_IRQ_LAST + 83)
-#define PPC_IRQ_CPM_FCC3 (PPC_STD_IRQ_LAST + 84)
-#define PPC_IRQ_CPM_RES_I (PPC_STD_IRQ_LAST + 85)
-#define PPC_IRQ_CPM_MCC1 (PPC_STD_IRQ_LAST + 86)
-#define PPC_IRQ_CPM_MCC2 (PPC_STD_IRQ_LAST + 87)
-#define PPC_IRQ_CPM_RES_J (PPC_STD_IRQ_LAST + 88)
-#define PPC_IRQ_CPM_RES_K (PPC_STD_IRQ_LAST + 89)
-#define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 90)
-#define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 91)
-#define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 92)
-#define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 93)
-#define PPC_IRQ_CPM_RES_L (PPC_STD_IRQ_LAST + 94)
-#define PPC_IRQ_CPM_RES_M (PPC_STD_IRQ_LAST + 95)
-#define PPC_IRQ_CPM_RES_N (PPC_STD_IRQ_LAST + 96)
-#define PPC_IRQ_CPM_RES_O (PPC_STD_IRQ_LAST + 97)
-#define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 98)
-#define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 99)
-#define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 100)
-#define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 101)
-#define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 102)
-#define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 103)
-#define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 104)
-#define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 105)
-#define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 106)
-#define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 107)
-#define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 108)
-#define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 109)
-#define PPC_IRQ_CPM_PC3 (PPC_STD_IRQ_LAST + 110)
-#define PPC_IRQ_CPM_PC2 (PPC_STD_IRQ_LAST + 111)
-#define PPC_IRQ_CPM_PC1 (PPC_STD_IRQ_LAST + 112)
-#define PPC_IRQ_CPM_PC0 (PPC_STD_IRQ_LAST + 113)
-
-#define PPC_IRQ_LAST PPC_IRQ_CPM_PC0
-
-#endif
-
-
-/*
- * If the maximum number of exception sources is too low,
- * then fix it
- */
-
-#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
-#undef PPC_INTERRUPT_MAX
-#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
-#endif
-
-/*
- * Machine Status Register (MSR) Constants Used by RTEMS
- */
-
-/*
- * Some PPC model manuals refer to the Exception Prefix (EP) bit as
- * IP for no apparent reason.
- */
-
-#define PPC_MSR_RI 0x000000002 /* bit 30 - recoverable exception */
-#define PPC_MSR_DR 0x000000010 /* bit 27 - data address translation */
-#define PPC_MSR_IR 0x000000020 /* bit 26 - instruction addr translation*/
-
-#if (PPC_HAS_EXCEPTION_PREFIX)
-#define PPC_MSR_EP 0x000000040 /* bit 25 - exception prefix */
-#else
-#define PPC_MSR_EP 0x000000000 /* bit 25 - exception prefix */
-#endif
-
-#if (PPC_HAS_FPU)
-#define PPC_MSR_FP 0x000002000 /* bit 18 - floating point enable */
-#else
-#define PPC_MSR_FP 0x000000000 /* bit 18 - floating point enable */
-#endif
-
-#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
-#define PPC_MSR_POW 0x000000000 /* bit 13 - power management enable */
-#else
-#define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */
-#endif
-
-#define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */
-#define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */
-
-#if (PPC_HAS_RFCI)
-#define PPC_MSR_CE 0x000020000 /* bit 14 - critical interrupt enable */
-#else
-#define PPC_MSR_CE 0x000000000 /* bit 14 - critical interrupt enable */
-#endif
-
-#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
-
-/*
- * Initial value for the FPSCR register
- */
-
-#define PPC_INIT_FPSCR 0x000000f8
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ! _INCLUDE_PPC_h */
-/* end of include file */
-
-
diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/types.h b/c/src/exec/score/cpu/powerpc/rtems/score/types.h
deleted file mode 100644
index 13fdf35538..0000000000
--- a/c/src/exec/score/cpu/powerpc/rtems/score/types.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* types.h
- *
- * This include file contains type definitions pertaining to the PowerPC
- * processor family.
- *
- * Author: Andrew Bray <andy@i-cubed.co.uk>
- *
- * COPYRIGHT (c) 1995 by i-cubed ltd.
- *
- * To anyone who acknowledges that this file is provided "AS IS"
- * without any express or implied warranty:
- * permission to use, copy, modify, and distribute this file
- * for any purpose is hereby granted without fee, provided that
- * the above copyright notice and this notice appears in all
- * copies, and that the name of i-cubed limited not be used in
- * advertising or publicity pertaining to distribution of the
- * software without specific, written prior permission.
- * i-cubed limited makes no representations about the suitability
- * of this software for any purpose.
- *
- * Derived from c/src/exec/cpu/no_cpu/no_cputypes.h:
- *
- * COPYRIGHT (c) 1989-1997.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may in
- * the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#ifndef __PPC_TYPES_h
-#define __PPC_TYPES_h
-
-#ifndef ASM
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * This section defines the basic types for this processor.
- */
-
-typedef unsigned char unsigned8; /* unsigned 8-bit integer */
-typedef unsigned short unsigned16; /* unsigned 16-bit integer */
-typedef unsigned int unsigned32; /* unsigned 32-bit integer */
-typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
-
-typedef unsigned32 Priority_Bit_map_control;
-
-typedef signed char signed8; /* 8-bit signed integer */
-typedef signed short signed16; /* 16-bit signed integer */
-typedef signed int signed32; /* 32-bit signed integer */
-typedef signed long long signed64; /* 64 bit signed integer */
-
-typedef unsigned32 boolean; /* Boolean value */
-
-typedef float single_precision; /* single precision float */
-typedef double double_precision; /* double precision float */
-
-typedef void ppc_isr;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !ASM */
-
-#endif
-/* end of include file */
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-19 14:41:36 +0000