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authorJoel Sherrill <joel.sherrill@OARcorp.com>1998-10-01 18:50:43 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>1998-10-01 18:50:43 +0000
commit086836e10e022ccb1da931a975a307c7f326b14a (patch)
tree92b5d3d2d8f0705762166654b10d6fa71669fdd6 /c/src/exec/score/cpu/powerpc/ppc.h
parentRegenerated. (diff)
downloadrtems-086836e10e022ccb1da931a975a307c7f326b14a.tar.bz2
Patch from Thomas Doerfler <td@imd.m.isar.de> to improve 403 support.
- c/src/exec/score/cpu/powerpc/ppc.h: some small changes (added ppc403 characteristics like a exception vector prefix register, some special register definitions). I am quite sure, they are compatible with the existing sources, although I did not check - c/src/exec/score/cpu/powerpc/cpu.c: There is one severe limitation in the exception entries: Due to the current code arrangement, the "branch absolute" to the ISR handler may only jump to the first 128MByte or the last 128MByte of the 4GByte address range. When the ppc403 is running out of ROM, the ROM functions are located in the last 128MByte (0xFFF00000 and up). These addresses were not handled correctly (sign reduced) in "install_raw_handler". The change I added should work on existing ppc BSPs aswell...
Diffstat (limited to '')
-rw-r--r--c/src/exec/score/cpu/powerpc/ppc.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/c/src/exec/score/cpu/powerpc/ppc.h b/c/src/exec/score/cpu/powerpc/ppc.h
index 56fd820709..a4b091c430 100644
--- a/c/src/exec/score/cpu/powerpc/ppc.h
+++ b/c/src/exec/score/cpu/powerpc/ppc.h
@@ -112,6 +112,7 @@ extern "C" {
#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_IBM4xx
#define PPC_HAS_EXCEPTION_PREFIX 0
+#define PPC_HAS_EVPR 1
#elif defined(ppc601)
/*
@@ -287,6 +288,15 @@ extern "C" {
#endif
/*
+ * Unless otherwise specified, assume the model does NOT have
+ * 403 style EVPR register to set the exception address prefix.
+ */
+
+#ifndef PPC_HAS_EVPR
+#define PPC_HAS_EVPR 0
+#endif
+
+/*
* If no low power mode model was specified, then assume there is none.
*/