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authorJoel Sherrill <joel.sherrill@OARcorp.com>2001-11-08 23:32:59 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2001-11-08 23:32:59 +0000
commit95e0ca9337eb7a5e30abd44235d6c0a077c7892f (patch)
tree271981c061529e2d7f6bc1159e3f1fa402c5918c /c/src/exec/score/cpu/powerpc/asm.h
parent0aa09608669a84cc1a6d3914c5ba85857e876dd2 (diff)
downloadrtems-95e0ca9337eb7a5e30abd44235d6c0a077c7892f.tar.bz2
2001-11-08 Dennis Ehlin (ECS) <Dennis.Ehlin@ecs.ericsson.se>
This modification is part of the submitted modifications necessary to support the IBM PPC405 family. This submission was reviewed by Thomas Doerfler <Thomas.Doerfler@imd-systems.de> who ensured it did not negatively impact the ppc403 BSPs. The submission and tracking process was captured as PR50. * shared/asm.h, shared/ppc.h: Added PPC405 support.
Diffstat (limited to 'c/src/exec/score/cpu/powerpc/asm.h')
-rw-r--r--c/src/exec/score/cpu/powerpc/asm.h13
1 files changed, 10 insertions, 3 deletions
diff --git a/c/src/exec/score/cpu/powerpc/asm.h b/c/src/exec/score/cpu/powerpc/asm.h
index 3c2e28ad5c..a33ee828d4 100644
--- a/c/src/exec/score/cpu/powerpc/asm.h
+++ b/c/src/exec/score/cpu/powerpc/asm.h
@@ -164,10 +164,10 @@
*/
#define srr0 0x01a
#define srr1 0x01b
-#ifdef ppc403
+#if defined(ppc403) || defined(ppc405)
#define srr2 0x3de /* IBM 400 series only */
#define srr3 0x3df /* IBM 400 series only */
-#endif /* ppc403 */
+#endif /* ppc403 or ppc405 */
#define sprg0 0x110
#define sprg1 0x111
@@ -177,15 +177,22 @@
#define dar 0x013 /* Data Address Register */
#define dec 0x016 /* Decrementer Register */
-#if defined(ppc403)
+#if defined(ppc403) || defined(ppc405)
/* the following SPR/DCR registers exist only in IBM 400 series */
#define dear 0x3d5
#define evpr 0x3d6 /* SPR: exception vector prefix register */
#define iccr 0x3fb /* SPR: instruction cache control reg. */
#define dccr 0x3fa /* SPR: data cache control reg. */
+#if defined (ppc403)
#define exisr 0x040 /* DCR: external interrupt status register */
#define exier 0x042 /* DCR: external interrupt enable register */
+#endif /* ppc403 */
+#if defined(ppc405)
+#define exisr 0x0C0 /* DCR: external interrupt status register */
+#define exier 0x0C2 /* DCR: external interrupt enable register */
+#endif /* ppc405 */
+
#define br0 0x080 /* DCR: memory bank register 0 */
#define br1 0x081 /* DCR: memory bank register 1 */
#define br2 0x082 /* DCR: memory bank register 2 */