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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-05-18 17:41:16 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-05-18 17:41:16 +0000 |
| commit | 5a064dca14ba83898ec91aaf791fb004248a46ef (patch) | |
| tree | 3d51e127d687cc139c122401de561f1e0ffa8779 /c/src/exec/score/cpu/mips/cpu_asm.S | |
| parent | Regenerated. (diff) | |
| download | rtems-5a064dca14ba83898ec91aaf791fb004248a46ef.tar.bz2 | |
Patch from Daniel Kelley <dank@icube.com>:
I found a small buglet in the mips64orion _CPU_ISR_Set_level; the
original was wiping out the level argument, and then comparing the
current interrupt level with some random value of v0. See patch below.
Diffstat (limited to '')
| -rw-r--r-- | c/src/exec/score/cpu/mips/cpu_asm.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/c/src/exec/score/cpu/mips/cpu_asm.S b/c/src/exec/score/cpu/mips/cpu_asm.S index 7dcb8fbda7..125b4d58d4 100644 --- a/c/src/exec/score/cpu/mips/cpu_asm.S +++ b/c/src/exec/score/cpu/mips/cpu_asm.S @@ -153,12 +153,12 @@ ENDFRAME(_CPU_ISR_Get_level) FRAME(_CPU_ISR_Set_level,sp,0,ra) nop - mfc0 a0,C0_SR + mfc0 v0,C0_SR nop - andi a0,SR_EXL - beqz a0,_CPU_ISR_Set_1 /* normalize a0 */ + andi v0,SR_EXL + beqz v0,_CPU_ISR_Set_1 /* normalize v0 */ nop - li a0,1 + li v0,1 _CPU_ISR_Set_1: beq v0,a0,_CPU_ISR_Set_exit /* if (current_level != new_level ) */ nop |