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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-03-15 19:47:36 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-03-15 19:47:36 +0000 |
| commit | 293c0e30f8067a51ea716fb3700c8d81c0da13d1 (patch) | |
| tree | cc613e15131777fbf9f8fb5ab58f51335f1e1300 /c/src/exec/score/cpu/mips/cpu_asm.S | |
| parent | 2002-03-15 Eric Norum <eric.norum@usask.ca> (diff) | |
| download | rtems-293c0e30f8067a51ea716fb3700c8d81c0da13d1.tar.bz2 | |
2002-03-13 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
* rtems/score/cpu.h: Fixed register numbering in comments and made
interrupt enable/disable more robust.
Diffstat (limited to 'c/src/exec/score/cpu/mips/cpu_asm.S')
| -rw-r--r-- | c/src/exec/score/cpu/mips/cpu_asm.S | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/c/src/exec/score/cpu/mips/cpu_asm.S b/c/src/exec/score/cpu/mips/cpu_asm.S index e19a9f4f4e..63796714c1 100644 --- a/c/src/exec/score/cpu/mips/cpu_asm.S +++ b/c/src/exec/score/cpu/mips/cpu_asm.S @@ -945,10 +945,19 @@ _ISR_Handler_1: #if __mips == 3 li t1,SR_EXL | SR_IE #elif __mips == 1 - li t1,SR_IEC | SR_KUC /* ints off, kernel mode on (kernel mode enabled is bit clear..argh!) */ + /* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */ + li t1,SR_IEC | SR_KUP | SR_KUC #endif not t1 and t0, t1 + +#if __mips == 1 + /* make sure previous int enable is on because we're returning from an interrupt + ** which means interrupts have to be enabled + */ + li t1,SR_IEP + or t0,t1 +#endif MTC0 t0, C0_SR NOP |