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authorJoel Sherrill <joel.sherrill@OARcorp.com>2002-02-01 15:00:30 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2002-02-01 15:00:30 +0000
commite6dec71c2703bd6b54e957746931b532d2fb44fa (patch)
tree7c103f1cdc6e9c63bcb05fc3719313320aabf3f2 /c/src/exec/score/cpu/mips/ChangeLog
parent6d41a8747caf7d7139a23a32bcb0cf155295d663 (diff)
downloadrtems-e6dec71c2703bd6b54e957746931b532d2fb44fa.tar.bz2
2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu.c: Enhancements and fixes for modifying the SR when changing the interrupt level. * cpu_asm.S: Fixed handling of FP enable bit so it is properly managed on a per-task basis, improved handling of interrupt levels, and made deferred FP contexts work on the MIPS. * rtems/score/cpu.h: Modified to support above changes.
Diffstat (limited to 'c/src/exec/score/cpu/mips/ChangeLog')
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diff --git a/c/src/exec/score/cpu/mips/ChangeLog b/c/src/exec/score/cpu/mips/ChangeLog
index c69cde159a..ff63919afb 100644
--- a/c/src/exec/score/cpu/mips/ChangeLog
+++ b/c/src/exec/score/cpu/mips/ChangeLog
@@ -1,3 +1,12 @@
+2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov>
+
+ * cpu.c: Enhancements and fixes for modifying the SR when changing
+ the interrupt level.
+ * cpu_asm.S: Fixed handling of FP enable bit so it is properly
+ managed on a per-task basis, improved handling of interrupt levels,
+ and made deferred FP contexts work on the MIPS.
+ * rtems/score/cpu.h: Modified to support above changes.
+
2002-01-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* rtems/Makefile.am: Removed.