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authorJoel Sherrill <joel.sherrill@OARcorp.com>2002-03-15 19:47:36 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2002-03-15 19:47:36 +0000
commit293c0e30f8067a51ea716fb3700c8d81c0da13d1 (patch)
treecc613e15131777fbf9f8fb5ab58f51335f1e1300 /c/src/exec/score/cpu/mips/ChangeLog
parent5ab8aef5719d30b8d44b28d50e0dbf132e7a511f (diff)
downloadrtems-293c0e30f8067a51ea716fb3700c8d81c0da13d1.tar.bz2
2002-03-13 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug. * rtems/score/cpu.h: Fixed register numbering in comments and made interrupt enable/disable more robust.
Diffstat (limited to 'c/src/exec/score/cpu/mips/ChangeLog')
-rw-r--r--c/src/exec/score/cpu/mips/ChangeLog7
1 files changed, 6 insertions, 1 deletions
diff --git a/c/src/exec/score/cpu/mips/ChangeLog b/c/src/exec/score/cpu/mips/ChangeLog
index 888947d33c..ddb8d5f32a 100644
--- a/c/src/exec/score/cpu/mips/ChangeLog
+++ b/c/src/exec/score/cpu/mips/ChangeLog
@@ -1,5 +1,10 @@
-2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov>
+2002-03-13 Greg Menke <gregory.menke@gsfc.nasa.gov>
+ * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
+ * rtems/score/cpu.h: Fixed register numbering in comments and made
+ interrupt enable/disable more robust.
+
+2002-03-05 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Added support for the debug exception vector, cleaned
up the exception processing & exception return stuff. Re-added
EPC in the task context structure so the gdb stub will know where