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authorRalf Corsepius <ralf.corsepius@rtems.org>2002-07-22 09:46:48 +0000
committerRalf Corsepius <ralf.corsepius@rtems.org>2002-07-22 09:46:48 +0000
commit2b3e9d9b244e279ef5693a7cf5dacc7903164af5 (patch)
tree955e5242d4d08a8ec747c8350f55003bb9d4b519 /c/src/exec/score/cpu/m68k
parentRemove everything. (diff)
downloadrtems-2b3e9d9b244e279ef5693a7cf5dacc7903164af5.tar.bz2
Remove, moved to cpukit.
Diffstat (limited to 'c/src/exec/score/cpu/m68k')
-rw-r--r--c/src/exec/score/cpu/m68k/.cvsignore14
-rw-r--r--c/src/exec/score/cpu/m68k/ChangeLog145
-rw-r--r--c/src/exec/score/cpu/m68k/Makefile.am54
-rw-r--r--c/src/exec/score/cpu/m68k/asm.h144
-rw-r--r--c/src/exec/score/cpu/m68k/configure.ac30
-rw-r--r--c/src/exec/score/cpu/m68k/cpu.c213
-rw-r--r--c/src/exec/score/cpu/m68k/cpu_asm.S263
-rw-r--r--c/src/exec/score/cpu/m68k/m68302.h661
-rw-r--r--c/src/exec/score/cpu/m68k/m68360.h889
-rw-r--r--c/src/exec/score/cpu/m68k/memcpy.c87
-rw-r--r--c/src/exec/score/cpu/m68k/qsm.h205
-rw-r--r--c/src/exec/score/cpu/m68k/rtems/.cvsignore2
-rw-r--r--c/src/exec/score/cpu/m68k/rtems/score/.cvsignore2
-rw-r--r--c/src/exec/score/cpu/m68k/rtems/score/cpu.h678
-rw-r--r--c/src/exec/score/cpu/m68k/rtems/score/m68k.h416
-rw-r--r--c/src/exec/score/cpu/m68k/rtems/score/types.h57
-rw-r--r--c/src/exec/score/cpu/m68k/sim.h334
17 files changed, 0 insertions, 4194 deletions
diff --git a/c/src/exec/score/cpu/m68k/.cvsignore b/c/src/exec/score/cpu/m68k/.cvsignore
deleted file mode 100644
index d29e5050f5..0000000000
--- a/c/src/exec/score/cpu/m68k/.cvsignore
+++ /dev/null
@@ -1,14 +0,0 @@
-Makefile
-Makefile.in
-aclocal.m4
-autom4te.cache
-config.cache
-config.guess
-config.log
-config.status
-config.sub
-configure
-depcomp
-install-sh
-missing
-mkinstalldirs
diff --git a/c/src/exec/score/cpu/m68k/ChangeLog b/c/src/exec/score/cpu/m68k/ChangeLog
deleted file mode 100644
index 6cf037728b..0000000000
--- a/c/src/exec/score/cpu/m68k/ChangeLog
+++ /dev/null
@@ -1,145 +0,0 @@
-2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: RTEMS_TOP(../../../..).
-
-2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems.S: Remove.
- * Makefile.am: Reflect changes above.
-
-2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Remove RTEMS_PROJECT_ROOT.
-
-2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Add RTEMS_PROG_CCAS
-
-2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
- Add AC_PROG_RANLIB.
-
-2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
- Use ../../../aclocal.
-
-2002-05-28 Chris Johns <ccj@acm.org>
-
- * rtems/score/m68k.h: Per PR227, mc68060 does not require FPSP
- since it is now multilib'ed.
-
-2001-04-03 Joel Sherrill <joel@OARcorp.com>
-
- * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
- * include/rtems/score/ispsh7750.h, score/ispsh7750.c: Account for
- name change.
-
-2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac:
- AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
- AM_INIT_AUTOMAKE([no-define foreign 1.6]).
- * Makefile.am: Remove AUTOMAKE_OPTIONS.
-
-2002-03-15 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/score/m68k.h: m68k_swap_u32 fix typo.
-
-2002-03-06 Victor V. Vengerov <vvv@oktet.ru>
-
- * rtems/score/m68k.h [M68K_COLDFIRE_ARCH] (CPU_swap_u16, CPU_swap_u32):
- Generic implementation of endian swap primitives added for Coldfire
- family.
-
-2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/Makefile.am: Removed.
- * rtems/score/Makefile.am: Removed.
- * configure.ac: Reflect changes above.
- * Makefile.am: Reflect changes above.
-
-2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Add multilib support.
-
-2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * .cvsignore: Add autom4te.cache for autoconf > 2.52.
- * configure.in: Remove.
- * configure.ac: New file, generated from configure.in by autoupdate.
-
-2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
- * Makefile.am: Use 'PREINSTALL_FILES ='.
-
-2001-08-09 Chris Johns <ccj@acm.org>
-
- * cpu_asm.S: This patch was co-developed with Eric Norum
- <eric.norum@usask.ca>. It closes a one instruction window
- on some m68k CPU cores. It fixes symptoms seen as:
- 1) No more `interrupt handler invoked twice for
- a single interrupt'.
- 2) No more `lockup when mc68360 CPM and PIT interrupts
- are at different levels'.
- It does insert a little more overhead on machines without hardware
- interrupt stacks but correctness has a price.
-
-2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am, rtems/score/Makefile.am:
- Apply include_*HEADERS instead of H_FILES.
-
-2001-01-03 Joel Sherrill <joel@OARcorp.com>
-
- * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
- * cpu_asm.S: Modify to properly dereference _ISR_Vector_table
- now that it is dynamically allocated.
-
-2000-12-19 Joel Sherrill <joel@OARcorp.com>
-
- * cpu.c: Do not read or write raw interrupt vector table if
- we are on a CPU that does not have a %vbr register and the
- BSP is configured as having the table in ROM.
-
-2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
-
-2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
-
-2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
- Switch to GNU canonicalization.
-
-2000-10-19 Antti P Miettinen <anmietti@trshp.ntc.nokia.com>
-
- * rtems/score/cpu.h: define CPU_Exception_frame for rdbg.
- * m68302.h: Make buffer pointer in m302_SCC_bd volatile.
-
-2000-10-12 John S Gwynne <jgwynne@mrcday.com>
-
- * sim.h: These changes enable RTEMS to automatically generate
- the ram_init file used by gdb with the BDM patches. The 332 has
- on-board chip select lines (for RAM and FLASH) that must be
- configured before use of these peripherals. These patches parse
- data from start.c where the chip select lines are configured in
- the runtime executable and automatically generates the gdb
- initialization file using the same settings. A great time saver.
- A similar file, ram_init_FW (flash writable), is also generated
- that the flash programming tool uses.
- * BSP/start/start.c: Must be modified to support above.
- * BSP/start/ram_init.ld, BSP/start/ram_init.sed: New files.
-
-2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Include compile.am.
-
-2000-08-10 Joel Sherrill <joel@OARcorp.com>
-
- * ChangeLog: New file.
diff --git a/c/src/exec/score/cpu/m68k/Makefile.am b/c/src/exec/score/cpu/m68k/Makefile.am
deleted file mode 100644
index 147cbfae7d..0000000000
--- a/c/src/exec/score/cpu/m68k/Makefile.am
+++ /dev/null
@@ -1,54 +0,0 @@
-##
-## $Id$
-##
-
-ACLOCAL_AMFLAGS = -I ../../../aclocal
-
-include $(top_srcdir)/../../../automake/multilib.am
-include $(top_srcdir)/../../../automake/compile.am
-include $(top_srcdir)/../../../automake/lib.am
-
-$(PROJECT_INCLUDE)/%.h: %.h
- $(INSTALL_DATA) $< $@
-
-$(PROJECT_INCLUDE):
- $(mkinstalldirs) $@
-
-$(PROJECT_INCLUDE)/rtems:
- $(mkinstalldirs) $@
-
-$(PROJECT_INCLUDE)/rtems/score:
- $(mkinstalldirs) $@
-
-include_HEADERS = asm.h m68302.h m68360.h qsm.h sim.h
-PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%)
-
-include_rtems_scoredir = $(includedir)/rtems/score
-include_rtems_score_HEADERS = \
- rtems/score/cpu.h \
- rtems/score/m68k.h \
- rtems/score/types.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \
- $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h)
-
-C_FILES = cpu.c memcpy.c
-C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
-
-S_FILES = cpu_asm.S
-S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o)
-
-REL = $(ARCH)/rtems-cpu.rel
-
-rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES)
-
-$(REL): $(rtems_cpu_rel_OBJECTS)
- $(make-rel)
-
-all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \
- $(TMPINSTALL_FILES)
-
-.PRECIOUS: $(REL)
-
-EXTRA_DIST = cpu.c cpu_asm.S memcpy.c
-
-include $(top_srcdir)/../../../automake/local.am
diff --git a/c/src/exec/score/cpu/m68k/asm.h b/c/src/exec/score/cpu/m68k/asm.h
deleted file mode 100644
index 6c388fb396..0000000000
--- a/c/src/exec/score/cpu/m68k/asm.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* asm.h
- *
- * This include file attempts to address the problems
- * caused by incompatible flavors of assemblers and
- * toolsets. It primarily addresses variations in the
- * use of leading underscores on symbols and the requirement
- * that register names be preceded by a %.
- *
- *
- * NOTE: The spacing in the use of these macros
- * is critical to them working as advertised.
- *
- * COPYRIGHT:
- *
- * This file is based on similar code found in newlib available
- * from ftp.cygnus.com. The file which was used had no copyright
- * notice. This file is freely distributable as long as the source
- * of the file is noted. This file is:
- *
- * COPYRIGHT (c) 1994-1997.
- * On-Line Applications Research Corporation (OAR).
- *
- * $Id$
- */
-
-#ifndef __M68k_ASM_h
-#define __M68k_ASM_h
-
-/*
- * Indicate we are in an assembly file and get the basic CPU definitions.
- */
-
-#ifndef ASM
-#define ASM
-#endif
-#include <rtems/score/cpuopts.h>
-#include <rtems/score/cpu.h>
-
-/*
- * Recent versions of GNU cpp define variables which indicate the
- * need for underscores and percents. If not using GNU cpp or
- * the version does not support this, then you will obviously
- * have to define these as appropriate.
- */
-
-#ifndef __USER_LABEL_PREFIX__
-#define __USER_LABEL_PREFIX__ _
-#endif
-
-#ifndef __REGISTER_PREFIX__
-#define __REGISTER_PREFIX__
-#endif
-
-/* ANSI concatenation macros. */
-
-#define CONCAT1(a, b) CONCAT2(a, b)
-#define CONCAT2(a, b) a ## b
-
-/* Use the right prefix for global labels. */
-
-#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
-
-/* Use the right prefix for registers. */
-
-#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
-
-#define d0 REG (d0)
-#define d1 REG (d1)
-#define d2 REG (d2)
-#define d3 REG (d3)
-#define d4 REG (d4)
-#define d5 REG (d5)
-#define d6 REG (d6)
-#define d7 REG (d7)
-#define a0 REG (a0)
-#define a1 REG (a1)
-#define a2 REG (a2)
-#define a3 REG (a3)
-#define a4 REG (a4)
-#define a5 REG (a5)
-#define a6 REG (a6)
-#define a7 REG (a7)
-#define sp REG (sp)
-
-#define msp REG (msp)
-#define usp REG (usp)
-#define isp REG (isp)
-#define sr REG (sr)
-#define vbr REG (vbr)
-#define dfc REG (dfc)
-#define sfc REG (sfc)
-
-/* mcf52xx special regs */
-#define cacr REG (cacr)
-#define acr0 REG (acr0)
-#define acr1 REG (acr1)
-#define rambar0 REG (rambar0)
-#define mbar REG (mbar)
-
-
-#define fp0 REG (fp0)
-#define fp1 REG (fp1)
-#define fp2 REG (fp2)
-#define fp3 REG (fp3)
-#define fp4 REG (fp4)
-#define fp5 REG (fp5)
-#define fp6 REG (fp6)
-#define fp7 REG (fp7)
-
-#define fpc REG (fpc)
-#define fpi REG (fpi)
-#define fps REG (fps)
-#define fpsr REG (fpsr)
-
-
-/*
- * Define macros to handle section beginning and ends.
- */
-
-
-#define BEGIN_CODE_DCL .text
-#define END_CODE_DCL
-#define BEGIN_DATA_DCL .data
-#define END_DATA_DCL
-#define BEGIN_CODE .text
-#define END_CODE
-#define BEGIN_DATA .data
-#define END_DATA
-#define BEGIN_BSS .bss
-#define END_BSS
-#define END
-
-/*
- * Following must be tailor for a particular flavor of the C compiler.
- * They may need to put underscores in front of the symbols.
- */
-
-#define PUBLIC(sym) .globl SYM (sym)
-#define EXTERN(sym) .globl SYM (sym)
-
-#endif
-/* end of include file */
-
-
diff --git a/c/src/exec/score/cpu/m68k/configure.ac b/c/src/exec/score/cpu/m68k/configure.ac
deleted file mode 100644
index b812d9897a..0000000000
--- a/c/src/exec/score/cpu/m68k/configure.ac
+++ /dev/null
@@ -1,30 +0,0 @@
-## Process this file with autoconf to produce a configure script.
-##
-## $Id$
-
-AC_PREREQ(2.52)
-AC_INIT([rtems-c-src-exec-score-cpu-m68k],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com])
-AC_CONFIG_SRCDIR([cpu_asm.S])
-RTEMS_TOP(../../../..)
-AC_CONFIG_AUX_DIR(../../../..)
-
-RTEMS_CANONICAL_TARGET_CPU
-
-AM_INIT_AUTOMAKE([no-define foreign 1.6])
-AM_MAINTAINER_MODE
-
-RTEMS_ENV_RTEMSCPU
-
-RTEMS_CHECK_CPU
-RTEMS_CANONICAL_HOST
-
-RTEMS_PROG_CC_FOR_TARGET
-RTEMS_PROG_CCAS
-RTEMS_CANONICALIZE_TOOLS
-AC_PROG_RANLIB
-
-RTEMS_CHECK_NEWLIB
-
-# Explicitly list all Makefiles here
-AC_CONFIG_FILES([Makefile])
-AC_OUTPUT
diff --git a/c/src/exec/score/cpu/m68k/cpu.c b/c/src/exec/score/cpu/m68k/cpu.c
deleted file mode 100644
index c7337c378e..0000000000
--- a/c/src/exec/score/cpu/m68k/cpu.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Motorola MC68xxx Dependent Source
- *
- * COPYRIGHT (c) 1989-1999.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#include <rtems/system.h>
-#include <rtems/score/isr.h>
-
-/* _CPU_Initialize
- *
- * This routine performs processor dependent initialization.
- *
- * INPUT PARAMETERS:
- * cpu_table - CPU table to initialize
- * thread_dispatch - entry pointer to thread dispatcher
- *
- * OUTPUT PARAMETERS: NONE
- */
-
-void _CPU_Initialize(
- rtems_cpu_table *cpu_table,
- void (*thread_dispatch) /* ignored on this CPU */
-)
-{
-#if ( M68K_HAS_VBR == 0 )
- /* fill the isr redirect table with the code to place the format/id
- onto the stack */
-
- unsigned32 slot;
-
- for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++)
- {
- _CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7;
- _CPU_ISR_jump_table[slot].format_id = slot << 2;
- _CPU_ISR_jump_table[slot].jmp = M68K_JMP;
- _CPU_ISR_jump_table[slot].isr_handler = (unsigned32) 0xDEADDEAD;
- }
-#endif /* M68K_HAS_VBR */
-
- _CPU_Table = *cpu_table;
-}
-
-/*PAGE
- *
- * _CPU_ISR_Get_level
- */
-
-unsigned32 _CPU_ISR_Get_level( void )
-{
- unsigned32 level;
-
- m68k_get_interrupt_level( level );
-
- return level;
-}
-
-/*PAGE
- *
- * _CPU_ISR_install_raw_handler
- */
-
-void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-)
-{
- proc_ptr *interrupt_table = NULL;
-
-#if (M68K_HAS_FPSP_PACKAGE == 1)
- /*
- * If this vector being installed is one related to FP, then the
- * FPSP will install the handler itself and handle it completely
- * with no intervention from RTEMS.
- */
-
- if (*_FPSP_install_raw_handler &&
- (*_FPSP_install_raw_handler)(vector, new_handler, *old_handler))
- return;
-#endif
-
-
- /*
- * On CPU models without a VBR, it is necessary for there to be some
- * header code for each ISR which saves a register, loads the vector
- * number, and jumps to _ISR_Handler.
- */
-
- m68k_get_vbr( interrupt_table );
-#if ( M68K_HAS_VBR == 1 )
- *old_handler = interrupt_table[ vector ];
- interrupt_table[ vector ] = new_handler;
-#else
-
- /*
- * Install handler into RTEMS jump table and if VBR table is in
- * RAM, install the pointer to the appropriate jump table slot.
- * If the VBR table is in ROM, it is the BSP's responsibility to
- * load it appropriately to vector to the RTEMS jump table.
- */
-
- *old_handler = _CPU_ISR_jump_table[vector].isr_handler;
- _CPU_ISR_jump_table[vector].isr_handler = (unsigned32) new_handler;
- if ( (unsigned32) interrupt_table != 0xFFFFFFFF )
- interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector];
-#endif /* M68K_HAS_VBR */
-}
-
-/*PAGE
- *
- * _CPU_ISR_install_vector
- *
- * This kernel routine installs the RTEMS handler for the
- * specified vector.
- *
- * Input parameters:
- * vector - interrupt vector number
- * new_handler - replacement ISR for this vector number
- * old_handler - former ISR for this vector number
- *
- * Output parameters: NONE
- */
-
-void _CPU_ISR_install_vector(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-)
-{
- proc_ptr ignored;
-
- *old_handler = _ISR_Vector_table[ vector ];
-
- _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
-
- _ISR_Vector_table[ vector ] = new_handler;
-}
-
-
-/*PAGE
- *
- * _CPU_Install_interrupt_stack
- */
-
-void _CPU_Install_interrupt_stack( void )
-{
-#if ( M68K_HAS_SEPARATE_STACKS == 1 )
- void *isp = _CPU_Interrupt_stack_high;
-
- asm volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) );
-#endif
-}
-
-#if ( M68K_HAS_BFFFO != 1 )
-/*
- * Returns table for duplication of the BFFFO instruction (16 bits only)
- */
-const unsigned char __BFFFOtable[256] = {
- 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
- 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-#endif
-
-/*PAGE
- *
- * The following code context switches the software FPU emulation
- * code provided with GCC.
- */
-
-#if (CPU_SOFTWARE_FP == TRUE)
-extern Context_Control_fp _fpCCR;
-
-void CPU_Context_save_fp (void **fp_context_ptr)
-{
- Context_Control_fp *fp;
-
- fp = (Context_Control_fp *) *fp_context_ptr;
-
- *fp = _fpCCR;
-}
-
-void CPU_Context_restore_fp (void **fp_context_ptr)
-{
- Context_Control_fp *fp;
-
- fp = (Context_Control_fp *) *fp_context_ptr;
-
- _fpCCR = *fp;
-}
-#endif
-
diff --git a/c/src/exec/score/cpu/m68k/cpu_asm.S b/c/src/exec/score/cpu/m68k/cpu_asm.S
deleted file mode 100644
index 0d14c16401..0000000000
--- a/c/src/exec/score/cpu/m68k/cpu_asm.S
+++ /dev/null
@@ -1,263 +0,0 @@
-/* cpu_asm.s
- *
- * This file contains all assembly code for the MC68020 implementation
- * of RTEMS.
- *
- * COPYRIGHT (c) 1989-2001.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-
-#include <asm.h>
-
- .text
-
-/* void _CPU_Context_switch( run_context, heir_context )
- *
- * This routine performs a normal non-FP context.
- */
-
- .align 4
- .global SYM (_CPU_Context_switch)
-
-.set RUNCONTEXT_ARG, 4 | save context argument
-.set HEIRCONTEXT_ARG, 8 | restore context argument
-
-SYM (_CPU_Context_switch):
- moval a7@(RUNCONTEXT_ARG),a0| a0 = running thread context
- movw sr,d1 | d1 = status register
- movml d1-d7/a2-a7,a0@ | save context
-
- moval a7@(HEIRCONTEXT_ARG),a0| a0 = heir thread context
-restore: movml a0@,d1-d7/a2-a7 | restore context
- movw d1,sr | restore status register
- rts
-
-/*PAGE
- * void __CPU_Context_save_fp_context( &fp_context_ptr )
- * void __CPU_Context_restore_fp_context( &fp_context_ptr )
- *
- * These routines are used to context switch a MC68881 or MC68882.
- *
- * NOTE: Context save and restore code is based upon the code shown
- * on page 6-38 of the MC68881/68882 Users Manual (rev 1).
- *
- * CPU_FP_CONTEXT_SIZE is higher than expected to account for the
- * -1 pushed at end of this sequence.
- *
- * Neither of these entries is required if we have software FPU
- * emulation. But if we don't have an FPU or emulation, then
- * we need the stub versions of these routines.
- */
-
-#if (CPU_SOFTWARE_FP == FALSE)
-
-.set FPCONTEXT_ARG, 4 | save FP context argument
-
- .align 4
- .global SYM (_CPU_Context_save_fp)
-SYM (_CPU_Context_save_fp):
-#if ( M68K_HAS_FPU == 1 )
- moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area
- moval a1@,a0 | a0 = Save context area
- fsave a0@- | save 68881/68882 state frame
- tstb a0@ | check for a null frame
- beq.b nosv | Yes, skip save of user model
- fmovem fp0-fp7,a0@- | save data registers (fp0-fp7)
- fmovem fpc/fps/fpi,a0@- | and save control registers
- movl #-1,a0@- | place not-null flag on stack
-nosv: movl a0,a1@ | save pointer to saved context
-#endif
- rts
-
- .align 4
- .global SYM (_CPU_Context_restore_fp)
-SYM (_CPU_Context_restore_fp):
-#if ( M68K_HAS_FPU == 1 )
- moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area
- moval a1@,a0 | a0 = address of saved context
- tstb a0@ | Null context frame?
- beq.b norst | Yes, skip fp restore
- addql #4,a0 | throwaway non-null flag
- fmovem a0@+,fpc/fps/fpi | restore control registers
- fmovem a0@+,fp0-fp7 | restore data regs (fp0-fp7)
-norst: frestore a0@+ | restore the fp state frame
- movl a0,a1@ | save pointer to saved context
-#endif
- rts
-#endif
-
-/*PAGE
- * void _ISR_Handler()
- *
- * This routine provides the RTEMS interrupt management.
- *
- * NOTE:
- * Upon entry, the master stack will contain an interrupt stack frame
- * back to the interrupted thread and the interrupt stack will contain
- * a throwaway interrupt stack frame. If dispatching is enabled, and this
- * is the outer most interrupt, and a context switch is necessary or
- * the current thread has pending signals, then set up the master stack to
- * transfer control to the interrupt dispatcher.
- */
-
-#if ( M68K_COLDFIRE_ARCH == 1 )
-.set SR_OFFSET, 2 | Status register offset
-.set PC_OFFSET, 4 | Program Counter offset
-.set FVO_OFFSET, 0 | Format/vector offset
-#elif ( M68K_HAS_VBR == 1)
-.set SR_OFFSET, 0 | Status register offset
-.set PC_OFFSET, 2 | Program Counter offset
-.set FVO_OFFSET, 6 | Format/vector offset
-#else
-.set SR_OFFSET, 2 | Status register offset
-.set PC_OFFSET, 4 | Program Counter offset
-.set FVO_OFFSET, 0 | Format/vector offset placed in the stack
-#endif /* M68K_HAS_VBR */
-
-.set SAVED, 16 | space for saved registers
-
- .align 4
- .global SYM (_ISR_Handler)
-
-SYM (_ISR_Handler):
- addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking
-#if ( M68K_COLDFIRE_ARCH == 0 )
- moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1
-#else
- lea a7@(-SAVED),a7
- movm.l d0-d1/a0-a1,a7@ | save d0-d1,a0-a1
-#endif
- movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
- andl #0x0ffc,d0 | d0 = vector offset in vbr
-
-
-#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
- movel _CPU_Interrupt_stack_high,a0 | a0 now point just above interrupt stack
- cmpl _CPU_Interrupt_stack_low,a7 | stack below interrupt stack?
- bcs.b 1f | yes, switch to interrupt stack
- cmpl a0,a7 | stack above interrupt stack?
- bcs.b 2f | no, do not switch stacks
-1:
- movel a7,a1 | copy task stack pointer
- movel a0,a7 | switch to interrupt stack
- movel a1,a7@- | store task stack pointer on interrupt stack
-2:
-#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
-
- movel SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table
-#if ( M68K_HAS_PREINDEXING == 1 )
- movel (a0,d0:w:1),a0 | a0 = address of user routine
-#else
- addal d0,a0 | a0 = address of vector
- movel (a0),a0 | a0 = address of user routine
-#endif
-
- lsrl #2,d0 | d0 = vector number
- movel d0,a7@- | push vector number
- jbsr a0@ | invoke the user ISR
- addql #4,a7 | remove vector number
-
-#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
- movel _CPU_Interrupt_stack_high,a0
- subql #4,a0
- cmpl a0,a7 | At top of interrupt stack?
- bne.b 1f | No, do not restore task stack pointer
- movel (a7),a7 | Restore task stack pointer
-1:
-#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
-
- subql #1,SYM (_Thread_Dispatch_disable_level)
- | unnest multitasking
- bne.b exit | If dispatch disabled, exit
-
-#if ( M68K_HAS_SEPARATE_STACKS == 1 )
- movew #0xf000,d0 | isolate format nibble
- andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO
- cmpiw #0x1000,d0 | is it a throwaway isf?
- bne.b exit | NOT outer level, so branch
-#else
-/*
- * If we have a CPU which allows a higher-priority interrupt to preempt a
- * lower priority handler before the lower-priority handler can increment
- * _Thread_Dispatch_disable_level then we must check the PC on the stack to
- * see if it is _ISR_Handler. If it is we have the case of nesting interrupts
- * without the dispatch level being incremented.
- */
- #if ( M68K_COLDFIRE_ARCH == 0 && M68K_MC68060_ARCH == 0 )
- cmpl #_ISR_Handler,a7@(SAVED+PC_OFFSET)
- beq.b exit
- #endif
-#endif
- tstl SYM (_Context_Switch_necessary)
- | Is thread switch necessary?
- bne.b bframe | Yes, invoke dispatcher
-
- tstl SYM (_ISR_Signals_to_thread_executing)
- | signals sent to Run_thread
- | while in interrupt handler?
- beq.b exit | No, then exit
-
-bframe: clrl SYM (_ISR_Signals_to_thread_executing)
- | If sent, will be processed
-#if ( M68K_HAS_SEPARATE_STACKS == 1 )
- movec msp,a0 | a0 = master stack pointer
- movew #0,a0@- | push format word
- movel #SYM(_ISR_Dispatch),a0@- | push return addr
- movew a0@(6),a0@- | push saved sr
- movec a0,msp | set master stack pointer
-#else
- jsr SYM (_Thread_Dispatch) | Perform context switch
-#endif
-
-#if ( M68K_COLDFIRE_ARCH == 0 )
-exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1
-#else
-exit: moveml a7@,d0-d1/a0-a1 | restore d0-d1,a0-a1
- lea a7@(SAVED),a7
-#endif
-
-#if ( M68K_HAS_VBR == 0 )
- addql #2,a7 | pop format/id
-#endif /* M68K_HAS_VBR */
- rte | return to thread
- | OR _Isr_dispatch
-
-/*PAGE
- * void _ISR_Dispatch()
- *
- * Entry point from the outermost interrupt service routine exit.
- * The current stack is the supervisor mode stack if this processor
- * has separate stacks.
- *
- * 1. save all registers not preserved across C calls.
- * 2. invoke the _Thread_Dispatch routine to switch tasks
- * or a signal to the currently executing task.
- * 3. restore all registers not preserved across C calls.
- * 4. return from interrupt
- */
-
- .global SYM (_ISR_Dispatch)
-SYM (_ISR_Dispatch):
-#if ( M68K_COLDFIRE_ARCH == 0 )
- movml d0-d1/a0-a1,a7@-
- jsr SYM (_Thread_Dispatch)
- movml a7@+,d0-d1/a0-a1
-#else
- lea a7@(-SAVED),a7
- movml d0-d1/a0-a1,a7@
- jsr SYM (_Thread_Dispatch)
- movml a7@,d0-d1/a0-a1
- lea a7@(SAVED),a7
-#endif
-
-#if ( M68K_HAS_VBR == 0 )
- addql #2,a7 | pop format/id
-#endif /* M68K_HAS_VBR */
- rte
diff --git a/c/src/exec/score/cpu/m68k/m68302.h b/c/src/exec/score/cpu/m68k/m68302.h
deleted file mode 100644
index c4bd0a5586..0000000000
--- a/c/src/exec/score/cpu/m68k/m68302.h
+++ /dev/null
@@ -1,661 +0,0 @@
-/*
- *------------------------------------------------------------------
- *
- * m68302.h - Definitions for Motorola MC68302 processor.
- *
- * Section references in this file refer to revision 2 of Motorola's
- * "MC68302 Integrated Multiprotocol Processor User's Manual".
- * (Motorola document MC68302UM/AD REV 2.)
- *
- * Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k
- * on 17 February, 1993.
- *
- * Copyright 1995 David W. Glessner.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the following conditions are met:
- * 1. Redistribution of source code and documentation must retain
- * the above copyright notice, this list of conditions and the
- * following disclaimer.
- * 2. The name of the author may not be used to endorse or promote
- * products derived from this software without specific prior
- * written permission.
- *
- * This software is provided "AS IS" without warranty of any kind,
- * either expressed or implied, including, but not limited to, the
- * implied warranties of merchantability, title and fitness for a
- * particular purpose.
- *
- *
- * $Id$
- *
- *------------------------------------------------------------------
- */
-
-#ifndef __MOTOROLA_MC68302_DEFINITIONS_h
-#define __MOTOROLA_MC68302_DEFINITIONS_h
-
-/*
- * BAR - Base Address Register
- * Section 2.7
- */
-#define M302_BAR (*((volatile rtems_unsigned16 *) 0xf2))
-
-/*
- * SCR - System Control Register
- * Section 3.8.1
- */
-#define M302_SCR (*((volatile rtems_unsigned32 *) 0xf4))
-/*
- * SCR bits
- */
-#define RBIT_SCR_IPA 0x08000000
-#define RBIT_SCR_HWT 0x04000000
-#define RBIT_SCR_WPV 0x02000000
-#define RBIT_SCR_ADC 0x01000000
-
-#define RBIT_SCR_ERRE 0x00400000
-#define RBIT_SCR_VGE 0x00200000
-#define RBIT_SCR_WPVE 0x00100000
-#define RBIT_SCR_RMCST 0x00080000
-#define RBIT_SCR_EMWS 0x00040000
-#define RBIT_SCR_ADCE 0x00020000
-#define RBIT_SCR_BCLM 0x00010000
-
-#define RBIT_SCR_FRZW 0x00008000
-#define RBIT_SCR_FRZ2 0x00004000
-#define RBIT_SCR_FRZ1 0x00002000
-#define RBIT_SCR_SAM 0x00001000
-#define RBIT_SCR_HWDEN 0x00000800
-#define RBIT_SCR_HWDCN2 0x00000400
-#define RBIT_SCR_HWDCN1 0x00000200 /* 512 clocks */
-#define RBIT_SCR_HWDCN0 0x00000100 /* 128 clocks */
-
-#define RBIT_SCR_LPREC 0x00000080
-#define RBIT_SCR_LPP16 0x00000040
-#define RBIT_SCR_LPEN 0x00000020
-#define RBIT_SCR_LPCLKDIV 0x0000001f
-
-
-/*
- * 68000 interrupt and trap vector numbers
- */
-#define M68K_IVEC_BUS_ERROR 2
-#define M68K_IVEC_ADDRESS_ERROR 3
-#define M68K_IVEC_ILLEGAL_OPCODE 4
-#define M68K_IVEC_ZERO_DIVIDE 5
-#define M68K_IVEC_CHK 6
-#define M68K_IVEC_TRAPV 7
-#define M68K_IVEC_PRIVILEGE 8
-#define M68K_IVEC_TRACE 9
-#define M68K_IVEC_LINE_A 10
-#define M68K_IVEC_LINE_F 11
-/* Unassigned, Reserved 12-14 */
-#define M68K_IVEC_UNINITIALIZED_INT 15
-/* Unassigned, Reserved 16-23 */
-#define M68K_IVEC_SPURIOUS_INT 24
-
-#define M68K_IVEC_LEVEL1_AUTOVECTOR 25
-#define M68K_IVEC_LEVEL2_AUTOVECTOR 26
-#define M68K_IVEC_LEVEL3_AUTOVECTOR 27
-#define M68K_IVEC_LEVEL4_AUTOVECTOR 28
-#define M68K_IVEC_LEVEL5_AUTOVECTOR 29
-#define M68K_IVEC_LEVEL6_AUTOVECTOR 30
-#define M68K_IVEC_LEVEL7_AUTOVECTOR 31
-
-#define M68K_IVEC_TRAP0 32
-#define M68K_IVEC_TRAP1 33
-#define M68K_IVEC_TRAP2 34
-#define M68K_IVEC_TRAP3 35
-#define M68K_IVEC_TRAP4 36
-#define M68K_IVEC_TRAP5 37
-#define M68K_IVEC_TRAP6 38
-#define M68K_IVEC_TRAP7 39
-#define M68K_IVEC_TRAP8 40
-#define M68K_IVEC_TRAP9 41
-#define M68K_IVEC_TRAP10 42
-#define M68K_IVEC_TRAP11 43
-#define M68K_IVEC_TRAP12 44
-#define M68K_IVEC_TRAP13 45
-#define M68K_IVEC_TRAP14 46
-#define M68K_IVEC_TRAP15 47
-/*
- * Unassigned, Reserved 48-59
- *
- * Note: Vectors 60-63 are used by the MC68302 (e.g. BAR, SCR).
- */
-
-/*
- * MC68302 Interrupt Vectors
- * Section 3.2
- */
-enum m68302_ivec_e {
- M302_IVEC_ERR =0,
- M302_IVEC_PB8 =1, /* General-Purpose Interrupt 0 */
- M302_IVEC_SMC2 =2,
- M302_IVEC_SMC1 =3,
- M302_IVEC_TIMER3 =4,
- M302_IVEC_SCP =5,
- M302_IVEC_TIMER2 =6,
- M302_IVEC_PB9 =7, /* General-Purpose Interrupt 1 */
- M302_IVEC_SCC3 =8,
- M302_IVEC_TIMER1 =9,
- M302_IVEC_SCC2 =10,
- M302_IVEC_IDMA =11,
- M302_IVEC_SDMA =12, /* SDMA Channels Bus Error */
- M302_IVEC_SCC1 =13,
- M302_IVEC_PB10 =14, /* General-Purpose Interrupt 2 */
- M302_IVEC_PB11 =15, /* General-Purpose Interrupt 3 */
- M302_IVEC_IRQ1 =17, /* External Device */
- M302_IVEC_IRQ6 =22, /* External Device */
- M302_IVEC_IRQ7 =23 /* External Device */
-};
-
-
-/*
- * GIMR - Global Interrupt Mode Register
- * Section 3.2.5.1
- */
-#define RBIT_GIMR_MOD (1<<15)
-#define RBIT_GIMR_IV7 (1<<14)
-#define RBIT_GIMR_IV6 (1<<13)
-#define RBIT_GIMR_IV1 (1<<12)
-#define RBIT_GIMR_ET7 (1<<10)
-#define RBIT_GIMR_ET6 (1<<9)
-#define RBIT_GIMR_ET1 (1<<8)
-#define RBIT_GIMR_VECTOR (7<<5)
-
-/*
- * IPR - Interrupt Pending Register (Section 3.2.5.2)
- * IMR - Interrupt Mask Register (Section 3.2.5.3)
- * ISR - Interrupt In-Service Register (Section 3.2.5.4)
- */
-#define RBIT_IPR_PB11 (1<<15)
-#define RBIT_IPR_PB10 (1<<14)
-#define RBIT_IPR_SCC1 (1<<13)
-#define RBIT_IPR_SDMA (1<<12)
-#define RBIT_IPR_IDMA (1<<11)
-#define RBIT_IPR_SCC2 (1<<10)
-#define RBIT_IPR_TIMER1 (1<<9)
-#define RBIT_IPR_SCC3 (1<<8)
-#define RBIT_IPR_PB9 (1<<7)
-#define RBIT_IPR_TIMER2 (1<<6)
-#define RBIT_IPR_SCP (1<<5)
-#define RBIT_IPR_TIMER3 (1<<4)
-#define RBIT_IPR_SMC1 (1<<3)
-#define RBIT_IPR_SMC2 (1<<2)
-#define RBIT_IPR_PB8 (1<<1)
-#define RBIT_IPR_ERR (1<<0)
-
-#define RBIT_ISR_PB11 (1<<15)
-#define RBIT_ISR_PB10 (1<<14)
-#define RBIT_ISR_SCC1 (1<<13)
-#define RBIT_ISR_SDMA (1<<12)
-#define RBIT_ISR_IDMA (1<<11)
-#define RBIT_ISR_SCC2 (1<<10)
-#define RBIT_ISR_TIMER1 (1<<9)
-#define RBIT_ISR_SCC3 (1<<8)
-#define RBIT_ISR_PB9 (1<<7)
-#define RBIT_ISR_TIMER2 (1<<6)
-#define RBIT_ISR_SCP (1<<5)
-#define RBIT_ISR_TIMER3 (1<<4)
-#define RBIT_ISR_SMC1 (1<<3)
-#define RBIT_ISR_SMC2 (1<<2)
-#define RBIT_ISR_PB8 (1<<1)
-
-#define RBIT_IMR_PB11 (1<<15) /* PB11 Interrupt Mask */
-#define RBIT_IMR_PB10 (1<<14) /* PB10 Interrupt Mask */
-#define RBIT_IMR_SCC1 (1<<13) /* SCC1 Interrupt Mask */
-#define RBIT_IMR_SDMA (1<<12) /* SDMA Interrupt Mask */
-#define RBIT_IMR_IDMA (1<<11) /* IDMA Interrupt Mask */
-#define RBIT_IMR_SCC2 (1<<10) /* SCC2 Interrupt Mask */
-#define RBIT_IMR_TIMER1 (1<<9) /* TIMER1 Interrupt Mask */
-#define RBIT_IMR_SCC3 (1<<8) /* SCC3 Interrupt Mask */
-#define RBIT_IMR_PB9 (1<<7) /* PB9 Interrupt Mask */
-#define RBIT_IMR_TIMER2 (1<<6) /* TIMER2 Interrupt Mask */
-#define RBIT_IMR_SCP (1<<5) /* SCP Interrupt Mask */
-#define RBIT_IMR_TIMER3 (1<<4) /* TIMER3 Interrupt Mask */
-#define RBIT_IMR_SMC1 (1<<3) /* SMC1 Interrupt Mask */
-#define RBIT_IMR_SMC2 (1<<2) /* SMC2 Interrupt Mask */
-#define RBIT_IMR_PB8 (1<<1) /* PB8 Interrupt Mask */
-
-
-/*
- * DRAM Refresh
- * Section 3.9
- *
- * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7
- * structures in the parameter RAM.
- *
- * Access to the DRAM registers can be accomplished by
- * the following approach:
- *
- * volatile m302_DRAM_refresh_t *dram;
- * dram = (volatile m302_DRAM_refresh_t *) &m302.scc2.bd.tx[6];
- *
- * Then simply use pointer references (e.g. dram->count = 3).
- */
-typedef struct {
- rtems_unsigned16 dram_high; /* DRAM high address and FC */
- rtems_unsigned16 dram_low; /* DRAM low address */
- rtems_unsigned16 increment; /* increment step (bytes/row) */
- rtems_unsigned16 count; /* RAM refresh cycle count (#rows) */
- rtems_unsigned16 t_ptr_h; /* temporary refresh high addr & FC */
- rtems_unsigned16 t_ptr_l; /* temporary refresh low address */
- rtems_unsigned16 t_count; /* temporary refresh cycles count */
- rtems_unsigned16 res; /* reserved */
-} m302_DRAM_refresh_t;
-
-
-/*
- * TMR - Timer Mode Register (for timers 1 and 2)
- * Section 3.5.2.1
- */
-#define RBIT_TMR_ICLK_STOP (0<<1)
-#define RBIT_TMR_ICLK_MASTER (1<<1)
-#define RBIT_TMR_ICLK_MASTER16 (2<<1)
-#define RBIT_TMR_ICLK_TIN (3<<1)
-
-#define RBIT_TMR_OM (1<<5)
-#define RBIT_TMR_ORI (1<<4)
-#define RBIT_TMR_FRR (1<<3)
-#define RBIT_TMR_RST (1<<0)
-
-
-/*
- * TER - Timer Event Register (for timers 1 and 2)
- * Section 3.5.2.5
- */
-#define RBIT_TER_REF (1<<1) /* Output Reference Event */
-#define RBIT_TER_CAP (1<<0) /* Capture Event */
-
-
-/*
- * SCC Buffer Descriptors and Buffer Descriptors Table
- * Section 4.5.5
- */
-typedef struct m302_SCC_bd {
- rtems_unsigned16 status; /* status and control */
- rtems_unsigned16 length; /* data length */
- volatile rtems_unsigned8 *buffer; /* data buffer pointer */
-} m302_SCC_bd_t;
-
-typedef struct {
- m302_SCC_bd_t rx[8]; /* receive buffer descriptors */
- m302_SCC_bd_t tx[8]; /* transmit buffer descriptors */
-} m302_SCC_bd_table_t;
-
-
-/*
- * SCC Parameter RAM (offset 0x080 from an SCC Base)
- * Section 4.5.6
- *
- * Each SCC parameter RAM area begins at offset 0x80 from each SCC base
- * area (0x400, 0x500, or 0x600 from the dual-port RAM base).
- *
- * Offsets 0x9c-0xbf from each SCC base area compose the protocol-specific
- * portion of the SCC parameter RAM.
- */
-typedef struct {
- rtems_unsigned8 rfcr; /* Rx Function Code */
- rtems_unsigned8 tfcr; /* Tx Function Code */
- rtems_unsigned16 mrblr; /* Maximum Rx Buffer Length */
- rtems_unsigned16 _rstate; /* Rx Internal State */
- rtems_unsigned8 res2;
- rtems_unsigned8 rbd; /* Rx Internal Buffer Number */
- rtems_unsigned32 _rdptr; /* Rx Internal Data Pointer */
- rtems_unsigned16 _rcount; /* Rx Internal Byte Count */
- rtems_unsigned16 _rtmp; /* Rx Temp */
- rtems_unsigned16 _tstate; /* Tx Internal State */
- rtems_unsigned8 res7;
- rtems_unsigned8 tbd; /* Tx Internal Buffer Number */
- rtems_unsigned32 _tdptr; /* Tx Internal Data Pointer */
- rtems_unsigned16 _tcount; /* Tx Internal Byte Count */
- rtems_unsigned16 _ttmp; /* Tx Temp */
-} m302_SCC_parameters_t;
-
-/*
- * UART-Specific SCC Parameter RAM
- * Section 4.5.11.3
- */
-typedef struct {
- rtems_unsigned16 max_idl; /* Maximum IDLE Characters (rx) */
- rtems_unsigned16 idlc; /* Temporary rx IDLE counter */
- rtems_unsigned16 brkcr; /* Break Count Register (tx) */
- rtems_unsigned16 parec; /* Receive Parity Error Counter */
- rtems_unsigned16 frmec; /* Receive Framing Error Counter */
- rtems_unsigned16 nosec; /* Receive Noise Counter */
- rtems_unsigned16 brkec; /* Receive Break Condition Counter */
- rtems_unsigned16 uaddr1; /* UART ADDRESS Character 1 */
- rtems_unsigned16 uaddr2; /* UART ADDRESS Character 2 */
- rtems_unsigned16 rccr; /* Receive Control Character Register */
- rtems_unsigned16 character[8]; /* Control Characters 1 through 8*/
-} m302_SCC_UartSpecific_t;
-/*
- * This definition allows for the checking of receive buffers
- * for errors.
- */
-
-#define RCV_ERR 0x003F
-
-/*
- * UART receive buffer descriptor bit definitions.
- * Section 4.5.11.14
- */
-#define RBIT_UART_CTRL (1<<11) /* buffer contains a control char */
-#define RBIT_UART_ADDR (1<<10) /* first byte contains an address */
-#define RBIT_UART_MATCH (1<<9) /* indicates which addr char matched */
-#define RBIT_UART_IDLE (1<<8) /* buffer closed due to IDLE sequence */
-#define RBIT_UART_BR (1<<5) /* break sequence was received */
-#define RBIT_UART_FR (1<<4) /* framing error was received */
-#define RBIT_UART_PR (1<<3) /* parity error was received */
-#define RBIT_UART_OV (1<<1) /* receiver overrun occurred */
-#define RBIT_UART_CD (1<<0) /* carrier detect lost */
-#define RBIT_UART_STATUS 0x003B /* all status bits */
-
-/*
- * UART transmit buffer descriptor bit definitions.
- * Section 4.5.11.15
- */
-#define RBIT_UART_CR (1<<11) /* clear-to-send report
- * this results in two idle bits
- * between back-to-back frames
- */
-#define RBIT_UART_A (1<<10) /* buffer contains address characters
- * only valid in multidrop mode (UM0=1)
- */
-#define RBIT_UART_PREAMBLE (1<<9) /* send preamble before data */
-#define RBIT_UART_CTS_LOST (1<<0) /* CTS lost */
-
-/*
- * UART event register
- * Section 4.5.11.16
- */
-#define M302_UART_EV_CTS (1<<7) /* CTS status changed */
-#define M302_UART_EV_CD (1<<6) /* carrier detect status changed */
-#define M302_UART_EV_IDL (1<<5) /* IDLE sequence status changed */
-#define M302_UART_EV_BRK (1<<4) /* break character was received */
-#define M302_UART_EV_CCR (1<<3) /* control character received */
-#define M302_UART_EV_TX (1<<1) /* buffer has been transmitted */
-#define M302_UART_EV_RX (1<<0) /* buffer has been received */
-
-
-/*
- * HDLC-Specific SCC Parameter RAM
- * Section 4.5.12.3
- *
- * c_mask_l should be 0xF0B8 for 16-bit CRC, 0xdebb for 32-bit CRC
- * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC
- */
-typedef struct {
- rtems_unsigned16 rcrc_l; /* Temp Receive CRC Low */
- rtems_unsigned16 rcrc_h; /* Temp Receive CRC High */
- rtems_unsigned16 c_mask_l; /* CRC Mask Low */
- rtems_unsigned16 c_mask_h; /* CRC Mask High */
- rtems_unsigned16 tcrc_l; /* Temp Transmit CRC Low */
- rtems_unsigned16 tcrc_h; /* Temp Transmit CRC High */
-
- rtems_unsigned16 disfc; /* Discard Frame Counter */
- rtems_unsigned16 crcec; /* CRC Error Counter */
- rtems_unsigned16 abtsc; /* Abort Sequence Counter */
- rtems_unsigned16 nmarc; /* Nonmatching Address Received Cntr */
- rtems_unsigned16 retrc; /* Frame Retransmission Counter */
-
- rtems_unsigned16 mflr; /* Maximum Frame Length Register */
- rtems_unsigned16 max_cnt; /* Maximum_Length Counter */
-
- rtems_unsigned16 hmask; /* User Defined Frame Address Mask */
- rtems_unsigned16 haddr1; /* User Defined Frame Address */
- rtems_unsigned16 haddr2; /* " */
- rtems_unsigned16 haddr3; /* " */
- rtems_unsigned16 haddr4; /* " */
-} m302_SCC_HdlcSpecific_t;
-/*
- * HDLC receiver buffer descriptor bit definitions
- * Section 4.5.12.10
- */
-#define RBIT_HDLC_EMPTY_BIT 0x8000 /* buffer associated with BD is empty */
-#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in a frame */
-#define RBIT_HDLC_FIRST_BIT 0x0400 /* buffer is first in a frame */
-#define RBIT_HDLC_FRAME_LEN 0x0020 /* receiver frame length violation */
-#define RBIT_HDLC_NONOCT_Rx 0x0010 /* received non-octet aligned frame */
-#define RBIT_HDLC_ABORT_SEQ 0x0008 /* received abort sequence */
-#define RBIT_HDLC_CRC_ERROR 0x0004 /* frame contains a CRC error */
-#define RBIT_HDLC_OVERRUN 0x0002 /* receiver overrun occurred */
-#define RBIT_HDLC_CD_LOST 0x0001 /* carrier detect lost */
-
-/*
- * HDLC transmit buffer descriptor bit definitions
- * Section 4.5.12.11
- */
-#define RBIT_HDLC_READY_BIT 0x8000 /* buffer is ready to transmit */
-#define RBIT_HDLC_EXT_BUFFER 0x4000 /* buffer is in external memory */
-#define RBIT_HDLC_WRAP_BIT 0x2000 /* last buffer in bd table, so wrap */
-#define RBIT_HDLC_WAKE_UP 0x1000 /* interrupt when buffer serviced */
-#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in the frame */
-#define RBIT_HDLC_TxCRC_BIT 0x0400 /* transmit a CRC sequence */
-#define RBIT_HDLC_UNDERRUN 0x0002 /* transmitter underrun */
-#define RBIT_HDLC_CTS_LOST 0x0001 /* CTS lost */
-
-/*
- * HDLC event register bit definitions
- * Section 4.5.12.12
- */
-#define RBIT_HDLC_CTS 0x80 /* CTS status changed */
-#define RBIT_HDLC_CD 0x40 /* carrier detect status changed */
-#define RBIT_HDLC_IDL 0x20 /* IDLE sequence status changed */
-#define RBIT_HDLC_TXE 0x10 /* transmit error */
-#define RBIT_HDLC_RXF 0x08 /* received frame */
-#define RBIT_HDLC_BSY 0x04 /* frame rcvd and discarded due to
- * lack of buffers
- */
-#define RBIT_HDLC_TXB 0x02 /* buffer has been transmitted */
-#define RBIT_HDLC_RXB 0x01 /* received buffer */
-
-
-
-typedef struct {
- m302_SCC_bd_table_t bd; /* +000 Buffer Descriptor Table */
- m302_SCC_parameters_t parm; /* +080 Common Parameter RAM */
- union { /* +09C Protocol-Specific Parm RAM */
- m302_SCC_UartSpecific_t uart;
- m302_SCC_HdlcSpecific_t hdlc;
- } prot;
- rtems_unsigned8 res[0x040]; /* +0C0 reserved, (not implemented) */
-} m302_SCC_t;
-
-
-/*
- * Common SCC Registers
- */
-typedef struct {
- rtems_unsigned16 res1;
- rtems_unsigned16 scon; /* SCC Configuration Register 4.5.2 */
- rtems_unsigned16 scm; /* SCC Mode Register 4.5.3 */
- rtems_unsigned16 dsr; /* SCC Data Synchronization Register 4.5.4 */
- rtems_unsigned8 scce; /* SCC Event Register 4.5.8.1 */
- rtems_unsigned8 res2;
- rtems_unsigned8 sccm; /* SCC Mask Register 4.5.8.2 */
- rtems_unsigned8 res3;
- rtems_unsigned8 sccs; /* SCC Status Register 4.5.8.3 */
- rtems_unsigned8 res4;
- rtems_unsigned16 res5;
-} m302_SCC_Registers_t;
-
-/*
- * SCON - SCC Configuration Register
- * Section 4.5.2
- */
-#define RBIT_SCON_WOMS (1<<15) /* Wired-OR Mode Select (NMSI mode only)
- * When set, the TXD driver is an
- * open-drain output */
-#define RBIT_SCON_EXTC (1<<14) /* External Clock Source */
-#define RBIT_SCON_TCS (1<<13) /* Transmit Clock Source */
-#define RBIT_SCON_RCS (1<<12) /* Receive Clock Source */
-
-/*
- * SCM - SCC Mode Register bit definitions
- * Section 4.5.3
- * The parameter-specific mode bits occupy bits 15 through 6.
- */
-#define RBIT_SCM_ENR (1<<3) /* Enable receiver */
-#define RBIT_SCM_ENT (1<<2) /* Enable transmitter */
-
-
-/*
- * Internal MC68302 Registers
- * starts at offset 0x800 from dual-port RAM base
- * Section 2.8
- */
-typedef struct {
- /* offset +800 */
- rtems_unsigned16 res0;
- rtems_unsigned16 cmr; /* IDMA Channel Mode Register */
- rtems_unsigned32 sapr; /* IDMA Source Address Pointer */
- rtems_unsigned32 dapr; /* IDMA Destination Address Pointer */
- rtems_unsigned16 bcr; /* IDMA Byte Count Register */
- rtems_unsigned8 csr; /* IDMA Channel Status Register */
- rtems_unsigned8 res1;
- rtems_unsigned8 fcr; /* IDMA Function Code Register */
- rtems_unsigned8 res2;
-
- /* offset +812 */
- rtems_unsigned16 gimr; /* Global Interrupt Mode Register */
- rtems_unsigned16 ipr; /* Interrupt Pending Register */
- rtems_unsigned16 imr; /* Interrupt Mask Register */
- rtems_unsigned16 isr; /* Interrupt In-Service Register */
- rtems_unsigned16 res3;
- rtems_unsigned16 res4;
-
- /* offset +81e */
- rtems_unsigned16 pacnt; /* Port A Control Register */
- rtems_unsigned16 paddr; /* Port A Data Direction Register */
- rtems_unsigned16 padat; /* Port A Data Register */
- rtems_unsigned16 pbcnt; /* Port B Control Register */
- rtems_unsigned16 pbddr; /* Port B Data Direction Register */
- rtems_unsigned16 pbdat; /* Port B Data Register */
- rtems_unsigned16 res5;
-
- /* offset +82c */
- rtems_unsigned16 res6;
- rtems_unsigned16 res7;
-
- rtems_unsigned16 br0; /* Base Register (CS0) */
- rtems_unsigned16 or0; /* Option Register (CS0) */
- rtems_unsigned16 br1; /* Base Register (CS1) */
- rtems_unsigned16 or1; /* Option Register (CS1) */
- rtems_unsigned16 br2; /* Base Register (CS2) */
- rtems_unsigned16 or2; /* Option Register (CS2) */
- rtems_unsigned16 br3; /* Base Register (CS3) */
- rtems_unsigned16 or3; /* Option Register (CS3) */
-
- /* offset +840 */
- rtems_unsigned16 tmr1; /* Timer Unit 1 Mode Register */
- rtems_unsigned16 trr1; /* Timer Unit 1 Reference Register */
- rtems_unsigned16 tcr1; /* Timer Unit 1 Capture Register */
- rtems_unsigned16 tcn1; /* Timer Unit 1 Counter */
- rtems_unsigned8 res8;
- rtems_unsigned8 ter1; /* Timer Unit 1 Event Register */
- rtems_unsigned16 wrr; /* Watchdog Reference Register */
- rtems_unsigned16 wcn; /* Watchdog Counter */
- rtems_unsigned16 res9;
- rtems_unsigned16 tmr2; /* Timer Unit 2 Mode Register */
- rtems_unsigned16 trr2; /* Timer Unit 2 Reference Register */
- rtems_unsigned16 tcr2; /* Timer Unit 2 Capture Register */
- rtems_unsigned16 tcn2; /* Timer Unit 2 Counter */
- rtems_unsigned8 resa;
- rtems_unsigned8 ter2; /* Timer Unit 2 Event Register */
- rtems_unsigned16 resb;
- rtems_unsigned16 resc;
- rtems_unsigned16 resd;
-
- /* offset +860 */
- rtems_unsigned8 cr; /* Command Register */
- rtems_unsigned8 rese[0x1f];
-
- /* offset +880, +890, +8a0 */
- m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */
-
- /* offset +8b0 */
- rtems_unsigned16 spmode; /* SCP,SMC Mode and Clock Cntrl Reg */
- rtems_unsigned16 simask; /* Serial Interface Mask Register */
- rtems_unsigned16 simode; /* Serial Interface Mode Register */
-} m302_internalReg_t ;
-
-
-/*
- * MC68302 dual-port RAM structure.
- * (Includes System RAM, Parameter RAM, and Internal Registers).
- * Section 2.8
- */
-typedef struct {
- rtems_unsigned8 mem[0x240]; /* +000 User Data Memory */
- rtems_unsigned8 res1[0x1c0]; /* +240 reserved, (not implemented) */
- m302_SCC_t scc1; /* +400 SCC1 */
- m302_SCC_t scc2; /* +500 SCC2 */
- m302_SCC_t scc3; /* +600 SCC3 */
- rtems_unsigned8 res2[0x100]; /* +700 reserved, (not implemented) */
- m302_internalReg_t reg; /* +800 68302 Internal Registers */
-} m302_dualPortRAM_t;
-
-/* some useful defines the some of the registers above */
-
-
-/* ----
- MC68302 Chip Select Registers
- p3-46 2nd Edition
-
- */
-#define BR_ENABLED 1
-#define BR_DISABLED 0
-#define BR_FC_NULL 0
-#define BR_READ_ONLY 0
-#define BR_READ_WRITE 2
-#define OR_DTACK_0 0x0000
-#define OR_DTACK_1 0x2000
-#define OR_DTACK_2 0x4000
-#define OR_DTACK_3 0x6000
-#define OR_DTACK_4 0x8000
-#define OR_DTACK_5 0xA000
-#define OR_DTACK_6 0xC000
-#define OR_DTACK_EXT 0xE000
-#define OR_SIZE_64K 0x1FE0
-#define OR_SIZE_128K 0x1FC0
-#define OR_SIZE_256K 0x1F80
-#define OR_SIZE_512K 0x1F00
-#define OR_SIZE_1M 0x1E00
-#define OR_SIZE_2M 0x1C00
-#define OR_MASK_RW 0x0000
-#define OR_NO_MASK_RW 0x0002
-#define OR_MASK_FC 0x0000
-#define OR_NO_MASK_FC 0x0001
-
-#define MAKE_BR(base_address, enable, rw, fc) \
- ((base_address >> 11) | fc | rw | enable)
-
-#define MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask) \
- (DtAck | ((~(bsize - 1) & 0x00FFFFFF) >> 11) | FC_Mask | RW_Mask)
-
-#define __REG_CAT(r, n) r ## n
-#define WRITE_BR(csel, base_address, enable, rw, fc) \
- __REG_CAT(m302.reg.br, csel) = MAKE_BR(base_address, enable, rw, fc)
-#define WRITE_OR(csel, bsize, DtAck, RW_Mask, FC_Mask) \
- __REG_CAT(m302.reg.or, csel) = MAKE_OR(bsize, DtAck, RW_Mask, FC_Mask)
-
-/* ----
- MC68302 Watchdog Timer Enable Bit
-
- */
-#define WATCHDOG_ENABLE (1)
-#define WATCHDOG_TRIGGER() (m302.reg.wrr = 0x10 | WATCHDOG_ENABLE, m302.reg.wcn = 0)
-#define WATCHDOG_TOGGLE() (m302.reg.wcn = WATCHDOG_TIMEOUT_PERIOD)
-#define DISABLE_WATCHDOG() (m302.reg.wrr = 0)
-
-/*
- * Declare the variable that's used to reference the variables in
- * the dual-port RAM.
- */
-extern volatile m302_dualPortRAM_t m302;
-
-#endif
-/* end of include file */
diff --git a/c/src/exec/score/cpu/m68k/m68360.h b/c/src/exec/score/cpu/m68k/m68360.h
deleted file mode 100644
index fd78fa1104..0000000000
--- a/c/src/exec/score/cpu/m68k/m68360.h
+++ /dev/null
@@ -1,889 +0,0 @@
-/*
- **************************************************************************
- **************************************************************************
- ** **
- ** MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC) **
- ** **
- ** HARDWARE DECLARATIONS **
- ** **
- ** **
- ** Submitted By: **
- ** **
- ** W. Eric Norum **
- ** Saskatchewan Accelerator Laboratory **
- ** University of Saskatchewan **
- ** 107 North Road **
- ** Saskatoon, Saskatchewan, CANADA **
- ** S7N 5C6 **
- ** **
- ** eric@skatter.usask.ca **
- ** **
- ** $Id$ **
- ** **
- **************************************************************************
- **************************************************************************
- */
-
-#ifndef __MC68360_h
-#define __MC68360_h
-
-/*
- *************************************************************************
- * REGISTER SUBBLOCKS *
- *************************************************************************
- */
-
-/*
- * Memory controller registers
- */
-typedef struct m360MEMCRegisters_ {
- unsigned long br;
- unsigned long or;
- unsigned long _pad[2];
-} m360MEMCRegisters_t;
-
-/*
- * Serial Communications Controller registers
- */
-typedef struct m360SCCRegisters_ {
- unsigned long gsmr_l;
- unsigned long gsmr_h;
- unsigned short psmr;
- unsigned short _pad0;
- unsigned short todr;
- unsigned short dsr;
- unsigned short scce;
- unsigned short _pad1;
- unsigned short sccm;
- unsigned char _pad2;
- unsigned char sccs;
- unsigned long _pad3[2];
-} m360SCCRegisters_t;
-
-/*
- * Serial Management Controller registers
- */
-typedef struct m360SMCRegisters_ {
- unsigned short _pad0;
- unsigned short smcmr;
- unsigned short _pad1;
- unsigned char smce;
- unsigned char _pad2;
- unsigned short _pad3;
- unsigned char smcm;
- unsigned char _pad4;
- unsigned long _pad5;
-} m360SMCRegisters_t;
-
-
-/*
- *************************************************************************
- * Miscellaneous Parameters *
- *************************************************************************
- */
-typedef struct m360MiscParms_ {
- unsigned short rev_num;
- unsigned short _res1;
- unsigned long _res2;
- unsigned long _res3;
-} m360MiscParms_t;
-
-/*
- *************************************************************************
- * RISC Timers *
- *************************************************************************
- */
-typedef struct m360TimerParms_ {
- unsigned short tm_base;
- unsigned short _tm_ptr;
- unsigned short _r_tmr;
- unsigned short _r_tmv;
- unsigned long tm_cmd;
- unsigned long tm_cnt;
-} m360TimerParms_t;
-
-/*
- * RISC Controller Configuration Register (RCCR)
- * All other bits in this register are either reserved or
- * used only with a Motorola-supplied RAM microcode packge.
- */
-#define M360_RCCR_TIME (1<<15) /* Enable timer */
-#define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */
-
-/*
- * Command register
- * Set up this register before issuing a M360_CR_OP_SET_TIMER command.
- */
-#define M360_TM_CMD_V (1<<31) /* Set to enable timer */
-#define M360_TM_CMD_R (1<<30) /* Set for automatic restart */
-#define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
-#define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
-
-/*
- *************************************************************************
- * DMA Controllers *
- *************************************************************************
- */
-typedef struct m360IDMAparms_ {
- unsigned short ibase;
- unsigned short ibptr;
- unsigned long _istate;
- unsigned long _itemp;
-} m360IDMAparms_t;
-
-/*
- *************************************************************************
- * Serial Communication Controllers *
- *************************************************************************
- */
-typedef struct m360SCCparms_ {
- unsigned short rbase;
- unsigned short tbase;
- unsigned char rfcr;
- unsigned char tfcr;
- unsigned short mrblr;
- unsigned long _rstate;
- unsigned long _pad0;
- unsigned short _rbptr;
- unsigned short _pad1;
- unsigned long _pad2;
- unsigned long _tstate;
- unsigned long _pad3;
- unsigned short _tbptr;
- unsigned short _pad4;
- unsigned long _pad5;
- unsigned long _rcrc;
- unsigned long _tcrc;
- union {
- struct {
- unsigned long _res0;
- unsigned long _res1;
- unsigned short max_idl;
- unsigned short _idlc;
- unsigned short brkcr;
- unsigned short parec;
- unsigned short frmec;
- unsigned short nosec;
- unsigned short brkec;
- unsigned short brklen;
- unsigned short uaddr[2];
- unsigned short _rtemp;
- unsigned short toseq;
- unsigned short character[8];
- unsigned short rccm;
- unsigned short rccr;
- unsigned short rlbc;
- } uart;
- struct {
- unsigned long crc_p;
- unsigned long crc_c;
- } transparent;
-
- } un;
-} m360SCCparms_t;
-
-typedef struct m360SCCENparms_ {
- unsigned short rbase;
- unsigned short tbase;
- unsigned char rfcr;
- unsigned char tfcr;
- unsigned short mrblr;
- unsigned long _rstate;
- unsigned long _pad0;
- unsigned short _rbptr;
- unsigned short _pad1;
- unsigned long _pad2;
- unsigned long _tstate;
- unsigned long _pad3;
- unsigned short _tbptr;
- unsigned short _pad4;
- unsigned long _pad5;
- unsigned long _rcrc;
- unsigned long _tcrc;
- union {
- struct {
- unsigned long _res0;
- unsigned long _res1;
- unsigned short max_idl;
- unsigned short _idlc;
- unsigned short brkcr;
- unsigned short parec;
- unsigned short frmec;
- unsigned short nosec;
- unsigned short brkec;
- unsigned short brklen;
- unsigned short uaddr[2];
- unsigned short _rtemp;
- unsigned short toseq;
- unsigned short character[8];
- unsigned short rccm;
- unsigned short rccr;
- unsigned short rlbc;
- } uart;
- struct {
- unsigned long c_pres;
- unsigned long c_mask;
- unsigned long crcec;
- unsigned long alec;
- unsigned long disfc;
- unsigned short pads;
- unsigned short ret_lim;
- unsigned short _ret_cnt;
- unsigned short mflr;
- unsigned short minflr;
- unsigned short maxd1;
- unsigned short maxd2;
- unsigned short _maxd;
- unsigned short dma_cnt;
- unsigned short _max_b;
- unsigned short gaddr1;
- unsigned short gaddr2;
- unsigned short gaddr3;
- unsigned short gaddr4;
- unsigned long _tbuf0data0;
- unsigned long _tbuf0data1;
- unsigned long _tbuf0rba0;
- unsigned long _tbuf0crc;
- unsigned short _tbuf0bcnt;
- unsigned short paddr_h;
- unsigned short paddr_m;
- unsigned short paddr_l;
- unsigned short p_per;
- unsigned short _rfbd_ptr;
- unsigned short _tfbd_ptr;
- unsigned short _tlbd_ptr;
- unsigned long _tbuf1data0;
- unsigned long _tbuf1data1;
- unsigned long _tbuf1rba0;
- unsigned long _tbuf1crc;
- unsigned short _tbuf1bcnt;
- unsigned short _tx_len;
- unsigned short iaddr1;
- unsigned short iaddr2;
- unsigned short iaddr3;
- unsigned short iaddr4;
- unsigned short _boff_cnt;
- unsigned short taddr_l;
- unsigned short taddr_m;
- unsigned short taddr_h;
- } ethernet;
- struct {
- unsigned long crc_p;
- unsigned long crc_c;
- } transparent;
- } un;
-} m360SCCENparms_t;
-
-/*
- * Receive and transmit function code register bits
- * These apply to the function code registers of all devices, not just SCC.
- */
-#define M360_RFCR_MOT (1<<4)
-#define M360_RFCR_DMA_SPACE 0x8
-#define M360_TFCR_MOT (1<<4)
-#define M360_TFCR_DMA_SPACE 0x8
-
-/*
- *************************************************************************
- * Serial Management Controllers *
- *************************************************************************
- */
-typedef struct m360SMCparms_ {
- unsigned short rbase;
- unsigned short tbase;
- unsigned char rfcr;
- unsigned char tfcr;
- unsigned short mrblr;
- unsigned long _rstate;
- unsigned long _pad0;
- unsigned short _rbptr;
- unsigned short _pad1;
- unsigned long _pad2;
- unsigned long _tstate;
- unsigned long _pad3;
- unsigned short _tbptr;
- unsigned short _pad4;
- unsigned long _pad5;
- union {
- struct {
- unsigned short max_idl;
- unsigned short _pad0;
- unsigned short brklen;
- unsigned short brkec;
- unsigned short brkcr;
- unsigned short _r_mask;
- } uart;
- struct {
- unsigned short _pad0[5];
- } transparent;
- } un;
-} m360SMCparms_t;
-
-/*
- * Mode register
- */
-#define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */
-#define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */
-#define M360_SMCMR_PARITY (1<<9) /* Enable parity */
-#define M360_SMCMR_EVEN (1<<8) /* Even parity */
-#define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */
-#define M360_SMCMR_SM_UART (2<<4) /* UART Mode */
-#define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
-#define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
-#define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */
-#define M360_SMCMR_TEN (1<<1) /* Enable transmitter */
-#define M360_SMCMR_REN (1<<0) /* Enable receiver */
-
-/*
- * Event and mask registers (SMCE, SMCM)
- */
-#define M360_SMCE_BRK (1<<4)
-#define M360_SMCE_BSY (1<<2)
-#define M360_SMCE_TX (1<<1)
-#define M360_SMCE_RX (1<<0)
-
-/*
- *************************************************************************
- * Serial Peripheral Interface *
- *************************************************************************
- */
-typedef struct m360SPIparms_ {
- unsigned short rbase;
- unsigned short tbase;
- unsigned char rfcr;
- unsigned char tfcr;
- unsigned short mrblr;
- unsigned long _rstate;
- unsigned long _pad0;
- unsigned short _rbptr;
- unsigned short _pad1;
- unsigned long _pad2;
- unsigned long _tstate;
- unsigned long _pad3;
- unsigned short _tbptr;
- unsigned short _pad4;
- unsigned long _pad5;
-} m360SPIparms_t;
-
-/*
- * Mode register (SPMODE)
- */
-#define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */
-#define M360_SPMODE_CI (1<<13) /* Clock invert */
-#define M360_SPMODE_CP (1<<12) /* Clock phase */
-#define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
-#define M360_SPMODE_REV (1<<10) /* Reverse data */
-#define M360_SPMODE_MASTER (1<<9) /* SPI is master */
-#define M360_SPMODE_EN (1<<8) /* Enable SPI */
-#define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */
-#define M360_SPMODE_PM(x) (x) /* Prescaler modulus */
-
-/*
- * Mode register (SPCOM)
- */
-#define M360_SPCOM_STR (1<<7) /* Start transmit */
-
-/*
- * Event and mask registers (SPIE, SPIM)
- */
-#define M360_SPIE_MME (1<<5) /* Multi-master error */
-#define M360_SPIE_TXE (1<<4) /* Tx error */
-#define M360_SPIE_BSY (1<<2) /* Busy condition*/
-#define M360_SPIE_TXB (1<<1) /* Tx buffer */
-#define M360_SPIE_RXB (1<<0) /* Rx buffer */
-
-/*
- *************************************************************************
- * SDMA (SCC, SMC, SPI) Buffer Descriptors *
- *************************************************************************
- */
-typedef struct m360BufferDescriptor_ {
- unsigned short status;
- unsigned short length;
- volatile void *buffer;
-} m360BufferDescriptor_t;
-
-/*
- * Bits in receive buffer descriptor status word
- */
-#define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M360_BD_LAST (1<<11) /* Ethernet, SPI */
-#define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */
-#define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
-#define M360_BD_ADDRESS (1<<10) /* SCC UART */
-#define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
-#define M360_BD_MISS (1<<8) /* Ethernet */
-#define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */
-#define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
-#define M360_BD_LONG (1<<5) /* Ethernet */
-#define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */
-#define M360_BD_NONALIGNED (1<<4) /* Ethernet */
-#define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
-#define M360_BD_SHORT (1<<3) /* Ethernet */
-#define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
-#define M360_BD_CRC_ERROR (1<<2) /* Ethernet */
-#define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M360_BD_COLLISION (1<<0) /* Ethernet */
-#define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */
-#define M360_BD_MASTER_ERROR (1<<0) /* SPI */
-
-/*
- * Bits in transmit buffer descriptor status word
- * Many bits have the same meaning as those in receiver buffer descriptors.
- */
-#define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
-#define M360_BD_PAD (1<<14) /* Ethernet */
-#define M360_BD_CTS_REPORT (1<<11) /* SCC UART */
-#define M360_BD_TX_CRC (1<<10) /* Ethernet */
-#define M360_BD_DEFER (1<<9) /* Ethernet */
-#define M360_BD_HEARTBEAT (1<<8) /* Ethernet */
-#define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
-#define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */
-#define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */
-#define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */
-#define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
-#define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */
-#define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */
-#define M360_BD_CTS_LOST (1<<0) /* SCC UART */
-
-/*
- *************************************************************************
- * IDMA Buffer Descriptors *
- *************************************************************************
- */
-typedef struct m360IDMABufferDescriptor_ {
- unsigned short status;
- unsigned short _pad;
- unsigned long length;
- void *source;
- void *destination;
-} m360IDMABufferDescriptor_t;
-
-/*
- *************************************************************************
- * RISC Communication Processor Module Command Register (CR) *
- *************************************************************************
- */
-#define M360_CR_RST (1<<15) /* Reset communication processor */
-#define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */
-#define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */
-#define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */
-#define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */
-#define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */
-#define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */
-#define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */
-#define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */
-#define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */
-#define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */
-#define M360_CR_OP_SET_TIMER (8<<8) /* Timer */
-#define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */
-#define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */
-#define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */
-#define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */
-#define M360_CR_CHAN_SCC2 (4<<4)
-#define M360_CR_CHAN_SPI (5<<4)
-#define M360_CR_CHAN_TIMER (5<<4)
-#define M360_CR_CHAN_SCC3 (8<<4)
-#define M360_CR_CHAN_SMC1 (9<<4)
-#define M360_CR_CHAN_IDMA1 (9<<4)
-#define M360_CR_CHAN_SCC4 (12<<4)
-#define M360_CR_CHAN_SMC2 (13<<4)
-#define M360_CR_CHAN_IDMA2 (13<<4)
-#define M360_CR_FLG (1<<0) /* Command flag */
-
-/*
- *************************************************************************
- * System Protection Control Register (SYPCR) *
- *************************************************************************
- */
-#define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */
-#define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */
-#define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */
-#define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */
-#define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */
-#define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */
-#define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */
-#define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */
-
-/*
- *************************************************************************
- * Memory Control Registers *
- *************************************************************************
- */
-#define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */
-#define M360_GMR_RFEN (1<<23) /* Refresh enable */
-#define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */
-#define M360_GMR_PGS(x) ((x)<<18) /* Page size */
-#define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */
-#define M360_GMR_DPS_16BIT (1<<16)
-#define M360_GMR_DPS_8BIT (2<<16)
-#define M360_GMR_DPS_DSACK (3<<16)
-#define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */
-#define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */
-#define M360_GMR_SYNC (1<<13) /* Synchronous external access */
-#define M360_GMR_EMWS (1<<12) /* External master wait state */
-#define M360_GMR_OPAR (1<<11) /* Odd parity */
-#define M360_GMR_PBEE (1<<10) /* Parity bus error enable */
-#define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */
-#define M360_GMR_NCS (1<<8) /* No CPU space */
-#define M360_GMR_DWQ (1<<7) /* Delay write for 360 */
-#define M360_GMR_DW40 (1<<6) /* Delay write for 040 */
-#define M360_GMR_GAMX (1<<5) /* Global address mux enable */
-
-#define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */
-#define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */
-#define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */
-#define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */
-#define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */
-#define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */
-#define M360_MEMC_BR_WP (1<<1) /* Write Protect */
-#define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */
-
-#define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */
-#define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1)
-#define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */
-#define M360_MEMC_OR_4KB 0x0FFFF000
-#define M360_MEMC_OR_8KB 0x0FFFE000
-#define M360_MEMC_OR_16KB 0x0FFFC000
-#define M360_MEMC_OR_32KB 0x0FFF8000
-#define M360_MEMC_OR_64KB 0x0FFF0000
-#define M360_MEMC_OR_128KB 0x0FFE0000
-#define M360_MEMC_OR_256KB 0x0FFC0000
-#define M360_MEMC_OR_512KB 0x0FF80000
-#define M360_MEMC_OR_1MB 0x0FF00000
-#define M360_MEMC_OR_2MB 0x0FE00000
-#define M360_MEMC_OR_4MB 0x0FC00000
-#define M360_MEMC_OR_8MB 0x0F800000
-#define M360_MEMC_OR_16MB 0x0F000000
-#define M360_MEMC_OR_32MB 0x0E000000
-#define M360_MEMC_OR_64MB 0x0C000000
-#define M360_MEMC_OR_128MB 0x08000000
-#define M360_MEMC_OR_256MB 0x00000000
-#define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */
-#define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */
-#define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */
-#define M360_MEMC_OR_32BIT (0<<1) /* Port size */
-#define M360_MEMC_OR_16BIT (1<<1)
-#define M360_MEMC_OR_8BIT (2<<1)
-#define M360_MEMC_OR_DSACK (3<<1)
-#define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */
-
-/*
- *************************************************************************
- * SI Mode Register (SIMODE) *
- *************************************************************************
- */
-#define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
-#define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
-#define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
-#define M360_SI_SMC2_BRG2 (1<<28)
-#define M360_SI_SMC2_BRG3 (2<<28)
-#define M360_SI_SMC2_BRG4 (3<<28)
-#define M360_SI_SMC2_CLK5 (0<<28)
-#define M360_SI_SMC2_CLK6 (1<<28)
-#define M360_SI_SMC2_CLK7 (2<<28)
-#define M360_SI_SMC2_CLK8 (3<<28)
-#define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
-#define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
-#define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
-#define M360_SI_SMC1_BRG2 (1<<12)
-#define M360_SI_SMC1_BRG3 (2<<12)
-#define M360_SI_SMC1_BRG4 (3<<12)
-#define M360_SI_SMC1_CLK1 (0<<12)
-#define M360_SI_SMC1_CLK2 (1<<12)
-#define M360_SI_SMC1_CLK3 (2<<12)
-#define M360_SI_SMC1_CLK4 (3<<12)
-
-/*
- *************************************************************************
- * SDMA Configuration Register (SDMA) *
- *************************************************************************
- */
-#define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */
-#define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */
-#define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */
-#define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */
-#define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */
-
-/*
- *************************************************************************
- * Baud (sic) Rate Generators *
- *************************************************************************
- */
-#define M360_BRG_RST (1<<17) /* Reset generator */
-#define M360_BRG_EN (1<<16) /* Enable generator */
-#define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
-#define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
-#define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
-#define M360_BRG_ATB (1<<13) /* Autobaud */
-#define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */
-#define M360_BRG_57600 (26<<1)
-#define M360_BRG_38400 (40<<1)
-#define M360_BRG_19200 (80<<1)
-#define M360_BRG_9600 (162<<1)
-#define M360_BRG_4800 (324<<1)
-#define M360_BRG_2400 (650<<1)
-#define M360_BRG_1200 (1301<<1)
-#define M360_BRG_600 (2603<<1)
-#define M360_BRG_300 ((324<<1) | 1)
-#define M360_BRG_150 ((650<<1) | 1)
-#define M360_BRG_75 ((1301<<1) | 1)
-
-/*
- *************************************************************************
- * MC68360 DUAL-PORT RAM AND REGISTERS *
- *************************************************************************
- */
-typedef struct m360_ {
- /*
- * Dual-port RAM
- */
- unsigned char dpram0[0x400]; /* Microcode program */
- unsigned char dpram1[0x200];
- unsigned char dpram2[0x100]; /* Microcode scratch */
- unsigned char dpram3[0x100]; /* Not on REV A or B masks */
- unsigned char _rsv0[0xC00-0x800];
- m360SCCENparms_t scc1p;
- unsigned char _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)];
- m360MiscParms_t miscp;
- unsigned char _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)];
- m360SCCparms_t scc2p;
- unsigned char _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)];
- m360SPIparms_t spip;
- unsigned char _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)];
- m360TimerParms_t tmp;
- unsigned char _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)];
- m360SCCparms_t scc3p;
- unsigned char _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)];
- m360IDMAparms_t idma1p;
- unsigned char _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)];
- m360SMCparms_t smc1p;
- unsigned char _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)];
- m360SCCparms_t scc4p;
- unsigned char _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)];
- m360IDMAparms_t idma2p;
- unsigned char _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)];
- m360SMCparms_t smc2p;
- unsigned char _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)];
-
- /*
- * SIM Block
- */
- unsigned long mcr;
- unsigned long _pad00;
- unsigned char avr;
- unsigned char rsr;
- unsigned short _pad01;
- unsigned char clkocr;
- unsigned char _pad02;
- unsigned short _pad03;
- unsigned short pllcr;
- unsigned short _pad04;
- unsigned short cdvcr;
- unsigned short pepar;
- unsigned long _pad05[2];
- unsigned short _pad06;
- unsigned char sypcr;
- unsigned char swiv;
- unsigned short _pad07;
- unsigned short picr;
- unsigned short _pad08;
- unsigned short pitr;
- unsigned short _pad09;
- unsigned char _pad10;
- unsigned char swsr;
- unsigned long bkar;
- unsigned long bcar;
- unsigned long _pad11[2];
-
- /*
- * MEMC Block
- */
- unsigned long gmr;
- unsigned short mstat;
- unsigned short _pad12;
- unsigned long _pad13[2];
- m360MEMCRegisters_t memc[8];
- unsigned char _pad14[0xF0-0xD0];
- unsigned char _pad15[0x100-0xF0];
- unsigned char _pad16[0x500-0x100];
-
- /*
- * IDMA1 Block
- */
- unsigned short iccr;
- unsigned short _pad17;
- unsigned short cmr1;
- unsigned short _pad18;
- unsigned long sapr1;
- unsigned long dapr1;
- unsigned long bcr1;
- unsigned char fcr1;
- unsigned char _pad19;
- unsigned char cmar1;
- unsigned char _pad20;
- unsigned char csr1;
- unsigned char _pad21;
- unsigned short _pad22;
-
- /*
- * SDMA Block
- */
- unsigned char sdsr;
- unsigned char _pad23;
- unsigned short sdcr;
- unsigned long sdar;
-
- /*
- * IDMA2 Block
- */
- unsigned short _pad24;
- unsigned short cmr2;
- unsigned long sapr2;
- unsigned long dapr2;
- unsigned long bcr2;
- unsigned char fcr2;
- unsigned char _pad26;
- unsigned char cmar2;
- unsigned char _pad27;
- unsigned char csr2;
- unsigned char _pad28;
- unsigned short _pad29;
- unsigned long _pad30;
-
- /*
- * CPIC Block
- */
- unsigned long cicr;
- unsigned long cipr;
- unsigned long cimr;
- unsigned long cisr;
-
- /*
- * Parallel I/O Block
- */
- unsigned short padir;
- unsigned short papar;
- unsigned short paodr;
- unsigned short padat;
- unsigned long _pad31[2];
- unsigned short pcdir;
- unsigned short pcpar;
- unsigned short pcso;
- unsigned short pcdat;
- unsigned short pcint;
- unsigned short _pad32;
- unsigned long _pad33[5];
-
- /*
- * TIMER Block
- */
- unsigned short tgcr;
- unsigned short _pad34;
- unsigned long _pad35[3];
- unsigned short tmr1;
- unsigned short tmr2;
- unsigned short trr1;
- unsigned short trr2;
- unsigned short tcr1;
- unsigned short tcr2;
- unsigned short tcn1;
- unsigned short tcn2;
- unsigned short tmr3;
- unsigned short tmr4;
- unsigned short trr3;
- unsigned short trr4;
- unsigned short tcr3;
- unsigned short tcr4;
- unsigned short tcn3;
- unsigned short tcn4;
- unsigned short ter1;
- unsigned short ter2;
- unsigned short ter3;
- unsigned short ter4;
- unsigned long _pad36[2];
-
- /*
- * CP Block
- */
- unsigned short cr;
- unsigned short _pad37;
- unsigned short rccr;
- unsigned short _pad38;
- unsigned long _pad39[3];
- unsigned short _pad40;
- unsigned short rter;
- unsigned short _pad41;
- unsigned short rtmr;
- unsigned long _pad42[5];
-
- /*
- * BRG Block
- */
- unsigned long brgc1;
- unsigned long brgc2;
- unsigned long brgc3;
- unsigned long brgc4;
-
- /*
- * SCC Block
- */
- m360SCCRegisters_t scc1;
- m360SCCRegisters_t scc2;
- m360SCCRegisters_t scc3;
- m360SCCRegisters_t scc4;
-
- /*
- * SMC Block
- */
- m360SMCRegisters_t smc1;
- m360SMCRegisters_t smc2;
-
- /*
- * SPI Block
- */
- unsigned short spmode;
- unsigned short _pad43[2];
- unsigned char spie;
- unsigned char _pad44;
- unsigned short _pad45;
- unsigned char spim;
- unsigned char _pad46[2];
- unsigned char spcom;
- unsigned short _pad47[2];
-
- /*
- * PIP Block
- */
- unsigned short pipc;
- unsigned short _pad48;
- unsigned short ptpr;
- unsigned long pbdir;
- unsigned long pbpar;
- unsigned short _pad49;
- unsigned short pbodr;
- unsigned long pbdat;
- unsigned long _pad50[6];
-
- /*
- * SI Block
- */
- unsigned long simode;
- unsigned char sigmr;
- unsigned char _pad51;
- unsigned char sistr;
- unsigned char sicmr;
- unsigned long _pad52;
- unsigned long sicr;
- unsigned short _pad53;
- unsigned short sirp[2];
- unsigned short _pad54;
- unsigned long _pad55[2];
- unsigned char siram[256];
-} m360_t;
-
-extern volatile m360_t m360;
-
-#endif /* __MC68360_h */
diff --git a/c/src/exec/score/cpu/m68k/memcpy.c b/c/src/exec/score/cpu/m68k/memcpy.c
deleted file mode 100644
index 3948411f4b..0000000000
--- a/c/src/exec/score/cpu/m68k/memcpy.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * C library memcpy routine
- *
- * This routine has code to optimize performance on the CPU32+
- * and another version for other 68k machines.
- *
- * It could be optimized more for machines with MOVE16 instructions.
- *
- * The routine is placed in this source directory to ensure that it
- * is picked up by all applications.
- *
- * W. Eric Norum
- * Saskatchewan Accelerator Laboratory
- * University of Saskatchewan
- * Saskatoon, Saskatchewan, CANADA
- * eric@skatter.usask.ca
- */
-
-#include <string.h>
-#include <rtems/score/m68k.h>
-
-#if defined(__mcpu32__)
-#define COPYSETUP(n) n--
-#define COPY(to,from,n,size) \
- asm volatile ("1:\n" \
- "\tmove." size " (%0)+,(%1)+\n" \
- "\tdbf %2,1b\n" \
- "\tsub.l #0x10000,%2\n" \
- "\tbpl.b 1b\n" : \
- "=a" (from), "=a" (to), "=d" (n) :\
- "0" (from), "1" (to), "2" (n) : \
- "cc", "memory")
-#else
-#define COPYSETUP(n)
-#define COPY(to,from,n,size) \
- asm volatile ("1:\n" \
- "\tmove." size " (%0)+,(%1)+\n" \
- "\tsubq.l #1,%2\n\tbne.b 1b\n" : \
- "=a" (from), "=a" (to), "=d" (n) :\
- "0" (from), "1" (to), "2" (n) : \
- "cc", "memory")
-#endif
-
-void *
-memcpy(void *s1, const void *s2, size_t n)
-{
- char *p1 = s1;
- const char *p2 = s2;
-
- if (n) {
- if (n < 16) {
- COPYSETUP (n);
- COPY (p1, p2, n, "b");
- }
- else {
- int nbyte;
- int nl;
- nbyte = (int)p1 & 0x3;
- if (nbyte) {
- nbyte = 4 - nbyte;
- n -= nbyte;
- COPYSETUP (nbyte);
- COPY (p1, p2, nbyte, "b");
- }
-#if (M68K_HAS_MISALIGNED == 0)
- /*
- * Take care of machines that can't
- * handle misaligned references.
- */
- if ((int)p2 & 0x1) {
- COPYSETUP (n);
- COPY (p1, p2, n, "b");
- return s1;
- }
-#endif
- nl = (unsigned int)n >> 2;
- COPYSETUP (nl);
- COPY (p1, p2, nl, "l");
- nbyte = (int)n & 0x3;
- if (nbyte) {
- COPYSETUP (nbyte);
- COPY (p1, p2, nbyte, "b");
- }
- }
- }
- return s1;
-}
diff --git a/c/src/exec/score/cpu/m68k/qsm.h b/c/src/exec/score/cpu/m68k/qsm.h
deleted file mode 100644
index 9853978115..0000000000
--- a/c/src/exec/score/cpu/m68k/qsm.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- *-------------------------------------------------------------------
- *
- * QSM -- Queued Serial Module
- *
- * The QSM contains two serial interfaces: (a) the queued serial
- * peripheral interface (QSPI) and the serial communication interface
- * (SCI). The QSPI provides peripheral expansion and/or interprocessor
- * communication through a full-duplex, synchronous, three-wire bus. A
- * self contained RAM queue permits serial data transfers without CPU
- * intervention and automatic continuous sampling. The SCI provides a
- * standard non-return to zero mark/space format with wakeup functions
- * to allow the CPU to run uninterrupted until woken
- *
- * For more information, refer to Motorola's "Modular Microcontroller
- * Family Queued Serial Module Reference Manual" (Motorola document
- * QSMRM/AD).
- *
- * This file has been created by John S. Gwynne for support of
- * Motorola's 68332 MCU in the efi332 project.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the following conditions are met:
- * 1. Redistribution of source code and documentation must retain
- * the above authorship, this list of conditions and the
- * following disclaimer.
- * 2. The name of the author may not be used to endorse or promote
- * products derived from this software without specific prior
- * written permission.
- *
- * This software is provided "AS IS" without warranty of any kind,
- * either expressed or implied, including, but not limited to, the
- * implied warranties of merchantability, title and fitness for a
- * particular purpose.
- *
- *------------------------------------------------------------------
- *
- * $Id$
- */
-
-#ifndef _QSM_H_
-#define _QSM_H_
-
-/* SAM-- shift and mask */
-#undef SAM
-#define SAM(a,b,c) ((a << b) & c)
-
-
-/* QSM_CRB (QSM Control Register Block) base address of the QSM
- control registers */
-#if SIM_MM == 0
-#define QSM_CRB 0x7ffc00
-#else
-#undef SIM_MM
-#define SIM_MM 1
-#define QSM_CRB 0xfffc00
-#endif
-
-
-#define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB)
- /* QSM Configuration Register */
-#define STOP 0x8000 /* Stop Enable */
-#define FRZ 0x6000 /* Freeze Control */
-#define SUPV 0x0080 /* Supervisor/Unrestricted */
-#define IARB 0x000f /* Inerrupt Arbitration */
-
-
-#define QTEST (volatile unsigned short int * const)(0x02 + QSM_CRB)
- /* QSM Test Register */
-/* Used only for factor testing */
-
-
-#define QILR (volatile unsigned char * const)(0x04 + QSM_CRB)
- /* QSM Interrupt Level Register */
-#define ILQSPI 0x38 /* Interrupt Level for QSPI */
-#define ILSCI 0x07 /* Interrupt Level for SCI */
-
-
-#define QIVR (volatile unsigned char * const)(0x05 + QSM_CRB)
- /* QSM Interrupt Vector Register */
-#define INTV 0xff /* Interrupt Vector Number */
-
-
-#define SCCR0 (volatile unsigned short int * const)(0x08 + QSM_CRB)
- /* SCI Control Register 0 */
-#define SCBR 0x1fff /* SCI Baud Rate */
-
-
-#define SCCR1 (volatile unsigned short int * const)(0x0a + QSM_CRB)
- /* SCI Control Register 1 */
-#define LOOPS 0x4000 /* Loop Mode */
-#define WOMS 0x2000 /* Wired-OR Mode for SCI Pins */
-#define ILT 0x1000 /* Idle-Line Detect Type */
-#define PT 0x0800 /* Parity Type */
-#define PE 0x0400 /* Parity Enable */
-#define M 0x0200 /* Mode Select */
-#define WAKE 0x0100 /* Wakeup by Address Mark */
-#define TIE 0x0080 /* Transmit Complete Interrupt Enable */
-#define TCIE 0x0040 /* Transmit Complete Interrupt Enable */
-#define RIE 0x0020 /* Receiver Interrupt Enable */
-#define ILIE 0x0010 /* Idle-Line Interrupt Enable */
-#define TE 0x0008 /* Transmitter Enable */
-#define RE 0x0004 /* Receiver Enable */
-#define RWU 0x0002 /* Receiver Wakeup */
-#define SBK 0x0001 /* Send Break */
-
-
-#define SCSR (volatile unsigned short int * const)(0x0c + QSM_CRB)
- /* SCI Status Register */
-#define TDRE 0x0100 /* Transmit Data Register Empty */
-#define TC 0x0080 /* Transmit Complete */
-#define RDRF 0x0040 /* Receive Data Register Full */
-#define RAF 0x0020 /* Receiver Active */
-#define IDLE 0x0010 /* Idle-Line Detected */
-#define OR 0x0008 /* Overrun Error */
-#define NF 0x0004 /* Noise Error Flag */
-#define FE 0x0002 /* Framing Error */
-#define PF 0x0001 /* Parity Error */
-
-
-#define SCDR (volatile unsigned short int * const)(0x0e + QSM_CRB)
- /* SCI Data Register */
-
-
-#define PORTQS (volatile unsigned char * const)(0x15 + QSM_CRB)
- /* Port QS Data Register */
-
-#define PQSPAR (volatile unsigned char * const)(0x16 + QSM_CRB)
- /* PORT QS Pin Assignment Rgister */
-/* Any bit cleared (zero) defines the corresponding pin to be an I/O
- pin. Any bit set defines the corresponding pin to be a QSPI
- signal. */
-/* note: PQS2 is a digital I/O pin unless the SPI is enabled in which
- case it becomes the SPI serial clock SCK. */
-/* note: PQS7 is a digital I/O pin unless the SCI transmitter is
- enabled in which case it becomes the SCI serial output TxD. */
-#define QSMFun 0x0
-#define QSMDis 0x1
-/*
- * PQSPAR Field | QSM Function | Discrete I/O pin
- *------------------+--------------+------------------ */
-#define PQSPA0 0 /* MISO | PQS0 */
-#define PQSPA1 1 /* MOSI | PQS1 */
-#define PQSPA2 2 /* SCK | PQS2 (see note)*/
-#define PQSPA3 3 /* PCSO/!SS | PQS3 */
-#define PQSPA4 4 /* PCS1 | PQS4 */
-#define PQSPA5 5 /* PCS2 | PQS5 */
-#define PQSPA6 6 /* PCS3 | PQS6 */
-#define PQSPA7 7 /* TxD | PQS7 (see note)*/
-
-
-#define DDRQS (volatile unsigned char * const)(0x17 + QSM_CRB)
- /* PORT QS Data Direction Register */
-/* Clearing a bit makes the corresponding pin an input; setting a bit
- makes the pin an output. */
-
-
-#define SPCR0 (volatile unsigned short int * const)(0x18 + QSM_CRB)
- /* QSPI Control Register 0 */
-#define MSTR 0x8000 /* Master/Slave Mode Select */
-#define WOMQ 0x4000 /* Wired-OR Mode for QSPI Pins */
-#define BITS 0x3c00 /* Bits Per Transfer */
-#define CPOL 0x0200 /* Clock Polarity */
-#define CPHA 0x0100 /* Clock Phase */
-#define SPBR 0x00ff /* Serial Clock Baud Rate */
-
-
-#define SPCR1 (volatile unsigned short int * const)(0x1a + QSM_CRB)
- /* QSPI Control Register 1 */
-#define SPE 0x8000 /* QSPI Enable */
-#define DSCKL 0x7f00 /* Delay before SCK */
-#define DTL 0x00ff /* Length of Delay after Transfer */
-
-
-#define SPCR2 (volatile unsigned short int * const)(0x1c + QSM_CRB)
- /* QSPI Control Register 2 */
-#define SPIFIE 0x8000 /* SPI Finished Interrupt Enable */
-#define WREN 0x4000 /* Wrap Enable */
-#define WRTO 0x2000 /* Wrap To */
-#define ENDQP 0x0f00 /* Ending Queue Pointer */
-#define NEWQP 0x000f /* New Queue Pointer Value */
-
-
-#define SPCR3 (volatile unsigned char * const)(0x1e + QSM_CRB)
- /* QSPI Control Register 3 */
-#define LOOPQ 0x0400 /* QSPI Loop Mode */
-#define HMIE 0x0200 /* HALTA and MODF Interrupt Enable */
-#define HALT 0x0100 /* Halt */
-
-
-#define SPSR (volatile unsigned char * const)(0x1f + QSM_CRB)
- /* QSPI Status Register */
-#define SPIF 0x0080 /* QSPI Finished Flag */
-#define MODF 0x0040 /* Mode Fault Flag */
-#define HALTA 0x0020 /* Halt Acknowlwdge Flag */
-#define CPTQP x0000f /* Completed Queue Pointer */
-
-#define QSPIRR (volatile unsigned char * const)(0x100 + QSM_CRB)
- /* QSPI Receive Data RAM */
-#define QSPITR (volatile unsigned char * const)(0x120 + QSM_CRB)
- /* QSPI Transmit Data RAM */
-#define QSPIcR (volatile unsigned char * const)(0x140 + QSM_CRB)
- /* QSPI Command RAM */
-
-#endif /* _QSM_H_ */
diff --git a/c/src/exec/score/cpu/m68k/rtems/.cvsignore b/c/src/exec/score/cpu/m68k/rtems/.cvsignore
deleted file mode 100644
index 282522db03..0000000000
--- a/c/src/exec/score/cpu/m68k/rtems/.cvsignore
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile
-Makefile.in
diff --git a/c/src/exec/score/cpu/m68k/rtems/score/.cvsignore b/c/src/exec/score/cpu/m68k/rtems/score/.cvsignore
deleted file mode 100644
index 282522db03..0000000000
--- a/c/src/exec/score/cpu/m68k/rtems/score/.cvsignore
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile
-Makefile.in
diff --git a/c/src/exec/score/cpu/m68k/rtems/score/cpu.h b/c/src/exec/score/cpu/m68k/rtems/score/cpu.h
deleted file mode 100644
index d988b4e4eb..0000000000
--- a/c/src/exec/score/cpu/m68k/rtems/score/cpu.h
+++ /dev/null
@@ -1,678 +0,0 @@
-/* cpu.h
- *
- * This include file contains information pertaining to the Motorola
- * m68xxx processor family.
- *
- * COPYRIGHT (c) 1989-1999.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#ifndef __CPU_h
-#define __CPU_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/m68k.h> /* pick up machine definitions */
-#ifndef ASM
-#include <rtems/score/types.h>
-#endif
-
-/* conditional compilation parameters */
-
-#define CPU_INLINE_ENABLE_DISPATCH TRUE
-#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE
-
-/*
- * Use the m68k's hardware interrupt stack support and have the
- * interrupt manager allocate the memory for it.
- */
-
-#if ( M68K_HAS_SEPARATE_STACKS == 1)
-#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
-#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
-#else
-#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
-#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
-#endif
-#define CPU_ALLOCATE_INTERRUPT_STACK 1
-
-/*
- * Does the RTEMS invoke the user's ISR with the vector number and
- * a pointer to the saved interrupt frame (1) or just the vector
- * number (0)?
- */
-
-#define CPU_ISR_PASSES_FRAME_POINTER 0
-
-/*
- * Some family members have no FP, some have an FPU such as the
- * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
- *
- * NOTE: If on a CPU without hardware FP, then one can use software
- * emulation. The gcc software FP emulation code has data which
- * must be contexted switched on a per task basis.
- */
-
-#if ( M68K_HAS_FPU == 1 )
-#define CPU_HARDWARE_FP TRUE
-#define CPU_SOFTWARE_FP FALSE
-#else
-#define CPU_HARDWARE_FP FALSE
-#if defined(__GNUC__)
-#define CPU_SOFTWARE_FP TRUE
-#else
-#define CPU_SOFTWARE_FP FALSE
-#endif
-#endif
-
-/*
- * All tasks are not by default floating point tasks on this CPU.
- * The IDLE task does not have a floating point context on this CPU.
- * It is safe to use the deferred floating point context switch
- * algorithm on this CPU.
- */
-
-#define CPU_ALL_TASKS_ARE_FP FALSE
-#define CPU_IDLE_TASK_IS_FP FALSE
-#define CPU_USE_DEFERRED_FP_SWITCH TRUE
-
-#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
-#define CPU_STACK_GROWS_UP FALSE
-#define CPU_STRUCTURE_ALIGNMENT
-
-/*
- * Define what is required to specify how the network to host conversion
- * routines are handled.
- */
-
-#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
-#define CPU_BIG_ENDIAN TRUE
-#define CPU_LITTLE_ENDIAN FALSE
-
-#ifndef ASM
-/* structures */
-
-/*
- * Basic integer context for the m68k family.
- */
-
-typedef struct {
- unsigned32 sr; /* (sr) status register */
- unsigned32 d2; /* (d2) data register 2 */
- unsigned32 d3; /* (d3) data register 3 */
- unsigned32 d4; /* (d4) data register 4 */
- unsigned32 d5; /* (d5) data register 5 */
- unsigned32 d6; /* (d6) data register 6 */
- unsigned32 d7; /* (d7) data register 7 */
- void *a2; /* (a2) address register 2 */
- void *a3; /* (a3) address register 3 */
- void *a4; /* (a4) address register 4 */
- void *a5; /* (a5) address register 5 */
- void *a6; /* (a6) address register 6 */
- void *a7_msp; /* (a7) master stack pointer */
-} Context_Control;
-
-/*
- * Floating point context ares
- */
-
-#if (CPU_SOFTWARE_FP == TRUE)
-
-/*
- * This is the same as gcc's view of the software FP condition code
- * register _fpCCR. The implementation of the emulation code is
- * in the gcc-VERSION/config/m68k directory. This structure is
- * correct as of gcc 2.7.2.2.
- */
-
-typedef struct {
- unsigned16 _exception_bits;
- unsigned16 _trap_enable_bits;
- unsigned16 _sticky_bits;
- unsigned16 _rounding_mode;
- unsigned16 _format;
- unsigned16 _last_operation;
- union {
- float sf;
- double df;
- } _operand1;
- union {
- float sf;
- double df;
- } _operand2;
-} Context_Control_fp;
-
-#else
-
-/*
- * FP context save area for the M68881/M68882 numeric coprocessors.
- */
-
-typedef struct {
- unsigned8 fp_save_area[332]; /* 216 bytes for FSAVE/FRESTORE */
- /* 96 bytes for FMOVEM FP0-7 */
- /* 12 bytes for FMOVEM CREGS */
- /* 4 bytes for non-null flag */
-} Context_Control_fp;
-#endif
-
-/*
- * The following structures define the set of information saved
- * on the current stack by RTEMS upon receipt of each exc/interrupt.
- * These are not used by m68k handlers.
- * The exception frame is for rdbg.
- */
-
-typedef struct {
- unsigned32 vecnum; /* vector number */
-} CPU_Interrupt_frame;
-
-typedef struct {
- unsigned32 vecnum; /* vector number */
- unsigned32 sr; /* status register */
- unsigned32 pc; /* program counter */
- unsigned32 d0, d1, d2, d3, d4, d5, d6, d7;
- unsigned32 a0, a1, a2, a3, a4, a5, a6, a7;
-} CPU_Exception_frame;
-
-/*
- * The following table contains the information required to configure
- * the m68k specific parameters.
- */
-
-typedef struct {
- void (*pretasking_hook)( void );
- void (*predriver_hook)( void );
- void (*postdriver_hook)( void );
- void (*idle_task)( void );
- boolean do_zero_of_workspace;
- unsigned32 idle_task_stack_size;
- unsigned32 interrupt_stack_size;
- unsigned32 extra_mpci_receive_server_stack;
- void * (*stack_allocate_hook)( unsigned32 );
- void (*stack_free_hook)( void* );
- /* end of fields required on all CPUs */
-
- m68k_isr *interrupt_vector_table;
-} rtems_cpu_table;
-
-/*
- * Macros to access required entires in the CPU Table are in
- * the file rtems/system.h.
- */
-
-/*
- * Macros to access M68K specific additions to the CPU Table
- */
-
-#define rtems_cpu_configuration_get_interrupt_vector_table() \
- (_CPU_Table.interrupt_vector_table)
-
-/* variables */
-
-SCORE_EXTERN void *_CPU_Interrupt_stack_low;
-SCORE_EXTERN void *_CPU_Interrupt_stack_high;
-
-extern char _VBR[];
-
-#if ( M68K_HAS_VBR == 0 )
-
-/*
- * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
- * pushed onto the stack. This is not is the same order as VBR processors.
- * The ISR handler takes the format and uses it for dispatching the user
- * handler.
- *
- * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
- *
- */
-
-typedef struct {
- unsigned16 move_a7; /* move #FORMAT_ID,%a7@- */
- unsigned16 format_id;
- unsigned16 jmp; /* jmp _ISR_Handlers */
- unsigned32 isr_handler;
-} _CPU_ISR_handler_entry;
-
-#define M68K_MOVE_A7 0x3F3C
-#define M68K_JMP 0x4EF9
-
- /* points to jsr-exception-table in targets wo/ VBR register */
-SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
-
-#endif /* M68K_HAS_VBR */
-#endif /* ASM */
-
-/* constants */
-
-/*
- * This defines the number of levels and the mask used to pick those
- * bits out of a thread mode.
- */
-
-#define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */
-#define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */
-
-/*
- * context size area for floating point
- */
-
-#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
-
-/*
- * extra stack required by the MPCI receive server thread
- */
-
-#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
-
-/*
- * m68k family supports 256 distinct vectors.
- */
-
-#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
-#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
-
-/*
- * This is defined if the port has a special way to report the ISR nesting
- * level. Most ports maintain the variable _ISR_Nest_level.
- */
-
-#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
-
-/*
- * Minimum size of a thread's stack.
- */
-
-#define CPU_STACK_MINIMUM_SIZE 4096
-
-/*
- * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries.
- */
-
-#define CPU_ALIGNMENT 4
-#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
-#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
-
-/*
- * On m68k thread stacks require no further alignment after allocation
- * from the Workspace.
- */
-
-#define CPU_STACK_ALIGNMENT 0
-
-#ifndef ASM
-
-/* macros */
-
-/*
- * ISR handler macros
- *
- * These macros perform the following functions:
- * + initialize the RTEMS vector table
- * + disable all maskable CPU interrupts
- * + restore previous interrupt level (enable)
- * + temporarily restore interrupts (flash)
- * + set a particular level
- */
-
-#define _CPU_Initialize_vectors()
-
-#define _CPU_ISR_Disable( _level ) \
- m68k_disable_interrupts( _level )
-
-#define _CPU_ISR_Enable( _level ) \
- m68k_enable_interrupts( _level )
-
-#define _CPU_ISR_Flash( _level ) \
- m68k_flash_interrupts( _level )
-
-#define _CPU_ISR_Set_level( _newlevel ) \
- m68k_set_interrupt_level( _newlevel )
-
-unsigned32 _CPU_ISR_Get_level( void );
-
-/* end of ISR handler macros */
-
-/*
- * Context handler macros
- *
- * These macros perform the following functions:
- * + initialize a context area
- * + restart the current thread
- * + calculate the initial pointer into a FP context area
- * + initialize an FP context area
- */
-
-#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
- _isr, _entry_point, _is_fp ) \
- do { \
- unsigned32 _stack; \
- \
- (_the_context)->sr = 0x3000 | ((_isr) << 8); \
- _stack = (unsigned32)(_stack_base) + (_size) - 4; \
- (_the_context)->a7_msp = (void *)_stack; \
- *(void **)_stack = (void *)(_entry_point); \
- } while ( 0 )
-
-#define _CPU_Context_Restart_self( _the_context ) \
- { asm volatile( "movew %0,%%sr ; " \
- "moval %1,%%a7 ; " \
- "rts" \
- : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
- : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
- }
-
-/*
- * Floating Point Context Area Support routines
- */
-
-#if (CPU_SOFTWARE_FP == TRUE)
-
-/*
- * This software FP implementation is only for GCC.
- */
-
-#define _CPU_Context_Fp_start( _base, _offset ) \
- ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
-
-
-#define _CPU_Context_Initialize_fp( _fp_area ) \
- { \
- Context_Control_fp *_fp; \
- _fp = *(Context_Control_fp **)_fp_area; \
- _fp->_exception_bits = 0; \
- _fp->_trap_enable_bits = 0; \
- _fp->_sticky_bits = 0; \
- _fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \
- _fp->_format = 0; /* NIL */ \
- _fp->_last_operation = 0; /* NOOP */ \
- _fp->_operand1.df = 0; \
- _fp->_operand2.df = 0; \
- }
-#else
-#define _CPU_Context_Fp_start( _base, _offset ) \
- ((void *) \
- _Addresses_Add_offset( \
- (_base), \
- (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
- ) \
- )
-
-#define _CPU_Context_Initialize_fp( _fp_area ) \
- { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \
- \
- *(--(_fp_context)) = 0; \
- *(_fp_area) = (unsigned8 *)(_fp_context); \
- }
-#endif
-
-/* end of Context handler macros */
-
-/*
- * Fatal Error manager macros
- *
- * These macros perform the following functions:
- * + disable interrupts and halt the CPU
- */
-
-#if ( M68K_COLDFIRE_ARCH == 1 )
-#define _CPU_Fatal_halt( _error ) \
- { asm volatile( "move.w %%sr,%%d0\n\t" \
- "or.l %2,%%d0\n\t" \
- "move.w %%d0,%%sr\n\t" \
- "move.l %1,%%d0\n\t" \
- "move.l #0xDEADBEEF,%%d1\n\t" \
- "halt" \
- : "=g" (_error) \
- : "0" (_error), "d"(0x0700) \
- : "d0", "d1" ); \
- }
-#else
-#define _CPU_Fatal_halt( _error ) \
- { asm volatile( "movl %0,%%d0; " \
- "orw #0x0700,%%sr; " \
- "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
- }
-#endif
-
-/* end of Fatal Error manager macros */
-
-/*
- * Bitfield handler macros
- *
- * These macros perform the following functions:
- * + scan for the highest numbered (MSB) set in a 16 bit bitfield
- *
- * NOTE:
- *
- * It appears that on the M68020 bitfield are always 32 bits wide
- * when in a register. This code forces the bitfield to be in
- * memory (it really always is anyway). This allows us to
- * have a real 16 bit wide bitfield which operates "correctly."
- */
-
-#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
-#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
-
-#if ( M68K_HAS_BFFFO == 1 )
-
-#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
- asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
-#else
-
-/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
- _CPU_Priority_bits_index is not needed), handles the 0 case, and
- does not molest _value -- jsg */
-#if ( M68K_COLDFIRE_ARCH == 1 )
-#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
- { \
- extern const unsigned char __BFFFOtable[256]; \
- register int dumby; \
- \
- asm volatile ( \
- " clr.l %1\n" \
- " move.w %2,%1\n" \
- " lsr.l #8,%1\n" \
- " beq.s 1f\n" \
- " move.b (%3,%1),%0\n" \
- " bra.s 0f\n" \
- "1: move.w %2,%1\n" \
- " move.b (%3,%1),%0\n" \
- " addq.l #8,%0\n" \
- "0: and.l #0xff,%0\n" \
- : "=&d" ((_output)), "=&d" ((dumby)) \
- : "d" ((_value)), "ao" ((__BFFFOtable)) \
- : "cc" ) ; \
- }
-#elif ( M68K_HAS_EXTB_L == 1 )
-#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
- { \
- extern const unsigned char __BFFFOtable[256]; \
- register int dumby; \
- \
- asm volatile ( " move.w %2,%1\n" \
- " lsr.w #8,%1\n" \
- " beq.s 1f\n" \
- " move.b (%3,%1.w),%0\n" \
- " extb.l %0\n" \
- " bra.s 0f\n" \
- "1: moveq.l #8,%0\n" \
- " add.b (%3,%2.w),%0\n" \
- "0:\n" \
- : "=&d" ((_output)), "=&d" ((dumby)) \
- : "d" ((_value)), "ao" ((__BFFFOtable)) \
- : "cc" ) ; \
- }
-#else
-#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
- { \
- extern const unsigned char __BFFFOtable[256]; \
- register int dumby; \
- \
- asm volatile ( " move.w %2,%1\n" \
- " lsr.w #8,%1\n" \
- " beq.s 1f\n" \
- " move.b (%3,%1.w),%0\n" \
- " and.l #0x000000ff,%0\n"\
- " bra.s 0f\n" \
- "1: moveq.l #8,%0\n" \
- " add.b (%3,%2.w),%0\n" \
- "0:\n" \
- : "=&d" ((_output)), "=&d" ((dumby)) \
- : "d" ((_value)), "ao" ((__BFFFOtable)) \
- : "cc" ) ; \
- }
-#endif
-
-#endif
-
-/* end of Bitfield handler macros */
-
-/*
- * Priority handler macros
- *
- * These macros perform the following functions:
- * + return a mask with the bit for this major/minor portion of
- * of thread priority set.
- * + translate the bit number returned by "Bitfield_find_first_bit"
- * into an index into the thread ready chain bit maps
- */
-
-#define _CPU_Priority_Mask( _bit_number ) \
- ( 0x8000 >> (_bit_number) )
-
-#define _CPU_Priority_bits_index( _priority ) \
- (_priority)
-
-/* end of Priority handler macros */
-
-/* functions */
-
-/*
- * _CPU_Initialize
- *
- * This routine performs CPU dependent initialization.
- */
-
-void _CPU_Initialize(
- rtems_cpu_table *cpu_table,
- void (*thread_dispatch)
-);
-
-/*
- * _CPU_ISR_install_raw_handler
- *
- * This routine installs a "raw" interrupt handler directly into the
- * processor's vector table.
- */
-
-void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-/*
- * _CPU_ISR_install_vector
- *
- * This routine installs an interrupt vector.
- */
-
-void _CPU_ISR_install_vector(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-/*
- * _CPU_Install_interrupt_stack
- *
- * This routine installs the hardware interrupt stack pointer.
- */
-
-void _CPU_Install_interrupt_stack( void );
-
-/*
- * _CPU_Context_switch
- *
- * This routine switches from the run context to the heir context.
- */
-
-void _CPU_Context_switch(
- Context_Control *run,
- Context_Control *heir
-);
-
-/*
- * _CPU_Context_save_fp
- *
- * This routine saves the floating point context passed to it.
- */
-
-void _CPU_Context_save_fp(
- void **fp_context_ptr
-);
-
-/*
- * _CPU_Context_restore_fp
- *
- * This routine restores the floating point context passed to it.
- */
-
-void _CPU_Context_restore_fp(
- void **fp_context_ptr
-);
-
-#if (M68K_HAS_FPSP_PACKAGE == 1)
-/*
- * Hooks for the Floating Point Support Package (FPSP) provided by Motorola
- *
- * NOTES:
- *
- * Motorola 68k family CPU's before the 68040 used a coprocessor
- * (68881 or 68882) to handle floating point. The 68040 has internal
- * floating point support -- but *not* the complete support provided by
- * the 68881 or 68882. The leftover functions are taken care of by the
- * M68040 Floating Point Support Package. Quoting from the MC68040
- * Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
- *
- * "When used with the M68040FPSP, the MC68040 FPU is fully
- * compliant with IEEE floating-point standards."
- *
- * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
- * is invoked early in the application code to insure that proper FP
- * behavior is installed. This is not left to the BSP to call, since
- * this would force all applications using that BSP to use FPSP which
- * is not necessarily desirable.
- *
- * There is a similar package for the 68060 but RTEMS does not yet
- * support the 68060.
- */
-
-void M68KFPSPInstallExceptionHandlers (void);
-
-SCORE_EXTERN int (*_FPSP_install_raw_handler)(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-#endif
-
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/* end of include file */
diff --git a/c/src/exec/score/cpu/m68k/rtems/score/m68k.h b/c/src/exec/score/cpu/m68k/rtems/score/m68k.h
deleted file mode 100644
index 62055d803e..0000000000
--- a/c/src/exec/score/cpu/m68k/rtems/score/m68k.h
+++ /dev/null
@@ -1,416 +0,0 @@
-/* m68k.h
- *
- * This include file contains information pertaining to the Motorola
- * m68xxx processor family.
- *
- * COPYRIGHT (c) 1989-1999.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#ifndef __M68k_h
-#define __M68k_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * This section contains the information required to build
- * RTEMS for a particular member of the Motorola MC68xxx
- * family. It does this by setting variables to indicate
- * which implementation dependent features are present in
- * a particular member of the family.
- *
- * Currently recognized:
- * -m68000
- * -m68000 -msoft-float
- * -m68020
- * -m68020 -msoft-float
- * -m68030
- * -m68040 -msoft-float
- * -m68040
- * -m68040 -msoft-float
- * -m68060
- * -m68060 -msoft-float
- * -m68302 (no FP) (deprecated, use -m68000)
- * -m68332 (no FP) (deprecated, use -mcpu32)
- * -mcpu32 (no FP)
- * -m5200 (no FP)
- *
- * As of gcc 2.8.1 and egcs 1.1, there is no distinction made between
- * the CPU32 and CPU32+. The option -mcpu32 generates code which can
- * be run on either core. RTEMS distinguishes between these two cores
- * because they have different alignment rules which impact performance.
- * If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should
- * be defined in your custom file (see make/custom/gen68360.cfg for an
- * example of how to do this. If gcc ever distinguishes between these
- * two cores, then RTEMS__mcpu32p__ usage will be replaced with the
- * appropriate compiler defined predefine.
- *
- * Here is some information on the 040 variants (courtesy of Doug McBride,
- * mcbride@rodin.colorado.edu):
- *
- * "The 68040 is a superset of the 68EC040 and the 68LC040. The
- * 68EC040 and 68LC040 do not have FPU's. The 68LC040 and the
- * 68EC040 have renamed the DLE pin as JS0 which must be tied to
- * Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1. The
- * 68EC040 has access control units instead of memory management units.
- * The 68EC040 should not have the PFLUSH or PTEST instructions executed
- * (cause an indeterminate result). The 68EC040 and 68LC040 do not
- * implement the DLE or multiplexed bus modes. The 68EC040 does not
- * implement the output buffer impedance selection mode of operation."
- *
- * M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
- * which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
- * 68010, 68302, 68306, 68307). This instruction is available on the 68020
- * up and the cpu32 based models.
- *
- * M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned
- * data access (68020, 68030, 68040, 68060, CPU32+).
- *
- * NOTE:
- * Eventually it would be nice to evaluate doing a lot of this section
- * by having each model specify which core it uses and then go from there.
- */
-
-/*
- * Figure out all CPU Model Feature Flags based upon compiler
- * predefines. Notice the only exception to this is that
- * gcc does not distinguish between CPU32 and CPU32+. This
- * feature selection logic is setup such that if RTEMS__mcpu32p__
- * is defined, then CPU32+ rules are used. Otherwise, the safe
- * but less efficient CPU32 rules are used for the CPU32+.
- */
-
-#if defined(__mc68020__)
-
-#define CPU_MODEL_NAME "m68020"
-#define M68K_HAS_VBR 1
-#define M68K_HAS_SEPARATE_STACKS 1
-#define M68K_HAS_BFFFO 1
-#define M68K_HAS_PREINDEXING 1
-#define M68K_HAS_EXTB_L 1
-#define M68K_HAS_MISALIGNED 1
-# if defined (__HAVE_68881__)
-# define M68K_HAS_FPU 1
-# define M68K_HAS_FPSP_PACKAGE 0
-# else
-# define M68K_HAS_FPU 0
-# define M68K_HAS_FPSP_PACKAGE 0
-# endif
-
-#elif defined(__mc68030__)
-
-#define CPU_MODEL_NAME "m68030"
-#define M68K_HAS_VBR 1
-#define M68K_HAS_SEPARATE_STACKS 1
-#define M68K_HAS_BFFFO 1
-#define M68K_HAS_PREINDEXING 1
-#define M68K_HAS_EXTB_L 1
-#define M68K_HAS_MISALIGNED 1
-# if defined (__HAVE_68881__)
-# define M68K_HAS_FPU 1
-# define M68K_HAS_FPSP_PACKAGE 0
-# else
-# define M68K_HAS_FPU 0
-# define M68K_HAS_FPSP_PACKAGE 0
-# endif
-
-#elif defined(__mc68040__)
-
-#define CPU_MODEL_NAME "m68040"
-#define M68K_HAS_VBR 1
-#define M68K_HAS_SEPARATE_STACKS 1
-#define M68K_HAS_BFFFO 1
-#define M68K_HAS_PREINDEXING 1
-#define M68K_HAS_EXTB_L 1
-#define M68K_HAS_MISALIGNED 1
-# if defined (__HAVE_68881__)
-# define M68K_HAS_FPU 1
-# define M68K_HAS_FPSP_PACKAGE 1
-# else
-# define M68K_HAS_FPU 0
-# define M68K_HAS_FPSP_PACKAGE 0
-# endif
-
-#elif defined(__mc68060__)
-
-#define CPU_MODEL_NAME "m68060"
-#define M68K_HAS_VBR 1
-#define M68K_HAS_SEPARATE_STACKS 0
-#define M68K_HAS_BFFFO 1
-#define M68K_HAS_PREINDEXING 1
-#define M68K_HAS_EXTB_L 1
-#define M68K_HAS_MISALIGNED 1
-# if defined (__HAVE_68881__)
-# define M68K_HAS_FPU 1
-# define M68K_HAS_FPSP_PACKAGE 0
-# else
-# define M68K_HAS_FPU 0
-# define M68K_HAS_FPSP_PACKAGE 0
-# endif
-
-#elif defined(__mc68302__)
-
-#define CPU_MODEL_NAME "m68302"
-#define M68K_HAS_VBR 0
-#define M68K_HAS_SEPARATE_STACKS 0
-#define M68K_HAS_BFFFO 0
-#define M68K_HAS_PREINDEXING 0
-#define M68K_HAS_EXTB_L 0
-#define M68K_HAS_MISALIGNED 0
-#define M68K_HAS_FPU 0
-#define M68K_HAS_FPSP_PACKAGE 0
-
- /* gcc and egcs do not distinguish between CPU32 and CPU32+ */
-#elif defined(RTEMS__mcpu32p__)
-
-#define CPU_MODEL_NAME "mcpu32+"
-#define M68K_HAS_VBR 1
-#define M68K_HAS_SEPARATE_STACKS 0
-#define M68K_HAS_BFFFO 0
-#define M68K_HAS_PREINDEXING 1
-#define M68K_HAS_EXTB_L 1
-#define M68K_HAS_MISALIGNED 1
-#define M68K_HAS_FPU 0
-#define M68K_HAS_FPSP_PACKAGE 0
-
-#elif defined(__mcpu32__)
-
-#define CPU_MODEL_NAME "mcpu32"
-#define M68K_HAS_VBR 1
-#define M68K_HAS_SEPARATE_STACKS 0
-#define M68K_HAS_BFFFO 0
-#define M68K_HAS_PREINDEXING 1
-#define M68K_HAS_EXTB_L 1
-#define M68K_HAS_MISALIGNED 0
-#define M68K_HAS_FPU 0
-#define M68K_HAS_FPSP_PACKAGE 0
-
-#elif defined(__mcf5200__)
-/* Motorola ColdFire V2 core - RISC/68020 hybrid */
-#define CPU_MODEL_NAME "m5200"
-#define M68K_HAS_VBR 1
-#define M68K_HAS_BFFFO 0
-#define M68K_HAS_SEPARATE_STACKS 0
-#define M68K_HAS_PREINDEXING 0
-#define M68K_HAS_EXTB_L 1
-#define M68K_HAS_MISALIGNED 1
-#define M68K_HAS_FPU 0
-#define M68K_HAS_FPSP_PACKAGE 0
-#define M68K_COLDFIRE_ARCH 1
-
-#elif defined(__mc68000__)
-
-#define CPU_MODEL_NAME "m68000"
-#define M68K_HAS_VBR 0
-#define M68K_HAS_SEPARATE_STACKS 0
-#define M68K_HAS_BFFFO 0
-#define M68K_HAS_PREINDEXING 0
-#define M68K_HAS_EXTB_L 0
-#define M68K_HAS_MISALIGNED 0
-# if defined (__HAVE_68881__)
-# define M68K_HAS_FPU 1
-# define M68K_HAS_FPSP_PACKAGE 0
-# else
-# define M68K_HAS_FPU 0
-# define M68K_HAS_FPSP_PACKAGE 0
-# endif
-
-#else
-
-#error "Unsupported CPU model -- are you sure you're running a 68k compiler?"
-
-#endif
-
-#ifndef ASM
-#include <rtems/score/types.h>
-#endif
-
-/*
- * If the above did not specify a ColdFire architecture, then set
- * this flag to indicate that it is not a ColdFire CPU.
- */
-
-#if !defined(M68K_COLDFIRE_ARCH)
-#define M68K_COLDFIRE_ARCH 0
-#endif
-
-/*
- * Define the name of the CPU family.
- */
-
-#if ( M68K_COLDFIRE_ARCH == 1 )
- #define CPU_NAME "Motorola ColdFire"
-#else
- #define CPU_NAME "Motorola MC68xxx"
-#endif
-
-#ifndef ASM
-
-#if ( M68K_COLDFIRE_ARCH == 1 )
-#define m68k_disable_interrupts( _level ) \
- do { register unsigned32 _tmpsr = 0x0700; \
- asm volatile ( "move.w %%sr,%0\n\t" \
- "or.l %0,%1\n\t" \
- "move.w %1,%%sr" \
- : "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) ); \
- } while( 0 )
-#else
-#define m68k_disable_interrupts( _level ) \
- asm volatile ( "move.w %%sr,%0\n\t" \
- "or.w #0x0700,%%sr" \
- : "=d" (_level))
-#endif
-
-#define m68k_enable_interrupts( _level ) \
- asm volatile ( "move.w %0,%%sr " : : "d" (_level));
-
-#if ( M68K_COLDFIRE_ARCH == 1 )
-#define m68k_flash_interrupts( _level ) \
- do { register unsigned32 _tmpsr = 0x0700; \
- asm volatile ( "move.w %2,%%sr\n\t" \
- "or.l %2,%1\n\t" \
- "move.w %1,%%sr" \
- : "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) ); \
- } while( 0 )
-#else
-#define m68k_flash_interrupts( _level ) \
- asm volatile ( "move.w %0,%%sr\n\t" \
- "or.w #0x0700,%%sr" \
- : : "d" (_level))
-#endif
-
-#define m68k_get_interrupt_level( _level ) \
- do { \
- register unsigned32 _tmpsr; \
- \
- asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
- _level = (_tmpsr & 0x0700) >> 8; \
- } while (0)
-
-#define m68k_set_interrupt_level( _newlevel ) \
- do { \
- register unsigned32 _tmpsr; \
- \
- asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
- _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
- asm volatile( "move.w %0,%%sr" : : "d" (_tmpsr)); \
- } while (0)
-
-#if ( M68K_HAS_VBR == 1 && M68K_COLDFIRE_ARCH == 0 )
-#define m68k_get_vbr( vbr ) \
- asm volatile ( "movec %%vbr,%0 " : "=r" (vbr))
-
-#define m68k_set_vbr( vbr ) \
- asm volatile ( "movec %0,%%vbr " : : "r" (vbr))
-
-#elif ( M68K_COLDFIRE_ARCH == 1 )
-#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
-
-#define m68k_set_vbr( _vbr ) \
- asm volatile ("move.l %%a7,%%d1 \n\t" \
- "move.l %0,%%a7\n\t" \
- "movec %%a7,%%vbr\n\t" \
- "move.l %%d1,%%a7\n\t" \
- : : "d" (_vbr) : "d1" );
-
-#else
-#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
-#define m68k_set_vbr( _vbr )
-#endif
-
-/*
- * The following routine swaps the endian format of an unsigned int.
- * It must be static because it is referenced indirectly.
- */
-#if ( M68K_COLDFIRE_ARCH == 1 )
-
-/* There are no rotate commands in Coldfire architecture. We will use
- * generic implementation of endian swapping for Coldfire.
- */
-static inline unsigned int m68k_swap_u32(
- unsigned int value
- )
-{
- unsigned32 byte1, byte2, byte3, byte4, swapped;
-
- byte4 = (value >> 24) & 0xff;
- byte3 = (value >> 16) & 0xff;
- byte2 = (value >> 8) & 0xff;
- byte1 = value & 0xff;
-
- swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
- return( swapped );
-}
-
-static inline unsigned int m68k_swap_u16(
- unsigned int value
-)
-{
- return (((value & 0xff) << 8) | ((value >> 8) & 0xff));
-}
-
-#else
-
-static inline unsigned int m68k_swap_u32(
- unsigned int value
-)
-{
- unsigned int swapped = value;
-
- asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
- asm volatile( "swap %0" : "=d" (swapped) : "0" (swapped) );
- asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
-
- return( swapped );
-}
-
-static inline unsigned int m68k_swap_u16(
- unsigned int value
-)
-{
- unsigned short swapped = value;
-
- asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
-
- return( swapped );
-}
-#endif
-
-#define CPU_swap_u32( value ) m68k_swap_u32( value )
-#define CPU_swap_u16( value ) m68k_swap_u16( value )
-
-
-/*
- * _CPU_virtual_to_physical
- *
- * DESCRIPTION:
- *
- * This function is used to map virtual addresses to physical
- * addresses.
- *
- * FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE
- * PHYSICAL ADDRESSES
- */
-static inline void * _CPU_virtual_to_physical (
- const void * d_addr )
-{
- return (void *) d_addr;
-}
-
-
-#endif /* !ASM */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __M68K_h */
-/* end of include file */
diff --git a/c/src/exec/score/cpu/m68k/rtems/score/types.h b/c/src/exec/score/cpu/m68k/rtems/score/types.h
deleted file mode 100644
index 7b1a1c643e..0000000000
--- a/c/src/exec/score/cpu/m68k/rtems/score/types.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* m68ktypes.h
- *
- * This include file contains type definitions pertaining to the Motorola
- * m68xxx processor family.
- *
- * COPYRIGHT (c) 1989-1999.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#ifndef __M68k_TYPES_h
-#define __M68k_TYPES_h
-
-#ifndef ASM
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * This section defines the basic types for this processor.
- */
-
-typedef unsigned char unsigned8; /* unsigned 8-bit integer */
-typedef unsigned short unsigned16; /* unsigned 16-bit integer */
-typedef unsigned int unsigned32; /* unsigned 32-bit integer */
-typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
-
-typedef unsigned16 Priority_Bit_map_control;
-
-typedef signed char signed8; /* 8-bit signed integer */
-typedef signed short signed16; /* 16-bit signed integer */
-typedef signed int signed32; /* 32-bit signed integer */
-typedef signed long long signed64; /* 64 bit signed integer */
-
-typedef unsigned32 boolean; /* Boolean value */
-
-typedef float single_precision; /* single precision float */
-typedef double double_precision; /* double precision float */
-
-typedef void m68k_isr;
-
-typedef void ( *m68k_isr_entry )( void );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !ASM */
-
-#endif
-/* end of include file */
diff --git a/c/src/exec/score/cpu/m68k/sim.h b/c/src/exec/score/cpu/m68k/sim.h
deleted file mode 100644
index db2ec89d3a..0000000000
--- a/c/src/exec/score/cpu/m68k/sim.h
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
- *-------------------------------------------------------------------
- *
- * SIM -- System Integration Module
- *
- * The system integration module (SIM) is used on many Motorola 16-
- * and 32-bit MCUs for the following functions:
- *
- * () System configuration and protection. Bus and software watchdog
- * monitors are provided in addition to periodic interrupt generators.
- *
- * () Clock signal generation for other intermodule bus (IMB) members
- * and external devices.
- *
- * () The generation of chip-select signals that simplify external
- * circuitry interface.
- *
- * () Data ports that are available for general purpose input and
- * output.
- *
- * () A system test block that is intended only for factory tests.
- *
- * For more information, refer to Motorola's "Modular Microcontroller
- * Family System Integration Module Reference Manual" (Motorola document
- * SIMRM/AD).
- *
- * This file has been created by John S. Gwynne for support of
- * Motorola's 68332 MCU in the efi332 project.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the following conditions are met:
- * 1. Redistribution of source code and documentation must retain
- * the above authorship, this list of conditions and the
- * following disclaimer.
- * 2. The name of the author may not be used to endorse or promote
- * products derived from this software without specific prior
- * written permission.
- *
- * This software is provided "AS IS" without warranty of any kind,
- * either expressed or implied, including, but not limited to, the
- * implied warranties of merchantability, title and fitness for a
- * particular purpose.
- *
- *------------------------------------------------------------------
- *
- * $Id$
- */
-
-#ifndef _SIM_H_
-#define _SIM_H_
-
-
-/* SAM-- shift and mask */
-#undef SAM
-#define SAM(a,b,c) ((a << b) & c)
-
-/*
- * These macros make this file usable from assembly.
- */
-
-#ifdef ASM
-#define SIM_VOLATILE_USHORT_POINTER
-#define SIM_VOLATILE_UCHAR_POINTER
-#else
-#define SIM_VOLATILE_USHORT_POINTER (volatile unsigned short int * const)
-#define SIM_VOLATILE_UCHAR_POINTER (volatile unsigned char * const)
-#endif
-
-/* SIM_CRB (SIM Control Register Block) base address of the SIM
- control registers */
-#ifndef SIM_CRB
-#if SIM_MM == 0
-#define SIM_CRB 0x7ffa00
-#else /* SIM_MM */
-#undef SIM_MM
-#define SIM_MM 1
-#define SIM_CRB 0xfffa00
-#endif /* SIM_MM */
-#endif /* SIM_CRB */
-
-
-#define SIMCR SIM_VOLATILE_USHORT_POINTER(0x00 + SIM_CRB)
- /* Module Configuration Register */
-#define EXOFF 0x8000 /* External Clock Off */
-#define FRZSW 0x4000 /* Freeze Software Enable */
-#define FRZBM 0x2000 /* Freeze Bus Monitor Enable */
-#define SLVEN 0x0800 /* Factory Test Model Enabled (ro)*/
-#define SHEN 0x0300 /* Show Cycle Enable */
-#define SUPV 0x0080 /* Supervisor/Unrestricted Data Space */
-#define MM 0x0040 /* Module Mapping */
-#define IARB 0x000f /* Interrupt Arbitration Field */
-
-
-
-#define SIMTR SIM_VOLATILE_USHORT_POINTER(0x02 + SIM_CRB)
- /* SIM Test Register */
-/* Used only for factor testing */
-
-
-
-#define SYNCR SIM_VOLATILE_USHORT_POINTER(0x04 + SIM_CRB)
- /* Clock Synthesizer Control Register */
-#define VCO 0x8000 /* Frequency Control (VCO) */
-#define PRESCALE 0x4000 /* Frequency Control Bit (Prescale) */
-#define COUNTER 0x3f00 /* Frequency Control Counter */
-#define EDIV 0x0080 /* ECLK Divide Rate */
-#define SLIMP 0x0010 /* Limp Mode Status */
-#define SLOCK 0x0008 /* Synthesizer Lock */
-#define RSTEN 0x0004 /* Reset Enable */
-#define STSIM 0x0002 /* Stop Mode SIM Clock */
-#define STEXT 0x0001 /* Stop Mode External Clock */
-
-
-
-#define RSR SIM_VOLATILE_UCHAR_POINTER(0x07 + SIM_CRB)
- /* Reset Status Register */
-#define EXT 0x0080 /* External Reset */
-#define POW 0x0040 /* Power-On Reset */
-#define SW 0x0020 /* Software Watchdog Reset */
-#define DBF 0x0010 /* Double Bus Fault Reset */
-#define LOC 0x0004 /* Loss of Clock Reset */
-#define SYS 0x0002 /* System Reset */
-#define TST 0x0001 /* Test Submodule Reset */
-
-
-
-#define SIMTRE SIM_VOLATILE_USHORT_POINTER(0x08 + SIM_CRB)
- /* System Integration Test Register */
-/* Used only for factor testing */
-
-
-
-#define PORTE0 SIM_VOLATILE_UCHAR_POINTER(0x11 + SIM_CRB)
-#define PORTE1 SIM_VOLATILE_UCHAR_POINTER(0x13 + SIM_CRB)
- /* Port E Data Register */
-#define DDRE SIM_VOLATILE_UCHAR_POINTER(0x15 + SIM_CRB)
- /* Port E Data Direction Register */
-#define PEPAR SIM_VOLATILE_UCHAR_POINTER(0x17 + SIM_CRB)
- /* Port E Pin Assignment Register */
-/* Any bit cleared (zero) defines the corresponding pin to be an I/O
- pin. Any bit set defines the corresponding pin to be a bus control
- signal. */
-
-
-
-#define PORTF0 SIM_VOLATILE_UCHAR_POINTER(0x19 + SIM_CRB)
-#define PORTF1 SIM_VOLATILE_UCHAR_POINTER(0x1b + SIM_CRB)
- /* Port F Data Register */
-#define DDRF SIM_VOLATILE_UCHAR_POINTER(0x1d + SIM_CRB)
- /* Port E Data Direction Register */
-#define PFPAR SIM_VOLATILE_UCHAR_POINTER(0x1f + SIM_CRB)
-/* Any bit cleared (zero) defines the corresponding pin to be an I/O
- pin. Any bit set defines the corresponding pin to be a bus control
- signal. */
-
-
-
-#define SYPCR SIM_VOLATILE_UCHAR_POINTER(0x21 + SIM_CRB)
-/* !!! can write to only once after reset !!! */
- /* System Protection Control Register */
-#define SWE 0x80 /* Software Watch Enable */
-#define SWP 0x40 /* Software Watchdog Prescale */
-#define SWT 0x30 /* Software Watchdog Timing */
-#define HME 0x08 /* Halt Monitor Enable */
-#define BME 0x04 /* Bus Monitor External Enable */
-#define BMT 0x03 /* Bus Monitor Timing */
-
-
-
-#define PICR SIM_VOLATILE_USHORT_POINTER(0x22 + SIM_CRB)
- /* Periodic Interrupt Control Reg. */
-#define PIRQL 0x0700 /* Periodic Interrupt Request Level */
-#define PIV 0x00ff /* Periodic Interrupt Level */
-
-
-
-#define PITR SIM_VOLATILE_USHORT_POINTER(0x24 + SIM_CRB)
- /* Periodic Interrupt Timer Register */
-#define PTP 0x0100 /* Periodic Timer Prescaler Control */
-#define PITM 0x00ff /* Periodic Interrupt Timing Modulus */
-
-
-
-#define SWSR SIM_VOLATILE_UCHAR_POINTER(0x27 + SIM_CRB)
- /* Software Service Register */
-/* write 0x55 then 0xaa to service the software watchdog */
-
-
-
-#define TSTMSRA SIM_VOLATILE_USHORT_POINTER(0x30 + SIM_CRB)
- /* Test Module Master Shift A */
-#define TSTMSRB SIM_VOLATILE_USHORT_POINTER(0x32 + SIM_CRB)
- /* Test Module Master Shift A */
-#define TSTSC SIM_VOLATILE_USHORT_POINTER(0x34 + SIM_CRB)
- /* Test Module Shift Count */
-#define TSTRC SIM_VOLATILE_USHORT_POINTER(0x36 + SIM_CRB)
- /* Test Module Repetition Counter */
-#define CREG SIM_VOLATILE_USHORT_POINTER(0x38 + SIM_CRB)
- /* Test Module Control */
-#define DREG SIM_VOLATILE_USHORT_POINTER(0x3a + SIM_CRB)
- /* Test Module Distributed */
-/* Used only for factor testing */
-
-
-
-#define PORTC SIM_VOLATILE_UCHAR_POINTER(0x41 + SIM_CRB)
- /* Port C Data */
-
-
-
-#define CSPAR0 SIM_VOLATILE_USHORT_POINTER(0x44 + SIM_CRB)
- /* Chip Select Pin Assignment
- Resgister 0 */
-/* CSPAR0 contains seven two-bit fields that determine the functions
- of corresponding chip-select pins. CSPAR0[15:14] are not
- used. These bits always read zero; write have no effect. CSPAR0 bit
- 1 always reads one; writes to CSPAR0 bit 1 have no effect. */
-#define CSPAR1 SIM_VOLATILE_USHORT_POINTER(0x46 + SIM_CRB)
- /* Chip Select Pin Assignment
- Register 1 */
-/* CSPAR1 contains five two-bit fields that determine the finctions of
- corresponding chip-select pins. CSPAR1[15:10] are not used. These
- bits always read zero; writes have no effect. */
-/*
- *
- * Bit Field | Description
- * ------------+---------------
- * 00 | Discrete Output
- * 01 | Alternate Function
- * 10 | Chip Select (8-bit port)
- * 11 | Chip Select (16-bit port)
- */
-#define DisOut 0x0
-#define AltFun 0x1
-#define CS8bit 0x2
-#define CS16bit 0x3
-/*
- *
- * CSPARx Field |Chip Select Signal | Alternate Signal | Discrete Output
- *-----------------+--------------------+--------------------+---------------*/
-#define CS_5 12 /* !CS5 | FC2 | PC2 */
-#define CS_4 10 /* !CS4 | FC1 | PC1 */
-#define CS_3 8 /* !CS3 | FC0 | PC0 */
-#define CS_2 6 /* !CS2 | !BGACK | */
-#define CS_1 4 /* !CS1 | !BG | */
-#define CS_0 2 /* !CS0 | !BR | */
-#define CSBOOT 0 /* !CSBOOT | | */
-/* | | | */
-#define CS_10 8 /* !CS10 | ADDR23 | ECLK */
-#define CS_9 6 /* !CS9 | ADDR22 | PC6 */
-#define CS_8 4 /* !CS8 | ADDR21 | PC5 */
-#define CS_7 2 /* !CS7 | ADDR20 | PC4 */
-#define CS_6 0 /* !CS6 | ADDR19 | PC3 */
-
-#define BS_2K 0x0
-#define BS_8K 0x1
-#define BS_16K 0x2
-#define BS_64K 0x3
-#define BS_128K 0x4
-#define BS_256K 0x5
-#define BS_512K 0x6
-#define BS_1M 0x7
-
-#define CSBARBT SIM_VOLATILE_USHORT_POINTER(0x48 + SIM_CRB)
-#define CSBAR0 SIM_VOLATILE_USHORT_POINTER(0x4c + SIM_CRB)
-#define CSBAR1 SIM_VOLATILE_USHORT_POINTER(0x50 + SIM_CRB)
-#define CSBAR2 SIM_VOLATILE_USHORT_POINTER(0x54 + SIM_CRB)
-#define CSBAR3 SIM_VOLATILE_USHORT_POINTER(0x58 + SIM_CRB)
-#define CSBAR4 SIM_VOLATILE_USHORT_POINTER(0x5c + SIM_CRB)
-#define CSBAR5 SIM_VOLATILE_USHORT_POINTER(0x60 + SIM_CRB)
-#define CSBAR6 SIM_VOLATILE_USHORT_POINTER(0x64 + SIM_CRB)
-#define CSBAR7 SIM_VOLATILE_USHORT_POINTER(0x68 + SIM_CRB)
-#define CSBAR8 SIM_VOLATILE_USHORT_POINTER(0x6c + SIM_CRB)
-#define CSBAR9 SIM_VOLATILE_USHORT_POINTER(0x70 + SIM_CRB)
-#define CSBAR10 SIM_VOLATILE_USHORT_POINTER(0x74 + SIM_CRB)
-
-#define MODE 0x8000
-#define Disable 0
-#define LowerByte 0x2000
-#define UpperByte 0x4000
-#define BothBytes 0x6000
-#define ReadOnly 0x0800
-#define WriteOnly 0x1000
-#define ReadWrite 0x1800
-#define SyncAS 0x0
-#define SyncDS 0x0400
-
-#define WaitStates_0 (0x0 << 6)
-#define WaitStates_1 (0x1 << 6)
-#define WaitStates_2 (0x2 << 6)
-#define WaitStates_3 (0x3 << 6)
-#define WaitStates_4 (0x4 << 6)
-#define WaitStates_5 (0x5 << 6)
-#define WaitStates_6 (0x6 << 6)
-#define WaitStates_7 (0x7 << 6)
-#define WaitStates_8 (0x8 << 6)
-#define WaitStates_9 (0x9 << 6)
-#define WaitStates_10 (0xa << 6)
-#define WaitStates_11 (0xb << 6)
-#define WaitStates_12 (0xc << 6)
-#define WaitStates_13 (0xd << 6)
-#define FastTerm (0xe << 6)
-#define External (0xf << 6)
-
-#define CPUSpace (0x0 << 4)
-#define UserSpace (0x1 << 4)
-#define SupSpace (0x2 << 4)
-#define UserSupSpace (0x3 << 4)
-
-#define IPLevel_any 0x0
-#define IPLevel_1 0x2
-#define IPLevel_2 0x4
-#define IPLevel_3 0x6
-#define IPLevel_4 0x8
-#define IPLevel_5 0xa
-#define IPLevel_6 0xc
-#define IPLevel_7 0xe
-
-#define AVEC 1
-
-#define CSORBT SIM_VOLATILE_USHORT_POINTER(0x4a + SIM_CRB)
-#define CSOR0 SIM_VOLATILE_USHORT_POINTER(0x4e + SIM_CRB)
-#define CSOR1 SIM_VOLATILE_USHORT_POINTER(0x52 + SIM_CRB)
-#define CSOR2 SIM_VOLATILE_USHORT_POINTER(0x56 + SIM_CRB)
-#define CSOR3 SIM_VOLATILE_USHORT_POINTER(0x5a + SIM_CRB)
-#define CSOR4 SIM_VOLATILE_USHORT_POINTER(0x5e + SIM_CRB)
-#define CSOR5 SIM_VOLATILE_USHORT_POINTER(0x62 + SIM_CRB)
-#define CSOR6 SIM_VOLATILE_USHORT_POINTER(0x66 + SIM_CRB)
-#define CSOR7 SIM_VOLATILE_USHORT_POINTER(0x6a + SIM_CRB)
-#define CSOR8 SIM_VOLATILE_USHORT_POINTER(0x6e + SIM_CRB)
-#define CSOR9 SIM_VOLATILE_USHORT_POINTER(0x72 + SIM_CRB)
-#define CSOR10 SIM_VOLATILE_USHORT_POINTER(0x76 + SIM_CRB)
-
-#endif /* _SIM_h_ */
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