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authorJoel Sherrill <joel.sherrill@OARcorp.com>2000-07-11 19:31:04 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2000-07-11 19:31:04 +0000
commitbc85fd5a6df8753543ba55c98a588e255471752b (patch)
treeb51e3eb5c77cca042081bb7ba88e5515560451d2 /c/src/exec/score/cpu/i960
parentPatch rtems-rc-20000711-2-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de> (diff)
downloadrtems-bc85fd5a6df8753543ba55c98a588e255471752b.tar.bz2
Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information are now in libcpu. This required significant rework of the score/cpu header files and the creation of multiple header files and subdirectories in libcpu/i960.
Diffstat (limited to 'c/src/exec/score/cpu/i960')
-rw-r--r--c/src/exec/score/cpu/i960/Makefile.am2
-rw-r--r--c/src/exec/score/cpu/i960/cpu.c108
-rw-r--r--c/src/exec/score/cpu/i960/cpu_asm.S39
-rw-r--r--c/src/exec/score/cpu/i960/i960RP.h318
-rw-r--r--c/src/exec/score/cpu/i960/rtems/score/cpu.h7
-rw-r--r--c/src/exec/score/cpu/i960/rtems/score/i960.h408
6 files changed, 31 insertions, 851 deletions
diff --git a/c/src/exec/score/cpu/i960/Makefile.am b/c/src/exec/score/cpu/i960/Makefile.am
index f26a4e9382..cd40092077 100644
--- a/c/src/exec/score/cpu/i960/Makefile.am
+++ b/c/src/exec/score/cpu/i960/Makefile.am
@@ -10,7 +10,7 @@ SUBDIRS = rtems
C_FILES = cpu.c
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
-H_FILES = asm.h i960RP.h
+H_FILES = asm.h
S_FILES = cpu_asm.S
S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o)
diff --git a/c/src/exec/score/cpu/i960/cpu.c b/c/src/exec/score/cpu/i960/cpu.c
index 009e0d3ca4..78eeb3c5f2 100644
--- a/c/src/exec/score/cpu/i960/cpu.c
+++ b/c/src/exec/score/cpu/i960/cpu.c
@@ -11,18 +11,6 @@
*
* $Id$
*/
-/*
- * 1999/04/26: added support for Intel i960RP
- */
-
-#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
-#elif defined(__i960RP__)
-#elif defined(__i960KA__)
-
-#else
-#warning "*** ENTIRE FILE IMPLEMENTED & TESTED FOR CA & RP ONLY ***"
-#warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
-#endif
#include <rtems/system.h>
#include <rtems/score/isr.h>
@@ -64,45 +52,6 @@ unsigned32 _CPU_ISR_Get_level( void )
/*PAGE
*
- * _CPU_ISR_install_raw_handler
- */
-
-#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
-#define i960_vector_caching_enabled( _prcb ) \
- ((_prcb)->control_tbl->icon & 0x2000)
-#elif defined(__i960RP__)
-#define i960_vector_caching_enabled( _prcb ) \
- ((*((unsigned int *) ICON_ADDR)) & 0x2000)
-#elif defined(__i960KA__)
-#define i960_vector_caching_enabled( _prcb ) 0
-#endif
-
-void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-)
-{
- i960_PRCB *prcb = _CPU_Table.Prcb;
- proc_ptr *cached_intr_tbl = NULL;
-
- /* The i80960CA does not support vectors 0-7. The first 9 entries
- * in the Interrupt Table are used to manage pending interrupts.
- * Thus vector 8, the first valid vector number, is actually in
- * slot 9 in the table.
- */
-
- *old_handler = prcb->intr_tbl[ vector + 1 ];
-
- prcb->intr_tbl[ vector + 1 ] = new_handler;
-
- if ( i960_vector_caching_enabled( prcb ) )
- if ( (vector & 0xf) == 0x2 ) /* cacheable? */
- cached_intr_tbl[ vector >> 4 ] = new_handler;
-}
-
-/*PAGE
- *
* _CPU__ISR_install_vector
*
* Install the RTEMS vector wrapper in the CPU's interrupt table.
@@ -130,60 +79,3 @@ void _CPU_ISR_install_vector(
_ISR_Vector_table[ vector ] = new_handler;
}
-
-/*PAGE
- *
- * _CPU_Install_interrupt_stack
- */
-
-#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
-#define soft_reset( prcb ) \
- { register i960_PRCB *_prcb = (prcb); \
- register unsigned32 *_next=0; \
- register unsigned32 _cmd = 0x30000; \
- asm volatile( "lda next,%1; \
- sysctl %0,%1,%2; \
- next: mov g0,g0" \
- : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
- : "0" (_cmd), "1" (_next), "2" (_prcb) ); \
- }
-#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
-#define soft_reset( prcb ) \
- { register i960_PRCB *_prcb = (prcb); \
- register unsigned32 *_next=0; \
- register unsigned32 _cmd = 0x300; \
- asm volatile( "lda next,%1; \
- sysctl %0,%1,%2; \
- next: mov g0,g0" \
- : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
- : "0" (_cmd), "1" (_next), "2" (_prcb) ); \
- }
-#elif defined(__i960KA__)
-#define soft_reset( prcb )
-#endif
-
-void _CPU_Install_interrupt_stack( void )
-{
- i960_PRCB *prcb = _CPU_Table.Prcb;
- unsigned32 level;
-#if defined(__i960RP__) || defined(__i960_RP__)
- unsigned32 *isp = (int *) ISP_ADDR;
-#endif
-
- /*
- * Set the Interrupt Stack in the PRCB and force a reload of it.
- * Interrupts are disabled for safety.
- */
-
- _CPU_ISR_Disable( level );
-
- prcb->intr_stack = _CPU_Interrupt_stack_low;
-
-#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
- soft_reset( prcb );
-#elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
- *isp = (unsigned32) prcb->intr_stack;
-#endif
-
- _CPU_ISR_Enable( level );
-}
diff --git a/c/src/exec/score/cpu/i960/cpu_asm.S b/c/src/exec/score/cpu/i960/cpu_asm.S
index 88b07a5b45..f78c1ac15d 100644
--- a/c/src/exec/score/cpu/i960/cpu_asm.S
+++ b/c/src/exec/score/cpu/i960/cpu_asm.S
@@ -1,7 +1,5 @@
-/* cpu_asm.s
- *
- * This file contains all assembly code for the i960CA implementation
- * of RTEMS.
+/*
+ * This file contains all assembly code for the i960 port of RTEMS.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
@@ -13,12 +11,6 @@
* $Id$
*/
.data
- .align 4
-_soft_reset_reg_save:
- .word 0
- .word 0
- .word 0
- .word 0
_ISR_reg_save:
.word 0
.word 0
@@ -217,30 +209,3 @@ __ISR_Dispatch:
movq r12,g4
ret
-
-#if !defined(__i960KA__)
-/*PAGE
- *
- * void __i960_soft_reset_asm
- *
- * Flush the register cache and save the important (fp, pfp, sp) registers,
- * which are clobbered by the reinit operation. (Not documented, but it happens).
- */
-
- .globl __i960_soft_reset_asm
-__i960_soft_reset_asm:
- flushreg # flush register cache
- mov fp, r4
- mov pfp, r5
- mov sp, r6
- stt r4, _soft_reset_reg_save # save fp, pfp, sp
- lda __i960_reset_done, r4
- ldconst 0x300, r5
- sysctl r5, r4, g0 # reinit: clobbers almost all registers
-__i960_reset_done:
- ldt _soft_reset_reg_save, r4 # restore fp, pfp, sp
- mov r4, fp
- mov r5, pfp
- mov r6, sp
- ret
-#endif
diff --git a/c/src/exec/score/cpu/i960/i960RP.h b/c/src/exec/score/cpu/i960/i960RP.h
deleted file mode 100644
index 25ed29037a..0000000000
--- a/c/src/exec/score/cpu/i960/i960RP.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * i960RP Related Definitions.
- *
- * NOTE: There is some commonality with the JX series which is
- * not currently supported by RTEMS.
- *
- * $Id$
- */
-
-#ifndef __I960RP_h
-#define __I960RP_h
-
-/*----------------------------------------------------------*/
-/* Example 6. Include File (evrp.h) */
-/*----------------------------------------------------------*/
-/* Define JX Core memory mapped register addresses */
-/* Common to Jx and RP: */
-#define DLMCON_ADDR 0xff008100
-#define LMAR0_ADDR 0xff008108
-#define LMMR0_ADDR 0xff00810c
-#define LMAR1_ADDR 0xff008110
-#define LMMR1_ADDR 0xff008114
-#define IPB0_ADDR 0xff008400
-#define IPB1_ADDR 0xff008404
-#define DAB0_ADDR 0xff008420
-#define DAB1_ADDR 0xff008424
-#define BPCON_ADDR 0xff008440
-#define IPND_ADDR 0xff008500
-#define IMSK_ADDR 0xff008504
-#define ICON_ADDR 0xff008510
-#define IMAP0_ADDR 0xff008520
-#define IMAP1_ADDR 0xff008524
-#define IMAP2_ADDR 0xff008528
-#define PMCON0_ADDR 0xff008600
-#define PMCON2_ADDR 0xff008608
-#define PMCON4_ADDR 0xff008610
-#define PMCON6_ADDR 0xff008618
-#define PMCON8_ADDR 0xff008620
-#define PMCON10_ADDR 0xff008628
-#define PMCON12_ADDR 0xff008630
-#define PMCON14_ADDR 0xff008638
-#define BCON_ADDR 0xff0086fc
-#define PRCB_ADDR 0xff008700
-#define ISP_ADDR 0xff008704
-#define SSP_ADDR 0xff008708
-#define DEVID_ADDR 0xff008710
-#define TRR0_ADDR 0xff000300
-#define TCR0_ADDR 0xff000304
-#define TMR0_ADDR 0xff000308
-#define TRR1_ADDR 0xff000310
-#define TCR1_ADDR 0xff000314
-#define TMR1_ADDR 0xff000318
-
-/* RP-only addresses: */
-/* RP MMRs */
-
-/* PCI-to-PCI Bridge Unit 0000 1000H through 0000 10FFH */
-#define VIDR_ADDR 0x00001000
-#define DIDR_ADDR 0x00001002
-#define PCMDR_ADDR 0x00001004
-#define PSR_ADDR 0x00001006
-#define RIDR_ADDR 0x00001008
-#define CCR_ADDR 0x00001009
-#define CLSR_ADDR 0x0000100C
-#define PLTR_ADDR 0x0000100D
-#define HTR_ADDR 0x0000100E
-/* Reserved 0x0000100F through 0x00001017 */
-#define PBNR_ADDR 0x00001018
-#define SBNR_ADDR 0x00001019
-#define SUBBNR_ADDR 0x0000101A
-#define SLTR_ADDR 0x0000101B
-#define IOBR_ADDR 0x0000101C
-#define IOLR_ADDR 0x0000101D
-#define SSR_ADDR 0x0000101E
-#define MBR_ADDR 0x00001020
-#define MLR_ADDR 0x00001022
-#define PMBR_ADDR 0x00001024
-#define PMLR_ADDR 0x00001026
-/* Reserved 0x00001028 through 0x00001033 */
-#define BSVIR_ADDR 0x00001034
-#define BSIR_ADDR 0x00001036
-/* Reserved 0x00001038 through 0x0000103D */
-#define BCR_ADDR 0x0000103E
-#define EBCR_ADDR 0x00001040
-#define SISR_ADDR 0x00001042
-#define PBISR_ADDR 0x00001044
-#define SBISR_ADDR 0x00001048
-#define SACR_ADDR 0x0000104C
-#define PIRSR_ADDR 0x00001050
-#define SIOBR_ADDR 0x00001054
-#define SIOLR_ADDR 0x00001055
-#define SMBR_ADDR 0x00001058
-#define SMLR_ADDR 0x0000105A
-#define SDER_ADDR 0x0000105C
-/* Reserved 0x0000105E through 0x000011FFH */
-
-/* Address Translation Unit 0000 1200H through 0000 12FFH */
-#define ATUVID_ADDR 0x00001200
-#define ATUDID_ADDR 0x00001202
-#define PATUCMD_ADDR 0x00001204
-#define PATUSR_ADDR 0x00001206
-#define ATURID_ADDR 0x00001208
-#define ATUCCR_ADDR 0x00001209
-#define ATUCLSR_ADDR 0x0000120C
-#define ATULT_ADDR 0x0000120D
-#define ATUHTR_ADDR 0x0000120E
-#define ATUBISTR_ADDR 0x0000120F
-#define PIABAR_ADDR 0x00001210
-/* Reserved 0x00001214 */
-/* Reserved 0x00001218 */
-/* Reserved 0x0000121C */
-/* Reserved 0x00001220 */
-/* Reserved 0x00001224 */
-/* Reserved 0x00001228 */
-#define ASVIR_ADDR 0x0000122C
-#define ASIR_ADDR 0x0000122E
-#define ERBAR_ADDR 0x00001230
-/* Reserved 0x00001234 */
-/* Reserved 0x00001238 */
-#define ATUILR_ADDR 0x0000123C
-#define ATUIPR_ADDR 0x0000123D
-#define ATUMGNT_ADDR 0x0000123E
-#define ATUMLAT_ADDR 0x0000123F
-#define PIALR_ADDR 0x00001240
-#define PIATVR_ADDR 0x00001244
-#define SIABAR_ADDR 0x00001248
-#define SIALR_ADDR 0x0000124C
-#define SIATVR_ADDR 0x00001250
-#define POMWVR_ADDR 0x00001254
-/* Reserved 0x00001258 */
-#define POIOWVR_ADDR 0x0000125C
-#define PODWVR_ADDR 0x00001260
-#define POUDR_ADDR 0x00001264
-#define SOMWVR_ADDR 0x00001268
-#define SOIOWVR_ADDR 0x0000126C
-/* Reserved 0x00001270 */
-#define ERLR_ADDR 0x00001274
-#define ERTVR_ADDR 0x00001278
-/* Reserved 0x0000127C */
-/* Reserved 0x00001280 */
-/* Reserved 0x00001284 */
-#define ATUCR_ADDR 0x00001288
-/* Reserved 0x0000128C */
-#define PATUISR_ADDR 0x00001290
-#define SATUISR_ADDR 0x00001294
-#define SATUCMD_ADDR 0x00001298
-#define SATUSR_ADDR 0x0000129A
-#define SODWVR_ADDR 0x0000129C
-#define SOUDR_ADDR 0x000012A0
-#define POCCAR_ADDR 0x000012A4
-#define SOCCAR_ADDR 0x000012A8
-#define POCCDR_ADDR 0x000012AC
-#define SOCCDR_ADDR 0x000012B0
-/* Reserved 0x000012B4 through 0x000012FF */
-
-/* Messaging Unit 0000 1300H through 0000 13FFH */
-#define ARSR_ADDR 0x00001300
-/* Reserved 0x00001304 */
-#define AWR_ADDR 0x00001308
-/* Reserved 0x0000130C */
-#define IMR0_ADDR 0x00001310
-#define IMR1_ADDR 0x00001314
-#define OMR0_ADDR 0x00001318
-#define OMR1_ADDR 0x0000131C
-#define IDR_ADDR 0x00001320
-#define IISR_ADDR 0x00001324
-#define IIMR_ADDR 0x00001328
-#define ODR_ADDR 0x0000132C
-#define OISR_ADDR 0x00001330
-#define OIMR_ADDR 0x00001334
-/* Reserved 0x00001338 through 0x0000134F */
-#define MUCR_ADDR 0x00001350
-#define QBAR_ADDR 0x00001354
-/* Reserved 0x00001358 */
-/* Reserved 0x0000135C */
-#define IFHPR_ADDR 0x00001360
-#define IFTPR_ADDR 0x00001364
-#define IPHPR_ADDR 0x00001368
-#define IPTPR_ADDR 0x0000136C
-#define OFHPR_ADDR 0x00001370
-#define OFTPR_ADDR 0x00001374
-#define OPHPR_ADDR 0x00001378
-#define OPTPR_ADDR 0x0000137C
-#define IAR_ADDR 0x00001380
-/* Reserved 0x00001384 through 0x000013FF */
-
-/* DMA Controller 0000 1400H through 0000 14FFH */
-#define CCR0_ADDR 0x00001400
-#define CSR0_ADDR 0x00001404
-/* Reserved 0x00001408 */
-#define DAR0_ADDR 0x0000140C
-#define NDAR0_ADDR 0x00001410
-#define PADR0_ADDR 0x00001414
-#define PUADR0_ADDR 0x00001418
-#define LADR0_ADDR 0x0000141C
-#define BCR0_ADDR 0x00001420
-#define DCR0_ADDR 0x00001424
-/* Reserved 0x00001428 through 0x0000143F */
-#define CCR1_ADDR 0x00001440
-#define CSR1_ADDR 0x00001444
-/* Reserved 0x00001448 */
-#define DAR1_ADDR 0x0000144C
-#define NDAR1_ADDR 0x00001450
-#define PADR1_ADDR 0x00001454
-#define PUADR1_ADDR 0x00001458
-#define LADR1_ADDR 0x0000145C
-#define BCR1_ADDR 0x00001460
-#define DCR1_ADDR 0x00001464
-/* Reserved 0x00001468 through 0x0000147F */
-#define CCR2_ADDR 0x00001480
-#define CSR2_ADDR 0x00001484
-/* Reserved 0x00001488 */
-#define DAR2_ADDR 0x0000148C
-#define NDAR2_ADDR 0x00001490
-#define PADR2_ADDR 0x00001494
-#define PUADR2_ADDR 0x00001498
-#define LADR2_ADDR 0x0000149C
-#define BCR2_ADDR 0x000014A0
-#define DCR2_ADDR 0x000014A4
-/* Reserved 0x000014A8 through 0x000014FF */
-
-/* Memory Controller 0000 1500H through 0000 15FFH */
-#define MBCR_ADDR 0x00001500
-#define MBBAR0_ADDR 0x00001504
-#define MBRWS0_ADDR 0x00001508
-#define MBWWS0_ADDR 0x0000150C
-#define MBBAR1_ADDR 0x00001510
-#define MBRWS1_ADDR 0x00001514
-#define MBWWS1_ADDR 0x00001518
-#define DBCR_ADDR 0x0000151C
-#define DBAR_ADDR 0x00001520
-#define DRWS_ADDR 0x00001524
-#define DWWS_ADDR 0x00001528
-#define DRIR_ADDR 0x0000152C
-#define DPER_ADDR 0x00001530
-#define BMER_ADDR 0x00001534
-#define MEAR_ADDR 0x00001538
-#define LPISR_ADDR 0x0000153C
-/* Reserved 0x00001540 through 0x000015FF */
-
-/* Local Bus Arbitration Unit 0000 1600H through 0000 167FH
-*/
-#define LBACR_ADDR 0x00001600
-#define LBALCR_ADDR 0x00001604
-/* Reserved 0x00001608 through 0x0000167F */
-
-/* I2C Bus Interface Unit 0000 1680H through 0000 16FFH */
-#define ICR_ADDR 0x00001680
-#define ISR_ADDR 0x00001684
-#define ISAR_ADDR 0x00001688
-#define IDBR_ADDR 0x0000168C
-#define ICCR_ADDR 0x00001690
-/* Reserved 0x00001694 through 0x000016FF */
-
-/* PCI And Peripheral Interrupt Controller 0000 1700H through
-0000 177FH */
-#define NISR_ADDR 0x00001700
-#define X7ISR_ADDR 0x00001704
-#define X6ISR_ADDR 0x00001708
-#define PDDIR_ADDR 0x00001710
-/* Reserved 0x00001714 through 0x0000177F */
-
-/* APIC Bus Interface Unit 0000 1780H through 0000 17FFH */
-#define APICIDR_ADDR 0x00001780
-#define APICARBID_ADDR 0x00001784
-#define EVR_ADDR 0x00001788
-#define IMR_ADDR 0x0000178C
-#define APICCSR_ADDR 0x00001790
-/* Reserved 0x00001794 through 0x000017FF */
-
-/* Byte order bit for region configuration */
-/* Set to Little Endian for the 80960RP*/
-#define I960RP_BYTE_ORDER I960RP_BIG_ENDIAN(0)
-#define I960RP_BUS_WIDTH(bw) ((bw==16)?(1<<22):(0)) | ((bw==32)?(2<<22):(0))
-#define I960RP_BIG_ENDIAN(on) ((on)?(0x1<<31):0)
-#define I960RP_BYTE_N(n,data) (((unsigned)(data) >> (n*8)) & 0xFF)
-#define I960RP_BUS_WIDTH_8 0
-#define I960RP_BUS_WIDTH_16 (1<<22)
-#define I960RP_BUS_WIDTH_32 (1<<23)
-
-
-/* ATU Register Definitions */
-
-#define ATUCR_SECOUTEN 0x4
-#define ATUCR_PRIOUTEN 0x2
-#define ATUCR_DADRSELEN 0x100
-#define ATUCR_SECDADREN 0x80
-#define AUTCR_SECERRINTEN 0x20
-#define AUTCR_PRIERRINTEN 0x10
-
-#define ATUSCMD_IOEN 0x1
-#define ATUSCMD_MEMEN 0x2
-#define ATUSCMD_BUSMSTEN 0x4
-
-#define ATUPCMD_IOEN 0x1
-#define ATUPCMD_MEMEN 0x2
-#define ATUPCMD_BUSMSTEN 0x4
-
-/* EBCR Register Definitions */
-#define EBCR_CCR_MASK 0x4
-
-#define rp_readreg32( x) ( *((unsigned int *) x))
-#define rp_writereg32( x, v) ( *((unsigned int *) x) = v)
-#define rp_readreg16( x) ( *((unsigned short *) x))
-#define rp_writereg16( x, v) ( *((unsigned short *) x) = v)
-#define rp_readreg8( x) ( *((unsigned char *) x))
-#define rp_writereg8( x, v) ( *((unsigned char *) x) = v)
-
-
-/* i960 Memory Map values */
-
-#define RP_PRI_IO_WIND_BASE 0x90000000
-#define RP_SEC_IO_WIND_BASE 0x90010000
-#define RP_SEC_MEM_WIND_BASE 0x88000000
-#define RP_PRI_MEM_WIND_BASE 0x80000000
-
-#endif
-/* end of include file */
diff --git a/c/src/exec/score/cpu/i960/rtems/score/cpu.h b/c/src/exec/score/cpu/i960/rtems/score/cpu.h
index dd9ced0704..71834e6dd2 100644
--- a/c/src/exec/score/cpu/i960/rtems/score/cpu.h
+++ b/c/src/exec/score/cpu/i960/rtems/score/cpu.h
@@ -165,8 +165,6 @@ typedef struct {
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
-
- i960_PRCB *Prcb;
} rtems_cpu_table;
/*
@@ -176,11 +174,10 @@ typedef struct {
/*
* Macros to access i960 specific additions to the CPU Table
+ *
+ * NONE
*/
-#define rtems_cpu_configuration_get_prcb() \
- (_CPU_Table.Prcb)
-
/* variables */
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
diff --git a/c/src/exec/score/cpu/i960/rtems/score/i960.h b/c/src/exec/score/cpu/i960/rtems/score/i960.h
index de7b635869..799d493279 100644
--- a/c/src/exec/score/cpu/i960/rtems/score/i960.h
+++ b/c/src/exec/score/cpu/i960/rtems/score/i960.h
@@ -33,314 +33,60 @@ extern "C" {
* NOTE: RTEMS defines a canonical name for each cpu model.
*/
-#if defined(rtems_multilib)
/*
- * Figure out all CPU Model Feature Flags based upon compiler
- * predefines.
+ * Define the name of the CPU family.
*/
-#define CPU_MODEL_NAME "rtems_multilib"
-#define I960_HAS_FPU 0
-#define I960_CPU_ALIGNMENT 4
-#define I960_SOFT_RESET_COMMAND 0x30000
-
-#elif defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
-
-#define CPU_MODEL_NAME "i960ca"
-#define __RTEMS_I960CA__
-
-#elif defined(__i960KA__)
-#define CPU_MODEL_NAME "i960ka"
-
-#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
-
-#define CPU_MODEL_NAME "i960ha"
-#define __RTEMS_I960HA__
-
-#elif defined(__i960RP__)
-
-#include <i960RP.h>
-#define CPU_MODEL_NAME "i960rp"
-#define __RTEMS_I960RP__
-#define I960_CPU_ALIGNMENT 8
-#define I960_SOFT_RESET_COMMAND 0x300
-
-#else
-
-#error "Unsupported CPU Model"
-
-#endif
+#define CPU_NAME "Intel i960"
/*
- * Now default some CPU model variation parameters
+ * This should work since most i960 models do not have FPUs. The logic is:
+ *
+ * + If the user specifically asks for soft-float, give it to them
+ * regardless of hardware availability.
+ * + If the CPU has hardware FPU, then use it.
+ * + Otherwise, we have to use soft float.
*/
-#ifndef I960_HAS_FPU
+#if defined(_SOFT_FLOAT)
+#define I960_HAS_FPU 0
+#elif defined(_i960_KB__) || defined(_i960_SB__) || defined(_i960_SB__) || \
+ defined(_i960_JF__) || defined(_i960_MC__) || defined(_i960_CC__)
+#define I960_HAS_FPU 1
+#else
#define I960_HAS_FPU 0
-#endif
-
-#ifndef I960_CPU_ALIGNMENT
-#define I960_CPU_ALIGNMENT 4
-#endif
-
-#ifndef I960_SOFT_RESET_COMMAND
-#define I960_SOFT_RESET_COMMAND 0x30000
#endif
/*
- * Define the name of the CPU family.
+ * Some of the CPU models may have better performance with
+ * alignment of 8 or 16 but we don't know what model we are
+ * being compiled for based solely on the information provided
+ * when multilibbing.
*/
-#define CPU_NAME "Intel i960"
-
-#ifndef ASM
+#define I960_CPU_ALIGNMENT 4
/*
- * XXX should have an ifdef here and have stuff for the other
- * XXX family members...
- */
-
-#if defined(__RTEMS_I960CA__)
-/*
- * Now default some CPU model variation parameters
+ * This is not the perfect CPU model name but it is adequate and
+ * reflects what we know from multilib.
*/
-#ifndef I960_HAS_FPU
-#define I960_HAS_FPU 0
-#endif
-
-#ifndef I960_CPU_ALIGNMENT
-#define I960_CPU_ALIGNMENT 4
-#endif
-
-
-/* i960CA control structures */
-
-/* Intel i960CA Control Table */
-
-typedef struct {
- /* Control Group 0 */
- unsigned int ipb0; /* IP breakpoint 0 */
- unsigned int ipb1; /* IP breakpoint 1 */
- unsigned int dab0; /* data address breakpoint 0 */
- unsigned int dab1; /* data address breakpoint 1 */
- /* Control Group 1 */
- unsigned int imap0; /* interrupt map 0 */
- unsigned int imap1; /* interrupt map 1 */
- unsigned int imap2; /* interrupt map 2 */
- unsigned int icon; /* interrupt control */
- /* Control Group 2 */
- unsigned int mcon0; /* memory region 0 configuration */
- unsigned int mcon1; /* memory region 1 configuration */
- unsigned int mcon2; /* memory region 2 configuration */
- unsigned int mcon3; /* memory region 3 configuration */
- /* Control Group 3 */
- unsigned int mcon4; /* memory region 4 configuration */
- unsigned int mcon5; /* memory region 5 configuration */
- unsigned int mcon6; /* memory region 6 configuration */
- unsigned int mcon7; /* memory region 7 configuration */
- /* Control Group 4 */
- unsigned int mcon8; /* memory region 8 configuration */
- unsigned int mcon9; /* memory region 9 configuration */
- unsigned int mcon10; /* memory region 10 configuration */
- unsigned int mcon11; /* memory region 11 configuration */
- /* Control Group 5 */
- unsigned int mcon12; /* memory region 12 configuration */
- unsigned int mcon13; /* memory region 13 configuration */
- unsigned int mcon14; /* memory region 14 configuration */
- unsigned int mcon15; /* memory region 15 configuration */
- /* Control Group 6 */
- unsigned int reserved; /* reserved */
- unsigned int bpcon; /* breakpoint control */
- unsigned int tc; /* trace control */
- unsigned int bcon; /* bus configuration control */
-} i960ca_control_table;
-
-/* Intel i960CA Processor Control Block */
-
-typedef struct {
- unsigned int *fault_tbl; /* fault table base address */
- i960ca_control_table
- *control_tbl; /* control table base address */
- unsigned int initial_ac; /* AC register initial value */
- unsigned int fault_config; /* fault configuration word */
- void **intr_tbl; /* interrupt table base address */
- void *sys_proc_tbl; /* system procedure table
- base address */
- unsigned int reserved; /* reserved */
- unsigned int *intr_stack; /* interrupt stack pointer */
- unsigned int ins_cache_cfg; /* instruction cache
- configuration word */
- unsigned int reg_cache_cfg; /* register cache configuration word */
-} i960ca_PRCB;
-
-typedef i960ca_control_table i960_control_table;
-typedef i960ca_PRCB i960_PRCB;
-
-#elif defined(__RTEMS_I960HA__)
-
-/* i960HA control structures */
-
-/* Intel i960HA Control Table */
-
-typedef struct {
- /* Control Group 0 */
- unsigned int ipb0; /* IP breakpoint 0 */
- unsigned int ipb1; /* IP breakpoint 1 */
- unsigned int dab0; /* data address breakpoint 0 */
- unsigned int dab1; /* data address breakpoint 1 */
- /* Control Group 1 */
- unsigned int imap0; /* interrupt map 0 */
- unsigned int imap1; /* interrupt map 1 */
- unsigned int imap2; /* interrupt map 2 */
- unsigned int icon; /* interrupt control */
- /* Control Group 2 */
- unsigned int mcon0; /* memory region 0 configuration */
- unsigned int mcon1; /* memory region 1 configuration */
- unsigned int mcon2; /* memory region 2 configuration */
- unsigned int mcon3; /* memory region 3 configuration */
- /* Control Group 3 */
- unsigned int mcon4; /* memory region 4 configuration */
- unsigned int mcon5; /* memory region 5 configuration */
- unsigned int mcon6; /* memory region 6 configuration */
- unsigned int mcon7; /* memory region 7 configuration */
- /* Control Group 4 */
- unsigned int mcon8; /* memory region 8 configuration */
- unsigned int mcon9; /* memory region 9 configuration */
- unsigned int mcon10; /* memory region 10 configuration */
- unsigned int mcon11; /* memory region 11 configuration */
- /* Control Group 5 */
- unsigned int mcon12; /* memory region 12 configuration */
- unsigned int mcon13; /* memory region 13 configuration */
- unsigned int mcon14; /* memory region 14 configuration */
- unsigned int mcon15; /* memory region 15 configuration */
- /* Control Group 6 */
- unsigned int reserved; /* reserved */
- unsigned int bpcon; /* breakpoint control */
- unsigned int tc; /* trace control */
- unsigned int bcon; /* bus configuration control */
-} i960ha_control_table;
-
-/* Intel i960HA Processor Control Block */
-
-typedef struct {
- unsigned int *fault_tbl; /* fault table base address */
- i960ha_control_table
- *control_tbl; /* control table base address */
- unsigned int initial_ac; /* AC register initial value */
- unsigned int fault_config; /* fault configuration word */
- void **intr_tbl; /* interrupt table base address */
- void *sys_proc_tbl; /* system procedure table
- base address */
- unsigned int reserved; /* reserved */
- unsigned int *intr_stack; /* interrupt stack pointer */
- unsigned int ins_cache_cfg; /* instruction cache
- configuration word */
- unsigned int reg_cache_cfg; /* register cache configuration word */
-} i960ha_PRCB;
-
-typedef i960ha_control_table i960_control_table;
-typedef i960ha_PRCB i960_PRCB;
-
-#elif defined(__RTEMS_I960RP__)
-
-/* i960RP control structures */
-
-/* Intel i960RP Control Table */
-
-typedef struct {
- /* Control Group 0 */
- unsigned int rsvd00;
- unsigned int rsvd01;
- unsigned int rsvd02;
- unsigned int rsvd03;
- /* Control Group 1 */
- unsigned int imap0; /* interrupt map 0 */
- unsigned int imap1; /* interrupt map 1 */
- unsigned int imap2; /* interrupt map 2 */
- unsigned int icon; /* interrupt control */
- /* Control Group 2 */
- unsigned int pmcon0; /* memory region 0 configuration */
- unsigned int rsvd1;
- unsigned int pmcon2; /* memory region 2 configuration */
- unsigned int rsvd2;
- /* Control Group 3 */
- unsigned int pmcon4; /* memory region 4 configuration */
- unsigned int rsvd3;
- unsigned int pmcon6; /* memory region 6 configuration */
- unsigned int rsvd4;
- /* Control Group 4 */
- unsigned int pmcon8; /* memory region 8 configuration */
- unsigned int rsvd5;
- unsigned int pmcon10; /* memory region 10 configuration */
- unsigned int rsvd6;
- /* Control Group 5 */
- unsigned int pmcon12; /* memory region 12 configuration */
- unsigned int rsvd7;
- unsigned int pmcon14; /* memory region 14 configuration */
- unsigned int rsvd8;
- /* Control Group 6 */
- unsigned int rsvd9;
- unsigned int rsvd10;
- unsigned int tc; /* trace control */
- unsigned int bcon; /* bus configuration control */
-} i960rp_control_table;
-
-/* Intel i960RP Processor Control Block */
-
-typedef struct {
- unsigned int *fault_tbl; /* fault table base address */
- i960rp_control_table
- *control_tbl; /* control table base address */
- unsigned int initial_ac; /* AC register initial value */
- unsigned int fault_config; /* fault configuration word */
- void **intr_tbl; /* interrupt table base address */
- void *sys_proc_tbl; /* system procedure table
- base address */
- unsigned int reserved; /* reserved */
- unsigned int *intr_stack; /* interrupt stack pointer */
- unsigned int ins_cache_cfg; /* instruction cache
- configuration word */
- unsigned int reg_cache_cfg; /* register cache configuration word */
-} i960rp_PRCB;
-
-typedef i960rp_control_table i960_control_table;
-typedef i960rp_PRCB i960_PRCB;
-
-#elif defined(__i960KA__)
-
-/* i960KA control structures */
-
-/* Intel i960KA Control Table */
-
-typedef struct {
-int pad0;
-} i960ka_control_table;
-
-/* Intel i960KA Processor Control Block */
-
-typedef struct {
- void **intr_tbl; /* interrupt table base address */
- unsigned int *intr_stack; /* interrupt stack pointer */
-} i960ka_PRCB;
-
-typedef i960ka_control_table i960_control_table;
-typedef i960ka_PRCB i960_PRCB;
-
+#if I960_HAS_FPU
+#define CPU_MODEL_NAME "i960 w/FPU"
#else
-#error "invalid processor selection!"
+#define CPU_MODEL_NAME "i960 w/soft-float"
#endif
+#ifndef ASM
+
/*
* Miscellaneous Support Routines
*/
-#if !defined(__i960KA__)
#define i960_reload_ctl_group( group ) \
{ register int _cmd = ((group)|0x400) ; \
asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
}
-#endif
#define i960_atomic_modify( mask, addr, prev ) \
{ register unsigned int _mask = (mask); \
@@ -393,97 +139,15 @@ typedef i960ka_PRCB i960_PRCB;
(_level) = ((_level) & 0x1f0000) >> 16; \
} while ( 0 )
-#if !defined(__i960KA__)
#define i960_cause_intr( intr ) \
{ register int _intr = (intr); \
asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
}
-#endif
/*
* Interrupt Masking Routines
*/
-#if defined(__RTEMS_I960CA__) || defined(__RTEMS_I960HA__)
-
-#define i960_unmask_intr( xint ) \
- { register unsigned int _mask= (1<<(xint)); \
- asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
- }
-
-#define i960_mask_intr( xint ) \
- { register unsigned int _mask= (1<<(xint)); \
- asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
- }
-
-#define i960_clear_intr( xint ) \
- { register unsigned int _xint=(xint); \
-asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \
- bbs %0,sf0, loop_til_cleared" \
- : "=d" (_xint) : "0" (_xint) ); \
- }
-
-static inline unsigned int i960_pend_intrs()
-{ register unsigned int _intr=0;
- asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
- return ( _intr );
-}
-
-static inline unsigned int i960_mask_intrs()
-{ register unsigned int _intr=0;
- asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
- return( _intr );
-}
-
-#elif defined(__RTEMS_I960RP__)
-
-#define i960_unmask_intr( xint ) \
- { register unsigned int _mask= (1<<(xint)); \
- register unsigned int *_imsk = (int * ) IMSK_ADDR; \
- register unsigned int _val= *_imsk; \
- asm volatile( "or %0,%2,%0; \
- st %0,(%1)" \
- : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
- : "0" (_val), "1" (_imsk), "2" (_mask) ); \
- }
-
-#define i960_mask_intr( xint ) \
- { register unsigned int _mask= (1<<(xint)); \
- register unsigned int *_imsk = (int * ) IMSK_ADDR; \
- register unsigned int _val = *_imsk; \
- asm volatile( "andnot %2,%0,%0; \
- st %0,(%1)" \
- : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
- : "0" (_val), "1" (_imsk), "2" (_mask) ); \
- }
-#define i960_clear_intr( xint ) \
- { register unsigned int _xint=xint; \
- register unsigned int _mask=(1<<(xint)); \
- register unsigned int *_ipnd = (int * ) IPND_ADDR; \
- register unsigned int _rslt = 0; \
-asm volatile( "loop_til_cleared: mov 0, %0; \
- atmod %1, %2, %0; \
- bbs %3,%0, loop_til_cleared" \
- : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \
- : "0" (_rslt), "1" (_ipnd), "2" (_mask), "3" (_xint) ); \
- }
-
-static inline unsigned int i960_pend_intrs()
-{ register unsigned int _intr= *(unsigned int *) IPND_ADDR;
- /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \
- asm volatile( "mov (%0),%1" \
- : "=d" (_ipnd), "=d" (_mask) \
- : "0" (_ipnd), "1" (_mask) ); \ */
- return ( _intr );
-}
-
-static inline unsigned int i960_mask_intrs()
-{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR;
- /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/
- return( _intr );
-}
-#endif
-
static inline unsigned int i960_get_fp()
{ register unsigned int _fp=0;
asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
@@ -491,26 +155,6 @@ static inline unsigned int i960_get_fp()
}
/*
- * Soft Reset
- */
-
-#if defined(I960_SOFT_RESET_COMMAND)
-#define i960_soft_reset( prcb ) \
- { register i960_PRCB *_prcb = (prcb); \
- register unsigned int *_next=0; \
- register unsigned int _cmd = I960_SOFT_RESET_COMMAND; \
- asm volatile( "lda next,%1; \
- sysctl %0,%1,%2; \
- next: mov g0,g0" \
- : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
- : "0" (_cmd), "1" (_next), "2" (_prcb) ); \
- }
-
-#elif !defined(__i960KA__)
-#warning "I960_SOFT_RESET_COMMAND is not defined"
-#endif
-
-/*
* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.
*