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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1998-07-23 22:02:34 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1998-07-23 22:02:34 +0000 |
| commit | 67a2288991ce3662a588ee83c0bea9c9efae5f1e (patch) | |
| tree | a8d68b22bfd313619f2a0d0b2e3b4755b8278b9d /c/src/exec/score/cpu/i386/cpu.h | |
| parent | Patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>: (diff) | |
| download | rtems-67a2288991ce3662a588ee83c0bea9c9efae5f1e.tar.bz2 | |
Patch from Eric VALETTE <valette@crf.canon.fr>:
Here is a enhanced version of my previous patch. This patch enables
to potentially share the new interrupt management code for all Intel targets
(pc386, go32 and force386) bsp.
Note : this patch is complete only for pc386. It still needs to
be completed for go32 and force386. I carrefully checked
that anything needed is in for force386 (only some function
name changes for IDT manipulation and GDT segment
manipulation). But anyway I will not be able to test any
of theses targets...
Diffstat (limited to '')
| -rw-r--r-- | c/src/exec/score/cpu/i386/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/c/src/exec/score/cpu/i386/cpu.h b/c/src/exec/score/cpu/i386/cpu.h index 42ec7db6f5..4bca613eb7 100644 --- a/c/src/exec/score/cpu/i386/cpu.h +++ b/c/src/exec/score/cpu/i386/cpu.h @@ -22,6 +22,8 @@ extern "C" { #endif #include <rtems/score/i386.h> /* pick up machine definitions */ +#include <libcpu/cpu.h> + #ifndef ASM #include <rtems/score/i386types.h> #endif |