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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-04-18 13:18:11 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-04-18 13:18:11 +0000 |
| commit | e80ac7f6c253169db44455b883783b134a469a51 (patch) | |
| tree | a12f781d2aa23d95d0c3b225c731c8e24fe60950 /c/src/exec/score/cpu/arm/rtems/score/cpu.h | |
| parent | 2002-04-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de> (diff) | |
| download | rtems-e80ac7f6c253169db44455b883783b134a469a51.tar.bz2 | |
2002-04-18 Jay Monkman <jtm@smoothsmoothie.com>
* rtems/score/cpu.h (CPU_ISR_Disable and CPU_ISR_Enable): Correct them
where they correctly inform the compiler about the register they
are modifying.
Diffstat (limited to '')
| -rw-r--r-- | c/src/exec/score/cpu/arm/rtems/score/cpu.h | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/c/src/exec/score/cpu/arm/rtems/score/cpu.h b/c/src/exec/score/cpu/arm/rtems/score/cpu.h index ebe494504b..a626068e2c 100644 --- a/c/src/exec/score/cpu/arm/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/arm/rtems/score/cpu.h @@ -540,9 +540,10 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); #define _CPU_ISR_Disable( _level ) \ { \ (_level) = 0; \ - asm volatile ("MRS r0, cpsr \n" ); \ - asm volatile ("ORR r0, r0, #0xc0 \n" ); \ - asm volatile ("MSR cpsr, r0 \n" ); \ + asm volatile ("MRS r0, cpsr \n" \ + "ORR r0, r0, #0xc0 \n" \ + "MSR cpsr, r0 \n" \ + : : : "r0"); \ } /* @@ -553,9 +554,10 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); #define _CPU_ISR_Enable( _level ) \ { \ - asm volatile ("MRS r0, cpsr \n" ); \ - asm volatile ("AND r0, r0, #0xFFFFFF3F \n" ); \ - asm volatile ("MSR cpsr, r0 \n" ); \ + asm volatile ("MRS r0, cpsr \n" \ + "AND r0, r0, #0xFFFFFF3F \n" \ + "MSR cpsr, r0 \n" \ + : : : "r0" ); \ } /* |