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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-22 08:01:48 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-28 15:02:12 +0200 |
| commit | fe2cd01ba71a04b5c11eae8ade7969ac1db8640d (patch) | |
| tree | ad55192e8deaddac1df0211afd3c0ac8da198261 /bsps | |
| parent | riscv: Add dummy SMP support (diff) | |
| download | rtems-fe2cd01ba71a04b5c11eae8ade7969ac1db8640d.tar.bz2 | |
bsp/riscv: Add device tree support
Update #3433.
Diffstat (limited to 'bsps')
| -rw-r--r-- | bsps/riscv/riscv/include/bsp.h | 2 | ||||
| -rw-r--r-- | bsps/riscv/riscv/start/start.S | 18 |
2 files changed, 14 insertions, 6 deletions
diff --git a/bsps/riscv/riscv/include/bsp.h b/bsps/riscv/riscv/include/bsp.h index 79f359ac34..6298966a8c 100644 --- a/bsps/riscv/riscv/include/bsp.h +++ b/bsps/riscv/riscv/include/bsp.h @@ -44,6 +44,8 @@ extern "C" { #endif +#define BSP_FDT_IS_SUPPORTED + /** * @defgroup riscv_generic Register Definitions * diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S index 1d0bde164b..f40ceeff50 100644 --- a/bsps/riscv/riscv/start/start.S +++ b/bsps/riscv/riscv/start/start.S @@ -27,10 +27,11 @@ * SUCH DAMAGE. */ -#include <bsp/linker-symbols.h> -#include <rtems/score/riscv-utility.h> -#include <rtems/score/cpu.h> #include <rtems/asm.h> +#include <rtems/score/cpu.h> +#include <rtems/score/riscv-utility.h> +#include <bsp/linker-symbols.h> +#include <bspopts.h> EXTERN(bsp_section_bss_begin) EXTERN(bsp_section_bss_end) @@ -57,12 +58,17 @@ SYM(_start): bnez s0, .Lloop_forever #endif - la t0, ISR_Handler - csrw mtvec, t0 - /* load stack and frame pointers */ la sp, _Configuration_Interrupt_stack_area_end +#ifdef BSP_START_COPY_FDT_FROM_U_BOOT + mv a0, a1 + call bsp_fdt_copy +#endif + + la t0, ISR_Handler + csrw mtvec, t0 + /* Clear .bss */ la a0, bsp_section_bss_begin li a1, 0 |