Do not use RTEMS_INLINE_ROUTINE

Directly use "static inline" which is available in C99 and later.  This brings
the RTEMS implementation closer to standard C.

Close #3935.

12 files changed, 56 insertions, 56 deletions

diff --git a/bsps/i386/pc386/include/edid.h b/bsps/i386/pc386/include/edid.h
index c76cec8330..9945ee5ae7 100644
--- a/bsps/i386/pc386/include/edid.h
+++ b/bsps/i386/pc386/include/edid.h
@@ -34,7 +34,7 @@ extern "C" {
 #endif /* __cplusplus */
 
 #include <rtems/score/basedefs.h>
-#define EDID_INLINE_ROUTINE     RTEMS_INLINE_ROUTINE
+#define EDID_INLINE_ROUTINE     static inline
 
 /*  VESA Enhanced Extended Display Identification Data (E-EDID) Proposed
     Release A, March 27, 2007 */
diff --git a/bsps/include/grlib/grlib_impl.h b/bsps/include/grlib/grlib_impl.h
index 919f6d69ab..4781d0aa1f 100644
--- a/bsps/include/grlib/grlib_impl.h
+++ b/bsps/include/grlib/grlib_impl.h
@@ -66,24 +66,24 @@ extern "C" {
 
 #if (((__RTEMS_MAJOR__ << 16) | (__RTEMS_MINOR__ << 8) | __RTEMS_REVISION__) >= 0x050000)
 
-RTEMS_INLINE_ROUTINE void *grlib_malloc(size_t size)
+static inline void *grlib_malloc(size_t size)
 {
  return rtems_malloc(size);
 }
 
-RTEMS_INLINE_ROUTINE void *grlib_calloc(size_t nelem, size_t elsize)
+static inline void *grlib_calloc(size_t nelem, size_t elsize)
 {
  return rtems_calloc(nelem, elsize);
 }
 
 #else
 
-RTEMS_INLINE_ROUTINE void *grlib_malloc(size_t size)
+static inline void *grlib_malloc(size_t size)
 {
  return malloc(size);
 }
 
-RTEMS_INLINE_ROUTINE void *grlib_calloc(size_t nelem, size_t elsize)
+static inline void *grlib_calloc(size_t nelem, size_t elsize)
 {
  return calloc(nelem, elsize);
 }
@@ -92,7 +92,7 @@ RTEMS_INLINE_ROUTINE void *grlib_calloc(size_t nelem, size_t elsize)
 
 #ifdef __sparc__
 
-RTEMS_INLINE_ROUTINE unsigned char grlib_read_uncached8(unsigned int address)
+static inline unsigned char grlib_read_uncached8(unsigned int address)
 {
        unsigned char tmp;
        __asm__ (" lduba [%1]1, %0 "
@@ -102,7 +102,7 @@ RTEMS_INLINE_ROUTINE unsigned char grlib_read_uncached8(unsigned int address)
        return tmp;
 }
 
-RTEMS_INLINE_ROUTINE unsigned short grlib_read_uncached16(unsigned int addr) {
+static inline unsigned short grlib_read_uncached16(unsigned int addr) {
        unsigned short tmp;
        __asm__ (" lduha [%1]1, %0 "
          : "=r"(tmp)
@@ -112,7 +112,7 @@ RTEMS_INLINE_ROUTINE unsigned short grlib_read_uncached16(unsigned int addr) {
 }
 
 
-RTEMS_INLINE_ROUTINE unsigned int grlib_read_uncached32(unsigned int address)
+static inline unsigned int grlib_read_uncached32(unsigned int address)
 {
 	unsigned int tmp;
 	__asm__ (" lda [%1]1, %0 "
@@ -122,7 +122,7 @@ RTEMS_INLINE_ROUTINE unsigned int grlib_read_uncached32(unsigned int address)
 	return tmp;
 }
 
-RTEMS_INLINE_ROUTINE uint64_t grlib_read_uncached64(uint64_t *address)
+static inline uint64_t grlib_read_uncached64(uint64_t *address)
 {
 	uint64_t tmp;
 	__asm__ (" ldda [%1]1, %0 "
@@ -147,7 +147,7 @@ static __inline__ unsigned short grlib_read_uncached16(unsigned int address) {
 	return tmp;
 }
 
-RTEMS_INLINE_ROUTINE unsigned int grlib_read_uncached32(unsigned int address)
+static inline unsigned int grlib_read_uncached32(unsigned int address)
 {
 	unsigned int tmp = (*(volatile unsigned int *)(address));
 	return tmp;
diff --git a/bsps/m68k/shared/cache/cache.h b/bsps/m68k/shared/cache/cache.h
index 18797d4695..0fb63f7d2f 100644
--- a/bsps/m68k/shared/cache/cache.h
+++ b/bsps/m68k/shared/cache/cache.h
@@ -76,10 +76,10 @@
 
 /* Only the mc68030 has a data cache; it is writethrough only. */
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_flush_1_data_line(const void * d_addr) {}
-RTEMS_INLINE_ROUTINE void _CPU_cache_flush_entire_data(void) {}
+static inline void _CPU_cache_flush_1_data_line(const void * d_addr) {}
+static inline void _CPU_cache_flush_entire_data(void) {}
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_data_line(
+static inline void _CPU_cache_invalidate_1_data_line(
   const void * d_addr
 )
 {
@@ -88,27 +88,27 @@ RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_data_line(
   _CPU_CACR_OR(0x00000400);
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_data(void)
+static inline void _CPU_cache_invalidate_entire_data(void)
 {
   _CPU_CACR_OR( 0x00000800 );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_data(void)
+static inline void _CPU_cache_freeze_data(void)
 {
   _CPU_CACR_OR( 0x00000200 );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_data(void)
+static inline void _CPU_cache_unfreeze_data(void)
 {
   _CPU_CACR_AND( 0xFFFFFDFF );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_enable_data(void)
+static inline void _CPU_cache_enable_data(void)
 {
   _CPU_CACR_OR( 0x00000100 );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_disable_data(void)
+static inline void _CPU_cache_disable_data(void)
 {
   _CPU_CACR_AND( 0xFFFFFEFF );
 }
@@ -117,7 +117,7 @@ RTEMS_INLINE_ROUTINE void _CPU_cache_disable_data(void)
 
 /* Both the 68020 and 68030 have instruction caches */
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_instruction_line(
+static inline void _CPU_cache_invalidate_1_instruction_line(
   const void * d_addr
 )
 {
@@ -126,27 +126,27 @@ RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_instruction_line(
   _CPU_CACR_OR( 0x00000004 );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_instruction(void)
+static inline void _CPU_cache_invalidate_entire_instruction(void)
 {
   _CPU_CACR_OR( 0x00000008 );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_instruction(void)
+static inline void _CPU_cache_freeze_instruction(void)
 {
   _CPU_CACR_OR( 0x00000002);
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_instruction(void)
+static inline void _CPU_cache_unfreeze_instruction(void)
 {
   _CPU_CACR_AND( 0xFFFFFFFD );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_enable_instruction(void)
+static inline void _CPU_cache_enable_instruction(void)
 {
   _CPU_CACR_OR( 0x00000001 );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_disable_instruction(void)
+static inline void _CPU_cache_disable_instruction(void)
 {
   _CPU_CACR_AND( 0xFFFFFFFE );
 }
@@ -155,12 +155,12 @@ RTEMS_INLINE_ROUTINE void _CPU_cache_disable_instruction(void)
 #elif ( defined(__mc68040__) || defined (__mc68060__) )
 
 /* Cannot be frozen */
-RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_data(void) {}
-RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_data(void) {}
-RTEMS_INLINE_ROUTINE void _CPU_cache_freeze_instruction(void) {}
-RTEMS_INLINE_ROUTINE void _CPU_cache_unfreeze_instruction(void) {}
+static inline void _CPU_cache_freeze_data(void) {}
+static inline void _CPU_cache_unfreeze_data(void) {}
+static inline void _CPU_cache_freeze_instruction(void) {}
+static inline void _CPU_cache_unfreeze_instruction(void) {}
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_flush_1_data_line(
+static inline void _CPU_cache_flush_1_data_line(
   const void * d_addr
 )
 {
@@ -168,7 +168,7 @@ RTEMS_INLINE_ROUTINE void _CPU_cache_flush_1_data_line(
   __asm__ volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_data_line(
+static inline void _CPU_cache_invalidate_1_data_line(
   const void * d_addr
 )
 {
@@ -176,44 +176,44 @@ RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_data_line(
   __asm__ volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_flush_entire_data(void)
+static inline void _CPU_cache_flush_entire_data(void)
 {
   __asm__ volatile ( "cpusha %%dc" :: );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_data(void)
+static inline void _CPU_cache_invalidate_entire_data(void)
 {
   __asm__ volatile ( "cinva %%dc" :: );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_enable_data(void)
+static inline void _CPU_cache_enable_data(void)
 {
   _CPU_CACR_OR( 0x80000000 );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_disable_data(void)
+static inline void _CPU_cache_disable_data(void)
 {
   _CPU_CACR_AND( 0x7FFFFFFF );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_1_instruction_line(
+static inline void _CPU_cache_invalidate_1_instruction_line(
   const void * i_addr )
 {
   void * p_address = (void *)  _CPU_virtual_to_physical( i_addr );
   __asm__ volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_invalidate_entire_instruction(void)
+static inline void _CPU_cache_invalidate_entire_instruction(void)
 {
   __asm__ volatile ( "cinva %%ic" :: );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_enable_instruction(void)
+static inline void _CPU_cache_enable_instruction(void)
 {
   _CPU_CACR_OR( 0x00008000 );
 }
 
-RTEMS_INLINE_ROUTINE void _CPU_cache_disable_instruction(void)
+static inline void _CPU_cache_disable_instruction(void)
 {
   _CPU_CACR_AND( 0xFFFF7FFF );
 }
diff --git a/bsps/powerpc/gen5200/include/tm27.h b/bsps/powerpc/gen5200/include/tm27.h
index bd3dbb2d85..77dc566e49 100644
--- a/bsps/powerpc/gen5200/include/tm27.h
+++ b/bsps/powerpc/gen5200/include/tm27.h
@@ -34,7 +34,7 @@ static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
                                               (rtems_irq_disable) nullFunc,
                                               (rtems_irq_is_enabled) nullFunc};
 
-RTEMS_INLINE_ROUTINE void Install_tm27_vector(void (*_handler)(void))
+static inline void Install_tm27_vector(void (*_handler)(void))
 {
   clockIrqData.hdl = _handler;
   if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
diff --git a/bsps/powerpc/motorola_powerpc/include/bsp.h b/bsps/powerpc/motorola_powerpc/include/bsp.h
index 7d362bf406..1c35d8e1b7 100644
--- a/bsps/powerpc/motorola_powerpc/include/bsp.h
+++ b/bsps/powerpc/motorola_powerpc/include/bsp.h
@@ -190,7 +190,7 @@ extern int rtems_dec21140_driver_attach(struct rtems_bsdnet_ifconfig *, int);
 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_ne_driver_attach
 extern int rtems_ne_driver_attach(struct rtems_bsdnet_ifconfig *, int);
 
-RTEMS_INLINE_ROUTINE const char* bsp_cmdline_arg(const char* arg)
+static inline const char* bsp_cmdline_arg(const char* arg)
 {
   return rtems_bsp_cmdline_get_param_raw(arg);
 }
diff --git a/bsps/powerpc/mvme5500/include/tm27.h b/bsps/powerpc/mvme5500/include/tm27.h
index bf255aeb79..99686dc85d 100644
--- a/bsps/powerpc/mvme5500/include/tm27.h
+++ b/bsps/powerpc/mvme5500/include/tm27.h
@@ -32,7 +32,7 @@ static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
                                               (rtems_irq_disable)nullFunc,
                                               (rtems_irq_is_enabled) nullFunc};
 
-RTEMS_INLINE_ROUTINE void Install_tm27_vector(void (*_handler)())
+static inline void Install_tm27_vector(void (*_handler)())
 {
   clockIrqData.hdl = _handler;
   if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
diff --git a/bsps/powerpc/psim/include/tm27.h b/bsps/powerpc/psim/include/tm27.h
index 8e20a3ebd1..c8781efe65 100644
--- a/bsps/powerpc/psim/include/tm27.h
+++ b/bsps/powerpc/psim/include/tm27.h
@@ -32,7 +32,7 @@ static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
                                               (rtems_irq_disable)nullFunc,
                                               (rtems_irq_is_enabled) nullFunc};
 
-RTEMS_INLINE_ROUTINE void Install_tm27_vector(void (*_handler)())
+static inline void Install_tm27_vector(void (*_handler)())
 {
   clockIrqData.hdl = _handler;
   if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
diff --git a/bsps/powerpc/qoriq/include/tm27.h b/bsps/powerpc/qoriq/include/tm27.h
index 89ae11fef6..4ac769de90 100644
--- a/bsps/powerpc/qoriq/include/tm27.h
+++ b/bsps/powerpc/qoriq/include/tm27.h
@@ -53,7 +53,7 @@
 
 #define IPI_INDEX_HIGH 2
 
-RTEMS_INLINE_ROUTINE void Install_tm27_vector(void (*handler)(rtems_vector_number))
+static inline void Install_tm27_vector(void (*handler)(rtems_vector_number))
 {
   rtems_status_code sc;
   rtems_vector_number low = QORIQ_IRQ_IPI_0 + IPI_INDEX_LOW;
@@ -84,24 +84,24 @@ RTEMS_INLINE_ROUTINE void Install_tm27_vector(void (*handler)(rtems_vector_numbe
   assert(sc == RTEMS_SUCCESSFUL);
 }
 
-RTEMS_INLINE_ROUTINE void qoriq_tm27_cause(uint32_t ipi_index)
+static inline void qoriq_tm27_cause(uint32_t ipi_index)
 {
   uint32_t self = ppc_processor_id();
 
   qoriq.pic.per_cpu[self].ipidr[ipi_index].reg = UINT32_C(1) << self;
 }
 
-RTEMS_INLINE_ROUTINE void Cause_tm27_intr(void)
+static inline void Cause_tm27_intr(void)
 {
   qoriq_tm27_cause(IPI_INDEX_LOW);
 }
 
-RTEMS_INLINE_ROUTINE void Clear_tm27_intr(void)
+static inline void Clear_tm27_intr(void)
 {
   /* Nothing to do */
 }
 
-RTEMS_INLINE_ROUTINE inline void Lower_tm27_intr(void)
+static inline inline void Lower_tm27_intr(void)
 {
   qoriq_tm27_cause(IPI_INDEX_HIGH);
 }
diff --git a/bsps/powerpc/t32mppc/include/bsp/irq.h b/bsps/powerpc/t32mppc/include/bsp/irq.h
index a860dc28e1..bb9b9b1564 100644
--- a/bsps/powerpc/t32mppc/include/bsp/irq.h
+++ b/bsps/powerpc/t32mppc/include/bsp/irq.h
@@ -39,7 +39,7 @@ extern "C" {
 
 #define BSP_INTERRUPT_VECTOR_COUNT 1
 
-RTEMS_INLINE_ROUTINE rtems_status_code bsp_interrupt_set_affinity(
+static inline rtems_status_code bsp_interrupt_set_affinity(
   rtems_vector_number   vector,
   const Processor_mask *affinity
 )
@@ -49,7 +49,7 @@ RTEMS_INLINE_ROUTINE rtems_status_code bsp_interrupt_set_affinity(
   return RTEMS_SUCCESSFUL;
 }
 
-RTEMS_INLINE_ROUTINE rtems_status_code bsp_interrupt_get_affinity(
+static inline rtems_status_code bsp_interrupt_get_affinity(
   rtems_vector_number  vector,
   Processor_mask      *affinity
 )
diff --git a/bsps/powerpc/virtex/console/consolelite.c b/bsps/powerpc/virtex/console/consolelite.c
index 4d0b2db17f..9a2595a535 100644
--- a/bsps/powerpc/virtex/console/consolelite.c
+++ b/bsps/powerpc/virtex/console/consolelite.c
@@ -57,28 +57,28 @@
 
 
 
-RTEMS_INLINE_ROUTINE uint32_t xlite_uart_control(uint32_t base)
+static inline uint32_t xlite_uart_control(uint32_t base)
 {
   uint32_t c = *((volatile uint32_t*)(base+CTRL_REG));
   return c;
 }
 
 
-RTEMS_INLINE_ROUTINE uint32_t xlite_uart_status(uint32_t base)
+static inline uint32_t xlite_uart_status(uint32_t base)
 {
   uint32_t c = *((volatile uint32_t*)(base+STAT_REG));
   return c;
 }
 
 
-RTEMS_INLINE_ROUTINE uint32_t xlite_uart_read(uint32_t base)
+static inline uint32_t xlite_uart_read(uint32_t base)
 {
   uint32_t c = *((volatile uint32_t*)(base+RECV_REG));
   return c;
 }
 
 
-RTEMS_INLINE_ROUTINE void xlite_uart_write(uint32_t base, char ch)
+static inline void xlite_uart_write(uint32_t base, char ch)
 {
   *(volatile uint32_t*)(base+TRAN_REG) = (uint32_t)ch;
   return;
diff --git a/bsps/sparc/erc32/include/bsp/irq.h b/bsps/sparc/erc32/include/bsp/irq.h
index 83b383ba7a..b03d8fec85 100644
--- a/bsps/sparc/erc32/include/bsp/irq.h
+++ b/bsps/sparc/erc32/include/bsp/irq.h
@@ -25,7 +25,7 @@
 
 #define BSP_INTERRUPT_CUSTOM_VALID_VECTOR
 
-RTEMS_INLINE_ROUTINE rtems_status_code bsp_interrupt_set_affinity(
+static inline rtems_status_code bsp_interrupt_set_affinity(
   rtems_vector_number   vector,
   const Processor_mask *affinity
 )
@@ -35,7 +35,7 @@ RTEMS_INLINE_ROUTINE rtems_status_code bsp_interrupt_set_affinity(
   return RTEMS_SUCCESSFUL;
 }
 
-RTEMS_INLINE_ROUTINE rtems_status_code bsp_interrupt_get_affinity(
+static inline rtems_status_code bsp_interrupt_get_affinity(
   rtems_vector_number  vector,
   Processor_mask      *affinity
 )
diff --git a/bsps/x86_64/amd64/start/page.c b/bsps/x86_64/amd64/start/page.c
index 64bdf21707..c2e3949556 100644
--- a/bsps/x86_64/amd64/start/page.c
+++ b/bsps/x86_64/amd64/start/page.c
@@ -83,7 +83,7 @@ uint64_t get_mask_for_bits(uint8_t start, uint8_t end)
   return mask;
 }
 
-RTEMS_INLINE_ROUTINE void assert_0s_from_bit(uint64_t entry, uint8_t bit_pos)
+static inline void assert_0s_from_bit(uint64_t entry, uint8_t bit_pos)
 {
   /* Confirm that bit_pos:64 are all 0s */
   assert((entry & get_mask_for_bits(bit_pos, 64)) == 0);